JP6863368B2 - Signal processing equipment and methods, image sensors, and electronic devices - Google Patents

Description

The present disclosure relates to signal processing devices and methods, image pickup devices, and electronic devices, and more particularly to signal processing devices and methods, image pickup devices, and electronic devices capable of suppressing an increase in area.

As a D / A conversion device that can control the slope of the reference signal for single slope integration type A / D conversion with high accuracy, the current source cells whose current is controlled by the gain control D / A conversion circuit are sequentially selected and flowed to the reference resistance. A D / A conversion circuit that changes the current has been proposed (see, for example, Patent Document 1). In this D / A conversion circuit, a mechanism is adopted in which the total current is kept constant by passing the current of the non-selective current source cell to the reference voltage.

Japanese Patent No. 4682750

However, in the case of this method, when multiple systems of reference signals are required at the same time, such as an adaptive gain multi-slope A / D converter and a multi-slope A / D converter, each system is used to generate a reference signal. A D / A converter was needed. Therefore, as the number of reference signal systems increases, the circuit area may increase.

The present disclosure has been made in view of such a situation, and makes it possible to suppress an increase in area.

The signal processing device of one aspect of the present technology is a D / A conversion unit that converts a digital signal into an analog signal, and is a digital input that receives a predetermined current generated by receiving a gain control signal that controls the gain. It is divided into a first output current and a first non-output current according to the value of the signal, and the first non-output current is divided into a second output current and a second non-output current according to the value of the digital signal. It is a signal processing device including a first D / A conversion unit which is divided into the above and outputs the first output current and the second output current as analog signals, respectively.

The value of the digital signal can be changed in the time direction so as to increase the first output current and decrease the second output current.

The value of the digital signal can be made to change in the time direction so as to increase the first output current and the second output current.

A current source that receives the gain control signal and generates the current can be further provided.

The first D / A conversion unit drives the digital signal as a control signal, and is connected to each signal line connected to each of a plurality of output terminals to which the analog signal is output, and a voltage source. It may have a switch that controls the connection between the signal line and the current source.

The first D / A conversion unit has a plurality of the switches configured in parallel, and transfers the current according to the ratio of the number of the switches connecting each signal line and the current source. It can be divided into a plurality of output currents and the non-output current.

For each of the plurality of output currents, a resistor for converting the output current into a voltage can be further provided.

The resistance values of the resistors corresponding to each output current can be different from each other.

A conversion unit that converts a digital signal into an analog signal, and a predetermined current generated by receiving a gain control signal that controls the gain, with a single output current and non-output according to the value of the input digital signal. A second D / A conversion unit that divides into currents and uses the output current to control the signal level of the analog signal output from the first D / A conversion unit can be further provided.

A gain control unit that generates the gain control signal and supplies it to the first D / A conversion unit to control the gain can be further provided.

A digital signal generation unit that generates the digital signal and supplies it to the first D / A conversion unit can be further provided.

An A / D conversion unit that converts an analog signal into a digital signal by using the plurality of analog signals output from the first D / A conversion unit as a reference signal can be further provided.

The A / D conversion unit can be configured so that the gain can be adaptively switched by using the plurality of analog signals as reference signals.

The plurality of analog signals can be utilized by the A / D converters that are different from each other.

The A / D conversion unit is provided for each column of the pixel array in which a plurality of unit pixels are arranged in a matrix, and a pixel signal read from each pixel of the column corresponding to itself is converted from an analog signal to a digital signal. Can be converted to.

The A / D conversion unit is provided for each area of the pixel array in which a plurality of unit pixels are arranged in a matrix, and a pixel signal read from each pixel in the area corresponding to itself is converted from an analog signal to a digital signal. Can be converted to.

In the signal processing method of one aspect of the present technology, a predetermined current generated by receiving a gain control signal for controlling the gain is subjected to a first output current and a first non-output according to the value of the input digital signal. It is divided into currents, and the first non-output current is divided into a second output current and a second non-output current according to the value of the digital signal, and the first output current and the second output current are divided. Is a signal processing method that outputs each as an analog signal.

The image pickup elements on the other side of the present technology are a pixel array in which a plurality of unit pixels are arranged in a matrix and a D / A conversion unit that converts a digital signal into an analog signal, and is a gain control signal that controls the gain. The predetermined current generated in response to the above is divided into a first output current and a first non-output current according to the value of the input digital signal, and the first non-output current is divided into the value of the digital signal. A D / A conversion unit that divides into a second output current and a second non-output current and outputs the first output current and the second output current as analog signals, respectively, and the D / A. An image pickup device including an A / D conversion unit that converts a pixel signal read from the pixel array, which is an analog signal, into a digital signal by using the plurality of analog signals output from the conversion unit as a reference signal. is there.

The electronic device on the other side of the present technology includes an imaging unit that images a subject and an image processing unit that processes image data obtained by imaging by the imaging unit, and the imaging unit is a plurality of units. A pixel array in which pixels are arranged in a matrix and a D / A converter that converts a digital signal into an analog signal, and a predetermined current generated by receiving a gain control signal that controls the gain is input. It is divided into a first output current and a first non-output current according to the value of the digital signal, and the first non-output current is divided into a second output current and a second non-output current according to the value of the digital signal. A reference signal is a D / A conversion unit that divides into a current and outputs the first output current and the second output current as analog signals, and the plurality of analog signals output from the D / A conversion unit. It is an electronic device including an A / D conversion unit that converts a pixel signal read from the pixel array, which is an analog signal, into a digital signal.

In the signal processing device and method of one aspect of the present technology, a predetermined current generated by receiving a gain control signal for controlling gain has a plurality of output currents and non-output currents depending on the value of the input digital signal. It is divided into two, and the plurality of output currents are output as a plurality of analog signals.

In the image pickup element on the other side of the present technology, a predetermined current generated by receiving the gain control signal for controlling the gain is divided into a plurality of output currents and non-output currents according to the value of the digital signal, and the current is divided into a plurality of output currents and non-output currents. Each of the plurality of output currents is regarded as an analog signal, the plurality of analog signals are used as reference signals, and the pixel signal of the analog signal read from the pixel array in which a plurality of unit pixels are arranged in a matrix is a digital signal. Is converted to.

In an electronic device of yet another aspect of the present technology, a predetermined current generated by receiving a gain control signal for controlling a gain is divided into a plurality of output currents and non-output currents according to the value of the digital signal. Each of the plurality of output currents is regarded as an analog signal, the plurality of analog signals are used as a reference signal, and the pixel signal of the analog signal read from the pixel array in which a plurality of unit pixels are arranged in a matrix is digital. It is converted into a signal, and image data composed of the digital signal is image-processed.

According to the present disclosure, signals can be processed. In particular, it is possible to suppress an increase in area.

It is a figure which shows the main structural example of an image sensor. It is a figure which shows the main configuration example of a unit pixel. It is a figure which shows the main configuration example of a column parallel processing part. It is a figure which shows the main configuration example of the reference signal generation part. It is a figure which shows the main configuration example of the gain control D / A conversion part. It is a figure which shows the main configuration example of a current mirror. It is a figure which shows the main configuration example of the slope D / A conversion part T. It is a figure explaining the example of the state of the current division. It is a figure explaining the example of the state of the current division. It is a figure which shows the main configuration example of the slope D / A conversion part B. It is a figure which shows the example of the digital signal waveform. It is a figure which shows the main configuration example of a shift register. It is a figure which shows the main configuration example of a flip-flop. It is a figure which shows the example of the digital signal waveform. It is a figure which shows the example of the output current waveform. It is a figure which shows the example of the reference signal waveform. It is a figure which shows the example of the transition of the current division. It is a figure which shows the example of the waveform of the signal about A / D conversion in the dark case. It is a figure which shows the example of the waveform of the signal about A / D conversion in the bright case. It is a figure which shows the other configuration example of a column parallel processing part. It is a figure which shows the example of the waveform of the signal about A / D conversion. It is a figure which shows the other structural example of the reference signal generation part. It is a figure which shows the other structural example of the slope D / A conversion part T. It is a figure which shows another example of the transition of the current shunt. It is a figure which shows the main configuration example of an image pickup apparatus.

Hereinafter, embodiments for carrying out the present disclosure (hereinafter referred to as embodiments) will be described. The explanation will be given in the following order.
1. 1. First Embodiment (Image Sensor)
2. Second embodiment (column parallel processing unit)
3. 3. Third Embodiment (Reference signal generation unit)
4. Other

<1. First Embodiment>
<Generation of multiple reference signals>
Conventionally, in A / D (Analog / Digital) conversion in a CMOS (Complementary Metal Oxide Semiconductor) image sensor, the slope signal is used as a reference voltage to compare the image signal with the comparator, and the time until the output of the comparator is inverted is calculated. Slope A / D converters that count are widely used. Furthermore, the column A / D converter, which arranges multiple A / D converters for each pixel string and performs A / D conversion at the same time, reduces the operating frequency of each A / D converter to achieve low noise and high speed. The area and power consumption efficiency are good because the reference voltage is shared by each A / D converter, and the compatibility with the CMOS image sensor is good compared to other A / D conversion methods.

As a D / A (Digital / Analog) conversion device that can control the tilt of the reference signal for single-slope integration type A / D conversion with high accuracy, the current source cells whose current is controlled by the gain control D / A conversion circuit are sequentially selected. , A D / A conversion circuit that changes the current flowing through the reference resistor has been proposed (see Patent Document 1). In this prior application, a mechanism is adopted in which the total current is kept constant by passing the current of the non-selective current source cell to the reference voltage. By making the total current constant, the power supply voltage drop becomes constant regardless of the voltage level, so that the linearity of the reference signal is improved and the statically indeterminate time is shortened.

However, when it is necessary to generate a plurality of reference signals at the same time, such as an adaptive gain multi-slope A / D converter and a multi-slope A / D converter, a plurality of D / A converters are required. Therefore, as the number of reference signal systems increases, the circuit area may increase. As the circuit area increases, for example, it is necessary to increase the size of the semiconductor substrate and reduce the size of the pixel array (imaging area). Therefore, there is a risk that the cost will increase and the image quality will decrease. Further, as the number of reference signal systems increases, the power consumption may increase. Therefore, there is a risk that the cost will increase, the operable period when the battery is driven will be shortened, and the service life will be shortened.

For example, the D / A conversion circuit may occupy 0.85W of the total power of the image sensor of 3.0W, and the area and power may increase significantly in a configuration that requires twice the number of systems. there were.

<Generation of multiple reference signals>
Therefore, in the D / A conversion unit that converts a digital signal into an analog signal, a predetermined current generated by receiving the gain control signal that controls the gain is subjected to a plurality of output currents and a plurality of output currents according to the value of the input digital signal. It is divided into non-output currents, and the multiple output currents are output as multiple analog signals.

By doing so, it is possible to output a plurality of analog signals by one D / A conversion unit, and it is possible to suppress an increase in area and power consumption.

<Image sensor>
FIG. 1 shows a main configuration example of an image sensor, which is an embodiment of an image sensor to which the present technology is applied. The image sensor 100 shown in FIG. 1 is a device that photoelectrically converts light from a subject and outputs it as image data. For example, the image sensor 100 is configured as a CMOS image sensor using CMOS (Complementary Metal Oxide Semiconductor), a CCD image sensor using a CCD (Charge Coupled Device), and the like.

As shown in FIG. 1, the image sensor 100 includes a pixel array 101, a column parallel processing unit 102, a bus 103, an output terminal 104, a system control unit 111, a row scanning unit 112, and a column scanning unit 113.

The pixel array 101 is a pixel region in which a pixel configuration (unit pixel) having a photoelectric conversion element such as a photodiode is arranged in a plane or a curved surface. In the case of the example of FIG. 1, N × M unit pixels 121 (unit pixels 121-11 to unit pixels 121-NM) are arranged in a matrix (array shape) of N rows and M columns. In the following, when it is not necessary to distinguish the unit pixels 121-11 to the unit pixels 121-NM from each other and explain them, the unit pixels 121 to 121 are referred to as unit pixels 121. The arrangement of the unit pixels 121 is arbitrary, and may be an arrangement other than the matrix, for example, a so-called honeycomb structure or the like.

Each unit pixel 121 of the pixel array 101 is connected to a vertical signal line 122-1 to a vertical signal line 122-M for each unit pixel row (column). In the following, when it is not necessary to distinguish the vertical signal lines 122-1 to the vertical signal lines 122-M from each other, they are referred to as vertical signal lines 122. The analog signal read from each unit pixel 121 is column-parallel via the vertical signal line 122 (any of the vertical signal line 122-1 to the vertical signal line 122-M) corresponding to the unit pixel sequence (column). It is transmitted to the processing unit 102.

The column parallel processing unit 102 processes signals transmitted from each unit pixel 121 of the pixel array 101 via the vertical signal line 122 for each column independently of each other for each column. For example, the column parallel processing unit 102 A / D-converts the analog signals (for example, pixel signals) of each column read from the pixel array 101.

Further, the column parallel processing unit 102 is connected to the bus 103 for each column by the signal lines 123-1 to 123-M. In the following, when it is not necessary to distinguish the signal lines 123-1 to 123-M from each other, they are referred to as signal lines 123. The column parallel processing unit 102 inputs the signal processing result of each obtained column (for example, each digital data obtained by each A / D conversion) to the signal line 123 (signal line 123-1 to signal line 123-1 to the signal line) corresponding to the column. It is supplied to the bus 103 via any of 123-M).

Each digital data supplied from the column parallel processing unit 102 to the bus 103 via the signal line 123 is sequentially transferred to the output terminal 104 via the bus 103, and is transferred to the outside of the image sensor 100 via the output terminal 104. It is output.

The system control unit 111 controls the column parallel processing unit 102 by supplying a control signal via the control line 131. Further, the system control unit 111 controls the row scanning unit 112 by supplying a control signal via the control line 132. Further, the system control unit 111 controls the column scanning unit 113 by supplying a control signal via the control line 133. By controlling each part of the image sensor 100 in this way, the system control unit 111 controls the operation of the entire image sensor 100 (the operation of each part). In FIG. 1, the above-mentioned control lines 131 to 133 are each indicated by one dotted line (dotted line arrow), but each of these control lines is configured to be composed of a plurality of control lines. It may be.

The row scanning unit 112 is controlled by the system control unit 111 and supplies a control signal via the control lines 124-1 to 124-N, so that each unit pixel 121 of the pixel array 101 is divided into unit pixel rows. To control. In the following, when it is not necessary to distinguish the control lines 124-1 to 124-N from each other, they are referred to as control lines 124.

That is, the unit pixel 121 is connected to the vertical signal line 122 assigned to the column to which it belongs and the control line 124 assigned to the unit pixel line to which it belongs, and is supplied via the control line 124. It is driven based on the control signal, and the electric signal obtained by itself is supplied to the column parallel processing unit 102 via the vertical signal line 122.

The column scanning unit 113 controls the operation of the column parallel processing unit 102 for each column by being controlled by the system control unit 111 and supplying a control signal via the control lines 125-1 to 125-M. .. In the following, when it is not necessary to distinguish the control lines 125-1 to 125-M from each other, they are referred to as control lines 125.

Although the control line 124 of each unit pixel line is shown as one line in FIG. 1, the control line 124 of each unit pixel line may be composed of a plurality of control lines. .. Further, although the control line 125 of each column is shown as one line, the control line 125 of each column may be composed of a plurality of control lines.

<Unit pixel configuration>
FIG. 2 is a diagram showing an example of a main configuration of the circuit configuration of the unit pixel 121. As shown in FIG. 2, the unit pixel 121 includes a photodiode (PD) 151, a transfer transistor 152, a reset transistor 153, an amplification transistor 154, a selection transistor 155, and a floating diffusion (FD) 156.

The photodiode 151 photoelectrically converts the received light into a light charge (here, a photoelectron) having a charge amount corresponding to the light amount, and accumulates the light charge. The accumulated light charge is read out at a predetermined timing. The anode electrode of the photodiode 151 is connected to the ground (pixel ground) of the pixel region, and the cathode electrode is connected to the floating diffusion 156 via the transfer transistor 152. Further, for example, the cathode electrode of the photodiode 151 is connected to the power supply (pixel power supply) in the pixel region, the anode electrode is connected to the floating diffusion 156 via the transfer transistor 152, and the light charge is read out as an optical hole. Good.

The transfer transistor 152 controls the reading of the optical charge from the photodiode 151. In the transfer transistor 152, the drain electrode is connected to the floating diffusion, and the source electrode is connected to the cathode electrode of the photodiode 151. Further, a transfer control line (TRF) for transmitting a transfer control signal supplied from the row scanning unit 112 is connected to the gate electrode of the transfer transistor 152. This transfer control line (TRF) is a control line included in the control line 124 of FIG. When the transfer control line (TRF) signal (that is, the gate potential of the transfer transistor 152) is off, the optical charge is not transferred from the photodiode 151 (the optical charge is accumulated in the photodiode 151). On the other hand, when the signal of the transfer control line (TRF) is on, the optical charge accumulated in the photodiode 151 is transferred to the floating diffusion 156.

The reset transistor 153 resets the potential of the floating diffusion 156. In the reset transistor 153, the drain electrode is connected to the power supply potential, and the source electrode is connected to the floating diffusion 156. Further, a reset control line (RST) for transmitting a reset control signal supplied from the row scanning unit 112 is connected to the gate electrode of the reset transistor 153. This reset control line (RST) is a control line included in the control line 124 of FIG. When the reset control line (RST) signal (ie, the gate potential of the reset transistor 153) is off, the floating diffusion 156 is disconnected from the power supply potential. On the other hand, when the reset control line (RST) signal is on, the charge of the floating diffusion 156 is discarded to the power supply potential, and the floating diffusion 156 is reset.

The amplification transistor 154 amplifies the potential change of the floating diffusion 156 and outputs it as an electric signal (analog signal). In the amplification transistor 154, the gate electrode is connected to the floating diffusion 156, the drain electrode is connected to the source follower power supply voltage, and the source electrode is connected to the drain electrode of the selection transistor 155. For example, the amplification transistor 154 outputs the potential of the floating diffusion 156 reset by the reset transistor 153 to the selection transistor 155 as a reset signal (reset level). Further, the amplification transistor 154 outputs the potential of the floating diffusion 156 to which the optical charge is transferred by the transfer transistor 152 as an optical storage signal (signal level) to the selection transistor 155.

The selection transistor 155 controls the output of the electric signal supplied from the amplification transistor 154 to the vertical signal line (VSL) 122 (that is, the column parallel processing unit 102). In the selection transistor 155, the drain electrode is connected to the source electrode of the amplification transistor 154, and the source electrode is connected to the vertical signal line 122. Further, a select control line (SEL) for transmitting a select control signal supplied from the row scanning unit 112 is connected to the gate electrode of the selection transistor 155. This select control line (SEL) is a control line included in the control line 125 of FIG.

When the select control line (SEL) signal (that is, the gate potential of the selection transistor 155) is off, the amplification transistor 154 and the vertical signal line 122 are electrically separated. Therefore, in this state, the reset signal, the pixel signal, or the like is not output from the unit pixel 121. On the other hand, when the select control line (SEL) is on, the unit pixel 121 is in the selected state. That is, the amplification transistor 154 and the vertical signal line 122 are electrically connected, and the signal output from the amplification transistor 154 is supplied to the vertical signal line 122 as the signal of the unit pixel 121. That is, a reset signal, a pixel signal, or the like is read from the unit pixel 121.

The floating diffusion (FD) 156 is a charge storage unit that holds the electric charge read from the photodiode 151. As described above, for example, the potential change of the floating diffusion 156 is amplified by the amplification transistor 154 and output as an analog signal. Further, for example, the potential of the floating diffusion 156 is reset by the reset transistor 153.

The configuration of the unit pixel 121 is arbitrary and is not limited to the example of FIG. For example, various pixel configurations such as a 5-transistor type pixel configuration, a floating diffusion shared pixel configuration, a transistor shared pixel configuration, and a memory-mounted global shutter-operable pixel configuration can be applied.

<Column parallel processing unit>
FIG. 3 is a diagram showing a main configuration example of the column parallel processing unit 102. As shown in FIG. 3, the column parallel processing unit 102 includes a bias circuit 161-1 to a bias circuit 161-M. In the following, when it is not necessary to distinguish the bias circuits 161-1 to 161-M from each other, they are referred to as a bias circuit 161. The bias circuit 161 is provided for each vertical signal line 122 (that is, for each column). Each vertical signal line 122 is controlled to a predetermined voltage level by the bias circuit 161 corresponding to itself.

Further, the column parallel processing unit 102 includes a column A / D conversion unit 162-1 to a column A / D conversion unit 162-M. In the following, when it is not necessary to distinguish the column A / D conversion unit 162-1 to the column A / D conversion unit 162-M from each other, it is referred to as a column A / D conversion unit 162. The column A / D converter 162 is provided for each vertical signal line 122 (that is, for each column), and an analog signal (for example, from each unit pixel of the column) supplied via the vertical signal line 122 corresponding to the column A / D converter 162 is provided. The supplied pixel signal) is A / D converted. The column A / D conversion unit 162 supplies the digital signal obtained by the A / D conversion to the bus 103 via the signal line 123 corresponding to the column A / D conversion unit 162.

Further, the column parallel processing unit 102 includes a reference signal generation unit 163, and a reference signal line 164-1 and a reference signal line 164-2. The reference signal generation unit 163 generates a reference signal used by each column A / D conversion unit 162. The reference signal generation unit 163 generates two reference signals, a reference signal 1 and a reference signal 2. The reference signal 1 and the reference signal 2 are signals having a lamp waveform, and the slopes of the waveforms are different from each other. The reference signal 1 is supplied to each column A / D conversion unit 162 via the reference signal line 164-1. The reference signal 2 is supplied to each column A / D conversion unit 162 via the reference signal line 164-2. In the following, when it is not necessary to distinguish the reference signal line 164-1 and the reference signal line 164-2 from each other, they are referred to as reference signal lines 164.

The column A / D conversion unit 162 A / D-converts an analog signal supplied via the vertical signal line 122 by using such a reference signal of the ramp wave system. That is, the column A / D conversion unit 162 compares the reference signal and the analog signal, and outputs the length of the period until the comparison result is inverted as digital data (that is, the A / D conversion result of the analog signal). To do. As described above, the reference signal 1 and the reference signal 2 have different slope slopes. The column A / D conversion unit 162 selects and uses which of the two reference signals (reference signal 1 and reference signal 2) has an appropriate slope inclination with respect to the analog signal to be A / D converted. That is, the column A / D conversion unit 162 can adaptively switch the slope of the reference signal in the A / D conversion of the analog signal according to the signal level of the analog signal. As a result, the column A / D conversion unit 162 can realize more accurate A / D conversion at high speed and with a high dynamic range regardless of the signal level of the analog signal to be A / D converted.

Although not shown, the reference signal generation unit 163 is driven based on the control signal supplied from the system control unit 111 via the control line 131 (that is, the control of the system control unit 111). Further, the column A / D conversion unit 162 is driven based on a control signal (that is, control of the column scanning unit 113) supplied from the column scanning unit 113 via the control line 125.

The column A / D conversion unit 162 includes a comparison unit 171, a counter 172, a determination value latch 173, a selector 174, a capacitor 175, and a capacitor 176.

The comparison unit 171 compares the signal levels of each signal input to the two input terminals, and outputs the comparison result from one output terminal. One input terminal of the comparison unit 171 is connected to the selector 174 via the capacitor 175, and the reference signal 1 or the reference signal 2 is input. Further, the other input terminal of the comparison unit 171 is connected to the vertical signal line 122 via a capacitor 176, and an analog signal supplied from a unit pixel of the column is input. That is, the comparison unit 171 compares the signal level of the reference signal 1 or the reference signal 2 with the signal level of the analog signal supplied via the vertical signal line 122. The comparison unit 171 supplies information indicating which signal has the higher signal level to the counter 172 and the determination value latch 173 as the comparison result.

For example, this comparison result is 1-bit digital data. For example, when the signal level of the reference signal is higher than the signal level of the analog signal, the value of this comparison result is "0", and in the opposite case, the value is "1". Of course, the method of taking this value may be reversed. Further, the bit length of this comparison result is arbitrary, and may be information composed of a plurality of bits.

The counter 172 has an input terminal connected to an output terminal of the comparison unit 171 and an output terminal connected to a signal line 123 of a column corresponding to the counter 172. The comparison result is supplied to the counter 172 from the comparison unit 171. The counter 172 measures the time from the start of counting until the comparison result is inverted (the signal level of the output signal of the comparison unit 171 changes) (for example, counting the number of clocks of a predetermined clock signal). Then, the counter 172 uses the count value up to that point as the A / D conversion result (digital data) of the analog signal read from the unit pixel 121 when the comparison result is inverted, via the signal line 123. Supply to 103.

The determination value latch 173 holds the comparison result supplied from the comparison unit 171. The determination value latch 173 generates a control signal for controlling the operation (selection) of the selector 174 according to the comparison result held by the determination value latch 173 or the control of the column scanning unit 113 (system control unit 111), and generates the control signal. It supplies to the selector 174.

In the 2-input 1-output selector 174, one of the input terminals is connected to the reference signal line 164-1, the other input terminal is connected to the reference signal line 164-2, and the output terminal is a comparison unit via the capacitor 175. It is connected to one of the input terminals of 171. The selector 174 selects a reference signal to be supplied to the comparison unit 171 based on the control signal supplied from the determination value latch 173.

The capacitor 175 is provided between the output terminal of the selector 174 and one input terminal of the comparison unit 171. The capacitor 176 is provided between the vertical signal line 122 and the other input terminal of the comparison unit 171. Capacitors 175 and 176 are capacitive elements for analog CDS that cancel analog element variations.

For example, the determination value latch 173 causes the selector 174 to select the reference signal 1 in the first P phase of the correlated double sampling (CDS), and causes the selector 174 to select the reference signal 2 in the second P phase. .. The comparison unit 171 sequentially compares the reset signal with these reference signals. That is, the reset signal is A / D converted using each reference signal.

Further, for example, the determination value latch 173 causes the selector 174 to select a reference signal according to the signal level of the pixel signal in the D phase of the CDS. That is, the selector 174 selects the reference signal 1 or the reference signal 2 (that is, the slope of the reference signal) according to the comparison result (that is, the magnitude of the signal level of the analog signal). Then, the comparison unit 171 compares the pixel signal with the selected reference signal, and the counter 172 counts the period until the comparison result is inverted. That is, the pixel signal is A / D converted using the reference signal corresponding to the signal level.

By doing so, the column A / D converter 162 uses a reference signal (for example, a reference signal having a slope with a more appropriate slope) that is more appropriate for the signal level of the pixel signal in the D phase. A / D conversion of pixel signals can be performed. That is, the column A / D conversion unit 162 can omit the A / D conversion using an unnecessary reference signal in the D phase, and realize a high-speed, high dynamic range, and more accurate A / D conversion. Can be done.

<Reference signal generator>
FIG. 4 is a block diagram showing a main configuration example of the reference signal generation unit 163. As shown in FIG. 4, the reference signal generation unit 163 includes a constant voltage generation unit 201, a gain control decoder 202, a gain control D / A conversion unit 203, and a current mirror 204. Further, the reference signal generation unit 163 includes a slope D / A conversion unit T205, a slope D / A conversion unit B206 (slope D / A conversion unit B1), and a slope D / A conversion unit B207 (slope D / A conversion unit B2). , Resistance 208, and resistance 209. Further, the reference signal generation unit 163 has a frequency divider 211, a NOT gate 212, a shift register 213, a frequency divider 221 and a NOT gate 222, a shift register 223, a NOT gate 224, and a NOT gate 225.

The constant voltage generation unit 201 generates a constant voltage Vb and supplies it to the gain control D / A conversion unit 203. The gain control decoder 202 decodes the gain control signals (not shown) supplied from the system control unit 111 to generate (n + 1) gain control signals PGC [n: 0], and obtains them as gain control D /. It is supplied to the A conversion unit 203.

The gain control D / A conversion unit 203 generates a current corresponding to the constant voltage Vb supplied from the constant voltage generation unit 201, and sets the value of the gain control signal PGC [n: 0] supplied from the gain control decoder 202. The current is divided into the current Ipgcu and the current Ipgc at the corresponding ratios. In the gain control D / A conversion unit 203, (n + 1) configurations are installed in parallel to generate a current corresponding to a constant voltage Vb and allocate the current to the current Ipgcu or the current Ipgc. n is an arbitrary natural number. That is, the number of this configuration is arbitrary. By allocating the current according to the value corresponding to itself in the gain control signal PGC [n: 0] in each of these (n + 1) configurations, the current corresponding to the constant voltage Vb can be obtained as a whole. It is divided into current Ipgcu and current Ipgc at a ratio according to the value of the gain control signal PGC [n: 0]. In other words, the sum of the current Ipgcu and the current Ipgc (that is, the current corresponding to the constant voltage Vb) is constant regardless of the code of the gain control signal. The current Ipgcu is output to the ground (GND), and the current Ipgc is supplied to the current mirror 204.

The current mirror 204 converts the current Ipgc into a current voltage to generate a bias voltage Vpg. This bias voltage Vpg is supplied to the slope D / A conversion unit T205, the slope D / A conversion unit B206, and the slope D / A conversion unit 207.

The slope D / A converter T205 generates a current Itt according to the bias voltage Vpg, and calculates the current Itt at a ratio corresponding to the values of the digital signal TH1 [k: 0] and the digital signal xTH2 [k: 0]. , Current It1, Current It2, Current Itu. In the slope D / A conversion unit T205, (k + 1) configurations are installed in parallel to generate a current Itt according to the bias voltage Vpg and assign the current Itt to any of the current It1, the current It2, and the current Itu. There is. k is an arbitrary natural number. That is, the number of this configuration is arbitrary. This (k + 1) configuration is the whole by allocating the current Itt according to the value corresponding to itself in the digital signal TH1 [k: 0] and the digital signal xTH2 [k: 0], respectively. As a result, the current Itt according to the bias voltage Vpg is divided into the current It1, the current It2, and the current Itu at a ratio corresponding to the values of the digital signal TH1 [k: 0] and the digital signal xTH2 [k: 0]. In other words, Itt = It1 + It2 + Itu regardless of the values of the digital signal TH1 [k: 0] and the digital signal xTH2 [k: 0].

A resistor 208 having a resistance value R1 and a reference signal line 164-1 are connected to the signal line through which the current It1 flows. The current It1 is converted into a voltage by the resistor 208 and is converted into a voltage as an analog signal (reference signal 1). It is output from line 164-1. Further, a resistance 209 having a resistance value R2 and a reference signal line 164-2 are connected to the signal line through which the current It2 flows, and the current It2 is converted into a voltage by the resistance 209 and used as an analog signal (reference signal 2). It is output from the reference signal line 164-2. As described above, the reference signal 1 and the reference signal 2 are supplied to the column A / D conversion unit 162. Further, the signal line through which the current Itu flows is connected to the power supply potential AVD (for example, 3.3V).

That is, the current It1 and the current It2 are the output currents that are output, and the current Itu is the non-output current (also referred to as the discard current) that is not output. That is, the slope D / A conversion unit T205 generates a predetermined current Itt according to the bias voltage Vpg, and converts the current Itt into the values of the digital signal TH1 [k: 0] and the digital signal xTH2 [k: 0]. It is divided into multiple output currents (current It1 and current It2) and non-output currents (current Itu) at appropriate ratios. Then, the plurality of output currents are converted into voltages and output as analog signals (reference signal 1 and reference signal 2).

The slope D / A conversion unit B206 (slope D / A conversion unit B1) is a binary code current source for the reference signal 1. The slope D / A converter B206 generates a current Itb1 according to the bias voltage Vpg, and divides the current Itb1 into a current Ib1 and a current Ibu1 at a ratio corresponding to the value of the digital signal CK1 [4: 0]. To do. The slope D / A conversion unit B206 controls, for example, the lower bits of the signal level of the reference signal 1 by the current Ib1. In the slope D / A conversion unit B206, five configurations are installed in parallel to generate a current Itb1 according to the bias voltage Vpg and allocate the current Itb1 to the current Ib1 or the current Ibu1. Each of these five configurations allocates the current Itb1 according to the value corresponding to itself in the digital signal CK1 [4: 0], so that the current Itb1 corresponding to the bias voltage Vpg is generated as a whole. , The current Ib1 and the current Ibu1 are divided at a ratio according to the value of the digital signal CK1 [4: 0]. In other words, Itb1 = Ib1 + Ibu1 regardless of the value of the digital signal CK1 [4: 0]. In this case, the slope D / A conversion unit B206 controls, for example, the lower 5 bits of the signal level of the reference signal 1.

Similarly, the slope D / A conversion unit B207 (slope D / A conversion unit B2) is a binary code current source for the reference signal 2. The slope D / A conversion unit B207 generates a current Itb2 according to the bias voltage Vpg, and divides the current Itb2 into a current Ib2 and a current Ibu2 at a ratio corresponding to the value of the digital signal CK2 [4: 0]. To do. The slope D / A conversion unit B207 controls, for example, the lower bits of the signal level of the reference signal 2 by the current Ib2. In the slope D / A conversion unit B207, five configurations are installed in parallel in which a current Itb2 corresponding to the bias voltage Vpg is generated and the current Itb2 is assigned to the current Ib2 or the current Ibu2. Each of these five configurations allocates the current Itb2 according to the value corresponding to itself in the digital signal CK2 [4: 0], so that the current Itb2 corresponding to the bias voltage Vpg is generated as a whole. , The current Ib2 and the current Ibu2 are divided at a ratio according to the value of the digital signal CK2 [4: 0]. In other words, Itb2 = Ib2 + Ibu2 regardless of the value of the digital signal CK2 [4: 0]. In this case, the slope D / A conversion unit B207 controls, for example, the lower 5 bits of the signal level of the reference signal 2.

The current Ib1 is converted into a voltage by the resistor 208 and output as an analog signal (reference signal 1) from the reference signal line 164-1. The voltage of the reference signal 1 is AVD− (It1 + Ib1) × R1. The current Ib2 is converted into a voltage by the resistor 209 and output as an analog signal (reference signal 2) from the reference signal line 164-2. The voltage of the reference signal 2 is AVD− (It2 + Ib2) × R2. The signal line through which the current Ibu1 flows and the signal line through which the current Ibu2 flows are connected to the power supply potential AVD (for example, 3.3V).

That is, the current Ib1 is the output current that is output, and the current Ibu1 is the non-output current that is not output (also referred to as the discard current). That is, the slope D / A conversion unit B206 generates a predetermined current Itb1 according to the bias voltage Vpg, and the current Itb1 is converted into a single output current at a ratio corresponding to the value of the digital signal CK1 [4: 0]. It is divided into (current Ib1) and non-output current (current Ibu1). Then, this singular output current (current Ib1) is converted into a voltage and output as an analog signal (reference signal 1). That is, the slope D / A conversion unit B206 uses this singular output current (current Ib1) to control the signal level of the analog signal (reference signal 1) output from the slope D / A conversion unit T205.

Similarly, the current Ib2 is the output current that is output, and the current Ibu2 is the non-output current (also referred to as the discard current) that is not output. That is, the slope D / A conversion unit B207 generates a predetermined current Itb2 according to the bias voltage Vpg, and uses the current Itb2 as a single output current at a ratio corresponding to the value of the digital signal xCK2 [4: 0]. It is divided into (current Ib2) and non-output current (current Ibu2). Then, this singular output current (current Ib2) is converted into a voltage and output as an analog signal (reference signal 2). That is, the slope D / A conversion unit B207 uses this singular output current (current Ib2) to control the signal level of the analog signal (reference signal 2) output from the slope D / A conversion unit T205.

The number of parallel slope D / A conversion units B206 and slope D / A conversion unit B207 is arbitrary and may be other than five.

The resistor 208 is a resistor having a resistance value of R1 in which one end is connected to the power supply potential AVD and the other end is connected to the signal line through which the current It1 flows or the reference signal line 164-1 through which the reference signal 1 flows. .. That is, the resistor 208 converts the current It1 and the current Ib1 into a voltage. The resistor 209 is a resistor having a resistance value of R2 in which one end is connected to the power supply potential AVD and the other end is connected to the signal line through which the current It2 flows or the reference signal line 164-2 through which the reference signal 2 flows. .. That is, the resistor 209 converts the current It2 and the current Ib2 into a voltage. The resistance value R1 of the resistor 208 and the resistance value R2 of the resistor 209 may be different from each other.

The frequency divider 211 divides the input clock INCK and generates a digital signal CK1 [4: 0]. The NOT gate 212 inverts the digital signal CK1 [4] and generates the digital signal xCK1 [4]. The shift register 213 generates a digital signal TH1 [k: 0] using the digital signal xCK1 [4]. The shift register 213 supplies the digital signal TH1 [k: 0] to the slope D / A conversion unit T205. Further, the frequency divider 211 supplies the generated digital signal CK1 [4: 0] to the slope D / A conversion unit B206 (slope D / A conversion unit B1).

The frequency divider 221 divides the input clock INCK and generates a digital signal CK2 [4: 0]. By setting the frequency division ratios of the frequency divider 211 and the frequency divider 221 to different values, the digital signal CK1 [4] and the digital signal CK2 [4] can have different frequencies. The NOT gate 222 inverts the digital signal CK2 [4] and generates the digital signal xCK2 [4]. The shift register 223 uses the digital signal xCK2 [4] to generate a digital signal TH2 [k: 0]. The NOT gate 224 inverts the digital signal TH2 [k: 0] to generate the digital signal xTH2 [k: 0]. The NOT gate 224 supplies the digital signal xTH2 [k: 0] to the slope D / A conversion unit T205. Further, the NOT gate 225 inverts the digital signal CK2 [4: 0] generated by the frequency divider 221 to generate the digital signal xCK2 [4: 0]. The NOT gate 225 supplies the generated digital signal xCK2 [4: 0] to the slope D / A conversion unit B207 (slope D / A conversion unit B2).

As shown by the dotted line in FIG. 4, a resistor 208 and a resistor 209 may be added to the slope D / A conversion unit T205 to form the slope D / A conversion unit T231. The slope D / A conversion unit T231 can perform D / A conversion of the digital signal TH1 [k: 0] and the digital signal xTH2 [k: 0], and output the reference signal 1 and the reference signal 2 as analog signals. .. Further, as shown by the dotted line in FIG. 4, the slope D / A conversion unit B206 and the slope D / A conversion unit B207 are added to the configuration of the slope D / A conversion unit T231 to form the slope D / A conversion unit 232. May be good. The slope D / A conversion unit 232 D / A-converts the digital signal TH1 [k: 0], the digital signal xTH2 [k: 0], the digital signal CK1 [4: 0], and the digital signal xCK2 [4: 0]. , The reference signal 1 and the reference signal 2 including the lower bits can be output as analog signals.

As shown by the dotted line in FIG. 4, the constant voltage generation unit 201, the gain control decoder 202, the gain control D / A conversion unit 203, and the current mirror 204 may be collectively referred to as the gain control unit 233. The gain control unit 233 generates a bias voltage Vpg according to the input gain control signal, and converts the bias voltage Vpg into a slope D / A conversion unit 232 (slope D / A conversion unit T205, slope D / A conversion unit B206). , Slope D / A conversion unit B207).

Further, as shown by the dotted line in FIG. 4, the frequency divider 211, the NOT gate 212, the shift register 213, the frequency divider 221 and the NOT gate 222, the shift register 223, the NOT gate 224, and the NOT gate 225 are grouped together. It may be a digital signal generation unit 234. Using the input clock INCK, the digital signal generator 234 uses the digital signal TH1 [k: 0], the digital signal xTH2 [k: 0], the digital signal CK1 [4: 0], and the digital signal xCK2 [4: 0]. Are generated and supplied to the slope D / A conversion unit 232.

<Gain control D / A converter>
FIG. 5 is a diagram showing a main configuration example of the gain control D / A conversion unit 203. In FIG. 5, only one of the (n + 1) configurations of the gain control D / A conversion unit 203 arranged in parallel is shown. Since the other n configurations are the same as the configurations shown in FIG. 5, the description thereof will be omitted.

As shown in FIG. 5, the gain control D / A conversion unit 203 has a PMOS current source 251. The photoresist current source 251 generates a current corresponding to the constant voltage Vb input as the bias voltage. Further, the gain control D / A conversion unit 203 includes a switch 252 and a switch 253. The switch 252 and the switch 253 are arranged in parallel and are controlled by using the NOT gate 254 so that when one is ON, the other is OFF. That is, the path through which the current generated by the MIMO current source 251 flows is selected. For example, when the switch 252 is on (the switch 253 is off), the current generated by the PBSO current source 251 flows toward the ground potential (GND) as the current Ipgcu. Further, for example, when the switch 252 is off (the switch 253 is on), the current generated by the MIMO current source 251 flows toward the current mirror 204 as the current Ipgc.

The control of the switch 252 and the switch 253 is performed by the digital signal PGC [n: 0]. In each of the (n + 1) such configurations arranged in parallel, the path through which the current generated by the MIMO current source 251 flows is selected so that the current generated by the MIMO current source 251 becomes a digital signal. It is divided into the current Ipgcu and the current Ipgc at a ratio according to the value of PGC [n: 0].

<Current mirror>
FIG. 6 is a diagram showing a main configuration example of the current mirror 204. As shown in FIG. 6, the current mirror 204 has an N MOSFET 261, and the N MOSFET 261 converts the current Ipgc into a bias voltage Vpg. The bias voltage Vpg is supplied to, for example, the slope D / A conversion unit T205, the slope D / A conversion unit B206, and the slope D / A conversion unit B207.

<Slope D / A conversion unit T>
FIG. 7 is a diagram showing a main configuration example of the slope D / A conversion unit T205. In FIG. 7, only one of the (k + 1) configurations of the slope D / A conversion unit T205 arranged in parallel is shown. Since the other k configurations are the same as the configurations shown in FIG. 7, the description thereof will be omitted.

As shown in FIG. 7, the slope D / A converter T205 includes an IMS switch 271, an NOTES switch 272, an NOTES switch 273, a NOT gate 274, a NOR gate 275, a NOR gate 276, and an MIMO current source 277 (NMOS current source). Has T).

The NMOS current source 277 generates a current Itt corresponding to the bias voltage Vpg. That is, the MIMO current source 277 receives the gain control signal and generates a predetermined current (current Itt). The NMOS switches 271 to 273 control the path of the current Itt. The NMOS switch 271 controls the connection between the MIMO current source 277 and the resistor 208. That is, the MIMO switch 271 controls whether or not the current Itt is set to the current It1. The NMOS switch 272 controls the connection between the MIMO current source 277 and the resistor 209. That is, the MIMO switch 272 controls whether or not the current Itt is set to the current It2. The NMOS switch 273 controls the connection between the MIMO current source 277 and the power potential AVD. That is, the MIMO switch 273 controls whether or not the current Itt is the current Itu.

The NMOS switches 271 to 273 are controlled by the digital signal TH1 [k: 0] and the digital signal xTH2 [k: 0] so that any one of them is turned on. The digital signal TH1 [k: 0] supplied from the shift register 213 is supplied to the gate of the MIMO switch 271, one input terminal of the NOR gate 275, and one input terminal of the NOR gate 276. Further, the digital signal xTH2 [k: 0] supplied from the NOT gate 224 is supplied to the other input terminals of the NOT gate 274 and the NOR gate 276. The NOT gate 274 inverts the value of the digital signal xTH2 [k: 0] and supplies it to the other input terminal of the NOR gate 275. The NOR gate 275 supplies a negative logical sum of the digital signal TH2 [k: 0] and the digital signal TH1 [k: 0] to the gate of the MIMO switch 272. The NOR gate 276 supplies a negative logical sum of the digital signal xTH2 [k: 0] and the digital signal TH1 [k: 0] to the gate of the MIMO switch 273.

For example, when the digital signal TH1 [k: 0] is "1", the MIMO switch 271 is turned on, and the MIMO switch 272 and the MIMO switch 273 are turned off. Further, for example, when the digital signal TH1 [k: 0] is "0", the MIMO switch 271 is turned off. At this time, if the digital signal xTH2 [k: 0] is "1", the MIMO switch 272 is turned on and the MIMO switch 273 is turned off. On the contrary, when the digital signal xTH2 [k: 0] is "0", the MIMO switch 272 is turned off and the MIMO switch 273 is turned on.

By doing so, the current Itt is either current It1, current It2, or current Itu. That is, the MIMO switches 271 to 273 select whether the current Itt is the current It1, the current It2, or the current Itu.

As shown by the dotted line in FIG. 7, the MIMO switches 271 to 273 may be collectively referred to as the switch 281. That is, the switch 281 drives the digital signal TH1 [k: 0] and the digital signal xTH2 [k: 0] as control signals, and a plurality of output signal lines (reference signal lines 164-1 and reference) from which analog signals are output. It has each signal line connected to each of the signal lines 164-2), and a switch for controlling the connection between the signal line connected to the voltage source (power supply potential AVD) and the current source (NMOS current source 277). .. The configuration of the switch 281 is arbitrary as long as the current Itt can be selected from the current It1, the current It2, and the current Itu. It is not limited to the configuration example of.

Further, as shown by the dotted line in FIG. 7, the NOT gate 274, the NOR gate 275, and the NOR gate 276 may be further added to the configuration of the switch 281 to form the D / A conversion unit 282. The D / A conversion unit 282 can output the current It1 and the current It2 according to the digital signal TH1 [k: 0] and the digital signal xTH2 [k: 0].

As described above, the slope D / A conversion unit T205 has (k + 1) configurations as shown in FIG. 7, and they are arranged in parallel. The NMOS current sources 277 of each configuration have the same size (W length, L length, number of parallels, etc.) and pass equal currents. In each of the (k + 1) such configurations arranged in parallel, a path through which the current generated by the MIMO current source 277 flows is selected. Therefore, in the entire slope D / A converter T205, the current Itt generated by the MIMO current source 277 is divided into the current It1, the current It2, and the current Itu according to the ratio of this selection. That is, the number of switches 281 connected to the NFS current source 277 to the signal line through which the current It1 flows, the number of switches 281 connected to the signal line passing the current It2, and the current Itu The current Itt is divided into the current It1, the current It2, and the current Itu according to the ratio of the number of switches 281 connected to the signal line through which the current is flowing. In other words, the current Itt is divided into the current It1, the current It2, and the current Itu according to the ratio of the number of the on-state MIMO switches 271, the number of the on-state MIMO switches 272, and the number of the on-state MIMO switches 273. To.

In the conventional case, the slope D / A converter divides a predetermined current generated by receiving a gain control signal for controlling a gain into a single output current and a non-output current (discard current). Therefore, as shown in A of FIG. 8 and B of FIG. 8, it is necessary to provide a slope D / A conversion unit for each gain. Therefore, there is a risk that the circuit area and power consumption will increase.

On the other hand, as shown in FIG. 9, the slope D / A conversion unit T205 applies a predetermined current generated by receiving the gain control signal for controlling the gain according to the value of the input digital signal. Divide into multiple output currents and non-output currents.

Therefore, the slope D / A conversion unit T205 can suppress an increase in the circuit area and power consumption as compared with the case of the example of FIG.

At that time, the slope D / A conversion unit T205 recursively repeats the division of the current (non-output current) into the output current and the non-output current. For example, the slope D / A conversion unit T205 divides a predetermined current into a first output current and a first non-output current at a ratio corresponding to the value of the digital signal, and further divides the first non-output current. Is divided into a second output current and a second non-output current at a ratio corresponding to the value of the digital signal, and the first output current and the second output current are output, respectively. The first output current and the second output current are converted into a voltage by a resistor and output as an analog signal.

More specifically, for example, the slope D / A converter T205 converts the current Itt into the current It1 and the current (Itt) at a ratio corresponding to the values of the digital signal TH1 [k: 0] and the digital signal xTH2 [k: 0]. -It1) and the current (Itt-It1) are further divided into the current It2 and the current Itu at a ratio according to the values of the digital signal TH1 [k: 0] and the digital signal xTH2 [k: 0]. Then, the current It1 and the current It2 are output respectively. The current It1 and the current It2 are converted into a voltage by the resistor 208 and the resistor 209, and are output as the reference signal 1 and the reference signal 2.

By doing so, the slope D / A conversion unit T205 can more easily divide the current generated by receiving the gain control signal into a plurality of output currents and a non-output current.

<Slope D / A conversion unit B>
FIG. 10 is a diagram showing a main configuration example of the slope D / A conversion unit B206 and the slope D / A conversion unit B207. FIG. 10A is a diagram showing a main configuration example of the slope D / A conversion unit B206, and FIG. 10B is a diagram showing a main configuration example of the slope D / A conversion unit B207. In A of FIG. 10 and B of FIG. 10, only one of the five configurations of the slope D / A conversion unit B206 and the slope D / A conversion unit B207 arranged in parallel is shown.

As shown in FIG. 10A, the slope D / A converter B206 has an IMSO switch 301, an NOTES switch 302, an NOT gate 303, and an MIMO current source 304.

The NMOS current source 304 (NMOS current source B1) produces a current Itb1 corresponding to the bias voltage Vpg. The NMOS switch 301 (Nb1) and the NMOS switch 302 (Nbu1) are arranged in parallel and are controlled by using a NOT gate 303 so that when one is ON, the other is OFF. .. That is, the path through which the current Itb1 generated by the MIMO current source 304 flows is selected. For example, when the MIMO switch 301 is on (NMOS switch 302 is off), the current Itb1 flows from the reference signal line 164-1 toward the ground potential GND as the current Ib1. Further, for example, when the MIMO switch 301 is off (NMOS switch 302 is on), the current Itb1 flows from the power supply potential AVD toward the ground potential GND as the current Ibu1. That is, depending on the states of the MIMO switch 301 (Nb1) and the MIMO switch 302 (Nbu1), it is selected whether the current Itb1 is the output current (current Ib1) or the non-output current (current Ibu1).

The control of the NMOS switch 301 and the NMOS switch 302 is performed by the digital signal CK1 [4: 0]. Further, the five configurations arranged in parallel as the slope D / A conversion unit B206 basically have the same configuration as A in FIG. However, the size (number of parallels or W / L) of the MIMO current source 304 is different. For example, assuming that the size of the MIMO current source 277 is 1, the size of each IMS current source 304 depends on the frequency ratio T1 between the digital signal CK1 [n] (n = 0 to 4) and the digital signal CK1 [4]. It may be 1/2 x 1 / T1 times the size. For example, in the case where the digital signal CK1 [0] is input, the size of the MIMO current source 304 is 1/32 times that of the digital signal CK1 [4] because the frequency of the digital signal CK1 [0] is 16 times that of the digital signal CK1 [4]. It may be.

In each of the five such configurations arranged in parallel, the path through which the current generated by the MIMO current source 304 flows is selected. Therefore, in the entire slope D / A conversion unit B206, the current Itb1 generated by the MIMO current source 304 is divided into the current Ib1 and the current Ibu1 according to the ratio of this selection. That is, the current Itb1 is divided into the current Ib1 and the current Ibu1 according to the ratio of the number of the ON MOS switches 301 to the number of the ON MOS switches 302.

As shown in FIG. 10B, the slope D / A converter B207 has an IMSO switch 311, an NOTES switch 312, an NOT gate 313, and an MIMO current source 314.

The NMOS current source 314 (NMOS current source B2) produces a current Itb2 corresponding to the bias voltage Vpg. The NMOS switch 311 (Nb2) and the NMOS switch 312 (Nbu2) are arranged in parallel and are controlled using NOT gate 313 so that when one is ON, the other is OFF. .. That is, the path through which the current Itb2 generated by the MIMO current source 314 flows is selected. For example, when the MIMO switch 311 is on (NMOS switch 312 is off), the current Itb2 flows from the reference signal line 164-2 toward the ground potential GND as the current Ib2. Further, for example, when the MIMO switch 311 is off (NMOS switch 312 is on), the current Itb2 flows from the power supply potential AVD toward the ground potential GND as the current Ibu2. That is, depending on the state of the MIMO switch 311 (Nb2) and the MIMO switch 312 (Nbu2), it is selected whether the current Itb2 is the output current (current Ib2) or the non-output current (current Ibu2).

The control of the NMOS switch 311 and the MIMO switch 312 is performed by the digital signal xCK2 [4: 0]. Further, the five configurations arranged in parallel as the slope D / A conversion unit B207 have basically the same configurations as B in FIG. However, the size (number of parallels or W / L) of the MIMO current source 314 is different. For example, assuming that the size of the MIMO current source 277 is 1, the size of each IMS current source 314 depends on the frequency ratio T2 between the digital signal CK2 [n] (n = 0 to 4) and the digital signal CK2 [4]. It may be 1/2 x 1 / T2 times the size.

In each of the five such configurations arranged in parallel, the path through which the current generated by the MIMO current source 314 flows is selected. Therefore, in the entire slope D / A conversion unit B207, the current Itb2 generated by the MIMO current source 314 is divided into the current Ib2 and the current Ibu2 according to the ratio of this selection. That is, the current Itb2 is divided into the current Ib2 and the current Ibu2 according to the ratio of the number of the ON MOS switches 311 to the number of the ON MOS switches 312.

<Digital signal waveform>
FIG. 11 is a diagram showing an example of a digital signal waveform. The input clock INCK input to the frequency divider 211 is divided by 1/2 from the digital signal CK1 [0] by the frequency divider 211, and the digital signal CK1 [4: 0] is generated. Of these, the digital signal xCK1 [4] serves as the reference clock for the shift register 213. The value of the shift register 213 changes at the edge of the digital signal xCK1 [4] from low to high. High is input to the first stage of the shift register 213, and the value sequentially transitions from digital signal TH1 [0] to digital signal TH1 [k] at the frequency of the digital signal CK1 [4].

The digital signal xCK2 [0] is controlled to be fixed at Low. The input clock INCK input to the frequency divider 221 is divided by 1/2 from the digital signal xCK2 [1] by the frequency divider 221 to generate the digital signal xCK1 [4: 0]. In this way, the division ratio can be changed more easily by changing the input stages of the system of the digital signal TH1 [k: 0] and the system of the digital signal TH2 [k: 0].

As described above, the digital signal CK2 [4] has twice the frequency of the digital signal CK1 [4]. The digital signal xTH2 [m-1: 0] is fixed to low by the initial setting operation by the reset set of the shift register, and the transition starts from the digital signal xTH2 [m]. When the digital signal xTH2 [k: 0] has a faster operating frequency than the digital signal TH1 [k: 0] as in the example of FIG. 11, the initial setting code of the shift register 223 is the same as the initial setting code T of the shift register 213. Or you can go ahead with the code.

<Shift register>
FIG. 12 is a diagram showing a main configuration example of the shift register 213. The shift register 213 includes flip-flops 331-0 to flip-flops 331-k, and a shift register initial value control signal decoder 332. In the following, when it is not necessary to distinguish the flip-flops 331-0 to the flip-flops 331-k from each other, they are referred to as flip-flops 331.

The flip-flops 331 are connected in (k + 1) permutations. A high signal is input to the D terminal of the first flip-flop. When the control signal xRS is set to low, the holding data of each flip-flop 331 is reset and the Q terminal is set to low. When advancing the initial setting of the shift register 213, the shift register initial value control signal decoder 332 sets the control signal ST [m-1: 0] to High at the same time as or after the timing of being reset by the control signal xRS. ), The digital signal TH1 [m-1: 0] can be set to High. When the clock operation of the digital signal CK1 [4] starts, the data transition of the shift register 213 is started from the digital signal TH [m]. The initial value control signal is decoded by the shift register initial value control signal decoder 332 into a thermometer code whose value is represented by the number of "1".

Each flip-flop 331 has a configuration as shown in FIG. 13, for example. However, the configuration of the flip-flop 331 is arbitrary and is not limited to the example of FIG.

Since the shift register 223 also has the same configuration as the shift register 213 described above and performs the same processing, the description of FIGS. 12 and 13 can be applied to the shift register 223. Therefore, the description of the shift register 223 will be omitted.

<Example of operating waveform of reference signal generator>
14 to 16 show examples of various signal waveforms related to the operation of the reference signal generation unit 163. The initial value code of the shift register 213 is set to 0, and the initial value code of the shift register 223 is set to (m-1). As shown in FIG. 14, the digital signal xCK2 [4] has twice the frequency of the digital signal CK1 [4]. Further, the resistance value R2 of the resistor 209 is twice as large as the resistance value R1 of the resistor 208.

The reference signal generation unit 163 performs processing based on various digital signals having a waveform as shown in FIG. 14, and outputs currents having a waveform as shown in FIG. 15 (current It1, current Ib1, current It2, current Ib2). To generate. As a result, the reference signal 1 and the reference signal 2 having the waveforms shown in FIG. 16 are generated and output from the reference signal generation unit 163. At this time, the relationship between the slope 1 of the reference signal 1 and the slope 2 of the reference signal 2 is [slope of the reference signal 2] = [slope of the reference signal 1] × (-4).

<Example of current value transition>
FIG. 17 shows the transition of the current values of the current It1, the current It2, and the current Itu in the example of FIG. Assuming that the current value per of the NMOS current sources 277 is It, the total current Itt of (k + 1) is Itt = (k + 1) × It. The initial value of the current It2 is set to (m-1) × It. The current Itt is constant with respect to time, and Itt = It1 + It2 + Itu. That is, the predetermined current generated by receiving the gain control signal for controlling the gain is divided into a plurality of output currents and non-output currents according to the value of the input digital signal. Therefore, it is not necessary to provide a slope D / A conversion unit for each gain, and an increase in circuit area and power consumption can be suppressed.

In the case of the example of FIG. 17, the current It2 is decreased as the current It1 is increased in the time direction. In this way, when the current is divided into two systems of output current and one system of non-output current, the first output current is increased and the second output current is decreased in the time direction. You may. In this way, by making the directions of change of each output current opposite to each other, the change in the time direction of the sum of the current It1 and the current It2 can be made smaller, so that the current Itt can be used more effectively. Can be done. Therefore, for example, it is not necessary to make the slopes of the currents It1 and the currents It2 gentle, or to shorten the period during which the reference signal can be used.

Of course, both the first output current and the second output current may be increased (or decreased) in the time direction. That is, the directions of change of each output current may be the same as each other.

In the case of the example of FIG. 7, when the digital signal TH1 [q] and the digital signal xTH2 [q] are set to High at the same time, the NOTES switch (N1) is better than the NOTES switch 272 (N2). Although it is prioritized and turned on (ON), it is not normally used because the slope inclination of the reference signal 2 fluctuates. Therefore, even if the digital signal TH1 [q] and the digital signal xTH2 [q] input to the qth configuration of the slope D / A converter T205 are operated with a constraint that they do not become high at the same time. Good.

<Signal waveform related to A / D conversion>
18 and 19 show examples of waveforms of various signals in the A / D conversion performed by the column A / D conversion unit 162 using the reference signal 1 and the reference signal 2 generated by the reference signal generation unit 163 as described above. Shown.

FIG. 18 is a diagram showing a waveform example of adaptive gain A / D conversion when the pixel signal is small (dark). The column A / D conversion unit 162 performs adaptive gain A / D conversion that can adaptively switch the reference signal to be used based on the magnitude of the pixel signal to be A / D converted.

The pixel reset level is acquired by the reference signal 1 (first P phase) and the reference signal 2 (second P phase), respectively. The vertical signal line signal after the pixel signal transfer is compared with the predetermined determination voltage generated by the set signal of the shift register of the reference signal 1, and when the pixel signal is small, the selector 174 sets the selector 174 as shown in FIG. The D phase is acquired while connected to the reference signal 1. The counter 172 counts from the start of the INCK clock transition to the timing at which the output of the comparison unit 171 transitions from high (High) to low (Low). The determination value latch 173 acquires the count value P1 of the first P phase and holds the count value P1 in its own holding circuit. After that, the determination value latch 173 resets the count value of the counter 172.

Further, the determination value latch 173 acquires the count value P2 of the second P phase. Upon receiving the determination result, the determination value latch 173 reads the count value P1 from the holding circuit, restores it, performs bit inversion, and sets -P1 as the initial value of the counter 172. Then, the determination value latch 173 causes the selector 174 to select the reference signal 1. The counter 172 can acquire the digital CDS D-P1 data by counting the D phase.

FIG. 19 is a diagram showing a waveform example of adaptive gain A / D conversion when the pixel signal is large (bright). Since the pixel signal is smaller than the determination voltage in the determination operation, the determination value latch 173 performs bit inversion and sets -P2 as the initial value of the counter 172. Then, the determination value latch 173 causes the selector 174 to select the reference signal 2. The counter 172 can acquire the digital CDS D-P2 data by counting the D phase.

As described above, the column A / D conversion unit 162 can perform adaptive gain A / D conversion using a plurality of reference signals (reference signal 1 and reference signal 2) generated by the reference signal generation unit 163. .. That is, the column A / D conversion unit 162 can realize more accurate A / D conversion at high speed and with a high dynamic range.

<2. Second Embodiment>
<Multi-slope A / D conversion>
Although the adaptive gain A / D conversion has been described above, the present technology can also be applied to the A / D conversion of other methods. For example, this technique can be applied to an A / D conversion unit that performs multi-slope A / D conversion.

<Column parallel processing unit>
FIG. 20 is a diagram showing another configuration example of the column parallel processing unit 102 to which the present technology is applied. As shown in FIG. 20, the column parallel processing unit 102 in this case replaces the column A / D conversion unit 162-1 to the column A / D conversion unit 162-M, and the column A / D conversion unit 411-1. It also has a column A / D conversion unit 411-M. In the following, when it is not necessary to distinguish and explain the column A / D conversion unit 411-1 to the column A / D conversion unit 411-M, the column A / D conversion unit 411 is referred to as a column A / D conversion unit 411.

The column A / D conversion unit 411 A / D-converts the analog signal to be A / D-converted using each of the plurality of reference signals, and based on the A / D conversion result (digital data), either one of them. Select the A / D conversion result Perform multi-slope A / D conversion.

As shown in FIG. 20, the column A / D converter 411 includes a comparison unit 421, a counter 422, a capacitor 423, and a capacitor 424, and a comparison unit 431, a counter 432, a capacitor 433, and a capacitor 434.

The comparison unit 421 to the capacitor 424 are configured with respect to the reference signal 1. One input terminal of the comparison unit 421 is connected to the reference signal line 164-1 via a capacitor 423. Further, the other input terminal of the comparison unit 421 is connected to the vertical signal line 122 via the capacitor 424. Further, the output terminal of the comparison unit 421 is connected to the counter 422.

The reference signal 1 is input to one input terminal of the comparison unit 421 connected to the capacitor 423 via the capacitor 423. Further, an analog signal (for example, a pixel signal or the like) read from the unit pixel 121 of the pixel array 101 is input to the other input terminal of the comparison unit 421 to which the capacitor 424 is connected. The comparison unit 421 compares the magnitudes of these signals and supplies information indicating which signal has the higher signal level to the counter 422 as a comparison result.

The input terminal of the counter 422 is connected to the output terminal of the comparison unit 421, and the comparison result is supplied from the comparison unit 421. The counter 422 measures the time from the start of counting until the comparison result is inverted (the signal level of the output signal of the comparison unit 421 changes) (for example, counting the number of clocks of a predetermined clock signal).

Capacitor 423 and capacitor 424 are capacitive elements for analog CDS that cancel analog element variation.

The comparison unit 431 to the capacitor 434 are configured with respect to the reference signal 2. One input terminal of the comparison unit 431 is connected to the reference signal line 164-2 via the capacitor 433. Further, the other input terminal of the comparison unit 431 is connected to the vertical signal line 122 via the capacitor 434. Further, the output terminal of the comparison unit 431 is connected to the counter 432.

The reference signal 2 is input to one input terminal of the comparison unit 431 connected to the capacitor 433 via the capacitor 433. Further, an analog signal (for example, a pixel signal or the like) read from the unit pixel 121 of the pixel array 101 is input to the other input terminal of the comparison unit 431 to which the capacitor 434 is connected. The comparison unit 431 compares the magnitudes of these signals and supplies information indicating which signal has the higher signal level to the counter 432 as a comparison result.

The input terminal of the counter 432 is connected to the output terminal of the comparison unit 431, and the comparison result is supplied from the comparison unit 431. The counter 432 measures the time from the start of counting until the comparison result is inverted (the signal level of the output signal of the comparison unit 431 changes) (for example, counting the number of clocks of a predetermined clock signal).

Capacitor 433 and capacitor 434 are capacitive elements for analog CDS that cancel analog element variation.

As described above, in the case of multi-slope A / D conversion, a plurality of reference signals (analog signals) are used by different A / D conversion units.

FIG. 21 is a diagram showing an example of an operation waveform in the case of this multi-slope A / D conversion. In the case of multi-slope A / D conversion, unlike the case of the adaptive gain A / D conversion described above, A / D conversion in parallel is possible, so the P phase and D phase need only be performed once. The slope of the reference signal 1 is gentle and the voltage range is small, and a count value (D-P1) can be obtained by the comparison unit 421 and the counter 422. The slope of the reference signal 2 is steep, but the voltage range is large, and a count value (D-P2) can be obtained by the comparison unit 431 and the counter 432. Since the reference signal 1 and the reference signal 2 have different inclination signs, the counter 432 reverses the count value (D-P2) positively and negatively and adds the offset value Y to obtain (P2-D + Y).

Y is determined so that P2-D + Y = 0 when the pixel signal in a completely shielded state is acquired. By selecting (D-P1) when P2-D + Y is smaller than the predetermined code and selecting (P2-D + Y) when it is larger than the predetermined code, A in the dark place without sacrificing the dynamic range or frame rate. / D resolution can be improved. Further, in the mode in which the A / D conversion is performed so that the inclination ratio of the reference signal 1 and the reference signal 2 becomes -1, there is an effect of improving random noise by the multiple A / D conversion. By taking the averaging by the calculation of ((D-P1) + (D-P2 + Y)) / 2, the random noise of the pixel is improved by 1 / √2 times in terms of voltage.

As described above, this technique can be applied to multi-slope A / D conversion, and by applying this technique, the same effect as in the case of adaptive gain A / D conversion can be obtained.

<3. Third Embodiment>
<Number of output analog signal systems>
In the above, the case of generating two analog signals (reference signals) has been described, but the present technology can also be applied to the case of generating three or more analog signals. That is, this technique can be applied when generating analog signals of a plurality of systems.

<Reference signal generator>
FIG. 22 is a diagram showing another configuration example of the reference signal generation unit 163 to which the present technology is applied. In this case, the reference signal generation unit 163 outputs three reference signals (reference signal 1 to reference signal 3). The reference signal 1 is output from the reference signal line 164-1. The reference signal 2 is output from the reference signal line 164-2. The reference signal 3 is output from the reference signal line 164-3.

In this case as well, since the gain control unit 233 has the same configuration as in the case of FIG. 4, the illustration thereof is omitted in FIG. 22. The reference signal generation unit 163 in this case has a slope D / A conversion unit T505 instead of the slope D / A conversion unit T205. Further, the reference signal generation unit 163 in this case further includes a slope D / A conversion unit B518 in addition to the slope D / A conversion unit B206 and the slope D / A conversion unit B207. Further, the reference signal generation unit 163 in this case has a resistor 520 having a resistance value of R3 in addition to the resistor 208 and the resistor 209.

Further, the reference signal generation unit 163 in this case has a frequency divider 531, a NOT gate 532, and a shift register 533 in addition to the frequency divider 211 to the shift register 213 and the frequency divider 221 to the NOT gate 225.

That is, since the reference signal generation unit 163 in this case has three analog signal output systems (reference signal lines 164) (three lines), each processing unit also corresponds to the analog signal output system (reference signal line 164).

The slope D / A converter 505 generates a current Itt according to the bias voltage Vpg, and uses the current Itt as a digital signal TH1 [k: 0], a digital signal xTH2 [k: 0], and a digital signal TH3 [k]. It is divided into current It1, current It2, current It3, and current Itu at a ratio according to the value of: 0]. In the slope D / A converter T505, (k + 1) current Itts are generated in parallel according to the bias voltage Vpg and the current Itt is assigned to any of the current It1, the current It2, the current It3, and the current Itu. is set up. k is an arbitrary natural number. That is, the number of this configuration is arbitrary. These (k + 1) configurations correspond to the values corresponding to themselves in the digital signal TH1 [k: 0], the digital signal xTH2 [k: 0], and the digital signal TH3 [k: 0], respectively. By allocating the current Itt, as a whole, the current Itt according to the bias voltage Vpg becomes the digital signal TH1 [k: 0], the digital signal xTH2 [k: 0], and the digital signal TH3 [k: 0]. It is divided into current It1, current It2, current It3, and current Itu at a ratio according to the value. In other words, Itt = It1 + It2 + It3 + Itu regardless of the values of the digital signal TH1 [k: 0], the digital signal xTH2 [k: 0], and the digital signal TH3 [k: 0].

A resistor 520 having a resistance value R3 and a reference signal line 164-3 are connected to the signal line through which the current It3 flows. The current It3 is converted into a voltage by the resistor 520 and is converted into a voltage as an analog signal (reference signal 3). It is output from line 164-3.

That is, the current It1, the current It2, and the current It3 are output currents that are output, and the current Itu is a non-output current (also referred to as a discard current) that is not output. That is, the slope D / A conversion unit T505 generates a predetermined current Itt according to the bias voltage Vpg, and uses the current Itt as the digital signal TH1 [k: 0], the digital signal xTH2 [k: 0], and the digital. It is divided into three output currents (current It1, current It2, current It3) and non-output current (current Itu) at a ratio according to the value of the signal TH3 [k: 0]. Then, the output currents of the three systems are converted into a voltage and output as analog signals of the three systems (reference signal 1, reference signal 2, reference signal 3).

The slope D / A conversion unit B518 (slope D / A conversion unit B3) is a binary code current source for the reference signal 3. The slope D / A conversion unit B518 generates a current Itb3 according to the bias voltage Vpg, and divides the current Itb3 into a current Ib3 and a current Ibu3 at a ratio corresponding to the value of the digital signal CK3 [4: 0]. To do. The slope D / A conversion unit B518 controls, for example, the lower bits of the signal level of the reference signal 3 by the current Ib3. In the slope D / A conversion unit B518, five configurations are installed in parallel to generate the current Itb3 according to the bias voltage Vpg and allocate the current Itb3 to the current Ib3 or the current Ibu3. Each of these five configurations allocates the current Itb3 according to the value corresponding to itself in the digital signal CK3 [4: 0], so that the current Itb3 corresponding to the bias voltage Vpg is generated as a whole. , The current Ib3 and the current Ibu3 are divided at a ratio according to the value of the digital signal CK3 [4: 0]. In other words, Itb3 = Ib3 + Ibu3 regardless of the value of the digital signal CK3 [4: 0]. In this case, the slope D / A conversion unit B518 controls, for example, the lower 5 bits of the signal level of the reference signal 3.

The current Ib3 is converted into a voltage by the resistor 520 and output as an analog signal (reference signal 3) from the reference signal line 164-3. The voltage of the reference signal 3 is AVD− (It3 + Ib3) × R3. The signal line through which the current Ibu3 flows is connected to the power supply potential AVD (for example, 3.3V).

That is, the current Ib3 is the output current that is output, and the current Ibu3 is the non-output current that is not output (also referred to as the discarded current). That is, the slope D / A conversion unit B518 generates a predetermined current Itb3 according to the bias voltage Vpg, and uses the current Itb3 as a single output current at a ratio corresponding to the value of the digital signal CK3 [4: 0]. It is divided into (current Ib3) and non-output current (current Ibu3). Then, this singular output current (current Ib3) is converted into a voltage and output as an analog signal (reference signal 3). That is, the slope D / A conversion unit B518 uses this singular output current (current Ib3) to control the signal level of the analog signal (reference signal 3) output from the slope D / A conversion unit T505.

The number of parallels of the slope D / A conversion unit B518 is arbitrary and may be other than five. Further, since the configuration of the slope D / A conversion unit B518 is the same as that of the slope D / A conversion unit B206 and the slope D / A conversion unit B207, the description thereof will be omitted.

The resistor 520 is a resistor having a resistance value of R3, one end of which is connected to the power supply potential AVD and the other end of which is connected to the signal line through which the current It3 flows and the reference signal line 164-3 through which the reference signal 3 flows. .. That is, the resistor 520 converts the current It3 and the current Ib3 into a voltage. The resistance value R3 of the resistor 520 may be different from the resistance value R1 of the resistor 208 and the resistance value R2 of the resistor 209.

The frequency divider 531 divides the input clock INCK and generates a digital signal CK3 [4: 0]. By setting the frequency division ratio of the frequency divider 531 to a value different from the frequency division ratio of the frequency divider 211 and the frequency divider 221, the digital signal CK3 [4] can be changed to the digital signal CK1 [4] or the digital signal CK2 [ The frequency can be different from 4]. The NOT gate 532 inverts the digital signal CK3 [4] and generates the digital signal xCK3 [4]. The shift register 533 generates a digital signal TH3 [k: 0] using the digital signal xCK3 [4]. The shift register 533 supplies the digital signal TH3 [k: 0] to the slope D / A conversion unit T505. Further, the frequency divider 531 supplies the generated digital signal CK3 [4: 0] to the slope D / A conversion unit B518 (slope D / A conversion unit B3).

In this case as well, the frequency of the digital signal xCK2 [4] is twice that of the digital signal xCK1 [4], as in the example of FIG. 11, but since the transition of the digital signal xCK2 [4] is fast, the digital signal xCK3 [4] 4] needs to be set to the same or slower frequency as the digital signal xCK1 [4]. Here, the frequency of the digital signal xCK3 [4] is 1/2 times that of the digital signal xCK1 [4].

As shown by the dotted line in FIG. 22, a resistor 208, a resistor 209, and a resistor 520 may be added to the slope D / A conversion unit T505 to form the slope D / A conversion unit T541. The slope D / A conversion unit T541 D / A-converts the digital signal TH1 [k: 0], the digital signal xTH2 [k: 0], and the digital signal TH3 [k: 0], and uses the reference signal 1 as an analog signal. -The reference signal 3 can be output. Further, as shown by the dotted line in FIG. 22, the slope D / A conversion unit B206, the slope D / A conversion unit B207, and the slope D / A conversion unit B518 are added to the configuration of the slope D / A conversion unit T541. , The slope D / A conversion unit 542 may be used. The slope D / A conversion unit 542 uses digital signal TH1 [k: 0], digital signal xTH2 [k: 0], digital signal TH3 [k: 0], digital signal CK1 [4: 0], and digital signal xCK2 [4]. 0], the digital signal CK3 [4: 0] is D / A converted, and the reference signal 1 to the reference signal 3 including the lower bits can be output as an analog signal.

As shown by the dotted line in FIG. 22, the frequency divider 211, the NOT gate 212, the shift register 213, the frequency divider 221 and the NOT gate 222, the shift register 223, the NOT gate 224, the NOT gate 225, and the frequency divider 531 , NOT gate 532 and shift register 533 may be collectively used as a digital signal generation unit 544. The digital signal generation unit 544 uses the input clock INCK to digital signal TH1 [k: 0], digital signal xTH2 [k: 0], digital signal TH3 [k: 0], digital signal CK1 [4: 0], A digital signal xCK2 [4: 0] and a digital signal CK3 [4: 0] are generated and supplied to the slope D / A conversion unit 542.

<Slope D / A conversion unit T>
FIG. 23 is a diagram showing a main configuration example of the slope D / A conversion unit T505. In FIG. 23, only one of the (k + 1) configurations of the slope D / A conversion unit T505 arranged in parallel is shown. Since the other k configurations are the same as the configurations shown in FIG. 23, the description thereof will be omitted.

As shown in FIG. 23, the slope D / A conversion unit T505 further includes an MIMO switch 551 in addition to the MIMO switch 271, the MIMO switch 272, and the MIMO switch 273. Further, the slope D / A conversion unit T505 has a NOT gate 561, a NOR gate 562, a NOT gate 563, a NOR gate 564, a NOR gate 565, and an MIMO current source 277 (NMOS current source T).

The NMOS switches 271 to 273, as well as the MIMO switch 551, control the path of the current Itt. The NMOS switch 551 controls the connection between the MIMO current source 277 and the resistor 520. That is, the MIMO switch 551 controls whether or not the current Itt is set to the current It3.

Any one of the NMOS switches 271 to 273 and the NMOS switch 551 is turned on by the digital signal TH1 [k: 0], the digital signal xTH2 [k: 0], and the digital signal TH3 [k: 0]. Is controlled to be.

The digital signal TH1 [k: 0] supplied from the shift register 213 is supplied to the NOT gate 561, the NOR gate 564, and the NOR gate 565. Further, the digital signal xTH2 [k: 0] supplied from the NOT gate 224 is supplied to the NOT gate 563 and the NOR gate 565. Further, the digital signal TH3 [k: 0] supplied from the shift register 533 is supplied to the NOR gate 562, the NOR gate 564, the gate of the MIMO switch 551, and the NOR gate 565.

For example, when the digital signal TH3 [k: 0] is "1", the MIMO switch 551 is turned on, and the MIMO switch 271, the MIMO switch 272, and the MIMO switch 273 are turned off. Further, for example, when the digital signal TH3 [k: 0] is "0", the MIMO switch 551 is turned off. At this time, if the digital signal xTH2 [k: 0] is "1", the MIMO switch 272 is turned on, and the MIMO switch 271 and the MIMO switch 273 are turned off. On the contrary, when the digital signal xTH2 [k: 0] is "0", the MIMO switch 272 is turned off, and the MIMO switch 271 and the MIMO switch 273 are turned on. At this time, if the digital signal TH1 [k: 0] is "1", the MIMO switch 271 is turned on and the MIMO switch 273 is turned off. On the contrary, when the digital signal TH1 [k: 0] is "0", the MIMO switch 271 is turned off and the MIMO switch 273 is turned on.

By doing so, the current Itt is either current It1, current It2, current It3, or current Itu. That is, the MIMO switches 271 to 273, and the MIMO switch 551 select whether the current Itt is the current Itt1, the current It2, the current It3, or the current Itu.

As shown by the dotted line in FIG. 23, the MIMO switches 271 to 273 and the MIMO switch 551 may be collectively referred to as the switch 581. That is, the switch 581 drives a digital signal TH1 [k: 0], a digital signal xTH2 [k: 0], and a digital signal TH3 [k: 0] as control signals, and a plurality of output signal lines to which an analog signal is output. Each signal line connected to each of (reference signal line 164-1 to reference signal line 164-1), a signal line connected to a voltage source (power supply potential AVD), and a current source (NMOS current source 277). It has a switch that controls the connection with. The configuration of the switch 581 is arbitrary as long as the current Itt can be selected from the current It1, the current It2, the current It3, and the current Itu, and is limited to the above configuration example. Not done.

Further, as shown by a dotted line in FIG. 23, a NOT gate 561, a NOR gate 562, a NOT gate 563, a NOR gate 564, and a NOR gate 565 are further added to the configuration of the switch 581 to form a D / A conversion unit 582. May be good. The D / A converter 582 outputs the current It1, the current It2, and the current It3 according to the digital signal TH1 [k: 0], the digital signal xTH2 [k: 0], and the digital signal TH3 [k: 0]. Can be done.

As described above, the slope D / A conversion unit T505 has (k + 1) configurations as shown in FIG. 23, and they are arranged in parallel. The NMOS current sources 277 of each configuration have the same size (W length, L length, number of parallels, etc.) and pass equal currents. In each of the (k + 1) such configurations arranged in parallel, a path through which the current generated by the MIMO current source 277 flows is selected. Therefore, in the entire slope D / A converter T505, the current Itt generated by the MIMO current source 277 is divided into the current It1, the current It2, the current It3, and the current Itu according to the ratio of this selection. That is, the number of switches 581 in which the MIMO current source 277 is connected to the signal line through which the current It1 is passed, the number of switches 581 in which the MIMO current source 277 is connected to the signal line in which the current It2 is passed, and the current It3 The current Itt is current Itt1, current It2, current It3, current according to the ratio of the number of switches 581 connected to the signal line through which the current is flowing and the number of switches 581 connected to the signal line through which the current Itu is passed. Divided into Itu. In other words, the current Itt is the current It1 depending on the ratio of the number of on-state MIMO switches 271, the number of on-state MIMO switches 272, the number of on-state MIMO switches 551, and the number of on-state MIMO switches 273. , Current It2, Current It3, Current Itu.

Therefore, the slope D / A conversion unit T505 can suppress an increase in circuit area and power consumption.

Also in this case, the slope D / A conversion unit T205 recursively repeats the division of the current (non-output current) into the output current and the non-output current. By doing so, the slope D / A conversion unit T505 can more easily divide the current generated by receiving the gain control signal into a plurality of output currents and a non-output current.

<Example of current value transition>
FIG. 24 shows an example of the transition of the current values of the current It1, the current It2, the current It3, and the current Itu in this case. Assuming that the current value per of the NMOS current sources 277 is It, the total current Itt of (k + 1) is Itt = (k + 1) × It. The initial value of the current It1 is set to (p-1) × It, and the initial value of the current It2 is set to (m-1) × It. The current Itt is constant with respect to time, and Itt = It1 + It2 + It3 + Itu. During the A / D conversion period, the initial value is set so that the digital signal TH1 [q] does not overtake the digital signal TH3 [q], and the digital signal TH1 [q] is initially set so that the digital signal xTH2 [q] does not overtake. Set the value.

When the ratio of the resistance value R1 of the resistor 208, the resistance value R2 of the resistor 209, and the resistance value R3 of the resistor 520 is R1: R2: R3 = 2: 4: 1, the respective slopes of the reference signal 1 to the reference signal 3 are obtained. The tilt ratio of is 4: -16: 1.

As described above, even when there are three or more analog signals to be output, the predetermined current generated by receiving the gain control signal that controls the gain is a plurality of output currents according to the value of the input digital signal. And is divided into non-output current. Therefore, it is not necessary to provide a slope D / A conversion unit for each gain, and an increase in circuit area and power consumption can be suppressed.

<4. Others>
<Column A / D conversion>
In the above, it has been described that the column A / D conversion unit 162 is provided for each column of the pixel array 101, but the number of columns A / D conversion unit 162 is arbitrary and is based on the number of columns of the pixel array 101. It may be more or less. For example, the column A / D conversion unit 162 may be provided for each of a plurality of columns, or the analog signal of one column may be A / D converted by the plurality of column A / D conversion units 162. Good.

<Area A / D conversion>
Further, in the above description, the analog signal read from each unit pixel is A / D converted by the column A / D conversion unit 162 (that is, for each column), but the A / D conversion unit The configuration is not limited to this. For example, in the pixel array 101, a pixel unit is formed for each of a predetermined number of unit pixels 121, and an A / D conversion unit (also referred to as an area A / D conversion unit) is provided for each pixel unit, and each unit pixel. The analog signal read from is A / D converted by this area A / D converter (that is, for each pixel unit).

The pixel unit is a unit pixel group composed of a plurality of unit pixels (for example, Y rows and X columns (X and Y are arbitrary natural numbers)). The pixel unit is formed in the entire pixel array 101, and each unit pixel 121 belongs to any of the pixel units. That is, the pixel unit is a unit pixel group included in a partial region for dividing the pixel region composed of the pixel array 101 into a plurality of pixels. The size (number of unit pixels 121 included in the pixel unit) and shape of the pixel unit are arbitrary. The size (number of unit pixels 121) and shape of each pixel unit do not have to be the same.

The analog signal (for example, a pixel signal) read from each unit pixel is supplied to the area A / D conversion unit via a signal line provided for each pixel unit. Similar to the column A / D conversion unit 162 and the column A / D conversion unit 411 described above, the area A / D conversion unit uses a plurality of reference signals generated by the reference signal generation unit 163 from each unit pixel. The read analog signal is A / D converted for each pixel unit.

Even in such a case, the reference signal generation unit 163 may have a configuration as described in each of the above-described embodiments. That is, the present technology can be applied even when A / D conversion is performed for each pixel unit, and the same effect as in the case of each of the above-described embodiments can be obtained.

<Other signals>
The present technology can also be applied to, for example, a case where analog signals read from all unit pixels of the pixel array 101 are A / D converted by one A / D conversion unit. That is, the present technology can be applied to any reference signal generator that generates reference signals of a plurality of systems, regardless of which A / D converter uses the reference signals of the plurality of systems. Good.

Further, the reference signal generated by applying this technology can be used for A / D conversion of an arbitrary signal, for example, for A / D conversion of a signal other than an analog signal read from a unit pixel. It may be used. That is, the present technology can be applied not only to an image sensor but also to any device. Further, the signal generated by applying the present technology does not have to be the reference signal used by the A / D converter. That is, the present technology can be applied when generating arbitrary signals of a plurality of systems.

<Multi-layer structure>
Further, the circuit configuration of the image sensor 100 may be formed on a single semiconductor substrate or may be formed on a plurality of semiconductor substrates. For example, the image sensor 100 has a semiconductor substrate having a multilayer structure in which a plurality of semiconductor substrates are superimposed on each other, and the circuit configuration of the image sensor 100 shown in FIG. 1 or the like is formed on those semiconductor substrates. May be good. For example, even if the pixel array 101 is formed on the first semiconductor substrate and the column parallel processing unit 102 (column A / D conversion unit 162, reference signal generation unit 163, etc.) is formed on the second semiconductor substrate. Good. The number of semiconductor substrates, the shape and size of each semiconductor substrate, which configuration is formed on which semiconductor substrate, and the like are arbitrary.

<Imaging device>
This technology can be applied to any system, device, processing unit, etc. For example, the present technology may be applied to an image pickup apparatus using an image pickup device. FIG. 25 is a block diagram showing a main configuration example of an image pickup apparatus as an example of an electronic device to which the present technology is applied. The image pickup device 600 shown in FIG. 25 is a device that takes an image of a subject and outputs a moving image or a still image of the subject as image data.

As shown in FIG. 25, the image pickup apparatus 600 includes an optical unit 611, a CMOS image sensor 612, an image processing unit 613, a display unit 614, a codec processing unit 615, a storage unit 616, an output unit 617, a communication unit 618, and a control unit 621. , An operating unit 622, and a drive 623.

The optical unit 611 performs processing related to optics at the time of imaging. For example, the optical unit 611 includes a lens that adjusts the focus to the subject and collects light from the focused position, an aperture that adjusts the exposure, a shutter that controls the timing of imaging, and the like. The image of the subject by the CMOS image sensor 612 is performed via the optical unit 611. That is, the light from the subject (incident light) is supplied to the CMOS image sensor 612 via the optical unit 611.

The CMOS image sensor 612 is an image pickup device, and performs processing related to imaging a subject. For example, the CMOS image sensor 612 receives light from a subject, photoelectrically converts it, generates an analog signal (pixel signal) for each pixel, and A / D-converts it to digital data (image data). Can be generated. Further, the CMOS image sensor 612 can perform signal processing such as CDS (Correlated Double Sampling) on the image data, and supply the processed image data to the image processing unit 613.

The image processing unit 613 performs processing related to image processing on the image data. For example, the image processing unit 613 can perform image processing on the image data. The content of this image processing is arbitrary. For example, the image processing unit 613 can perform color mixing correction, black level correction, white balance adjustment, demosaic processing, matrix processing, gamma correction, YC conversion, and the like. Further, for example, the image processing unit 613 can supply the image data to the display unit 614 and the codec processing unit 615. Further, for example, the image processing unit 613 can also acquire image data from the codec processing unit 615. For example, the image processing unit 613 can perform predetermined image processing on the image data obtained by the CMOS image sensor 612, and supply the image data after the image processing to the display unit 614 and the codec processing unit 615. .. Further, for example, the image processing unit 613 performs predetermined image processing on the image data supplied from the codec processing unit 615, and supplies the image data after the image processing to the display unit 614 and the codec processing unit 615. Can be done.

The display unit 614 has, for example, a liquid crystal display or the like, and performs processing related to displaying an image. For example, the display unit 614 can display an image of image data (for example, an image of a subject) supplied from the image processing unit 613.

The codec processing unit 615 performs processing related to coding / decoding of image data. For example, the codec processing unit 615 can encode the image data and generate the encoded data. For example, the codec processing unit 615 can acquire image data from the image processing unit 613, the storage unit 616, the communication unit 618, and the like, encode the image data, and generate the coded data. Further, for example, the codec processing unit 615 can decode the coded data and generate image data of the decoded image. For example, the codec processing unit 615 can acquire coded data from a storage unit 616, a communication unit 618, or the like, decode it, and generate image data of a decoded image. Further, for example, the codec processing unit 615 can supply image data and coded data to the image processing unit 613, the storage unit 616, the output unit 617, the communication unit 618, and the like.

The storage unit 616 has, for example, a hard disk, a semiconductor memory, or the like, and performs processing related to storage of encoded data and image data. For example, the storage unit 616 can store coded data, image data, and the like supplied from the codec processing unit 615. Further, for example, the storage unit 616 can read the stored coded data or image data at a predetermined timing or in response to a request from the codec processing unit 615 or the like and supply the stored coded data or image data to the codec processing unit 615.

The output unit 617 has an external output interface such as an external output terminal, and performs processing related to output of image data and coded data. For example, the output unit 617 can output the image data and the coded data supplied from the codec processing unit 615 to the outside of the image pickup apparatus 600 (for example, another apparatus, removable media, etc.).

The communication unit 618 has a communication interface of a predetermined communication standard, and performs processing related to transmission / reception of data with another device. For example, the communication unit 618 may supply various information such as image data and coded data supplied from the codec processing unit 615 to another device which is a communication partner of a predetermined communication (wired communication or wireless communication). it can. Further, for example, the communication unit 618 acquires various information such as image data and coded data from another device which is a communication partner of a predetermined communication (wired communication or wireless communication), and transfers the information to the codec processing unit 615. Can be supplied.

The control unit 621 controls the operation of each processing unit (each processing unit shown in the dotted line 620, the operation unit 622, and the drive 623) of the image pickup apparatus 600.

The operation unit 622 is composed of, for example, an arbitrary input device such as a jog dial (trademark), keys, buttons, or a touch panel, receives an operation input by a user or the like, and supplies a signal corresponding to the operation input to the control unit 621. To do.

The drive 623 reads out the information stored in the removable media 624 mounted on the drive 623, for example, a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory. The drive 623 reads various information such as programs and data from the removable media 624 and supplies the information to the control unit 621. Further, when the writable removable media 624 is attached to the drive 623, the drive 623 stores various information such as image data and coded data supplied via the control unit 621 in the removable media 624. be able to.

As the CMOS image sensor 612 of the image pickup apparatus 600 as described above, the above-described technology may be applied in each embodiment. That is, the image sensor 100 described above may be applied as the CMOS image sensor 612. As a result, the CMOS image sensor 612 can obtain the same effect as the image sensor 100. Therefore, the image pickup apparatus 600 can also obtain the same effect.

<Applicable fields of this technology>
Systems, devices, processing units, etc. to which this technology is applied can be used in any field such as transportation, medical care, crime prevention, agriculture, livestock industry, mining, beauty, factories, home appliances, weather, nature monitoring, etc. ..

For example, the present technology can be applied to systems and devices used for viewing images. In addition, for example, the present technology can be applied to systems and devices used for transportation. Further, for example, the present technology can be applied to systems and devices used for security purposes. In addition, for example, the present technology can be applied to systems and devices used for sports. Further, for example, the present technology can be applied to systems and devices used for agriculture. In addition, for example, the present technology can be applied to systems and devices used in the livestock industry. Further, for example, the present technology can be applied to systems and devices for monitoring natural conditions such as volcanoes, forests, and oceans. In addition, this technology can be applied to systems and devices used for meteorological observation. Furthermore, this technology can be applied to systems and devices for observing the ecology of wildlife such as birds, fish, reptiles, amphibians, mammals, insects, and plants.

<Others>
The embodiment of the present technology is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present technology.

For example, in the present specification, the system means a set of a plurality of components (devices, modules (parts), etc.), and it does not matter whether all the components are in the same housing. Therefore, a plurality of devices housed in separate housings and connected via a network, and a device in which a plurality of modules are housed in one housing are both systems. ..

Further, for example, the configuration described as one device (or processing unit) may be divided and configured as a plurality of devices (or processing units). On the contrary, the configurations described above as a plurality of devices (or processing units) may be collectively configured as one device (or processing unit). Further, of course, a configuration other than the above may be added to the configuration of each device (or each processing unit). Further, if the configuration and operation of the entire system are substantially the same, a part of the configuration of one device (or processing unit) may be included in the configuration of another device (or other processing unit). ..

It should be noted that the present techniques described in the present specification can be independently implemented independently as long as there is no contradiction. Of course, any plurality of the present technologies can be used in combination. For example, the present technology described in any of the embodiments can be implemented in combination with the present technology described in the other embodiments. In addition, any of the above-mentioned techniques can be carried out in combination with other techniques not described above.

The present technology can also have the following configurations.
(1) A D / A conversion unit that converts a digital signal into an analog signal, and a plurality of predetermined currents generated in response to a gain control signal that controls gain, depending on the value of the input digital signal. A signal processing device including a first D / A conversion unit that divides into an output current and a non-output current and outputs the plurality of output currents as a plurality of analog signals.
(2) The first D / A conversion unit divides the current into a first output current and a first non-output current according to the value of the digital signal, and divides the first non-output current into the first non-output current. The signal processing device according to (1), wherein the second output current and the second non-output current are divided according to the value of the digital signal, and the first output current and the second output current are output, respectively.
(3) The signal according to (1) or (2), wherein the value of the digital signal changes in the time direction so as to increase the first output current and decrease the second output current. Processing equipment.
(4) The signal processing apparatus according to any one of (1) to (3), wherein the value of the digital signal changes in the time direction so as to increase the first output current and the second output current. ..
(5) The signal processing apparatus according to any one of (1) to (4), further comprising a current source that receives the gain control signal and generates the current.
(6) The first D / A conversion unit drives the digital signal as a control signal, and connects to each signal line connected to each of a plurality of output terminals to which the analog signal is output, and a voltage source. The signal processing apparatus according to any one of (1) to (5), which has a switch for controlling the connection between the connected signal line and the current source.
(7) The first D / A conversion unit has a plurality of the switches configured in parallel, and the current corresponds to the ratio of the number of the switches connecting each signal line and the current source. The signal processing apparatus according to any one of (1) to (6).
(8) The signal processing apparatus according to any one of (1) to (7), further comprising a resistor for converting the output current into a voltage for each of the plurality of output currents.
(9) The signal processing apparatus according to any one of (1) to (8), wherein the resistance values of the resistors corresponding to each output current are different from each other.
(10) A conversion unit that converts a digital signal into an analog signal, and a predetermined current generated by receiving a gain control signal that controls the gain is a single output current according to the value of the input digital signal. A second D / A conversion unit is further provided, which is divided into a non-output current and the output current is used to control the signal level of the analog signal output from the first D / A conversion unit (1). The signal processing apparatus according to any one of (9) to (9).
(11) The signal processing apparatus according to any one of (1) to (10), further comprising a gain control unit that generates the gain control signal, supplies the gain control signal to the first D / A conversion unit, and controls the gain. ..
(12) The signal processing device according to any one of (1) to (11), further comprising a digital signal generation unit that generates the digital signal and supplies the digital signal to the first D / A conversion unit.
(13) An A / D conversion unit that converts an analog signal into a digital signal by using the plurality of analog signals output from the first D / A conversion unit as a reference signal is further provided (1) to (1) to ( 12) The signal processing apparatus according to any one of.
(14) The A / D conversion unit is configured to be configured to be able to adaptively switch the gain by using the plurality of analog signals as reference signals (1) to (13). The signal processing device described.
(15) The signal processing device according to any one of (1) to (14), wherein the plurality of analog signals are used by the A / D converters that are different from each other.
(16) The A / D conversion unit is provided for each column of the pixel array in which a plurality of unit pixels are arranged in a matrix, and a pixel signal read from each pixel of the column corresponding to itself is converted into an analog signal. The signal processing apparatus according to any one of (1) to (15).
(17) The A / D conversion unit is provided for each area of the pixel array in which a plurality of unit pixels are arranged in a matrix, and a pixel signal read from each pixel in the area corresponding to itself is converted into an analog signal. The signal processing apparatus according to any one of (1) to (16).
(18) A predetermined current generated by receiving a gain control signal for controlling gain is divided into a plurality of output currents and a non-output current according to the value of the input digital signal, and the plurality of output currents are divided into a plurality of output currents. A signal processing method that outputs as an analog signal of.
(19) A pixel array in which a plurality of unit pixels are arranged in a matrix and
It is a D / A converter that converts a digital signal into an analog signal, and a predetermined current generated by receiving a gain control signal that controls the gain is subjected to a plurality of output currents and a plurality of output currents according to the value of the input digital signal. A D / A converter that divides into non-output currents and outputs the plurality of output currents as a plurality of analog signals.
An A / D conversion unit that converts a pixel signal read from the pixel array, which is an analog signal, into a digital signal by using the plurality of analog signals output from the D / A conversion unit as reference signals. An image pickup element to be provided.
(20) An imaging unit that captures the subject and
It is provided with an image processing unit that processes image data obtained by imaging by the imaging unit.
The imaging unit
A pixel array in which multiple unit pixels are arranged in a matrix, and
It is a D / A converter that converts a digital signal into an analog signal, and a predetermined current generated by receiving a gain control signal that controls the gain is subjected to a plurality of output currents and a plurality of output currents according to the value of the input digital signal. A D / A converter that divides into non-output currents and outputs the plurality of output currents as a plurality of analog signals.
An A / D conversion unit that converts a pixel signal read from the pixel array, which is an analog signal, into a digital signal by using the plurality of analog signals output from the D / A conversion unit as reference signals. Electronic equipment to be equipped.

100 image sensor, 101 pixel array, 102 column parallel processing unit, 103 bus, 104 output terminal, 111 system control unit, 112 line scanning unit, 113 column scanning unit, 121 unit pixel, 122 vertical signal line, 123 signal line, 124 And 125 control lines, 131 to 133 control lines, 151 photodiodes, 152 transfer transistors, 153 reset transistors, 154 amplification transistors, 155 selection transistors, 156 floating diffusion, 161 bias circuits, 162 column A / D converters, 163 reference signals. Generation unit, 164 reference signal line, 171 comparison unit, 172 counter, 173 judgment value latch, 174 selector, 175 and 176 transistors, 201 constant voltage generation unit, 202 gain control decoder, 203 gain control D / A conversion unit, 204 current Mirror, 205 Slope D / A converter T, 206 and 207 Slope D / A converter B, 208 and 209 gains, 211 divider, 212 NOT gate, 213 shift register, 221 divider, 222 NOT gate, 223 Shift register, 224 and 225 NOT gate, 231 slope D / A conversion unit T, 232 slope D / A conversion unit, 233 gain control unit, 234 digital signal generation unit, 251 facsimile current source, 252 facsimile switch, 253 facsimile switch, 254 NOT gates, 261 N MOSFETs, 271 to 273 NMOS switches, 274 NOT gates, 275 and 276 NOR gates, 277 javax current sources, 281 switches, 282 D / A converters, 301 and 302 NMOS switches, 303 NOT gates, 304 NMOS Current source, 311 and 312 NMOS switches, 313 NOT gate, 314 javax current source, 331 flip flop, 332 shift register first Period value control signal decoder, 411 column A / D conversion unit, 421 comparison unit, 422 counter, 423 and 424 capacitors, 431 comparison unit, 432 counter, 433 and 434 capacitors, 505 slope D / A conversion unit T, 518 slope D / A converter B, 520 resistor, 531 divider, 532 NOT gate, 533 shift counter, 541 slope D / A converter T, 542 slope D / A converter, 544 digital signal generator, 551 NMOS switch, 561 NOT gate, 562 NOR gate, 563 NOT gate, 564 NOR gate, 565 NOR gate, 581 switch, 582 D / A converter, 600 image pickup device, 612 CMOS image sensor

Claims (19)

It is a D / A converter that converts a digital signal into an analog signal, and the predetermined current generated by receiving the gain control signal that controls the gain is the first output current according to the value of the input digital signal. And the first non-output current, and the first non-output current is divided into a second output current and a second non-output current according to the value of the digital signal. A signal processing device including a first D / A conversion unit that outputs each of the second output currents as an analog signal. The signal processing device according to claim 1, wherein the value of the digital signal changes in the time direction so as to increase the first output current and decrease the second output current. The value of the digital signal changes in the time direction so as to increase the first output current and the second output current.
The signal processing device according to claim 1. Further provided with a current source that receives the gain control signal and generates the current.
The signal processing device according to claim 1. The first D / A conversion unit drives the digital signal as a control signal, and is connected to each signal line connected to each of a plurality of output terminals to which the analog signal is output, and a voltage source. It has a switch that controls the connection between the signal line and the current source.
The signal processing device according to claim 4. The first D / A conversion unit has a plurality of the switches configured in parallel, and applies the current according to the ratio of the number of the switches connecting each signal line and the current source. The signal processing device according to claim 5, wherein the signal processing device is divided into a plurality of output currents and the non-output current. For each of the plurality of output currents, a resistor for converting the output current into a voltage is further provided.
The signal processing device according to claim 1. The resistance values of the resistors corresponding to each output current are different from each other.
The signal processing device according to claim 7. A conversion unit that converts a digital signal into an analog signal, and a predetermined current generated by receiving a gain control signal that controls the gain, with a single output current and non-output according to the value of the input digital signal. A second D / A conversion unit is further provided, which is divided into currents and uses the output current to control the signal level of the analog signal output from the first D / A conversion unit.
The signal processing device according to claim 1. The signal processing device according to claim 1, further comprising a gain control unit that generates the gain control signal, supplies the gain control signal to the first D / A conversion unit, and controls the gain. The signal processing device according to claim 1, further comprising a digital signal generation unit that generates the digital signal and supplies the digital signal to the first D / A conversion unit. The signal processing according to claim 1, further comprising an A / D conversion unit that converts an analog signal into a digital signal by using the plurality of analog signals output from the first D / A conversion unit as reference signals. apparatus. The A / D conversion unit is configured so that the gain can be adaptively switched by using the plurality of analog signals as reference signals.
The signal processing device according to claim 12. The plurality of analog signals are used by the A / D converters that are different from each other.
The signal processing device according to claim 12. The A / D conversion unit is provided for each column of the pixel array in which a plurality of unit pixels are arranged in a matrix, and a pixel signal read from each pixel of the column corresponding to itself is converted from an analog signal to a digital signal. Convert to
The signal processing device according to claim 12. The A / D conversion unit is provided for each area of the pixel array in which a plurality of unit pixels are arranged in a matrix, and a pixel signal read from each pixel in the area corresponding to itself is converted from an analog signal to a digital signal. Convert to
The signal processing device according to claim 12. The predetermined current generated by receiving the gain control signal for controlling the gain is divided into a first output current and a first non-output current according to the value of the input digital signal, and the first non-output current is divided. The current is divided into a second output current and a second non-output current according to the value of the digital signal, and the first output current and the second output current are output as analog signals, respectively.
Signal processing method. A pixel array in which multiple unit pixels are arranged in a matrix, and
It is a D / A converter that converts a digital signal into an analog signal, and the predetermined current generated by receiving the gain control signal that controls the gain is the first output current according to the value of the input digital signal. And the first non-output current, and the first non-output current is divided into a second output current and a second non-output current according to the value of the digital signal. A D / A converter that outputs the second output current as an analog signal, and
An A / D conversion unit that converts a pixel signal read from the pixel array, which is an analog signal, into a digital signal by using the plurality of analog signals output from the D / A conversion unit as reference signals.
An image sensor comprising. An imaging unit that captures the subject and
An image processing unit that processes image data obtained by imaging by the imaging unit
With
The imaging unit
A pixel array in which multiple unit pixels are arranged in a matrix, and
It is a D / A converter that converts a digital signal into an analog signal, and the predetermined current generated by receiving the gain control signal that controls the gain is the first output current according to the value of the input digital signal. And the first non-output current, and the first non-output current is divided into a second output current and a second non-output current according to the value of the digital signal. A D / A converter that outputs the second output current as an analog signal, and
An A / D conversion unit that converts a pixel signal read from the pixel array, which is an analog signal, into a digital signal by using the plurality of analog signals output from the D / A conversion unit as reference signals. Electronic equipment to be equipped.

Images