US20210026182A1 - Display panel and method of fabricating the same - Google Patents
Display panel and method of fabricating the same Download PDFInfo
- Publication number
- US20210026182A1 US20210026182A1 US16/937,589 US202016937589A US2021026182A1 US 20210026182 A1 US20210026182 A1 US 20210026182A1 US 202016937589 A US202016937589 A US 202016937589A US 2021026182 A1 US2021026182 A1 US 2021026182A1
- Authority
- US
- United States
- Prior art keywords
- display panel
- conductive traces
- substrate
- panel according
- bonding pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 230000002093 peripheral effect Effects 0.000 claims abstract description 16
- 238000005520 cutting process Methods 0.000 claims description 56
- 238000012360 testing method Methods 0.000 claims description 44
- 238000001514 detection method Methods 0.000 claims description 8
- 238000009413 insulation Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133351—Manufacturing of individual cells out of a plurality of cells, e.g. by dicing
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/0293—Individual printed conductors which are adapted for modification, e.g. fusable or breakable conductors, printed switches
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10128—Display
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/162—Testing a finished product, e.g. heat cycle testing of solder joints
Definitions
- the disclosure relates to an electronic device and a method of fabricating the same, and in particular, to a display panel and a method of fabricating the same.
- a display panel is composed of a thin film transistor array substrate and a display medium layer disposed thereon.
- the thin film transistor array substrate may be further divided into an active region and a peripheral circuit region.
- a pixel array is disposed in the active region, and elements such as a plurality of conductive traces (or leads), a plurality of bonding pads, and a testing transistor, etc. are disposed in the peripheral circuit region.
- a series of detection procedures are performed to determine whether display quality of the display panel meets the standard.
- the display panel needs to be cut to remove a testing pad used for an electrical test.
- a manner of configuring the conductive traces (for example, a width of the trace and a pitch between the traces) in the peripheral circuit region varies owing to different product designs (for example, pixel resolution). Therefore, during cutting, cutting parameters (such as a laser power or a depth of depression of a cutter wheel) usually need to be adjusted for display panels of different product specifications, so as to ensure that the cutting of the substrate causes no damage to the display panel.
- cutting parameters such as a laser power or a depth of depression of a cutter wheel
- the pitch between the conductive traces for testing continuously decreases. As such, an electrical short circuit to the conductive traces of the display panel is generated in the cutting direction after the testing pads are removed.
- the disclosure provides a display panel exhibiting a good production yield.
- the disclosure provides a method of fabricating a display panel, which exhibits a good cutting yield.
- a display panel of the disclosure includes a substrate, a plurality of bonding pads, and a plurality of conductive traces.
- the substrate includes a substrate edge, a display region, and a peripheral region disposed between the substrate edge and the display region.
- the plurality of bonding pads are arranged in the peripheral region of the substrate.
- the plurality of conductive traces are electrically connected to the bonding pads.
- the plurality of conductive traces extend between the bonding pads and the substrate edge and have a plurality of breaks.
- a method of fabricating a display panel of the disclosure includes the following steps.
- a breaking step for a plurality of conductive traces is performed, so that a plurality of bonding pads and a plurality of testing pads of the display panel are electrically separated.
- a cutting step for a substrate of the display panel is performed along a cutting line, and a flexible printed circuit board is electrically bonded to the bonding pads of the display panel.
- the bonding pads and the testing pads are disposed in a peripheral region of the display panel on at least one side of the substrate, and the conductive traces of the display panel are electrically connected between the bonding pads and the testing pads.
- each of the conductive traces has a plurality of breaks.
- the cutting line is located between the breaks of the conductive traces and the testing pads.
- the plurality of breaks are provided on the plurality of conductive traces connected between the plurality of bonding pads and the plurality of testing pads.
- the display panel is cut along the cutting line between the testing pads and the bonding pads to remove thee testing pads.
- the breaks of the conductive traces are disposed between the bonding pads and the cutting line, so that an electrical short circuit of the conductive traces may be avoided during the cutting, and a cutting yield of the display panel is thereby improved. Therefore, in the display panel according to an embodiment of the disclosure, each of the plurality of conductive traces extending between the cut substrate edge and the plurality of bonding pads has the breaks.
- FIG. 1 is a schematic top view of a motherboard of a display panel according to an embodiment of the disclosure.
- FIG. 2A to FIG. 2D are schematic top views of a process of fabricating the display panel according to an embodiment of the disclosure.
- FIG. 3A and FIG. 3B are schematic enlarged views of partial regions of the display panel in FIG. 2A and FIG. 2B , respectively.
- FIG. 4 is a schematic top view of a partial region of a display panel according to another embodiment of the disclosure.
- FIG. 5 is a schematic cross-sectional view of the display panel in FIG. 4 .
- FIG. 6 is a schematic top view of a partial region of a display panel according to still another embodiment of the disclosure.
- “about”, “approximately”, “essentially” or “substantially” is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ⁇ 30%, ⁇ 20%, ⁇ 15%, ⁇ 10%, ⁇ 5% of the stated value. Further, as used herein, “about”, “approximately”, “essentially” or “substantially” may depend on measurement properties, cutting properties, or other properties to select a more acceptable range of deviations or standard deviations without one standard deviation for all properties.
- connection may refer to a physical and/or electrical connection.
- electrical connection may mean that there are other elements between two elements.
- spatially relative terms such as “below”, “bottom”, “on” or “top” are used in this specification to describe a relationship between one element and another element, as shown in the figures. It should be understood that such spatially relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being “below” relative to another element will then be “above” relative to the other element. Therefore, the exemplary term “below” encompasses both the below and above orientations depending on the spatial orientation of the device.
- FIG. 1 is a schematic top view of a motherboard of a display panel according to an embodiment of the disclosure.
- FIG. 2A to FIG. 2D are schematic top views of a process of fabricating the display panel according to an embodiment of the disclosure.
- FIG. 3A and FIG. 3B are schematic enlarged views of partial regions of the display panel in FIG. 2A and FIG. 2B , respectively.
- FIG. 3A corresponds to a partial region I in FIG. 2A
- FIG. 3B corresponds to a partial region II in FIG. 2B .
- FIG. 1 omits illustration of a conductive trace CL and a signal line SL in FIG. 2A .
- a display panel 10 C includes a substrate 100 , a plurality of bonding pads BP, and a plurality of conductive traces CL′′.
- the substrate 100 has a substrate edge 100 e , a display region DR, and a peripheral region PR disposed between the substrate edge 100 e and the display region DR.
- the plurality of bonding pads BP are arranged in the peripheral region PR of the substrate 100 in a direction.
- the direction may be a direction in which the substrate edge 100 e extends, but the disclosure is not limited thereto.
- the plurality of conductive traces CL′′ are electrically connected to the plurality of bonding pads BP, respectively.
- the conductive traces CL′′ located in the peripheral region PR extend between the substrate edge 100 e and the bonding pads BP. It is worth noting that the conductive traces CL′′ have a plurality of breaks CLb. The breaks CLb are located between the substrate edge 100 e and the plurality of bonding pads BP. Through the above configuration of the breaks CLb, an electrical short circuit of the conductive traces CL′′ may be avoided during cutting, and a cutting yield of the display panel 10 C is thereby improved.
- the display panel 10 C may further include a counter substrate (not shown) and a display medium layer (not shown) disposed between the substrate 100 and the counter substrate.
- the display medium layer includes a plurality of liquid crystal molecules, for example.
- the display panel 10 C in the present embodiment may be a liquid crystal display panel, but the disclosure is not limited thereto.
- the display medium layer may further include a plurality of light emitting structures.
- the display panel may also be an organic light emitting diode (OLED) panel, a micro light emitting diode (micro-LED) panel, or a mini light emitting diode (mini-LED) panel.
- the substrate 100 and the counter substrate of the display panel 10 C are, for example, flexible substrates, but the disclosure is not limited thereto.
- a flexible printed circuit board (FPCB) 200 may be further provided on one side of the substrate edge 100 e of the substrate 100 .
- the FPCB 200 is electrically bonded to the bonding pads BP.
- the FPCB 200 is, for example, a transmission circuit board using a chip on film (COF) package.
- COF chip on film
- the FPCB 200 may be a package structure having a driver chip and a transmission line, but the disclosure is not limited thereto.
- the FPCB 200 may also be a transmission circuit board formed by using a tape automated bonding (TAB) technology.
- TAB tape automated bonding
- the FPCB 200 may not have a driver chip.
- the display panel 10 C further includes a plurality of signal lines SL.
- the signal lines SL are disposed in the display region DR and extend to the peripheral region PR to be electrically connected to the plurality of bonding pads BP.
- a plurality of pixel structures may be provided in the display region DR of the display panel 10 C.
- the pixel structures are electrically connected to the signal lines SL, respectively.
- a drive signal sent by the FPCB 200 may be transmitted to the pixel structure in the display region DR through transmission by the bonding pad BP and the signal line SL, to display an image.
- a process of fabricating the display panel 10 C is exemplarily described below.
- a method of fabricating the display panel 10 C includes: cutting a motherboard 1 to obtain a plurality of display panels 10 .
- the motherboard 1 has a plurality of display panels 10 arranged in an array.
- the display panels 10 are arranged in a plurality of columns and a plurality of rows in a direction X and a direction Y, respectively, but the disclosure is not limited thereto.
- the display panels may also have different sizes, and are not disposed on the motherboard in an array.
- the motherboard 1 is cut along a plurality of cutting lines C 1 and a plurality of cutting lines C 2 through mechanical cutting (for example, fixed knife cutting, rotary cutter wheel cutting, or fixed knife die cutting, etc.).
- mechanical cutting for example, fixed knife cutting, rotary cutter wheel cutting, or fixed knife die cutting, etc.
- a direction in which the cutting line C 1 extends intersects with a direction in which the cutting line C 2 extends, but the disclosure is not limited thereto.
- the motherboard 1 may also be cut through non-mechanical cutting (for example, laser cutting).
- the display panel 10 obtained by cutting the motherboard 1 has a plurality of testing pads TP.
- the testing pads TP are disposed on at least one side of a substrate 100 S of the display panel 10 .
- the substrate 100 S of the display panel 10 has a side edge 100 Se corresponding to the cutting line C 2 .
- the testing pads TP are located between the side edge 100 Se of the substrate 100 S and the plurality of bonding pads BP, but the disclosure is not limited thereto.
- the method of fabricating the display panel 10 C further includes: forming a plurality of conductive traces CL between the plurality of bonding pads BP and the plurality of testing pads TP.
- the conductive trace CL is electrically connected between one corresponding bonding pad BP and one corresponding testing pad TP.
- the disclosure is not limited thereto. According to other embodiments, the conductive trace may also be electrically connected between a plurality of corresponding bonding pads BP and one corresponding testing pad TP.
- the conductive trace CL has an extension section 121 , a connection portion 122 , and an extension section 123 .
- the connection portion 122 is electrically connected between the extension section 121 and the extension section 123 .
- the connection portion 122 of the conductive trace CL has a width W 1 in the direction X
- the extension section 123 (or the extension section 121 ) of the conductive trace CL has a width W 2 in the direction X.
- the width W 1 is less than the width W 2 , but the disclosure is not limited thereto.
- a ratio of the width W 1 of the connection portion 122 of the conductive trace CL to the width W 2 of the extension portion 123 is less than 0.5.
- the widths of the extension section 121 and the extension section 123 of the conductive trace CL in the direction X may be selectively the same, but the disclosure is not limited thereto. In other embodiments, the widths of the two extension sections of the conductive trace in the direction X may also be different, and both are greater than the width W 1 of the connection portion 122 .
- the detection step for the display panel 10 includes abutting a plurality of probe pins of a testing machine to the plurality of testing pads TP of the display panel 10 and applying at least one voltage signal between the testing pads TP for electrical testing and/or reliability testing.
- the at least one voltage signal may be a DC voltage signal provided by a power supply PS 1 of the testing machine, but the disclosure is not limited thereto. It should be noted that the electrical connection between the power supply PS 1 and the plurality of testing pads TP in FIG. 2A is merely for illustration, and the disclosure is not limited to the disclosure in the drawings.
- a breaking step for the plurality of conductive traces CL is performed to electrically separate the bonding pads BP and the testing pads TP. It is worth noting that after the breaking step for the conductive trace CL is completed, a conductive trace CL′ having a break CLb is formed.
- the breaking step for the conductive trace CL may be performed by the above testing machine. The difference therebetween is that two ends (for example, a high-potential end and a low-potential end) of a power supply PS 2 (or the power supply PS 1 ) of the testing machine are electrically connected to the bonding pad BP and the testing pad TP, respectively.
- the width W 2 of the connection portion 122 of the conductive trace CL is less than the width W 1 of the extension portion 123 (or the width of the extension portion 121 ), a resistivity of the connection portion 122 is greater than a resistivity of the extension portion 123 (or a resistivity of the extension portion 121 ). Therefore, when the power source PS 2 is enabled to apply a current Ic is applied between the bonding pad BP and the testing pad TP, the current Ic flowing through the conductive trace CL generates a relatively large amount of heat energy when passing through the connection portion 122 . As a result, a temperature of the connection portion 122 increases and exceeds a melting point thereof. In this case, the connection portion 122 of the conductive trace CL is broken and forms a break CLb. For example, a ratio of a current Ic value used for the breaking step to a current used for detection may be between 1 and 5, but the disclosure is not limited thereto.
- the conductive trace CL′ formed after the conductive trace CL is broken further has an end portion 1211 and an end portion 1231 that define the break CLb.
- the end portion 1211 and the end portion 1231 are connected to the extension section 121 and the extension section 123 , respectively.
- the end portion 1211 of the conductive trace CL′ has a width W 1 ′ in the direction X.
- the width W 1 ′ of the end portion 1211 (or a width of the end portion 1231 in the direction X) is less than the width W 2 of the extension section 123 in the direction X (or the width of the extension section 121 in the direction X).
- a cutting step for the substrate 100 S is performed along a cutting line C 3 to obtain a display panel 10 C.
- the cutting line C 3 is located between the plurality of breaks CLb of the plurality of conductive traces CL′ and the plurality of testing pads TP, or the plurality of connection portions 122 of the plurality of conductive traces CL are located between the cutting line C 3 and the plurality of bonding pads BP (shown in FIG. 3A ).
- the shortest distance d may be greater than or equal to 50 microns, but the disclosure is not limited thereto.
- the cutting line C 3 may be disposed in a region between the testing pad TP and a position at least 50 microns away from the break CLb. Accordingly, an adjustment margin of the cutting process of the substrate 100 S may be increased.
- the breaks CLb of the conductive trace CL′ are disposed between the bonding pad BP and the testing pad TP, so that an electrical short circuit of the conductive trace CL′ may be avoided during the cutting, and a cutting yield of the display panel is thereby improved.
- the cut conductive trace CL′′ extends between the substrate edge 100 e of the substrate 100 and the bonding pad BP, and has a break CLb. It is worth noting that, due to the configuration relationship of the cutting line C 3 (shown in FIG. 2C ), a shortest distance d between the substrate edge 100 e of the cut substrate 100 and the plurality of breaks CLb may be greater than or equal to 50 microns, but the disclosure is not limited thereto.
- the FPCB 200 may be electrically bonded to the plurality of bonding pads BP.
- the FPCB 200 may have a plurality of pins, and the FPCB 200 is electrically connected to a plurality of signal lines SL on the substrate 100 through thermocompression bonding of the pins and the plurality of bonding pads BP.
- FIG. 4 is a schematic top view of a partial region of a display panel according to another embodiment of the disclosure.
- FIG. 5 is a schematic cross-sectional view of the display panel in FIG. 4 . It should be particularly noted that, for clarity, FIG. 4 omits illustration of an insulation layer 110 in FIG. 5 .
- a main difference between the display panel 11 in the present embodiment and the display panel 10 in FIG. 3A lies in different compositions of conductive traces.
- a conductive trace CL-A of the display panel 11 has an extension section 121 A and an extension section 123 A structurally separated from each other and a connection portion 122 A electrically connected between the extension section 121 A and the extension section 123 A.
- a step of forming a plurality of conductive traces CL-A may selectively include forming an insulation layer 110 between the extension section and the connection portion 122 A.
- the connection portion 122 A and the extension section of the conductive trace CL-A may belong to different film layers.
- the insulation layer 110 covers the extension section 121 A and the extension section 123 A of the conductive trace CL-A.
- the connection portion 122 A of the conductive trace CL-A is disposed on the insulation layer 110 , and two ends of the connection portion 122 A penetrate through the insulation layer 110 to be electrically connected to the extension section 121 A and the extension section 123 A, respectively.
- the disclosure is not limited thereto.
- the connection portion of the conductive trace may also be disposed between the insulation layer 110 and the substrate 100 S, and the two extension sections each penetrate through the insulation layer 110 to be electrically connected to the connection portion.
- resistivities of the two extension sections of the conductive trace CL-A may be smaller than a resistivity of the connection portion 122 A. Therefore, in the breaking step for the conductive trace CL-A, a current flowing through the conductive trace CL-A generates a relatively large amount of heat energy when passing through the connection portion 122 A. As a result, a temperature of the connection portion 122 A increases and exceeds a melting point thereof. In this case, the connection portion 122 A of the conductive trace CL-A is broken and forms a break (not shown). Through the disposed break, an electrical short circuit of the conductive traces CL-A may be avoided during a subsequent cutting process, and a cutting yield of the display panel 11 is thereby improved.
- FIG. 6 is a schematic top view of a partial region of a display panel according to still another embodiment of the disclosure.
- a difference between a display panel 12 in the present embodiment and the display panel 10 in FIG. 3A lies in different configurations of connection portions of conductive traces.
- a plurality of connection portions 122 B of a plurality of conductive traces CL-B of the display panel 12 are staggered from each other in a direction (for example, a direction X) in which the bonding pads BP are arranged.
- a connection portion 122 B of any of the plurality of conductive traces CL-B may overlap an extension section 121 B or an extension section 123 B of an adjacent conductive trace CL-B in the direction X.
- a plurality of breaks formed by the conductive traces CL-B after a breaking step are also staggered from each other in the direction X (not shown). It is worth mentioning that, through the staggering relationship of the plurality of connection portions 122 B of the plurality of conductive traces CL-B, heat energy generated when a current passes through the connection portions 122 B may be dispersed, and that independent electrical properties of the bonding pads BP are ensured after a cutting step for the substrate 100 S is completed.
- the plurality of breaks are provided on the plurality of conductive traces connected between the plurality of bonding pads and the plurality of testing pads.
- the display panel is cut along the cutting line between the testing pads and the bonding pads to remove these testing pads.
- the breaks of the conductive traces are disposed between the bonding pads and the cutting line, so that an electrical short circuit of the conductive traces may be avoided during the cutting, a cutting yield of the display panel is thereby improved. Therefore, in the display panel according to an embodiment of the disclosure, each of the plurality of conductive traces extending between the cut substrate edge and the plurality of bonding pads has the breaks.
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
Description
- This application claims the priority benefits of U.S. provisional application Ser. No. 62/878,857, filed on Jul. 26, 2019, and Taiwan application serial no. 109109750, filed on Mar. 24, 2020. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
- The disclosure relates to an electronic device and a method of fabricating the same, and in particular, to a display panel and a method of fabricating the same.
- Generally, a display panel is composed of a thin film transistor array substrate and a display medium layer disposed thereon. Particularly, the thin film transistor array substrate may be further divided into an active region and a peripheral circuit region. A pixel array is disposed in the active region, and elements such as a plurality of conductive traces (or leads), a plurality of bonding pads, and a testing transistor, etc. are disposed in the peripheral circuit region. Generally, after a display panel is fabricated, a series of detection procedures are performed to determine whether display quality of the display panel meets the standard.
- Generally, after the detection procedures are performed, the display panel needs to be cut to remove a testing pad used for an electrical test. A manner of configuring the conductive traces (for example, a width of the trace and a pitch between the traces) in the peripheral circuit region varies owing to different product designs (for example, pixel resolution). Therefore, during cutting, cutting parameters (such as a laser power or a depth of depression of a cutter wheel) usually need to be adjusted for display panels of different product specifications, so as to ensure that the cutting of the substrate causes no damage to the display panel. However, as resolution of display panels continuously increases, the pitch between the conductive traces for testing continuously decreases. As such, an electrical short circuit to the conductive traces of the display panel is generated in the cutting direction after the testing pads are removed.
- The disclosure provides a display panel exhibiting a good production yield.
- The disclosure provides a method of fabricating a display panel, which exhibits a good cutting yield.
- A display panel of the disclosure includes a substrate, a plurality of bonding pads, and a plurality of conductive traces. The substrate includes a substrate edge, a display region, and a peripheral region disposed between the substrate edge and the display region. The plurality of bonding pads are arranged in the peripheral region of the substrate. The plurality of conductive traces are electrically connected to the bonding pads. The plurality of conductive traces extend between the bonding pads and the substrate edge and have a plurality of breaks.
- A method of fabricating a display panel of the disclosure includes the following steps. A breaking step for a plurality of conductive traces is performed, so that a plurality of bonding pads and a plurality of testing pads of the display panel are electrically separated. A cutting step for a substrate of the display panel is performed along a cutting line, and a flexible printed circuit board is electrically bonded to the bonding pads of the display panel. The bonding pads and the testing pads are disposed in a peripheral region of the display panel on at least one side of the substrate, and the conductive traces of the display panel are electrically connected between the bonding pads and the testing pads. After the breaking step is completed, each of the conductive traces has a plurality of breaks. In the cutting step for the substrate, the cutting line is located between the breaks of the conductive traces and the testing pads.
- Based on the above, in the method of fabricating the display panel according to an embodiment of the disclosure, in the uncut display panel, the plurality of breaks are provided on the plurality of conductive traces connected between the plurality of bonding pads and the plurality of testing pads. In the cutting step for the substrate, the display panel is cut along the cutting line between the testing pads and the bonding pads to remove thee testing pads. The breaks of the conductive traces are disposed between the bonding pads and the cutting line, so that an electrical short circuit of the conductive traces may be avoided during the cutting, and a cutting yield of the display panel is thereby improved. Therefore, in the display panel according to an embodiment of the disclosure, each of the plurality of conductive traces extending between the cut substrate edge and the plurality of bonding pads has the breaks.
-
FIG. 1 is a schematic top view of a motherboard of a display panel according to an embodiment of the disclosure. -
FIG. 2A toFIG. 2D are schematic top views of a process of fabricating the display panel according to an embodiment of the disclosure. -
FIG. 3A andFIG. 3B are schematic enlarged views of partial regions of the display panel inFIG. 2A andFIG. 2B , respectively. -
FIG. 4 is a schematic top view of a partial region of a display panel according to another embodiment of the disclosure. -
FIG. 5 is a schematic cross-sectional view of the display panel inFIG. 4 . -
FIG. 6 is a schematic top view of a partial region of a display panel according to still another embodiment of the disclosure. - As used herein, “about”, “approximately”, “essentially” or “substantially” is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±15%, ±10%, ±5% of the stated value. Further, as used herein, “about”, “approximately”, “essentially” or “substantially” may depend on measurement properties, cutting properties, or other properties to select a more acceptable range of deviations or standard deviations without one standard deviation for all properties.
- In the accompanying drawings, the thicknesses of layers, films, panels, regions, and the like are enlarged for clarity. It should be understood that when a component such as a layer, film, region or substrate is referred to as being “on” or “connected to” another component, it may be directly on or connected to the another component, or intervening components may also be present. In contrast, when a component is referred to as being “directly on” or “directly connected to” another component, there are no intervening components present. As used herein, “connection” may refer to a physical and/or electrical connection. Furthermore, “electrical connection” may mean that there are other elements between two elements.
- In addition, spatially relative terms such as “below”, “bottom”, “on” or “top” are used in this specification to describe a relationship between one element and another element, as shown in the figures. It should be understood that such spatially relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being “below” relative to another element will then be “above” relative to the other element. Therefore, the exemplary term “below” encompasses both the below and above orientations depending on the spatial orientation of the device. Similarly, if the device in the figures is turned over, an element described as being “below” or “lower” relative to another element will then be “above” or “upper” relative to the other element. Therefore, the exemplary term “above” or “below” encompasses both the above and below orientations.
- Exemplary embodiments of the disclosure are described in detail, and examples of the exemplary embodiments are shown in the accompanying drawings. Whenever possible, the same element symbols are used in the drawings and descriptions to indicate the same or similar parts.
-
FIG. 1 is a schematic top view of a motherboard of a display panel according to an embodiment of the disclosure.FIG. 2A toFIG. 2D are schematic top views of a process of fabricating the display panel according to an embodiment of the disclosure.FIG. 3A andFIG. 3B are schematic enlarged views of partial regions of the display panel inFIG. 2A andFIG. 2B , respectively. In particular,FIG. 3A corresponds to a partial region I inFIG. 2A , andFIG. 3B corresponds to a partial region II inFIG. 2B . For clarity,FIG. 1 omits illustration of a conductive trace CL and a signal line SL inFIG. 2A . - Referring to
FIG. 2D , in the present embodiment, adisplay panel 10C includes asubstrate 100, a plurality of bonding pads BP, and a plurality of conductive traces CL″. Thesubstrate 100 has asubstrate edge 100 e, a display region DR, and a peripheral region PR disposed between thesubstrate edge 100 e and the display region DR. The plurality of bonding pads BP are arranged in the peripheral region PR of thesubstrate 100 in a direction. In the present embodiment, the direction may be a direction in which thesubstrate edge 100 e extends, but the disclosure is not limited thereto. The plurality of conductive traces CL″ are electrically connected to the plurality of bonding pads BP, respectively. More specifically, the conductive traces CL″ located in the peripheral region PR extend between thesubstrate edge 100 e and the bonding pads BP. It is worth noting that the conductive traces CL″ have a plurality of breaks CLb. The breaks CLb are located between thesubstrate edge 100 e and the plurality of bonding pads BP. Through the above configuration of the breaks CLb, an electrical short circuit of the conductive traces CL″ may be avoided during cutting, and a cutting yield of thedisplay panel 10C is thereby improved. - Further, the
display panel 10C may further include a counter substrate (not shown) and a display medium layer (not shown) disposed between thesubstrate 100 and the counter substrate. In the present embodiment, the display medium layer includes a plurality of liquid crystal molecules, for example. In other words, thedisplay panel 10C in the present embodiment may be a liquid crystal display panel, but the disclosure is not limited thereto. According to other embodiments, the display medium layer may further include a plurality of light emitting structures. In other words, the display panel may also be an organic light emitting diode (OLED) panel, a micro light emitting diode (micro-LED) panel, or a mini light emitting diode (mini-LED) panel. In the present embodiment, thesubstrate 100 and the counter substrate of thedisplay panel 10C are, for example, flexible substrates, but the disclosure is not limited thereto. - It should be understood that, in the present embodiment, a flexible printed circuit board (FPCB) 200 may be further provided on one side of the
substrate edge 100 e of thesubstrate 100. TheFPCB 200 is electrically bonded to the bonding pads BP. In the present embodiment, theFPCB 200 is, for example, a transmission circuit board using a chip on film (COF) package. In other words, theFPCB 200 may be a package structure having a driver chip and a transmission line, but the disclosure is not limited thereto. In other embodiments, theFPCB 200 may also be a transmission circuit board formed by using a tape automated bonding (TAB) technology. In another embodiment, theFPCB 200 may not have a driver chip. - In addition, the
display panel 10C further includes a plurality of signal lines SL. The signal lines SL are disposed in the display region DR and extend to the peripheral region PR to be electrically connected to the plurality of bonding pads BP. For example, a plurality of pixel structures (not shown) may be provided in the display region DR of thedisplay panel 10C. The pixel structures are electrically connected to the signal lines SL, respectively. In other words, a drive signal sent by theFPCB 200 may be transmitted to the pixel structure in the display region DR through transmission by the bonding pad BP and the signal line SL, to display an image. A process of fabricating thedisplay panel 10C is exemplarily described below. - Referring to
FIG. 1 andFIG. 2A toFIG. 2D , a method of fabricating thedisplay panel 10C includes: cutting amotherboard 1 to obtain a plurality ofdisplay panels 10. In the present embodiment, themotherboard 1 has a plurality ofdisplay panels 10 arranged in an array. In other words, thedisplay panels 10 are arranged in a plurality of columns and a plurality of rows in a direction X and a direction Y, respectively, but the disclosure is not limited thereto. In other embodiments, in order to optimize utilization of the motherboard, the display panels may also have different sizes, and are not disposed on the motherboard in an array. For example, in the present embodiment, themotherboard 1 is cut along a plurality of cutting lines C1 and a plurality of cutting lines C2 through mechanical cutting (for example, fixed knife cutting, rotary cutter wheel cutting, or fixed knife die cutting, etc.). A direction in which the cutting line C1 extends intersects with a direction in which the cutting line C2 extends, but the disclosure is not limited thereto. In other embodiments, themotherboard 1 may also be cut through non-mechanical cutting (for example, laser cutting). - The
display panel 10 obtained by cutting themotherboard 1 has a plurality of testing pads TP. The testing pads TP are disposed on at least one side of asubstrate 100S of thedisplay panel 10. In the present embodiment, thesubstrate 100S of thedisplay panel 10 has a side edge 100Se corresponding to the cutting line C2. The testing pads TP are located between the side edge 100Se of thesubstrate 100S and the plurality of bonding pads BP, but the disclosure is not limited thereto. Referring toFIG. 2A andFIG. 3A , the method of fabricating thedisplay panel 10C further includes: forming a plurality of conductive traces CL between the plurality of bonding pads BP and the plurality of testing pads TP. The conductive trace CL is electrically connected between one corresponding bonding pad BP and one corresponding testing pad TP. However, the disclosure is not limited thereto. According to other embodiments, the conductive trace may also be electrically connected between a plurality of corresponding bonding pads BP and one corresponding testing pad TP. - Further, the conductive trace CL has an
extension section 121, aconnection portion 122, and anextension section 123. Theconnection portion 122 is electrically connected between theextension section 121 and theextension section 123. For example, in the present embodiment, theconnection portion 122 of the conductive trace CL has a width W1 in the direction X, and the extension section 123 (or the extension section 121) of the conductive trace CL has a width W2 in the direction X. The width W1 is less than the width W2, but the disclosure is not limited thereto. In an exemplary embodiment, a ratio of the width W1 of theconnection portion 122 of the conductive trace CL to the width W2 of theextension portion 123 is less than 0.5. It should be noted that, in the present embodiment, the widths of theextension section 121 and theextension section 123 of the conductive trace CL in the direction X may be selectively the same, but the disclosure is not limited thereto. In other embodiments, the widths of the two extension sections of the conductive trace in the direction X may also be different, and both are greater than the width W1 of theconnection portion 122. - Still referring to
FIG. 2A , after the cutting step for themotherboard 1 is completed, a detection step for thedisplay panel 10 is performed. For example, the detection step for thedisplay panel 10 includes abutting a plurality of probe pins of a testing machine to the plurality of testing pads TP of thedisplay panel 10 and applying at least one voltage signal between the testing pads TP for electrical testing and/or reliability testing. In the present embodiment, the at least one voltage signal may be a DC voltage signal provided by a power supply PS1 of the testing machine, but the disclosure is not limited thereto. It should be noted that the electrical connection between the power supply PS1 and the plurality of testing pads TP inFIG. 2A is merely for illustration, and the disclosure is not limited to the disclosure in the drawings. - After the detection step for the
display panel 10 is completed, as shown inFIG. 2B andFIG. 3B , a breaking step for the plurality of conductive traces CL is performed to electrically separate the bonding pads BP and the testing pads TP. It is worth noting that after the breaking step for the conductive trace CL is completed, a conductive trace CL′ having a break CLb is formed. For example, the breaking step for the conductive trace CL may be performed by the above testing machine. The difference therebetween is that two ends (for example, a high-potential end and a low-potential end) of a power supply PS2 (or the power supply PS1) of the testing machine are electrically connected to the bonding pad BP and the testing pad TP, respectively. Since the width W2 of theconnection portion 122 of the conductive trace CL is less than the width W1 of the extension portion 123 (or the width of the extension portion 121), a resistivity of theconnection portion 122 is greater than a resistivity of the extension portion 123 (or a resistivity of the extension portion 121). Therefore, when the power source PS2 is enabled to apply a current Ic is applied between the bonding pad BP and the testing pad TP, the current Ic flowing through the conductive trace CL generates a relatively large amount of heat energy when passing through theconnection portion 122. As a result, a temperature of theconnection portion 122 increases and exceeds a melting point thereof. In this case, theconnection portion 122 of the conductive trace CL is broken and forms a break CLb. For example, a ratio of a current Ic value used for the breaking step to a current used for detection may be between 1 and 5, but the disclosure is not limited thereto. - It is worth noting that the conductive trace CL′ formed after the conductive trace CL is broken further has an end portion 1211 and an
end portion 1231 that define the break CLb. The end portion 1211 and theend portion 1231 are connected to theextension section 121 and theextension section 123, respectively. In the present embodiment, the end portion 1211 of the conductive trace CL′ has a width W1′ in the direction X. The width W1′ of the end portion 1211 (or a width of theend portion 1231 in the direction X) is less than the width W2 of theextension section 123 in the direction X (or the width of theextension section 121 in the direction X). - Referring to
FIG. 2C andFIG. 3B , after the breaking step for the conductive trace CL is completed, a cutting step for thesubstrate 100S is performed along a cutting line C3 to obtain adisplay panel 10C. It is worth noting that the cutting line C3 is located between the plurality of breaks CLb of the plurality of conductive traces CL′ and the plurality of testing pads TP, or the plurality ofconnection portions 122 of the plurality of conductive traces CL are located between the cutting line C3 and the plurality of bonding pads BP (shown inFIG. 3A ). For example, there is a shortest distance d between the plurality of breaks CLb of the plurality of conductive traces CL′ and the cutting line C3. The shortest distance d may be greater than or equal to 50 microns, but the disclosure is not limited thereto. In other words, the cutting line C3 may be disposed in a region between the testing pad TP and a position at least 50 microns away from the break CLb. Accordingly, an adjustment margin of the cutting process of thesubstrate 100S may be increased. From another point of view, the breaks CLb of the conductive trace CL′ are disposed between the bonding pad BP and the testing pad TP, so that an electrical short circuit of the conductive trace CL′ may be avoided during the cutting, and a cutting yield of the display panel is thereby improved. - Referring to
FIG. 2D , the cut conductive trace CL″ extends between thesubstrate edge 100 e of thesubstrate 100 and the bonding pad BP, and has a break CLb. It is worth noting that, due to the configuration relationship of the cutting line C3 (shown inFIG. 2C ), a shortest distance d between thesubstrate edge 100 e of thecut substrate 100 and the plurality of breaks CLb may be greater than or equal to 50 microns, but the disclosure is not limited thereto. Further, after the cutting step for thesubstrate 100S is completed, theFPCB 200 may be electrically bonded to the plurality of bonding pads BP. For example, theFPCB 200 may have a plurality of pins, and theFPCB 200 is electrically connected to a plurality of signal lines SL on thesubstrate 100 through thermocompression bonding of the pins and the plurality of bonding pads BP. - Some other embodiments are listed below to describe the disclosure in detail. The same components are marked with the same symbols, and the descriptions of the same technical contents are omitted. For the omitted parts, refer to the foregoing embodiments, and the descriptions thereof are omitted herein.
-
FIG. 4 is a schematic top view of a partial region of a display panel according to another embodiment of the disclosure.FIG. 5 is a schematic cross-sectional view of the display panel inFIG. 4 . It should be particularly noted that, for clarity,FIG. 4 omits illustration of aninsulation layer 110 inFIG. 5 . Referring toFIG. 4 andFIG. 5 , a main difference between thedisplay panel 11 in the present embodiment and thedisplay panel 10 inFIG. 3A lies in different compositions of conductive traces. Specifically, a conductive trace CL-A of thedisplay panel 11 has anextension section 121A and anextension section 123A structurally separated from each other and aconnection portion 122A electrically connected between theextension section 121A and theextension section 123A. In the present embodiment, a step of forming a plurality of conductive traces CL-A may selectively include forming aninsulation layer 110 between the extension section and theconnection portion 122A. In other words, theconnection portion 122A and the extension section of the conductive trace CL-A may belong to different film layers. - For example, in the present embodiment, the
insulation layer 110 covers theextension section 121A and theextension section 123A of the conductive trace CL-A. Theconnection portion 122A of the conductive trace CL-A is disposed on theinsulation layer 110, and two ends of theconnection portion 122A penetrate through theinsulation layer 110 to be electrically connected to theextension section 121A and theextension section 123A, respectively. However, the disclosure is not limited thereto. In other embodiments not shown, the connection portion of the conductive trace may also be disposed between theinsulation layer 110 and thesubstrate 100S, and the two extension sections each penetrate through theinsulation layer 110 to be electrically connected to the connection portion. - It is worth mentioning that, in the present embodiment, resistivities of the two extension sections of the conductive trace CL-A may be smaller than a resistivity of the
connection portion 122A. Therefore, in the breaking step for the conductive trace CL-A, a current flowing through the conductive trace CL-A generates a relatively large amount of heat energy when passing through theconnection portion 122A. As a result, a temperature of theconnection portion 122A increases and exceeds a melting point thereof. In this case, theconnection portion 122A of the conductive trace CL-A is broken and forms a break (not shown). Through the disposed break, an electrical short circuit of the conductive traces CL-A may be avoided during a subsequent cutting process, and a cutting yield of thedisplay panel 11 is thereby improved. -
FIG. 6 is a schematic top view of a partial region of a display panel according to still another embodiment of the disclosure. Referring toFIG. 6 , a difference between a display panel 12 in the present embodiment and thedisplay panel 10 inFIG. 3A lies in different configurations of connection portions of conductive traces. Specifically, a plurality ofconnection portions 122B of a plurality of conductive traces CL-B of the display panel 12 are staggered from each other in a direction (for example, a direction X) in which the bonding pads BP are arranged. In other words, aconnection portion 122B of any of the plurality of conductive traces CL-B may overlap anextension section 121B or anextension section 123B of an adjacent conductive trace CL-B in the direction X. - It should be understood that a plurality of breaks formed by the conductive traces CL-B after a breaking step are also staggered from each other in the direction X (not shown). It is worth mentioning that, through the staggering relationship of the plurality of
connection portions 122B of the plurality of conductive traces CL-B, heat energy generated when a current passes through theconnection portions 122B may be dispersed, and that independent electrical properties of the bonding pads BP are ensured after a cutting step for thesubstrate 100S is completed. - In view of the foregoing, in the method of fabricating the display panel according to an embodiment of the disclosure, in the uncut display panel, the plurality of breaks are provided on the plurality of conductive traces connected between the plurality of bonding pads and the plurality of testing pads. In the cutting step for the substrate, the display panel is cut along the cutting line between the testing pads and the bonding pads to remove these testing pads. The breaks of the conductive traces are disposed between the bonding pads and the cutting line, so that an electrical short circuit of the conductive traces may be avoided during the cutting, a cutting yield of the display panel is thereby improved. Therefore, in the display panel according to an embodiment of the disclosure, each of the plurality of conductive traces extending between the cut substrate edge and the plurality of bonding pads has the breaks.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/937,589 US11327372B2 (en) | 2019-07-26 | 2020-07-24 | Display panel and method of fabricating the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201962878857P | 2019-07-26 | 2019-07-26 | |
TW109109750A TWI770484B (en) | 2019-07-26 | 2020-03-24 | Display panel and method of fabricating the same |
TW109109750 | 2020-03-24 | ||
US16/937,589 US11327372B2 (en) | 2019-07-26 | 2020-07-24 | Display panel and method of fabricating the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20210026182A1 true US20210026182A1 (en) | 2021-01-28 |
US11327372B2 US11327372B2 (en) | 2022-05-10 |
Family
ID=72650595
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/937,589 Active 2040-08-27 US11327372B2 (en) | 2019-07-26 | 2020-07-24 | Display panel and method of fabricating the same |
Country Status (2)
Country | Link |
---|---|
US (1) | US11327372B2 (en) |
CN (1) | CN111736380A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113097094A (en) * | 2021-04-29 | 2021-07-09 | 云谷(固安)科技有限公司 | Substrate to be cut, display panel and preparation method of display panel |
US11379062B2 (en) * | 2019-12-18 | 2022-07-05 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel and testing method thereof |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20230127776A1 (en) * | 2021-08-31 | 2023-04-27 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate and display device |
CN113823643B (en) * | 2021-09-17 | 2024-03-01 | 京东方科技集团股份有限公司 | Array substrate mother board, array substrate, display panel and display device |
CN113903783A (en) * | 2021-09-29 | 2022-01-07 | 深圳市华星光电半导体显示技术有限公司 | Display panel and method for manufacturing the same |
CN114255683B (en) * | 2021-12-21 | 2024-03-22 | 武汉华星光电技术有限公司 | Display panel |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3863261A (en) * | 1973-05-11 | 1975-01-28 | Electroprint Inc | Electrically addressed apertured modulator for electrostatic printing |
JP3634138B2 (en) * | 1998-02-23 | 2005-03-30 | 株式会社 日立ディスプレイズ | Liquid crystal display |
CN101151544B (en) * | 2005-03-28 | 2011-08-03 | 株式会社半导体能源研究所 | Semiconductor device, and method for manufacturing and measuring same |
JP4921769B2 (en) * | 2005-10-25 | 2012-04-25 | 株式会社リコー | Printed wiring board, impedance adjustment method in printed wiring board, electronic device, and image forming apparatus |
JP4982609B2 (en) * | 2008-07-23 | 2012-07-25 | シャープ株式会社 | Active matrix substrate, display device, active matrix substrate inspection method, and display device inspection method |
US20110084589A1 (en) * | 2009-10-13 | 2011-04-14 | General Electric Company | Vibration resistant electric incandescent lamp and method for reducing vibration |
WO2012032661A1 (en) * | 2010-09-11 | 2012-03-15 | パイオニア株式会社 | Organic el panel |
KR101843360B1 (en) | 2010-12-24 | 2018-03-30 | 삼성디스플레이 주식회사 | Array substrate, display apparatus and method of operating the display apparatus |
US9097921B2 (en) * | 2011-07-15 | 2015-08-04 | Sharp Kabushiki Kaisha | Active matrix display device |
WO2013021992A1 (en) * | 2011-08-10 | 2013-02-14 | シャープ株式会社 | Active matrix display device |
CN102768421A (en) * | 2012-07-24 | 2012-11-07 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and manufacturing method thereof |
CN102789076B (en) | 2012-08-01 | 2016-02-03 | 深圳市华星光电技术有限公司 | The method for making of a kind of detection line and display panels |
TWI607267B (en) * | 2012-11-26 | 2017-12-01 | 元太科技工業股份有限公司 | Flexible display apparatus and manufacturing method thereof |
US20160205781A1 (en) * | 2012-11-26 | 2016-07-14 | E Ink Holdings Inc. | Flexible display apparatus and manufacturing method thereof |
KR102203281B1 (en) * | 2014-08-29 | 2021-01-13 | 엘지디스플레이 주식회사 | Display device and method of manufacturing the same |
CN104965321B (en) * | 2015-07-01 | 2018-11-23 | 深圳市华星光电技术有限公司 | display panel detection system and detection method |
CN204884440U (en) * | 2015-08-27 | 2015-12-16 | 京东方科技集团股份有限公司 | Flexible display panel and flexible display device |
KR20190013142A (en) * | 2017-07-31 | 2019-02-11 | 엘지디스플레이 주식회사 | Display apparatus and manufacturing method of the same |
CN107855665B (en) * | 2017-11-15 | 2019-06-04 | 京东方科技集团股份有限公司 | A kind of display panel and its cutting method, display device |
US10707289B2 (en) * | 2018-02-08 | 2020-07-07 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Flexible display panel and flexible display |
CN108565278A (en) * | 2018-02-28 | 2018-09-21 | 京东方科技集团股份有限公司 | Array substrate motherboard, array substrate, display device and preparation method thereof |
CN208722547U (en) | 2018-09-30 | 2019-04-09 | 惠科股份有限公司 | Display panel tests circuit and testing device of display panel |
CN109192117B (en) | 2018-10-18 | 2020-06-30 | 武汉华星光电半导体显示技术有限公司 | Test circuit layout structure of display panel |
CN109638058B (en) * | 2018-12-20 | 2020-06-16 | 武汉华星光电半导体显示技术有限公司 | Manufacturing method of flexible display device and flexible display device |
-
2020
- 2020-06-23 CN CN202010581138.0A patent/CN111736380A/en active Pending
- 2020-07-24 US US16/937,589 patent/US11327372B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11379062B2 (en) * | 2019-12-18 | 2022-07-05 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel and testing method thereof |
CN113097094A (en) * | 2021-04-29 | 2021-07-09 | 云谷(固安)科技有限公司 | Substrate to be cut, display panel and preparation method of display panel |
Also Published As
Publication number | Publication date |
---|---|
CN111736380A (en) | 2020-10-02 |
US11327372B2 (en) | 2022-05-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11327372B2 (en) | Display panel and method of fabricating the same | |
US8816343B2 (en) | Display panel | |
KR101195688B1 (en) | Flexible substrate and electric circuit structure | |
US8446556B2 (en) | Flexible printed circuit and electric circuit structure | |
KR102245304B1 (en) | Display device with power supply in cover type | |
KR101944795B1 (en) | tape film package and manufacturing method of the same | |
TW200919015A (en) | Display device | |
US9929083B2 (en) | Semiconductor packages and package modules using the same | |
JP6427360B2 (en) | Display device | |
US9741753B2 (en) | Array substrate and manufacturing method thereof, and display apparatus thereof | |
US20190103416A1 (en) | Display device and method for manufacturing display device | |
TWI770484B (en) | Display panel and method of fabricating the same | |
JP4786976B2 (en) | WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE | |
JP2001100229A (en) | Liquid crystal display device and method for repairing disconnection thereof | |
CN109407358B (en) | Display panel and repairing method thereof | |
TW201024874A (en) | Thin film transistor array substrate of liquid crystal display module and method for repairing the same | |
JP6762196B2 (en) | Electro-optic display | |
EP4300470A1 (en) | Drive substrate and preparation method therefor, and light-emitting apparatus | |
US20220238771A1 (en) | Array substrate and display device | |
KR102196180B1 (en) | Display device | |
JP2009238926A (en) | Tab tape and method of manufacturing the same | |
US9377641B2 (en) | Tape package and display panel module having the same | |
US11425818B2 (en) | Electronic device | |
JP4442079B2 (en) | Conductive connection structure, electro-optical device, and electronic apparatus | |
JP2010212396A (en) | Electronic device, electro-optical device, and connection structure of substrate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: AU OPTRONICS CORPORATION, TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YU, CHIH-YU;TSAI, YI-WEI;LAN, YUNG-HSIANG;AND OTHERS;REEL/FRAME:053299/0429 Effective date: 20200715 |
|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |