US20200186146A1 - Sampling circuit and sampling method - Google Patents
Sampling circuit and sampling method Download PDFInfo
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- US20200186146A1 US20200186146A1 US16/708,876 US201916708876A US2020186146A1 US 20200186146 A1 US20200186146 A1 US 20200186146A1 US 201916708876 A US201916708876 A US 201916708876A US 2020186146 A1 US2020186146 A1 US 2020186146A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
- G01R19/2506—Arrangements for conditioning or analysing measured signals, e.g. for indicating peak values ; Details concerning sampling, digitizing or waveform capturing
- G01R19/2509—Details concerning sampling, digitizing or waveform capturing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/129—Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling ; Out-of-range indication
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45544—Indexing scheme relating to differential amplifiers the IC comprising one or more capacitors, e.g. coupling capacitors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45551—Indexing scheme relating to differential amplifiers the IC comprising one or more switched capacitors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45586—Indexing scheme relating to differential amplifiers the IC comprising offset generating means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45588—Indexing scheme relating to differential amplifiers the IC comprising offset compensating means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
Definitions
- the present application relates to sampling circuits and sampling methods.
- Sampling circuits are used to sample an analog input signal at specified times, and may be part of an analog-to-digital converter (ADC), for example.
- ADC analog-to-digital converter
- One type of sampling circuit is based on switched capacitors. In this case, a sampling capacitor is connected in a first operating phase (sampling phase) to a signal input, and is connected in a second operating phase (redistribution phase) to a reference voltage, for instance ground.
- this circuit is usually duplicated, i.e. two capacitors are used.
- a differential quantity to be measured may be far smaller than the absolute values of the sampled input quantities.
- a sensing resistor can be used for a current measurement, with the voltage measured differentially across the resistor.
- the voltage drop across such a resistor may be several orders of magnitude smaller than the absolute voltage values that appear at the resistor.
- voltages in the region of 40 V may arise in such cases, whereas a differential voltage across such a sensing resistor lies in the millivolt range.
- a sampling circuit includes a first input, which is configured to receive a first signal; a second input, which is configured to receive a second signal; a first sampling capacitor; a second sampling capacitor; a common-mode signal generating circuit, which is configured to generate a common-mode signal, which corresponds to a common-mode component of the first signal and of the second signal; and a switching circuit, which is configured to couple, in a first operating phase, a first terminal of the first sampling capacitor to the first input, and a first terminal of the second sampling capacitor to the second input, and to couple, in a second operating phase, the first terminal of the first sampling capacitor and the first terminal of the second sampling capacitor to the common-mode signal.
- a sampling method includes in a first operating phase, coupling a first terminal of a first capacitor to a first input signal, and a first terminal of a second capacitor to a second input signal; and in a second operating phase, coupling the first terminal of the first capacitor and the first terminal of the second capacitor to a common-mode signal, which corresponds to a common-mode component of the first signal and of the second signal.
- FIG. 1 is a block diagram of a sampling circuit according to an exemplary embodiment.
- FIG. 2 is a circuit diagram of a sampling circuit according to a further exemplary embodiment
- FIG. 3 is a circuit diagram of a sampling circuit according to a further exemplary embodiment
- FIG. 4 is a circuit diagram of a sampling circuit according to a further exemplary embodiment
- FIG. 5 is a circuit diagram of a sampling circuit according to a further exemplary embodiment
- FIG. 6 is a circuit diagram of a common-mode signal generating circuit for use in various exemplary embodiments.
- FIG. 7 is a flow diagram for illustrating methods according to various exemplary embodiments.
- connections or couplings between components described below are electrical connections or couplings unless stated otherwise. Such connections or couplings may be direct or indirect (i.e., involving additional interposed elements) so long as the fundamental function of the connection or coupling, for instance transferring a signal such as a voltage signal or a current signal, is essentially maintained. In other words, connections or couplings can be modified provided this does not affect their function.
- FIG. 1 shows a block diagram of a sampling circuit according to an exemplary embodiment.
- the sampling circuit of FIG. 1 comprises a first input 11 A and a second input 11 B.
- a first signal S 1 is fed to the input 11 A
- a second signal S 2 is fed to the input 11 B.
- the signals S 1 , 2 S in particular may be voltage signals.
- the signals S 1 , S 2 together form a differential signal, i.e. the signal value represented by the differential signal equals a difference in values (for example voltage values) of the signals S 1 , S 2 .
- the signals S 1 , S 2 are fed to a switching circuit 13 .
- the signals S 1 , S 2 are fed to a common-mode signal generating circuit 12 .
- the common-mode signal generating circuit 12 generates from the signals S 1 , S 2 a common-mode signal cm, which represents a common-mode component of the signals S 1 , S 2 .
- the common-mode component cm to be cm
- the signal S 1 can then also be written as cm+d/2, and the signal S 2 can also be written as cm ⁇ d/2. If the signals S 1 , S 2 are voltage signals, cm is the corresponding common-mode voltage.
- one of the signals S 1 and S 2 may be the actual wanted signal, whereas the other signal, for instance S 2 , may be a corresponding reference potential.
- a first input 15 A of a first sampling capacitor 14 A, and a first input 15 B of a second sampling capacitor 14 B are coupled to the switching circuit 13 .
- the sampling capacitors 14 A, 14 B have the same capacitance values. They can, however, also have different capacitance values.
- the switching circuit 13 is configured to operate the sampling circuit 10 in at least two operating phases.
- the term “operating phase” is used here generally to denote different operating phases of a sampling circuit.
- a first operating phase which corresponds to the sampling phase
- the switching circuit 13 connects the input 11 A to the first input 15 A of the first capacitor 14 A, and the input 11 B to the first terminal 15 B of the second capacitor 14 B.
- the first sampling capacitor 14 A is thereby charged to a voltage corresponding to the first signal S 1
- the second sampling capacitor 14 B is charged to a voltage corresponding to the second signal S 2 .
- the switching circuit 13 decouples the terminals 15 A, 15 B from the inputs 11 A and 11 B respectively, and connects each of them to the common-mode signal cm.
- a sampling circuit is therefore a circuit that is configured to sample one or more input signals. It may also comprise further circuit components for processing the sampled signals, so is not limited to containing just the circuit components needed for the sampling.
- using the common-mode signal cm in the second operating phase can avoid problems that might otherwise arise if the voltage difference S 1 -S 2 is significantly smaller, e.g. at most 1/10 or at least 1/100, than the absolute value of the signals S 1 , S 2 .
- resultant voltage differences can cause problems for subsequent processing circuits such as amplifiers, or there is no fixed sampling time defined.
- processing circuits can be designed for lower maximum voltages than the switching circuit 13 and/or the common-mode signal generating circuit 12 .
- FIG. 2 shows a sampling circuit 20 according to a further exemplary embodiment.
- a sensor 21 which generates differential signals S 1 , S 2 , is shown in FIG. 2 as an example of a source of signals to be sampled.
- the sensor 21 is a sensing resistor for measuring current, and the signals S 1 , S 2 correspond to the voltages at the resistor.
- a difference in the signals S 1 -S 2 then equals the voltage drop across the sensor 21 , which is linked directly to the current flow through the sensor by the resistance of the sensor 21 . This constitutes only a simple example, however, and other signal sources can also be used.
- the resistance value is usually chosen to be as small as possible in order to reduce the power loss. This results in a correspondingly small voltage drop, which may lie in the millivolt range, for instance.
- the absolute values of the voltages of the signals S 1 and S 2 may be significantly higher, however, for example 10 V and above.
- the signals S 1 , S 2 are fed to a common-mode signal generating circuit for generating a common-mode signal cm.
- Said common-mode signal generating circuit in the exemplary embodiment of FIG. 2 comprises a resistive divider circuit comprising resistors 22 A, 22 B connected in series.
- the common-mode signal cm can be tapped at a node between the resistors 22 A, 22 B.
- this signal is additionally buffered by a buffer 23 , with the result that the common-mode signal is output as a buffered signal cmBuf.
- the resistors 22 A and 22 B have the same resistance values, within manufacturing tolerances, in the exemplary embodiment of FIG. 2 .
- the resistors 22 A, 22 B may be selected to be relatively high impedance, for instance having resistance values of several 100 ohms, several kilohms or in the megaohm range, in order to reduce the current flow and thus the power loss.
- a high-impedance implementation of this type also places a relatively low load on the sensor 21 , reducing distortion of the sensor signal, for instance. In the case of a current sensor as described above, for a high-impedance resistive divider, only a small part of the current flows through the resistive divider, so that the sensor 21 continues to measure substantially the entire current.
- the sampling circuit 20 comprises a switching circuit comprising switches 24 A, 24 B, 25 A, 25 B.
- a first operating phase denoted in FIG. 2 by a control signal ⁇ 1
- the switches 24 A, 24 B are in a closed state, and the switches 25 A, 25 B are open.
- first terminals of the sampling capacitors 14 A, 14 B already discussed are connected to the sensor 21 in order to receive the signals S 1 , S 2 , with the result that the sampling capacitor 14 A is charged according to the signal S 1 , and the second sampling capacitor 14 B according to the signal S 2 .
- This phase corresponds to the actual sampling phase.
- a second operating phase identified in FIG. 2 by a control signal ⁇ 2
- the switches 24 A, 24 B are opened, and the switches 25 A, 25 B are closed.
- the first terminals of the sampling capacitors 14 A, 14 B are thereby connected to an output of the buffer 23 and hence to the common-mode signal cm.
- This phase corresponds to the redistribution phase.
- the designations ⁇ 0 , ⁇ 1 , ⁇ 2 etc. are used in this application both for the operating phases and for the corresponding drive signals for the switches during these operating phases.
- the resistive divider 22 A, 22 B can be in the off state during the first operating phase in order to reduce the power loss, because the common-mode signal cm only needs to be generated during the second operating phase in FIG. 2 .
- Second terminals of the sampling capacitors 14 A, 14 B are connected to further circuit components for processing the signals, in the case of FIG. 2 to a differential amplifier 26 .
- Other types of circuits for instance amplifiers having a single-pole output or comparators can also be used.
- common-mode signal cm in the second operating phase can lessen problems that may arise with conventional approaches in subsequent processing, for instance by means of the amplifier 26 .
- this applies in particular to cases in which a voltage difference between the signals S 1 , S 2 is far smaller than the absolute value of the signals S 1 , S 2 , and in conventional approaches this can lead to problems during the subsequent processing, for instance as a result of ground fluctuations.
- the common-mode signal cm is generated continuously, so to speak. In other exemplary embodiments, the common-mode signal cm can additionally be sampled. A corresponding exemplary embodiment is shown in FIG. 3 .
- FIG. 3 The exemplary embodiment of FIG. 3 is based on the exemplary embodiment of FIG. 2 , and identical elements carry the same reference signs.
- a switch 31 and a third sampling capacitor 32 are connected as shown between the resistive divider comprising the resistors 22 A, 22 B and the buffer 23 .
- a ground potential to which the third sampling capacitor 32 is connected is denoted by “gnd a” to distinguish it from a ground potential, denoted by “gnd s” in FIG. 3 , to which the sensor 21 is connected.
- the third sampling capacitor 32 is charged according to the common-mode signal between the resistors 22 A, 22 B.
- the switch 31 is then reopened, and the common-mode signal, which has been charged, so to speak, onto the third sampling capacitor 32 , is processed further by the buffer 23 in order to output the buffered common-mode signal cmBuf.
- the switch 31 can be switched together with the switches 24 A, 24 B.
- the switches 24 A, 24 B are opened sequentially to the switch 31 , which corresponds to sampling the signals S 1 , S 2 at a time offset to the common-mode signal cm.
- the switches 24 A, 24 B can be opened first, and then the switch 31 can be opened in a further operating phase, in accordance with the control signal ⁇ 0 , before the switches 25 A, 25 B are then closed.
- This time-offset sampling can reduce cross-talk between the common-mode signal and the input signals in some implementations.
- using the third sampling capacitor 32 to sample the common-mode voltage can increase the robustness in some exemplary embodiments.
- a time gap between sampling the common-mode signal and sampling in the first operating phase is significantly smaller than a typical timescale at which the common-mode signal changes. This means that any time offset between sampling the common-mode signal and sampling the input signals is essentially negligible in terms of the accuracy of the common-mode signal.
- FIG. 4 shows a sampling circuit 40 according to a further exemplary embodiment.
- switches such as the switches 24 A, 24 B, 25 A, 25 B of the previous exemplary embodiments are implemented as transistors.
- the buffer circuit 23 is also implemented using transistors.
- MOS metal oxide semiconductor
- other types of transistors can also be used, for instance bipolar transistors or IGBT transistors (isolated gate bipolar transistors).
- Transistors are described generically as having a control terminal and two load terminals.
- field effect transistors such as MOS transistors
- the control terminal is the gate terminal
- the load terminals are the source and drain terminals.
- the control terminal is the base terminal
- the load terminals are the collector and emitter terminals.
- IGBTs the control terminal is the gate terminal, and the load terminals are the collector and emitter terminals.
- the sampling circuit 40 of FIG. 4 again comprises a divider circuit.
- this divider circuit is essentially a resistive divider circuit comprising resistors 41 A, 41 B, which are connected in series between the inputs 11 A, 11 B.
- the divider circuit also comprises a diode-connected NMOS transistor 42 A and a diode-connected PMOS transistor 42 B.
- the common-mode signal cm lies at a node between the transistors 42 A, 42 B.
- a diode threshold of the diode-connected transistor 42 A may lie above the common-mode signal cm, whereas a diode threshold of the transistor 42 B may lie below the common-mode signal cm.
- an NMOS transistor 43 A and a PMOS transistor 43 B connected as a complementary source-follower between a voltage VDDMAX and ground are used as the buffer circuit.
- a gate terminal of the transistor 43 A is connected to the gate terminal of the transistor 42 A
- a gate terminal of the transistor 43 B is connected to a gate terminal of the transistor 42 B.
- the transistors 42 A, 42 B thus provide a control voltage for the transistors 43 A, 43 B, so that the buffered common-mode signal cmBuf lies at a node between the transistors 43 A, 43 B.
- the buffered common-mode signal cmBuf corresponds to the common-mode signal cm mirrored by the transistors 42 A, 42 B, 43 A, 43 B.
- the exemplary embodiment of FIG. 4 comprises a PMOS transistor 44 A and an NMOS transistor 44 B, which essentially have the function of the switches 24 A, 24 B from the previous figures, and comprises an NMOS transistor 45 A and a PMOS transistor 45 B, which essentially have the function of the switches 25 A, 25 B of FIGS. 2 and 3 .
- the switches 44 A, 44 B are closed by suitable control signals ⁇ 1 and ⁇ 1 , where ⁇ 1 is the inverted signal of ⁇ 1 , because the transistors are of opposite polarity. First terminals of the sampling capacitors 14 A, 14 B are thereby coupled to the inputs 11 A and 11 B respectively.
- the transistors 44 A, 44 B are then opened, and the transistors 45 A, 45 B are closed by suitable control signals ⁇ 2 , ⁇ 2 , in order to connect the first terminals of the sampling capacitors 14 A, 14 B to the buffered common-mode signal cmBuf.
- Control signals for the transistors 44 A, 44 B, 45 A, 45 B can be generated in this case by means of a controller contained in the switching circuit 13 .
- This controller can comprise an oscillator for generating a clock, and level converters for generating control signals at suitable signal levels.
- the divider circuit in the case of FIG. 4 the divider circuits 41 A, 41 B, 42 A, 42 B
- the divider circuit can be switched off to lower the power consumption.
- the common-mode signal cm is not needed after opening the switch 31 of FIG. 3 until a next sampling.
- sampling of the common-mode signal can be facilitated.
- FIG. 5 A corresponding exemplary embodiment is shown in FIG. 5 .
- a sampling circuit 50 of FIG. 5 is based on the sampling circuit 40 of FIG. 4 , and identical or corresponding elements carry the same reference signs and are not described again.
- the sampling circuit 50 of FIG. 5 comprises switches 51 A, 51 B.
- the switch 51 A is coupled between gate and drain of the transistor 42 A
- the switch 51 B is coupled between gate and drain of the transistor 42 B.
- a switch 52 is coupled between the gate terminals of the transistors 42 A, 42 B.
- a third sampling capacitor 53 A is coupled between the gate terminal of the transistor 42 B and ground
- a fourth sampling capacitor 53 B is coupled between the gate terminal of the transistor 42 A and ground. If the switches 51 A, 51 B are closed, and the switch 52 is open, the sampling capacitors 53 A, 53 B are pre-charged to corresponding gate voltages, which then after the switches 51 A, 51 B are opened and the switch 52 is closed, drive the buffer circuit 43 A, 43 B suitably to output the buffered common-mode signal cmBuf. If the switches 51 A, 51 B are open and the switch 52 closed, in addition the divider circuit is disabled, and therefore no current can flow here. Said disabling of the divider circuit can also be provided independently of the sampling by means of the sampling capacitors 53 A, 53 B.
- Resistive divider circuits are used in the exemplary embodiments discussed with reference to FIGS. 2-5 .
- FIG. 6 shows a common-mode signal generating circuit 60 according to such an exemplary embodiment. This common-mode signal generating circuit of FIG. 6 can replace the resistive divider circuit of FIG. 3 , for example. It is also possible for the other exemplary embodiments shown in FIGS. 2, 4, and 5 to use corresponding capacitive divider circuits instead of resistive divider circuits.
- FIG. 6 shows only the common-mode signal generating circuit 60 itself. Other components of a sampling circuit can be implemented as described with reference to FIGS. 1-5 .
- the common-mode signal generating circuit 60 of FIG. 6 comprises a capacitive divider, which comprises a first capacitor 62 A and a second capacitor 62 B, which are coupled in series between the signals S 1 and S 2 in order to generate the common-mode signal cm.
- the capacitors 62 A, 62 B have the same capacitance values, within manufacturing tolerances.
- the capacitors 62 A, 62 B are connected to switches 63 A, 63 B, which are used for initializing the circuit of FIG. 6 .
- the capacitors 62 A, 62 B are discharged when these switches 63 A, 63 B are closed in an additional initialization phase, identified by a control signal ⁇ i.
- initialization can also be performed by charging the capacitors 62 A, 62 B to a predetermined voltage.
- a switch 61 is then closed while the previously discussed switch 31 is open. This produces the common-mode signal cm at a node between the capacitors 62 A, 62 B.
- the switch 61 is then opened, and the switch 31 closed, whereby the common-mode signal cm, as already discussed, serves to charge the third sampling capacitor 32 .
- a downstream buffer 23 again generates the buffered common-mode signal cmBuf.
- FIG. 7 shows a flow diagram for illustrating methods according to various exemplary embodiments.
- FIG. 7 can be implemented by the previously discussed sampling circuits of FIGS. 1-6 , and is described with reference to these figures. Variations and modifications that were described for the sampling circuits are also correspondingly applicable to the method of FIG. 7 .
- a first and a second sampling capacitor are coupled to corresponding signal inputs.
- the sampling capacitors 14 A, 14 B are coupled to the corresponding inputs 11 A, 11 B.
- the capacitors are coupled to a common-mode signal, which corresponds to a common-mode component of signals lying at the inputs, for instance corresponds to the common-mode component cm or the buffered common-mode component cmBuf.
- a sampling circuit ( 10 ; 20 ; 30 ; 40 ; 50 ), comprising:
- a first input 11 A, which is configured to receive a first signal (S 1 );
- a second input 11 B, which is configured to receive a second signal (S 2 );
- a common-mode signal generating circuit ( 12 ; 22 A, 22 B, 23 ; 31 , 32 ; 41 A, 41 B, 42 A, 42 B, 43 A, 43 B, 45 A, 45 B; 51 A; 51 B; 52 ; 53 A; 53 B; 60 , 61 , 62 A, 62 B, 63 A, 63 B), which is configured to generate a common-mode signal (cm), which corresponds to a common-mode component of the first signal (S 1 ) and of the second signal (S 2 ); and
- a switching circuit ( 13 ; 24 A, 24 B, 25 A, 25 B; 44 A, 44 B), which is configured to couple, in a first operating phase, a first terminal ( 15 A) of the first sampling capacitor ( 14 A) to the first input ( 11 A), and a first terminal ( 15 B) of the second sampling capacitor ( 14 B) to the second input ( 11 B), and in a second operating phase, to couple the first terminal of the first sampling capacitor ( 14 A) and the first terminal of the second sampling capacitor ( 14 B) to the common-mode signal (cm).
- Example 2 The sampling circuit ( 10 ; 20 ; 30 ; 40 ; 50 ) according to Example 1, wherein the switching circuit ( 13 ; 24 A, 24 B, 25 A, 25 B; 44 A, 44 B) is configured to decouple the first terminal ( 15 A) of the first sampling capacitor ( 14 A) from the first input ( 11 A), and to decouple the first terminal ( 15 B) of the second sampling capacitor ( 14 B) from the second input ( 11 B), in the second operating phase.
- Example 3 The sampling circuit ( 10 ; 20 ; 30 ; 40 ; 50 ) according to Example 1 or 2, wherein the common-mode signal generating circuit ( 12 ; 22 A, 22 B, 23 ; 31 , 32 ; 41 A, 41 B, 42 A, 42 B, 43 A, 43 B, 45 A, 45 B; 51 A; 51 B; 52 ; 53 A; 53 B; 60 , 61 , 62 A, 62 B, 63 A, 63 B) is configured to sample the common-mode signal (cm) and to provide the sampled common-mode signal to the switching circuit ( 13 ; 24 A, 24 B, 25 A, 25 B; 44 A, 44 B).
- the common-mode signal generating circuit 12 ; 22 A, 22 B, 23 ; 31 , 32 ; 41 A, 41 B, 42 A, 42 B, 43 A, 43 B, 45 A, 45 B; 51 A; 51 B; 52 ; 53 A; 53 B; 60 , 61 , 62 A, 62 B, 63 A,
- Example 4 The sampling circuit ( 10 ; 20 ; 30 ; 40 ; 50 ) according to Example 3, wherein for the purpose of sampling the common-mode signal (cm), the common-mode signal generating circuit ( 12 ; 22 A, 22 B, 23 ; 31 , 32 ; 41 A, 41 B, 42 A, 42 B, 43 A, 43 B, 45 A, 45 B; 51 A; 51 B; 52 ; 53 A; 53 B; 60 , 61 , 62 A, 62 B, 63 A, 63 B) comprises at least one third sampling capacitor ( 32 ; 53 A, 53 B).
- Example 5 The sampling circuit ( 10 ; 20 ; 30 ; 40 ; 50 ) according to any of Examples 1 to 4, wherein the common-mode signal generating circuit ( 12 ; 22 A, 22 B, 23 ; 31 , 32 ; 41 A, 41 B, 42 A, 42 B, 43 A, 43 B, 45 A, 45 B; 51 A; 51 B; 52 ; 53 A; 53 B; 60 , 61 , 62 A, 62 B, 63 A, 63 B) comprises a divider circuit ( 22 A, 22 B; 41 A, 41 B, 42 A, 42 B, 43 A, 43 B; 62 A, 62 B; 63 A; 63 B) coupled between the first input ( 11 A) and the second input ( 11 B).
- the common-mode signal generating circuit ( 12 ; 22 A, 22 B, 23 ; 31 , 32 ; 41 A, 41 B, 42 A, 42 B, 43 A, 43 B, 45 A, 45 B; 51 A; 51 B; 52 ; 53 A; 53 B; 60
- Example 6 The sampling circuit ( 10 ; 20 ; 30 ; 40 ; 50 ) according to Example 5, wherein the common-mode signal generating circuit ( 12 ; 22 A, 22 B, 23 ; 31 , 32 ; 41 A, 41 B, 42 A, 42 B, 43 A, 43 B, 45 A, 45 B; 51 A; 51 B; 52 ; 53 A; 53 B; 60 , 61 , 62 A, 62 B, 63 A, 63 B) comprises a buffer circuit ( 23 ; 43 A, 43 B) coupled to an output node of the divider circuit ( 22 A, 22 B; 41 A, 41 B, 42 A, 42 B, 43 A, 43 B; 62 A, 62 B; 63 A; 63 B).
- Example 7 The sampling circuit ( 10 ; 20 ; 30 ; 40 ; 50 ) according to Example 5 or 6, wherein the divider circuit ( 22 A, 22 B; 41 A, 41 B, 42 A, 42 B, 43 A, 43 B) comprises a resistive divider circuit.
- Example 8 The sampling circuit ( 50 ) according to Example 6, wherein the divider circuit ( 41 A, 41 B, 42 A, 42 B, 43 A, 43 B) comprises a series circuit composed of a first resistor ( 41 A), a first diode-connected transistor ( 42 A), a second diode-connected transistor ( 42 B) and a second resistor ( 41 B), which series circuit is coupled between the first input ( 11 A) and the second input ( 11 B).
- Example 9 The sampling circuit ( 50 ) according to Example 8, wherein the divider circuit ( 41 A, 41 B, 42 A, 42 B, 43 A, 43 B) comprises a third transistor ( 43 A) and a fourth transistor ( 43 B), wherein a control terminal of the third transistor ( 43 A) is connected to a control terminal of the first diode-connected transistor ( 42 A), and wherein a control terminal of the fourth transistor ( 43 B) is connected to a control terminal of the second diode-connected transistor ( 42 B).
- Example 10 The sampling circuit according to Example 5 or 6, wherein the divider circuit ( 62 A, 62 B; 63 A, 63 B) comprises a capacitive divider circuit.
- Example 11 The sampling circuit according to Example 10, wherein the divider circuit ( 62 A, 62 B; 63 A; 63 B) comprises a series circuit composed of a first capacitor ( 62 A) and a second capacitor ( 62 B), which series circuit is coupled between the first input ( 11 A) and the second input ( 11 B), and an initialization circuit ( 63 A, 63 B) for initializing the first capacitor ( 62 A) and the second capacitor ( 62 B).
- Example 12 The sampling circuit ( 10 ; 20 ; 30 ; 40 ; 50 ) according to any of Examples 1 to 11, further comprising a processing circuit ( 26 ), which is coupled to a second terminal of the first capacitor ( 14 A) and to a second terminal of the second capacitor ( 14 B), wherein the processing circuit is designed for a lower maximum voltage than the common-mode signal generating circuit ( 12 ; 22 A, 22 B, 23 ; 31 , 32 ; 41 A, 41 B, 42 A, 42 B, 43 A, 43 B, 45 A, 45 B; 51 A; 51 B; 52 ; 53 A; 53 B; 60 , 61 , 62 A, 62 B, 63 A, 63 B) and/or the switching circuit ( 13 ; 24 A, 24 B, 25 A, 25 B; 44 A, 44 B).
- a processing circuit 26
- the processing circuit is designed for a lower maximum voltage than the common-mode signal generating circuit ( 12 ; 22 A, 22 B, 23 ; 31 , 32 ; 41 A, 41 B
- Example 13 The sampling circuit ( 10 ; 20 ; 30 ; 40 ; 50 ) according to any of Examples 1-12, wherein the common-mode signal generating circuit ( 12 ; 22 A, 22 B, 23 ; 31 , 32 ; 41 A, 41 B, 42 A, 42 B, 43 A, 43 B, 45 A, 45 B; 51 A; 51 B; 52 ; 53 A; 53 B; 60 , 61 , 62 A, 62 B, 63 A, 63 B) can be disabled.
- Example 14 A sampling method, comprising:
- Example 15 The sampling method according to Example 14, further comprising sampling the common-mode signal (cm), wherein in the second operating phase, the first terminal of the first capacitor ( 14 A) and the first terminal of the second capacitor ( 14 B) are coupled to the sampled input signal.
- Example 16 The sampling method according to Example 14 or 15, further comprising generating the common-mode signal (cm) using a divider circuit ( 22 A, 22 B; 41 A, 41 B, 42 A, 42 B, 43 A, 43 B; 62 A, 62 B; 63 A; 63 B), to which the first signal (S 1 ) and the second signal (S 2 ) are fed.
- a divider circuit 22 A, 22 B; 41 A, 41 B, 42 A, 42 B, 43 A, 43 B; 62 A, 62 B; 63 A; 63 B
- Example 17 The sampling method according to any of Examples 14-16, wherein a difference in the signal value of the first input signal and of the second input signal is less than 1/10 of a signal value of the first input signal and of the second input signal.
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Abstract
Description
- This application claims the benefit of German Patent Application No. 102018131711.5, filed on Dec. 11, 2018, which application is hereby incorporated herein by reference in its entirety.
- The present application relates to sampling circuits and sampling methods.
- Sampling circuits are used to sample an analog input signal at specified times, and may be part of an analog-to-digital converter (ADC), for example. One type of sampling circuit is based on switched capacitors. In this case, a sampling capacitor is connected in a first operating phase (sampling phase) to a signal input, and is connected in a second operating phase (redistribution phase) to a reference voltage, for instance ground.
- In the case of differential sampling circuits, this circuit is usually duplicated, i.e. two capacitors are used.
- In differential sampling circuits of this type, a differential quantity to be measured, for instance a differential voltage, may be far smaller than the absolute values of the sampled input quantities. For example, a sensing resistor can be used for a current measurement, with the voltage measured differentially across the resistor. The voltage drop across such a resistor may be several orders of magnitude smaller than the absolute voltage values that appear at the resistor. For example in automotive applications, voltages in the region of 40 V may arise in such cases, whereas a differential voltage across such a sensing resistor lies in the millivolt range.
- According to an exemplary embodiment, a sampling circuit includes a first input, which is configured to receive a first signal; a second input, which is configured to receive a second signal; a first sampling capacitor; a second sampling capacitor; a common-mode signal generating circuit, which is configured to generate a common-mode signal, which corresponds to a common-mode component of the first signal and of the second signal; and a switching circuit, which is configured to couple, in a first operating phase, a first terminal of the first sampling capacitor to the first input, and a first terminal of the second sampling capacitor to the second input, and to couple, in a second operating phase, the first terminal of the first sampling capacitor and the first terminal of the second sampling capacitor to the common-mode signal.
- According to a further exemplary embodiment, a sampling method includes in a first operating phase, coupling a first terminal of a first capacitor to a first input signal, and a first terminal of a second capacitor to a second input signal; and in a second operating phase, coupling the first terminal of the first capacitor and the first terminal of the second capacitor to a common-mode signal, which corresponds to a common-mode component of the first signal and of the second signal.
- The above summary merely provides a brief overview of some exemplary embodiments and is not intended to be limiting.
-
FIG. 1 is a block diagram of a sampling circuit according to an exemplary embodiment. -
FIG. 2 is a circuit diagram of a sampling circuit according to a further exemplary embodiment; -
FIG. 3 is a circuit diagram of a sampling circuit according to a further exemplary embodiment; -
FIG. 4 is a circuit diagram of a sampling circuit according to a further exemplary embodiment; -
FIG. 5 is a circuit diagram of a sampling circuit according to a further exemplary embodiment; -
FIG. 6 is a circuit diagram of a common-mode signal generating circuit for use in various exemplary embodiments; and -
FIG. 7 is a flow diagram for illustrating methods according to various exemplary embodiments. - Various exemplary embodiments are explained in detail below. This explanation is purely illustrative and not intended to be limiting. It should be noted in particular that further exemplary embodiments may also have fewer features than the explicitly shown and described exemplary embodiments. Further features, for instance further components, in particular components used in conventional sampling circuits, may also be provided in addition to the explicitly described features.
- Features of different exemplary embodiments can be combined with one another to form further exemplary embodiments. Modifications and variations described for one of the exemplary embodiments are also applicable to other exemplary embodiments unless explicitly stated otherwise.
- Couplings or connections between components described below are electrical connections or couplings unless stated otherwise. Such connections or couplings may be direct or indirect (i.e., involving additional interposed elements) so long as the fundamental function of the connection or coupling, for instance transferring a signal such as a voltage signal or a current signal, is essentially maintained. In other words, connections or couplings can be modified provided this does not affect their function.
-
FIG. 1 shows a block diagram of a sampling circuit according to an exemplary embodiment. The sampling circuit ofFIG. 1 comprises afirst input 11A and asecond input 11B. During operation, a first signal S1 is fed to theinput 11A, and a second signal S2 is fed to theinput 11B. The signals S1, 2S in particular may be voltage signals. In some exemplary embodiments, the signals S1, S2 together form a differential signal, i.e. the signal value represented by the differential signal equals a difference in values (for example voltage values) of the signals S1, S2. - In the
sampling circuit 10 ofFIG. 1 , the signals S1, S2 are fed to aswitching circuit 13. In addition, the signals S1, S2 are fed to a common-modesignal generating circuit 12. The common-modesignal generating circuit 12 generates from the signals S1, S2 a common-mode signal cm, which represents a common-mode component of the signals S1, S2. For example, the differential signal d, which is formed by the signals S1, S2, can be considered to be d=S1−S2, and the common-mode component cm to be cm=|(S1+S2)/2|. The signal S1 can then also be written as cm+d/2, and the signal S2 can also be written as cm−d/2. If the signals S1, S2 are voltage signals, cm is the corresponding common-mode voltage. - It should be noted that for other exemplary embodiments, one of the signals S1 and S2, for instance S1, may be the actual wanted signal, whereas the other signal, for instance S2, may be a corresponding reference potential.
- A
first input 15A of afirst sampling capacitor 14A, and afirst input 15B of asecond sampling capacitor 14B are coupled to theswitching circuit 13. In exemplary embodiments, thesampling capacitors - The
switching circuit 13 is configured to operate thesampling circuit 10 in at least two operating phases. The term “operating phase” is used here generally to denote different operating phases of a sampling circuit. In a first operating phase, which corresponds to the sampling phase, theswitching circuit 13 connects theinput 11A to thefirst input 15A of thefirst capacitor 14A, and theinput 11B to thefirst terminal 15B of thesecond capacitor 14B. Thefirst sampling capacitor 14A is thereby charged to a voltage corresponding to the first signal S1, and thesecond sampling capacitor 14B is charged to a voltage corresponding to the second signal S2. - In a second operating phase, which corresponds to the redistribution phase, the
switching circuit 13 decouples theterminals inputs second terminals capacitors capacitors - Within the meaning of the present application, a sampling circuit is therefore a circuit that is configured to sample one or more input signals. It may also comprise further circuit components for processing the sampled signals, so is not limited to containing just the circuit components needed for the sampling.
- For some exemplary embodiments, using the common-mode signal cm in the second operating phase can avoid problems that might otherwise arise if the voltage difference S1-S2 is significantly smaller, e.g. at most 1/10 or at least 1/100, than the absolute value of the signals S1, S2. In conventional approaches, resultant voltage differences can cause problems for subsequent processing circuits such as amplifiers, or there is no fixed sampling time defined. In some exemplary embodiments, such processing circuits can be designed for lower maximum voltages than the
switching circuit 13 and/or the common-modesignal generating circuit 12. - Further implementation options for sampling circuits are discussed below with reference to
FIGS. 2-6 . To avoid repetition, each discussion refers to the description of the preceding figures, and identical or corresponding elements carry the same reference signs and are not explained repeatedly in detail. -
FIG. 2 shows asampling circuit 20 according to a further exemplary embodiment. Asensor 21, which generates differential signals S1, S2, is shown inFIG. 2 as an example of a source of signals to be sampled. In a simple example, thesensor 21 is a sensing resistor for measuring current, and the signals S1, S2 correspond to the voltages at the resistor. A difference in the signals S1-S2 then equals the voltage drop across thesensor 21, which is linked directly to the current flow through the sensor by the resistance of thesensor 21. This constitutes only a simple example, however, and other signal sources can also be used. - In the case of such sensing resistors, the resistance value is usually chosen to be as small as possible in order to reduce the power loss. This results in a correspondingly small voltage drop, which may lie in the millivolt range, for instance. The absolute values of the voltages of the signals S1 and S2 may be significantly higher, however, for example 10 V and above.
- In the exemplary embodiment of
FIG. 2 , the signals S1, S2 are fed to a common-mode signal generating circuit for generating a common-mode signal cm. Said common-mode signal generating circuit in the exemplary embodiment ofFIG. 2 comprises a resistive dividercircuit comprising resistors resistors FIG. 2 , this signal is additionally buffered by abuffer 23, with the result that the common-mode signal is output as a buffered signal cmBuf. - The
resistors FIG. 2 . Theresistors sensor 21, reducing distortion of the sensor signal, for instance. In the case of a current sensor as described above, for a high-impedance resistive divider, only a small part of the current flows through the resistive divider, so that thesensor 21 continues to measure substantially the entire current. - In addition, the
sampling circuit 20 comprises a switchingcircuit comprising switches FIG. 2 by a control signal ϕ1, theswitches switches sampling capacitors sensor 21 in order to receive the signals S1, S2, with the result that thesampling capacitor 14A is charged according to the signal S1, and thesecond sampling capacitor 14B according to the signal S2. This phase corresponds to the actual sampling phase. - In a second operating phase, identified in
FIG. 2 by a control signal ϕ2, theswitches switches sampling capacitors buffer 23 and hence to the common-mode signal cm. This phase corresponds to the redistribution phase. The designations ϕ0, ϕ1, ϕ2 etc. are used in this application both for the operating phases and for the corresponding drive signals for the switches during these operating phases. - It should be noted that for some exemplary embodiments, the
resistive divider FIG. 2 . - Second terminals of the
sampling capacitors FIG. 2 to adifferential amplifier 26. Other types of circuits, for instance amplifiers having a single-pole output or comparators can also be used. - Using the common-mode signal cm in the second operating phase (redistribution phase) can lessen problems that may arise with conventional approaches in subsequent processing, for instance by means of the
amplifier 26. As already explained with reference toFIG. 1 , this applies in particular to cases in which a voltage difference between the signals S1, S2 is far smaller than the absolute value of the signals S1, S2, and in conventional approaches this can lead to problems during the subsequent processing, for instance as a result of ground fluctuations. - In the exemplary embodiment of
FIG. 2 , the common-mode signal cm is generated continuously, so to speak. In other exemplary embodiments, the common-mode signal cm can additionally be sampled. A corresponding exemplary embodiment is shown inFIG. 3 . - The exemplary embodiment of
FIG. 3 is based on the exemplary embodiment ofFIG. 2 , and identical elements carry the same reference signs. In addition to the components ofFIG. 2 , aswitch 31 and athird sampling capacitor 32 are connected as shown between the resistive divider comprising theresistors buffer 23. A ground potential to which thethird sampling capacitor 32 is connected is denoted by “gnd a” to distinguish it from a ground potential, denoted by “gnd s” inFIG. 3 , to which thesensor 21 is connected. - By closing the
switch 31 in accordance with a control signal ϕ0, thethird sampling capacitor 32 is charged according to the common-mode signal between theresistors switch 31 is then reopened, and the common-mode signal, which has been charged, so to speak, onto thethird sampling capacitor 32, is processed further by thebuffer 23 in order to output the buffered common-mode signal cmBuf. - The
switch 31 can be switched together with theswitches switches switch 31, which corresponds to sampling the signals S1, S2 at a time offset to the common-mode signal cm. For example in one implementation, theswitches switch 31 can be opened in a further operating phase, in accordance with the control signal ϕ0, before theswitches - This time-offset sampling can reduce cross-talk between the common-mode signal and the input signals in some implementations. Overall, using the
third sampling capacitor 32 to sample the common-mode voltage can increase the robustness in some exemplary embodiments. - It should be noted that in exemplary embodiments, a time gap between sampling the common-mode signal and sampling in the first operating phase, i.e. sampling the input signals, is significantly smaller than a typical timescale at which the common-mode signal changes. This means that any time offset between sampling the common-mode signal and sampling the input signals is essentially negligible in terms of the accuracy of the common-mode signal.
-
FIG. 4 shows asampling circuit 40 according to a further exemplary embodiment. - In the
sampling circuit 40, switches such as theswitches buffer circuit 23 is also implemented using transistors. In the exemplary embodiment ofFIG. 4 , MOS (metal oxide semiconductor) field effect transistors are used. In other exemplary embodiments, other types of transistors can also be used, for instance bipolar transistors or IGBT transistors (isolated gate bipolar transistors). Transistors are described generically as having a control terminal and two load terminals. In the case of field effect transistors such as MOS transistors, the control terminal is the gate terminal, and the load terminals are the source and drain terminals. In the case of bipolar transistors, the control terminal is the base terminal, and the load terminals are the collector and emitter terminals. In the case of IGBTs, the control terminal is the gate terminal, and the load terminals are the collector and emitter terminals. - In order to generate a common-mode signal cm, the
sampling circuit 40 ofFIG. 4 again comprises a divider circuit. In the case ofFIG. 4 , this divider circuit is essentially a resistive dividercircuit comprising resistors inputs NMOS transistor 42A and a diode-connectedPMOS transistor 42B. The common-mode signal cm lies at a node between thetransistors - A diode threshold of the diode-connected
transistor 42A may lie above the common-mode signal cm, whereas a diode threshold of thetransistor 42B may lie below the common-mode signal cm. - In the exemplary embodiment of
FIG. 4 , anNMOS transistor 43A and aPMOS transistor 43B connected as a complementary source-follower between a voltage VDDMAX and ground are used as the buffer circuit. A gate terminal of thetransistor 43A is connected to the gate terminal of thetransistor 42A, and a gate terminal of thetransistor 43B is connected to a gate terminal of thetransistor 42B. Thetransistors transistors transistors transistors - In addition, the exemplary embodiment of
FIG. 4 comprises aPMOS transistor 44A and anNMOS transistor 44B, which essentially have the function of theswitches NMOS transistor 45A and aPMOS transistor 45B, which essentially have the function of theswitches FIGS. 2 and 3 . In the first operating phase already discussed, theswitches ϕ1 , whereϕ1 is the inverted signal of ϕ1, because the transistors are of opposite polarity. First terminals of thesampling capacitors inputs transistors transistors ϕ2 , in order to connect the first terminals of thesampling capacitors - Control signals for the
transistors circuit 13. This controller can comprise an oscillator for generating a clock, and level converters for generating control signals at suitable signal levels. - When the sampling circuit is not needed or there is no need to generate the common-mode signal cm, in some exemplary embodiments, the divider circuit (in the case of
FIG. 4 thedivider circuits switch 31 ofFIG. 3 until a next sampling. In addition, including in an exemplary embodiment such as the exemplary embodiment ofFIG. 4 , sampling of the common-mode signal can be facilitated. A corresponding exemplary embodiment is shown inFIG. 5 . Asampling circuit 50 ofFIG. 5 is based on thesampling circuit 40 ofFIG. 4 , and identical or corresponding elements carry the same reference signs and are not described again. - As an addition to the
sampling circuit 40 ofFIG. 4 , thesampling circuit 50 ofFIG. 5 comprisesswitches switch 51A is coupled between gate and drain of thetransistor 42A, and theswitch 51B is coupled between gate and drain of thetransistor 42B. In addition, aswitch 52 is coupled between the gate terminals of thetransistors - A
third sampling capacitor 53A is coupled between the gate terminal of thetransistor 42B and ground, and afourth sampling capacitor 53B is coupled between the gate terminal of thetransistor 42A and ground. If theswitches switch 52 is open, thesampling capacitors switches switch 52 is closed, drive thebuffer circuit switches switch 52 closed, in addition the divider circuit is disabled, and therefore no current can flow here. Said disabling of the divider circuit can also be provided independently of the sampling by means of thesampling capacitors - Resistive divider circuits are used in the exemplary embodiments discussed with reference to
FIGS. 2-5 . In other exemplary embodiments, it is also possible to use a capacitive divider circuit for generating the common-mode signal cm.FIG. 6 shows a common-mode signal generating circuit 60 according to such an exemplary embodiment. This common-mode signal generating circuit ofFIG. 6 can replace the resistive divider circuit ofFIG. 3 , for example. It is also possible for the other exemplary embodiments shown inFIGS. 2, 4, and 5 to use corresponding capacitive divider circuits instead of resistive divider circuits. -
FIG. 6 shows only the common-mode signal generating circuit 60 itself. Other components of a sampling circuit can be implemented as described with reference toFIGS. 1-5 . - The common-mode signal generating circuit 60 of
FIG. 6 comprises a capacitive divider, which comprises afirst capacitor 62A and asecond capacitor 62B, which are coupled in series between the signals S1 and S2 in order to generate the common-mode signal cm. In the exemplary embodiment ofFIG. 6 , thecapacitors - The
capacitors switches FIG. 6 . Thecapacitors switches capacitors - In order to generate the common-mode signal cm, a
switch 61 is then closed while the previously discussedswitch 31 is open. This produces the common-mode signal cm at a node between thecapacitors switch 61 is then opened, and theswitch 31 closed, whereby the common-mode signal cm, as already discussed, serves to charge thethird sampling capacitor 32. Adownstream buffer 23 again generates the buffered common-mode signal cmBuf. -
FIG. 7 shows a flow diagram for illustrating methods according to various exemplary embodiments. - The method of
FIG. 7 can be implemented by the previously discussed sampling circuits ofFIGS. 1-6 , and is described with reference to these figures. Variations and modifications that were described for the sampling circuits are also correspondingly applicable to the method ofFIG. 7 . - In 70 of the method of
FIG. 7 , in a first operating phase, a first and a second sampling capacitor are coupled to corresponding signal inputs. For example, thesampling capacitors inputs - In 71, in a second operating phase, the capacitors are coupled to a common-mode signal, which corresponds to a common-mode component of signals lying at the inputs, for instance corresponds to the common-mode component cm or the buffered common-mode component cmBuf.
- In other respects, the explanations relating to the devices of
FIGS. 1-6 apply correspondingly to the method ofFIG. 7 . - The following examples define some exemplary embodiments:
- Example 1. A sampling circuit (10; 20; 30; 40; 50), comprising:
- a first input (11A), which is configured to receive a first signal (S1);
- a second input (11B), which is configured to receive a second signal (S2);
- a first sampling capacitor (14A);
- a second sampling capacitor (14B);
- a common-mode signal generating circuit (12; 22A, 22B, 23; 31, 32; 41A, 41B, 42A, 42B, 43A, 43B, 45A, 45B; 51A; 51B; 52; 53A; 53B; 60, 61, 62A, 62B, 63A, 63B), which is configured to generate a common-mode signal (cm), which corresponds to a common-mode component of the first signal (S1) and of the second signal (S2); and
- a switching circuit (13; 24A, 24B, 25A, 25B; 44A, 44B), which is configured to couple, in a first operating phase, a first terminal (15A) of the first sampling capacitor (14A) to the first input (11A), and a first terminal (15B) of the second sampling capacitor (14B) to the second input (11B), and in a second operating phase, to couple the first terminal of the first sampling capacitor (14A) and the first terminal of the second sampling capacitor (14B) to the common-mode signal (cm).
- Example 2. The sampling circuit (10; 20; 30; 40; 50) according to Example 1, wherein the switching circuit (13; 24A, 24B, 25A, 25B; 44A, 44B) is configured to decouple the first terminal (15A) of the first sampling capacitor (14A) from the first input (11A), and to decouple the first terminal (15B) of the second sampling capacitor (14B) from the second input (11B), in the second operating phase.
- Example 3. The sampling circuit (10; 20; 30; 40; 50) according to Example 1 or 2, wherein the common-mode signal generating circuit (12; 22A, 22B, 23; 31, 32; 41A, 41B, 42A, 42B, 43A, 43B, 45A, 45B; 51A; 51B; 52; 53A; 53B; 60, 61, 62A, 62B, 63A, 63B) is configured to sample the common-mode signal (cm) and to provide the sampled common-mode signal to the switching circuit (13; 24A, 24B, 25A, 25B; 44A, 44B).
- Example 4. The sampling circuit (10; 20; 30; 40; 50) according to Example 3, wherein for the purpose of sampling the common-mode signal (cm), the common-mode signal generating circuit (12; 22A, 22B, 23; 31, 32; 41A, 41B, 42A, 42B, 43A, 43B, 45A, 45B; 51A; 51B; 52; 53A; 53B; 60, 61, 62A, 62B, 63A, 63B) comprises at least one third sampling capacitor (32; 53A, 53B).
- Example 5. The sampling circuit (10; 20; 30; 40; 50) according to any of Examples 1 to 4, wherein the common-mode signal generating circuit (12; 22A, 22B, 23; 31, 32; 41A, 41B, 42A, 42B, 43A, 43B, 45A, 45B; 51A; 51B; 52; 53A; 53B; 60, 61, 62A, 62B, 63A, 63B) comprises a divider circuit (22A, 22B; 41A, 41B, 42A, 42B, 43A, 43B; 62A, 62B; 63A; 63B) coupled between the first input (11A) and the second input (11B).
- Example 6. The sampling circuit (10; 20; 30; 40; 50) according to Example 5, wherein the common-mode signal generating circuit (12; 22A, 22B, 23; 31, 32; 41A, 41B, 42A, 42B, 43A, 43B, 45A, 45B; 51A; 51B; 52; 53A; 53B; 60, 61, 62A, 62B, 63A, 63B) comprises a buffer circuit (23; 43A, 43B) coupled to an output node of the divider circuit (22A, 22B; 41A, 41B, 42A, 42B, 43A, 43B; 62A, 62B; 63A; 63B).
- Example 7. The sampling circuit (10; 20; 30; 40; 50) according to Example 5 or 6, wherein the divider circuit (22A, 22B; 41A, 41B, 42A, 42B, 43A, 43B) comprises a resistive divider circuit.
- Example 8. The sampling circuit (50) according to Example 6, wherein the divider circuit (41A, 41B, 42A, 42B, 43A, 43B) comprises a series circuit composed of a first resistor (41A), a first diode-connected transistor (42A), a second diode-connected transistor (42B) and a second resistor (41B), which series circuit is coupled between the first input (11A) and the second input (11B).
- Example 9. The sampling circuit (50) according to Example 8, wherein the divider circuit (41A, 41B, 42A, 42B, 43A, 43B) comprises a third transistor (43A) and a fourth transistor (43B), wherein a control terminal of the third transistor (43A) is connected to a control terminal of the first diode-connected transistor (42A), and wherein a control terminal of the fourth transistor (43B) is connected to a control terminal of the second diode-connected transistor (42B).
- Example 10. The sampling circuit according to Example 5 or 6, wherein the divider circuit (62A, 62B; 63A, 63B) comprises a capacitive divider circuit.
- Example 11. The sampling circuit according to Example 10, wherein the divider circuit (62A, 62B; 63A; 63B) comprises a series circuit composed of a first capacitor (62A) and a second capacitor (62B), which series circuit is coupled between the first input (11A) and the second input (11B), and an initialization circuit (63A, 63B) for initializing the first capacitor (62A) and the second capacitor (62B).
- Example 12. The sampling circuit (10; 20; 30; 40; 50) according to any of Examples 1 to 11, further comprising a processing circuit (26), which is coupled to a second terminal of the first capacitor (14A) and to a second terminal of the second capacitor (14B), wherein the processing circuit is designed for a lower maximum voltage than the common-mode signal generating circuit (12; 22A, 22B, 23; 31, 32; 41A, 41B, 42A, 42B, 43A, 43B, 45A, 45B; 51A; 51B; 52; 53A; 53B; 60, 61, 62A, 62B, 63A, 63B) and/or the switching circuit (13; 24A, 24B, 25A, 25B; 44A, 44B).
- Example 13. The sampling circuit (10; 20; 30; 40; 50) according to any of Examples 1-12, wherein the common-mode signal generating circuit (12; 22A, 22B, 23; 31, 32; 41A, 41B, 42A, 42B, 43A, 43B, 45A, 45B; 51A; 51B; 52; 53A; 53B; 60, 61, 62A, 62B, 63A, 63B) can be disabled.
- Example 14. A sampling method, comprising:
- in a first operating phase, coupling a first terminal of a capacitor (14A) to a first input signal (S1), and a first terminal of a second capacitor (14B) to a second input signal (S2); and
- in a second operating phase, coupling the first terminal of the first capacitor (14A) and the first terminal of the second capacitor (14B) to a common-mode signal (cm), which corresponds to a common-mode component of the first signal (S1) and of the second signal (S2).
- Example 15. The sampling method according to Example 14, further comprising sampling the common-mode signal (cm), wherein in the second operating phase, the first terminal of the first capacitor (14A) and the first terminal of the second capacitor (14B) are coupled to the sampled input signal.
- Example 16. The sampling method according to Example 14 or 15, further comprising generating the common-mode signal (cm) using a divider circuit (22A, 22B; 41A, 41B, 42A, 42B, 43A, 43B; 62A, 62B; 63A; 63B), to which the first signal (S1) and the second signal (S2) are fed.
- Example 17. The sampling method according to any of Examples 14-16, wherein a difference in the signal value of the first input signal and of the second input signal is less than 1/10 of a signal value of the first input signal and of the second input signal.
- Although specific exemplary embodiments have been illustrated and described in this description, it will be obvious to a person skilled in the art that a multitude of alternative and/or equivalent implementations can be chosen as a substitute for the specific exemplary embodiments shown and described in this description, without departing from the scope of the disclosed invention. The intention is that this application covers all the adaptations or variations of the specific exemplary embodiments discussed here. It is therefore intended that this invention is limited only by the claims and the equivalents of the claims.
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2018
- 2018-12-11 DE DE102018131711.5A patent/DE102018131711B3/en active Active
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2019
- 2019-12-09 CN CN201911250368.2A patent/CN111308171A/en active Pending
- 2019-12-10 US US16/708,876 patent/US20200186146A1/en not_active Abandoned
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2021
- 2021-06-08 US US17/341,941 patent/US11611341B2/en active Active
Also Published As
Publication number | Publication date |
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US11611341B2 (en) | 2023-03-21 |
US20210297077A1 (en) | 2021-09-23 |
CN111308171A (en) | 2020-06-19 |
DE102018131711B3 (en) | 2020-06-10 |
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