US20200058578A1 - Insulating component, semiconductor package, and semiconductor apparatus - Google Patents
Insulating component, semiconductor package, and semiconductor apparatus Download PDFInfo
- Publication number
- US20200058578A1 US20200058578A1 US16/487,546 US201816487546A US2020058578A1 US 20200058578 A1 US20200058578 A1 US 20200058578A1 US 201816487546 A US201816487546 A US 201816487546A US 2020058578 A1 US2020058578 A1 US 2020058578A1
- Authority
- US
- United States
- Prior art keywords
- metal layer
- insulating
- bond
- groove
- lead terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 98
- 239000002184 metal Substances 0.000 claims abstract description 98
- 239000000758 substrate Substances 0.000 claims abstract description 43
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 239000004020 conductor Substances 0.000 description 10
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 6
- 239000007769 metal material Substances 0.000 description 6
- 229910052750 molybdenum Inorganic materials 0.000 description 6
- 239000011733 molybdenum Substances 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 238000005219 brazing Methods 0.000 description 3
- 229910010293 ceramic material Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 2
- 229910001182 Mo alloy Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 2
- KGWWEXORQXHJJQ-UHFFFAOYSA-N [Fe].[Co].[Ni] Chemical compound [Fe].[Co].[Ni] KGWWEXORQXHJJQ-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000010344 co-firing Methods 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- WUUZKBJEUBFVMV-UHFFFAOYSA-N copper molybdenum Chemical compound [Cu].[Mo] WUUZKBJEUBFVMV-UHFFFAOYSA-N 0.000 description 2
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 2
- 239000006112 glass ceramic composition Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052863 mullite Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000005096 rolling process Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- RIRXDDRGHVUXNJ-UHFFFAOYSA-N [Cu].[P] Chemical compound [Cu].[P] RIRXDDRGHVUXNJ-UHFFFAOYSA-N 0.000 description 1
- SNAAJJQQZSMGQD-UHFFFAOYSA-N aluminum magnesium Chemical compound [Mg].[Al] SNAAJJQQZSMGQD-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/02208—Mountings; Housings characterised by the shape of the housings
- H01S5/02216—Butterfly-type, i.e. with electrode pins extending horizontally from the housings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/171—Frame
- H01L2924/1715—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
- H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0225—Out-coupling of light
- H01S5/02251—Out-coupling of light using optical fibres
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0233—Mounting configuration of laser chips
- H01S5/02345—Wire-bonding
Definitions
- the present invention relates to an insulating component, and a semiconductor package and a semiconductor apparatus each including the insulating component.
- a known insulating component includes an insulating substrate having a metal layer for transmitting high-frequency signals and a lead terminal fixed to the metal layer for transmitting signals to an external device (refer to Japanese Unexamined Patent Application Publication No. 2006-179839).
- Patent Literature 1 An insulating component described in Japanese Unexamined Patent Application Publication No. 2006-179839 (Patent Literature 1) includes an insulating substrate having side grooves each containing a bond for fixing a lead.
- the grooves each have a constant width, and may not easily hold a sufficient amount of bond between the metal layer and the lead terminal.
- An insulating component includes an insulating substrate, a metal layer, a bond, and a lead terminal.
- the insulating substrate is plate-like and has a groove located continuously from an upper surface to a side surface of the insulating substrate.
- the metal layer includes a first metal layer located on the upper surface of the insulating substrate and a second metal layer located on an inner surface of the groove and continuous with the first metal layer.
- the bond is located on an upper surface of the metal layer.
- the lead terminal is located on an upper surface of the first metal layer with the bond in between, and overlaps the groove.
- the bond includes a first bond fixing the lead terminal to the first metal layer and a second bond located on an upper surface of the second metal layer and continuous with the first bond.
- the groove includes an inner wall having a ridge. The second bond is located between the ridge and the lead terminal.
- a semiconductor package includes a base, a frame, and the above insulating component.
- the base has an upper surface.
- the upper surface of the base has a mount are on which a semiconductor device is mountable.
- the frame includes a side wall having a through-hole, and surrounds the mount area on the base.
- the insulating component is mounted in the through-hole.
- a semiconductor apparatus includes the above semiconductor package, a semiconductor device, and a lid.
- the semiconductor device is mounted on the mount area in the semiconductor package.
- the lid is joined to an upper edge of the frame included in the semiconductor package and covers the semiconductor device.
- FIG. 1 is a perspective view of a semiconductor apparatus according to an embodiment of the present invention.
- FIG. 2 is an enlarged view of part A of the semiconductor apparatus according to the embodiment of the present invention shown in FIG. 1 .
- FIG. 3 is a top perspective view of a semiconductor package according to the embodiment of the present invention.
- FIG. 4 is a top plan view of the semiconductor package according to the embodiment of the present invention.
- FIG. 5 is a cross-sectional view of the semiconductor package according to the embodiment of the present invention taken along line B-B in FIG. 4 .
- FIG. 6 is an exploded perspective view of the semiconductor package according to the embodiment of the present invention.
- FIG. 7 is a top perspective view of an insulating component according to the embodiment of the present invention.
- FIG. 8 is a bottom perspective view of the insulating component according to the embodiment of the present invention.
- FIG. 9 is a top perspective view of the insulating component without a bond according to the embodiment of the present invention.
- FIG. 10 is a top perspective view of an insulating component according to another embodiment of the present invention.
- FIG. 11 is a top perspective view of the insulating component without a bond according to the other embodiment of the present invention.
- a semiconductor apparatus includes a semiconductor package and insulating components described below.
- the insulating components may be used as, for example, input/output terminals in the semiconductor apparatus or the semiconductor package for electrically connecting a semiconductor device to an external circuit and transmitting, or receiving and outputting electric signals.
- FIG. 1 is a perspective view of the semiconductor apparatus according to one embodiment of the present invention. In FIG. 1 , a lid is removed.
- FIG. 2 is an enlarged view of part A of the semiconductor apparatus according to the embodiment of the present invention shown in FIG. 1 .
- the semiconductor apparatus, the semiconductor package, and the insulating component according to one or more embodiments of the present invention will now be described with reference to the drawings.
- FIG. 1 is a top perspective view of a semiconductor apparatus 100 according to the embodiment of the present invention.
- the semiconductor apparatus 100 includes a semiconductor package 10 , a semiconductor device 11 , and a lid 12 according to the embodiment of the present invention.
- the semiconductor device 11 may be a laser diode (LD), or may be a photodiode (PD).
- a frame 7 may have a through-hole to receive an optical fiber, in addition to through-holes 71 in which insulating components 1 are to be mounted.
- the lid 12 is joined to an upper edge of the frame 7 to cover the semiconductor package 10 .
- the lid 12 is rectangular in a plan view, and has the dimensions of 5 ⁇ 5 mm to 45 ⁇ 45 mm and a height of 0.5 to 3 mm.
- the lid 12 may be formed from, for example, a metal such as iron, copper, nickel, chromium, cobalt, molybdenum, or tungsten, or an alloy of these metals, such as a copper-tungsten alloy, a copper-molybdenum alloy, or an iron-nickel-cobalt alloy.
- a metal member for the lid 12 may be prepared by processing (e.g., rolling or punching) an ingot formed from such a metal material.
- FIG. 3 is a top perspective view of the semiconductor package according to the embodiment of the present invention.
- FIG. 4 is a top plan view of the semiconductor package according to the embodiment of the present invention.
- FIG. 5 is a cross-sectional view of the semiconductor package according to the embodiment of the present invention taken along line B-B in FIG. 4 .
- FIG. 6 is an exploded perspective view of the semiconductor package according to the embodiment of the present invention.
- the semiconductor package 10 includes the base 6 , the frame 7 , and the insulating components 1 described above according to the embodiment of the present invention.
- the base 6 is, for example, rectangular in a plan view.
- the base 6 has the dimensions of 5 ⁇ 5 mm to 50 ⁇ 50 mm and a thickness of 0.3 to 3 mm.
- the frame 7 surrounds the upper surface of the base 6 .
- the frame 7 is rectangular in a plan view, and has the dimensions of 5 ⁇ 5 mm to 45 ⁇ 45 mm and a height of 3 to 10 mm.
- the frame 7 has a thickness of 0.5 to 3 mm.
- the frame 7 has an outer shape smaller than the base 6 in a plan view.
- the insulating components 1 (described later) can be firmly fixed to the base 6 .
- the base 6 and the frame 7 may be formed from, for example, a metal such as iron, copper, nickel, chromium, cobalt, molybdenum, or tungsten, or an alloy of these metals, such as a copper-tungsten alloy, a copper-molybdenum alloy, or an iron-nickel-cobalt alloy.
- a metal member for the base 6 may be prepared by processing (e.g., rolling or punching) an ingot formed from such a metal material.
- the frame 7 has the through-holes 71 in its side walls as shown in FIG. 6 .
- the through-holes 71 receive and fix the insulating components 1 (described later).
- the insulating components 1 are used as input/output terminals. Structure of Insulating Component
- FIG. 7 is a top perspective view of the insulating component according to the embodiment of the present invention.
- FIG. 8 is a bottom perspective view of the insulating component according to the embodiment of the present invention.
- FIG. 9 is a top perspective view of the insulating component without a bond according to the embodiment of the present invention.
- FIG. 10 is a top perspective view of an insulating component according to another embodiment of the present invention.
- FIG. 11 is a top perspective view of the insulating component without a bond according to the other embodiment of the present invention.
- a lead terminal 5 is not shown in FIGS. 9, 10, and 11 .
- the insulating component 1 in these figures includes an insulating substrate 2 , a metal layer 3 , a bond 4 , and the lead terminal 5 .
- the insulating component 1 according to the other embodiment may include, in addition to the members described above, a wall 8 standing on an upper surface of the insulating substrate 2 .
- the insulating substrate 2 is a laminate of a first insulating layer 22 and a second insulating layer 23 formed from dielectric materials.
- the insulating substrate 2 is, for example, rectangular in a plan view, and has the dimensions of 2 ⁇ 2 mm to 20 ⁇ 20 mm and a height of 0.5 to 5 mm.
- Each insulating layer in the insulating substrate 2 is formed from a dielectric material.
- the dielectric material include ceramic materials such as sintered aluminum oxide, sintered mullite, sintered silicon carbide, sintered aluminum nitride, and sintered silicon nitride, as well as glass ceramic materials.
- the insulating substrate 2 has a groove 21 continuous from its upper surface (surface to which the lead terminal 5 is joined) to its side surface.
- the groove 21 is, for example, rectangular as viewed laterally, and has the dimensions of 0.3 ⁇ 0.3 mm to 4 ⁇ 4 mm.
- the groove 21 has a depth of, for example, 0.3 to 4 mm in a plan view.
- the groove 21 has a ridge 211 protruding on its inner walls.
- the ridge 211 constitutes 5 to 70% of the width of the groove 21 .
- the ridge 211 constituting at least 5% of the width of the groove 21 allows the bond 4 to easily fill an area between the ridge 211 and the lead terminal 5
- the ridge 211 constituting less than or equal to 70% of the width of the groove 21 allows the bond 4 to fill an area between the ridge 211 and the second insulating layer 23 .
- the ridge 211 allows the bond 4 to easily fill the area between the ridge 211 and the lead terminal 5 while reducing an excess amount of bond 4 around the lead terminal 5 .
- the ridge 211 is located below the midpoint of the side wall of the first insulating layer 22 (the side wall including the groove) in the layer stacking direction (direction from the second insulating layer 23 toward the lead terminal 5 ).
- the ridge 211 located below the midpoint allows more bond 4 to easily fill the area of the groove 21 nearer the lead terminal 5 (described later) or specifically the area between the ridge 211 and the lead terminal 5 , and less bond 4 to fill the area of the groove 21 farther from the lead terminal 5 or specifically the area between the ridge 211 and the second insulating layer 23 .
- the ridge 211 thus easily allows the bond 4 to be continuous across the area between the ridge 211 and the lead terminal 5 and the other area.
- the ridge 211 protrudes from the facing inner walls of the groove 21 (walls perpendicular to the upper surface of the insulating substrate 2 ), rather than from one of the facing inner walls.
- the ridge extends continuously along the inner wall of the groove 21 in the direction of the side wall of the first insulating layer 22 .
- the ridge 211 extends continuously along the inner walls of the groove 21 to have the same height in a direction perpendicular to the inner walls of the groove 21 .
- the ridge 211 protrudes from each of the facing inner walls of the groove 21 with the same height as described above.
- This structure places the bond 4 uniformly as well as in a sufficient amount on both sides of the lead terminal 5 (on the inner walls of the groove 21 ) in the area of the groove 21 between the ridge 211 and the lead terminal 5 .
- This improves the strength of the joint between the lead terminal 5 and the metal layer 3 with the bond 4 placed on both sides of the lead terminal 5 .
- the bond 4 further regulates stress acting on the joint between the lead terminal 5 and the metal layer 3 .
- the insulating component 1 according to the embodiment of the present invention can thus have less cracks or breaks in the insulating substrate 2 .
- the insulating substrate 2 may have a ground conductor on its bottom surface (surface opposite to the upper surface of the insulating substrate 2 ).
- the ground conductor is, for example, rectangular in a plan view, and has the dimensions of 2 ⁇ 2 mm to 20 ⁇ 20 mm.
- the ground conductor is formed from, for example, a metal material such as tungsten, molybdenum, manganese, or nickel.
- the metal layer 3 is located on the upper surface of the insulating substrate 2 , or specifically is located continuously from the upper surface of the first insulating layer 22 to the inner walls of the groove 21 .
- the metal layer 3 includes, on the upper surface of the insulating substrate 2 , a first metal layer 31 as a line conductor for transmitting electric signals, and a second metal layer 32 located on the inner walls of the groove 21 .
- the first metal layer 31 extends from an upper end of the groove 21 (nearer the lead terminal 5 ) toward another side wall of the first insulating layer 22 opposite to the side wall including the groove 21 .
- the first metal layer 31 and the second metal layer 32 are continuous with each other.
- the metal layer 3 is formed from, for example, a metal material such as gold, silver, copper, nickel, tungsten, molybdenum, or manganese, and may be formed on the surface of the first insulating layer 22 as a metallization layer or a plated layer by co-firing or metal plating.
- a metal material such as gold, silver, copper, nickel, tungsten, molybdenum, or manganese
- the first metal layer 31 is located to overlap the ground conductor on each insulating layer. This structure allows the first metal layer 31 and the ground conductor on each layer to form a strip line structure. This facilitates transmission of high-frequency signals.
- the groove 21 contains the second metal layer 32 on its inner walls.
- the second metal layer 32 and the first metal layer 31 are continuous with each other.
- the second metal layer 32 is located across all the inner walls of the groove 21 .
- the second metal layer 32 is formed from, for example, a metal material such as gold, silver, copper, nickel, tungsten, molybdenum, or manganese, and may be formed on the inner walls of the groove 21 as a metallization layer or a plated layer by co-firing or metal plating in the same manner as the first metal layer 31 .
- the metal layer 3 has the bond 4 on its surface.
- the bond 4 on the metal layer 3 joins and fixes the lead terminal 5 (described later) to the upper surface of the insulating substrate 2 .
- the bond 4 includes a first bond 41 located on the surface of the first metal layer 31 to join and fix the lead terminal 5 to the first metal layer 31 , and a second bond 42 located on the second metal layer 32 at the inner walls of the groove 21 .
- the bond 4 includes the first bond 41 and the second bond 42 that are continuous with each other.
- the bond 4 may be formed from a silver brazing material.
- the bond 4 may also be a phosphor copper brazing material or an aluminum-magnesium brazing material.
- the first bond 41 is located on the surface of the first metal layer 31 .
- the lead terminal 5 is joined and fixed with the first bond 41 .
- the second bond 42 is located between the ridge 211 in the groove 21 and the lead terminal 5 .
- the second bond 42 is also located below the ridge 211 , in addition to between the ridge 211 and the lead terminal 5 .
- the second bond 42 is located on a portion of the second metal layer 32 between the ridge 211 and the second insulating layer 23 .
- On each of the inner walls of the groove 21 more second bond 42 fills the area above the ridge 211 (nearer the lead terminal 5 ) than the area below the ridge 211 (nearer the second insulating layer 23 ). This makes it less likely to have an excess amount of bond 4 on the second metal layer 32 between the ridge 211 and the second insulating layer 23 from causing an unintended joint.
- the bond 4 on the second metal layer 32 between the ridge 211 and the lead terminal 5 joins and fixes the lead terminal 5 , and improves the strength of the joint between the lead terminal 5 and the metal layer 3 .
- any excess amount of second bond 42 on the second metal layer 32 between the ridge 211 and the second insulating layer 23 may cause cracks or breaks in the first insulating layer 22 including the ridge 211 under heat, due to the different thermal expansion coefficients of the second insulating layer 23 and the second bond 42 .
- the ridge 211 allows a small amount of bond 4 to flow to and be fixed on the second metal layer 32 between the ridge 211 and the second insulating layer 23 although more bond 4 is used to join the lead terminal 5 and the second metal layer 32 to improve the strength of the joint.
- This structure further allows an increased amount of bond 4 to flow to and be fixed on the second metal layer 32 between the ridge 211 and the lead terminal 5 .
- the insulating component 1 with the structure according to the embodiment of the present invention improves the strength of the joint between the insulating substrate 2 and the lead terminal 5 , and reduces cracks or breaks in the insulating substrate 2 . This is achieved by allowing more bond 4 to be easily held between the lead terminal 5 and the ridge 211 in the groove 21 included in the insulating substrate 2 , and also by allowing less bond 4 to be in the area below the ridge 211 . The bond 4 can thus be held more easily around the lead terminal 5 .
- this structure improves the strength of the joint between the lead terminal 5 and the insulating substrate 2 , and reduces stress caused by an external force applied to the lead terminal 5 and acting on the joint between the lead terminal 5 and the metal layer 3 . This reduces cracks and breaks in the insulating substrate 2 , thus enabling stable signal transmission.
- the first insulating layer 22 alone has the groove 21 .
- the second insulating layer has no groove on its side surface. This maintains the rigidity of the insulating substrate 2 .
- the second metal layer 32 is not located on a portion of the upper surface of the second insulating layer 23 overlapping the groove 21 .
- the upper surface of the second insulating layer 23 is thus exposed as viewed from above.
- the second insulating layer 23 tends not to receive a load from stress caused by the different thermal expansion coefficients of the second metal layer 32 and the second bond 42 . This reduces cracks and breaks in the second insulating layer 23 .
- the groove 21 is narrower than the first metal layer 31 as viewed from above. This allows the bond 4 to fill a space defined by the surface of the lead terminal 5 facing the first metal layer 31 and the inner walls of the groove 21 , and allows the lead terminal 5 to be more firmly fixed to the metal layer 3 .
- the insulating component 1 may include the wall 8 standing on the upper surface of the first insulating layer 22 .
- the wall 8 may externally protect the first metal layer 31 for transmitting signals.
- the upper surface of the wall 8 is joined to the frame 7 (described later).
- the frame 7 formed from a metal material and the insulating component 1 formed from a ceramic material can cause stress due to the different thermal expansion coefficients. A load applied to the insulating component 1 is less likely to affect the first metal layer 31 , and the insulation is maintained between the first metal layer 31 and the frame 7 .
- the wall 8 may be formed from a dielectric material.
- the dielectric material include ceramic materials such as sintered aluminum oxide, sintered mullite, sintered silicon carbide, sintered aluminum nitride, and sintered silicon nitride, as well as glass ceramic materials.
- the wall 8 may be formed integrally with the insulating substrate 2 .
- the integrated structure eliminates the bond or other materials for joining, and can thus simplify the manufacturing processes, or can have a reduced thickness. This structure further eliminates stress caused by the different thermal expansion coefficients of the insulating substrate 2 , the bond, and the wall 8 , and thus reduces a load from the stress applied to the insulating substrate 2 or the wall 8 .
- the insulating substrate 2 including multiple first insulating layers 22 or second insulating layers 23 formed from, for example, sintered aluminum oxide may be prepared in the manner described below.
- An aluminum oxide-containing powdery raw material is mixed with, for example, an appropriate organic binder and an appropriate solvent to form slurry.
- the slurry is then shaped into sheets using, for example, a doctor blade, to yield multiple ceramic green sheets.
- the ceramic green sheets are cut or punched into an appropriate shape.
- a ceramic green sheet to be the uppermost sheet has a groove to be the groove 21 .
- the ceramic green sheets are then stacked one on another and pressure-bonded.
- the metal layer 3 (first and second metal layers 31 and 32 ) and the ground conductors on the upper surfaces of the layers are formed from, for example, a metallization layer that may be formed from a metal having a high melting point, such as tungsten, molybdenum, or manganese, prepared in the manner described below.
- a metal powder with a high melting point is kneaded with an organic solvent and a binder fully into a metal paste.
- the metal paste is then printed at predetermined positions on the ceramic green sheets to be the upper surfaces of the first insulating layer 22 and the second insulating layer 23 by, for example, screen printing.
- the stacked ceramic green sheets are then fired at a temperature of about 1600° C. in a reducing atmosphere to complete the insulating substrate 2 .
- the metallization layers are applied to the upper surface and the interior of the insulating substrate 2 or between the insulating layers to serve as the ground conductors on the metal layer and the upper surfaces of the insulating layers.
Abstract
Description
- The present invention relates to an insulating component, and a semiconductor package and a semiconductor apparatus each including the insulating component.
- As wireless communication devices including mobile phones are used widely, these devices have higher frequencies to transmit larger volumes of information at a higher speed. Among such devices, a known insulating component includes an insulating substrate having a metal layer for transmitting high-frequency signals and a lead terminal fixed to the metal layer for transmitting signals to an external device (refer to Japanese Unexamined Patent Application Publication No. 2006-179839).
- An insulating component described in Japanese Unexamined Patent Application Publication No. 2006-179839 (Patent Literature 1) includes an insulating substrate having side grooves each containing a bond for fixing a lead. However, with the technique described in
Patent Literature 1, the grooves each have a constant width, and may not easily hold a sufficient amount of bond between the metal layer and the lead terminal. - An insulating component according to one or more aspects of the present invention includes an insulating substrate, a metal layer, a bond, and a lead terminal. The insulating substrate is plate-like and has a groove located continuously from an upper surface to a side surface of the insulating substrate. The metal layer includes a first metal layer located on the upper surface of the insulating substrate and a second metal layer located on an inner surface of the groove and continuous with the first metal layer. The bond is located on an upper surface of the metal layer. The lead terminal is located on an upper surface of the first metal layer with the bond in between, and overlaps the groove. The bond includes a first bond fixing the lead terminal to the first metal layer and a second bond located on an upper surface of the second metal layer and continuous with the first bond. The groove includes an inner wall having a ridge. The second bond is located between the ridge and the lead terminal.
- A semiconductor package according to another aspect of the present invention includes a base, a frame, and the above insulating component. The base has an upper surface. The upper surface of the base has a mount are on which a semiconductor device is mountable. The frame includes a side wall having a through-hole, and surrounds the mount area on the base. The insulating component is mounted in the through-hole.
- A semiconductor apparatus according to another aspect of the present invention includes the above semiconductor package, a semiconductor device, and a lid. The semiconductor device is mounted on the mount area in the semiconductor package. The lid is joined to an upper edge of the frame included in the semiconductor package and covers the semiconductor device.
-
FIG. 1 is a perspective view of a semiconductor apparatus according to an embodiment of the present invention. -
FIG. 2 is an enlarged view of part A of the semiconductor apparatus according to the embodiment of the present invention shown inFIG. 1 . -
FIG. 3 is a top perspective view of a semiconductor package according to the embodiment of the present invention. -
FIG. 4 is a top plan view of the semiconductor package according to the embodiment of the present invention. -
FIG. 5 is a cross-sectional view of the semiconductor package according to the embodiment of the present invention taken along line B-B inFIG. 4 . -
FIG. 6 is an exploded perspective view of the semiconductor package according to the embodiment of the present invention. -
FIG. 7 is a top perspective view of an insulating component according to the embodiment of the present invention. -
FIG. 8 is a bottom perspective view of the insulating component according to the embodiment of the present invention. -
FIG. 9 is a top perspective view of the insulating component without a bond according to the embodiment of the present invention. -
FIG. 10 is a top perspective view of an insulating component according to another embodiment of the present invention. -
FIG. 11 is a top perspective view of the insulating component without a bond according to the other embodiment of the present invention. - A semiconductor apparatus according to one or more embodiments of the present invention includes a semiconductor package and insulating components described below. The insulating components may be used as, for example, input/output terminals in the semiconductor apparatus or the semiconductor package for electrically connecting a semiconductor device to an external circuit and transmitting, or receiving and outputting electric signals.
FIG. 1 is a perspective view of the semiconductor apparatus according to one embodiment of the present invention. InFIG. 1 , a lid is removed.FIG. 2 is an enlarged view of part A of the semiconductor apparatus according to the embodiment of the present invention shown inFIG. 1 . The semiconductor apparatus, the semiconductor package, and the insulating component according to one or more embodiments of the present invention will now be described with reference to the drawings. -
FIG. 1 is a top perspective view of asemiconductor apparatus 100 according to the embodiment of the present invention. As shown in the figure, thesemiconductor apparatus 100 includes asemiconductor package 10, asemiconductor device 11, and alid 12 according to the embodiment of the present invention. - The
semiconductor device 11 may be a laser diode (LD), or may be a photodiode (PD). For an LD, aframe 7 may have a through-hole to receive an optical fiber, in addition to through-holes 71 in whichinsulating components 1 are to be mounted. - The
lid 12 is joined to an upper edge of theframe 7 to cover thesemiconductor package 10. Thelid 12 is rectangular in a plan view, and has the dimensions of 5×5 mm to 45×45 mm and a height of 0.5 to 3 mm. Thelid 12 may be formed from, for example, a metal such as iron, copper, nickel, chromium, cobalt, molybdenum, or tungsten, or an alloy of these metals, such as a copper-tungsten alloy, a copper-molybdenum alloy, or an iron-nickel-cobalt alloy. A metal member for thelid 12 may be prepared by processing (e.g., rolling or punching) an ingot formed from such a metal material. -
FIG. 3 is a top perspective view of the semiconductor package according to the embodiment of the present invention.FIG. 4 is a top plan view of the semiconductor package according to the embodiment of the present invention.FIG. 5 is a cross-sectional view of the semiconductor package according to the embodiment of the present invention taken along line B-B inFIG. 4 .FIG. 6 is an exploded perspective view of the semiconductor package according to the embodiment of the present invention. In these figures, thesemiconductor package 10 includes thebase 6, theframe 7, and theinsulating components 1 described above according to the embodiment of the present invention. - As shown in
FIGS. 3 to 6 , thebase 6 is, for example, rectangular in a plan view. Thebase 6 has the dimensions of 5×5 mm to 50×50 mm and a thickness of 0.3 to 3 mm. - The
frame 7 surrounds the upper surface of thebase 6. Theframe 7 is rectangular in a plan view, and has the dimensions of 5×5 mm to 45×45 mm and a height of 3 to 10 mm. Theframe 7 has a thickness of 0.5 to 3 mm. Theframe 7 has an outer shape smaller than thebase 6 in a plan view. The insulating components 1 (described later) can be firmly fixed to thebase 6. - The
base 6 and theframe 7 may be formed from, for example, a metal such as iron, copper, nickel, chromium, cobalt, molybdenum, or tungsten, or an alloy of these metals, such as a copper-tungsten alloy, a copper-molybdenum alloy, or an iron-nickel-cobalt alloy. A metal member for thebase 6 may be prepared by processing (e.g., rolling or punching) an ingot formed from such a metal material. - The
frame 7 has the through-holes 71 in its side walls as shown inFIG. 6 . The through-holes 71 receive and fix the insulating components 1 (described later). In thesemiconductor package 10, the insulatingcomponents 1 are used as input/output terminals. Structure of Insulating Component -
FIG. 7 is a top perspective view of the insulating component according to the embodiment of the present invention.FIG. 8 is a bottom perspective view of the insulating component according to the embodiment of the present invention.FIG. 9 is a top perspective view of the insulating component without a bond according to the embodiment of the present invention.FIG. 10 is a top perspective view of an insulating component according to another embodiment of the present invention.FIG. 11 is a top perspective view of the insulating component without a bond according to the other embodiment of the present invention. For ease of explanation, alead terminal 5 is not shown inFIGS. 9, 10, and 11 . The insulatingcomponent 1 in these figures includes an insulatingsubstrate 2, ametal layer 3, abond 4, and thelead terminal 5. As shown inFIGS. 10 and 11 , the insulatingcomponent 1 according to the other embodiment may include, in addition to the members described above, awall 8 standing on an upper surface of the insulatingsubstrate 2. - As shown in
FIGS. 10 and 11 , the insulatingsubstrate 2 is a laminate of a first insulatinglayer 22 and a second insulatinglayer 23 formed from dielectric materials. The insulatingsubstrate 2 is, for example, rectangular in a plan view, and has the dimensions of 2×2 mm to 20×20 mm and a height of 0.5 to 5 mm. Each insulating layer in the insulatingsubstrate 2 is formed from a dielectric material. Examples of the dielectric material include ceramic materials such as sintered aluminum oxide, sintered mullite, sintered silicon carbide, sintered aluminum nitride, and sintered silicon nitride, as well as glass ceramic materials. - The insulating
substrate 2 has agroove 21 continuous from its upper surface (surface to which thelead terminal 5 is joined) to its side surface. Thegroove 21 is, for example, rectangular as viewed laterally, and has the dimensions of 0.3×0.3 mm to 4×4 mm. Thegroove 21 has a depth of, for example, 0.3 to 4 mm in a plan view. - The
groove 21 has aridge 211 protruding on its inner walls. When viewed from above, theridge 211 constitutes 5 to 70% of the width of thegroove 21. Theridge 211 constituting at least 5% of the width of thegroove 21 allows thebond 4 to easily fill an area between theridge 211 and thelead terminal 5, whereas theridge 211 constituting less than or equal to 70% of the width of thegroove 21 allows thebond 4 to fill an area between theridge 211 and the second insulatinglayer 23. Theridge 211 allows thebond 4 to easily fill the area between theridge 211 and thelead terminal 5 while reducing an excess amount ofbond 4 around thelead terminal 5. - In the
groove 21, theridge 211 is located below the midpoint of the side wall of the first insulating layer 22 (the side wall including the groove) in the layer stacking direction (direction from the second insulatinglayer 23 toward the lead terminal 5). Theridge 211 located below the midpoint allowsmore bond 4 to easily fill the area of thegroove 21 nearer the lead terminal 5 (described later) or specifically the area between theridge 211 and thelead terminal 5, andless bond 4 to fill the area of thegroove 21 farther from thelead terminal 5 or specifically the area between theridge 211 and the second insulatinglayer 23. Theridge 211 thus easily allows thebond 4 to be continuous across the area between theridge 211 and thelead terminal 5 and the other area. - When the side wall of the first insulating
layer 22 is viewed laterally, theridge 211 protrudes from the facing inner walls of the groove 21 (walls perpendicular to the upper surface of the insulating substrate 2), rather than from one of the facing inner walls. In the cross-sectional view of thegroove 21 inFIG. 5 , the ridge extends continuously along the inner wall of thegroove 21 in the direction of the side wall of the first insulatinglayer 22. In thegroove 21, theridge 211 extends continuously along the inner walls of thegroove 21 to have the same height in a direction perpendicular to the inner walls of thegroove 21. - When the side wall of the first insulating
layer 22 is viewed laterally, theridge 211 protrudes from each of the facing inner walls of thegroove 21 with the same height as described above. This structure places thebond 4 uniformly as well as in a sufficient amount on both sides of the lead terminal 5 (on the inner walls of the groove 21) in the area of thegroove 21 between theridge 211 and thelead terminal 5. This improves the strength of the joint between thelead terminal 5 and themetal layer 3 with thebond 4 placed on both sides of thelead terminal 5. When thelead terminal 5 receives an external force, thebond 4 further regulates stress acting on the joint between thelead terminal 5 and themetal layer 3. The insulatingcomponent 1 according to the embodiment of the present invention can thus have less cracks or breaks in the insulatingsubstrate 2. - The insulating
substrate 2 may have a ground conductor on its bottom surface (surface opposite to the upper surface of the insulating substrate 2). The ground conductor is, for example, rectangular in a plan view, and has the dimensions of 2×2 mm to 20×20 mm. The ground conductor is formed from, for example, a metal material such as tungsten, molybdenum, manganese, or nickel. - As shown in
FIG. 9 , themetal layer 3 is located on the upper surface of the insulatingsubstrate 2, or specifically is located continuously from the upper surface of the first insulatinglayer 22 to the inner walls of thegroove 21. Themetal layer 3 includes, on the upper surface of the insulatingsubstrate 2, afirst metal layer 31 as a line conductor for transmitting electric signals, and asecond metal layer 32 located on the inner walls of thegroove 21. Thefirst metal layer 31 extends from an upper end of the groove 21 (nearer the lead terminal 5) toward another side wall of the first insulatinglayer 22 opposite to the side wall including thegroove 21. Thefirst metal layer 31 and thesecond metal layer 32 are continuous with each other. Themetal layer 3 is formed from, for example, a metal material such as gold, silver, copper, nickel, tungsten, molybdenum, or manganese, and may be formed on the surface of the first insulatinglayer 22 as a metallization layer or a plated layer by co-firing or metal plating. - When the ground conductor is located at least on the bottom surface of the insulating
substrate 2 or between the first insulatinglayer 22 and the second insulatinglayer 23, thefirst metal layer 31 is located to overlap the ground conductor on each insulating layer. This structure allows thefirst metal layer 31 and the ground conductor on each layer to form a strip line structure. This facilitates transmission of high-frequency signals. - The
groove 21 contains thesecond metal layer 32 on its inner walls. Thesecond metal layer 32 and thefirst metal layer 31 are continuous with each other. For example, thesecond metal layer 32 is located across all the inner walls of thegroove 21. Thesecond metal layer 32 is formed from, for example, a metal material such as gold, silver, copper, nickel, tungsten, molybdenum, or manganese, and may be formed on the inner walls of thegroove 21 as a metallization layer or a plated layer by co-firing or metal plating in the same manner as thefirst metal layer 31. - As shown in
FIG. 10 , themetal layer 3 has thebond 4 on its surface. Thebond 4 on themetal layer 3 joins and fixes the lead terminal 5 (described later) to the upper surface of the insulatingsubstrate 2. Thebond 4 includes afirst bond 41 located on the surface of thefirst metal layer 31 to join and fix thelead terminal 5 to thefirst metal layer 31, and asecond bond 42 located on thesecond metal layer 32 at the inner walls of thegroove 21. Thebond 4 includes thefirst bond 41 and thesecond bond 42 that are continuous with each other. Thebond 4 may be formed from a silver brazing material. Thebond 4 may also be a phosphor copper brazing material or an aluminum-magnesium brazing material. - The
first bond 41 is located on the surface of thefirst metal layer 31. Thelead terminal 5 is joined and fixed with thefirst bond 41. - The
second bond 42 is located between theridge 211 in thegroove 21 and thelead terminal 5. Thesecond bond 42 is also located below theridge 211, in addition to between theridge 211 and thelead terminal 5. In other words, thesecond bond 42 is located on a portion of thesecond metal layer 32 between theridge 211 and the second insulatinglayer 23. On each of the inner walls of thegroove 21, moresecond bond 42 fills the area above the ridge 211 (nearer the lead terminal 5) than the area below the ridge 211 (nearer the second insulating layer 23). This makes it less likely to have an excess amount ofbond 4 on thesecond metal layer 32 between theridge 211 and the second insulatinglayer 23 from causing an unintended joint. Thebond 4 on thesecond metal layer 32 between theridge 211 and thelead terminal 5 joins and fixes thelead terminal 5, and improves the strength of the joint between thelead terminal 5 and themetal layer 3. - Any excess amount of
second bond 42 on thesecond metal layer 32 between theridge 211 and the second insulatinglayer 23 may cause cracks or breaks in the first insulatinglayer 22 including theridge 211 under heat, due to the different thermal expansion coefficients of the second insulatinglayer 23 and thesecond bond 42. Theridge 211 allows a small amount ofbond 4 to flow to and be fixed on thesecond metal layer 32 between theridge 211 and the second insulatinglayer 23 althoughmore bond 4 is used to join thelead terminal 5 and thesecond metal layer 32 to improve the strength of the joint. This structure further allows an increased amount ofbond 4 to flow to and be fixed on thesecond metal layer 32 between theridge 211 and thelead terminal 5. - The insulating
component 1 with the structure according to the embodiment of the present invention improves the strength of the joint between the insulatingsubstrate 2 and thelead terminal 5, and reduces cracks or breaks in the insulatingsubstrate 2. This is achieved by allowingmore bond 4 to be easily held between thelead terminal 5 and theridge 211 in thegroove 21 included in the insulatingsubstrate 2, and also by allowingless bond 4 to be in the area below theridge 211. Thebond 4 can thus be held more easily around thelead terminal 5. In other words, this structure improves the strength of the joint between thelead terminal 5 and the insulatingsubstrate 2, and reduces stress caused by an external force applied to thelead terminal 5 and acting on the joint between thelead terminal 5 and themetal layer 3. This reduces cracks and breaks in the insulatingsubstrate 2, thus enabling stable signal transmission. - The first insulating
layer 22 alone has thegroove 21. In this case, the second insulating layer has no groove on its side surface. This maintains the rigidity of the insulatingsubstrate 2. - As viewed from above, the
second metal layer 32 is not located on a portion of the upper surface of the second insulatinglayer 23 overlapping thegroove 21. The upper surface of the second insulatinglayer 23 is thus exposed as viewed from above. The second insulatinglayer 23 tends not to receive a load from stress caused by the different thermal expansion coefficients of thesecond metal layer 32 and thesecond bond 42. This reduces cracks and breaks in the second insulatinglayer 23. - The
groove 21 is narrower than thefirst metal layer 31 as viewed from above. This allows thebond 4 to fill a space defined by the surface of thelead terminal 5 facing thefirst metal layer 31 and the inner walls of thegroove 21, and allows thelead terminal 5 to be more firmly fixed to themetal layer 3. - As shown in
FIGS. 10 and 11 , the insulatingcomponent 1 may include thewall 8 standing on the upper surface of the first insulatinglayer 22. Thewall 8 may externally protect thefirst metal layer 31 for transmitting signals. In this case, the upper surface of thewall 8 is joined to the frame 7 (described later). In particular, theframe 7 formed from a metal material and the insulatingcomponent 1 formed from a ceramic material can cause stress due to the different thermal expansion coefficients. A load applied to the insulatingcomponent 1 is less likely to affect thefirst metal layer 31, and the insulation is maintained between thefirst metal layer 31 and theframe 7. - The
wall 8 may be formed from a dielectric material. Examples of the dielectric material include ceramic materials such as sintered aluminum oxide, sintered mullite, sintered silicon carbide, sintered aluminum nitride, and sintered silicon nitride, as well as glass ceramic materials. Thewall 8 may be formed integrally with the insulatingsubstrate 2. The integrated structure eliminates the bond or other materials for joining, and can thus simplify the manufacturing processes, or can have a reduced thickness. This structure further eliminates stress caused by the different thermal expansion coefficients of the insulatingsubstrate 2, the bond, and thewall 8, and thus reduces a load from the stress applied to the insulatingsubstrate 2 or thewall 8. - The insulating
substrate 2 including multiple first insulatinglayers 22 or second insulatinglayers 23 formed from, for example, sintered aluminum oxide may be prepared in the manner described below. An aluminum oxide-containing powdery raw material is mixed with, for example, an appropriate organic binder and an appropriate solvent to form slurry. The slurry is then shaped into sheets using, for example, a doctor blade, to yield multiple ceramic green sheets. The ceramic green sheets are cut or punched into an appropriate shape. A ceramic green sheet to be the uppermost sheet has a groove to be thegroove 21. The ceramic green sheets are then stacked one on another and pressure-bonded. - The metal layer 3 (first and second metal layers 31 and 32) and the ground conductors on the upper surfaces of the layers are formed from, for example, a metallization layer that may be formed from a metal having a high melting point, such as tungsten, molybdenum, or manganese, prepared in the manner described below. A metal powder with a high melting point is kneaded with an organic solvent and a binder fully into a metal paste. The metal paste is then printed at predetermined positions on the ceramic green sheets to be the upper surfaces of the first insulating
layer 22 and the second insulatinglayer 23 by, for example, screen printing. The stacked ceramic green sheets are then fired at a temperature of about 1600° C. in a reducing atmosphere to complete the insulatingsubstrate 2. - Through these processes, the metallization layers are applied to the upper surface and the interior of the insulating
substrate 2 or between the insulating layers to serve as the ground conductors on the metal layer and the upper surfaces of the insulating layers. - The present invention is not limited to the above embodiments, but may be modified variously without departing from the spirit and scope of the invention. Modifications contained in the claims can fall within the scope of the present invention.
-
- 1 insulating component
- 2 insulating substrate
- 21 groove
- 211 ridge
- 22 first insulating layer
- 23 second insulating layer
- 24 ground conductor layer
- 3 metal layer
- 31 first metal layer
- 32 second metal layer
- 4 bond
- 41 first bond
- 42 second bond
- 5 lead terminal
- 6 base
- 61 mount area
- 7 frame
- 71 through-hole
- 8 wall
- 10 semiconductor package
- 11 semiconductor device
- 12 lid
- 100 semiconductor apparatus
Claims (10)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017031899 | 2017-02-23 | ||
JPJP2017-031899 | 2017-02-23 | ||
JP2017-031899 | 2017-02-23 | ||
PCT/JP2018/005080 WO2018155282A1 (en) | 2017-02-23 | 2018-02-14 | Insulating support, semiconductor package and semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2018/005080 A-371-Of-International WO2018155282A1 (en) | 2017-02-23 | 2018-02-14 | Insulating support, semiconductor package and semiconductor device |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/722,529 Continuation US11901247B2 (en) | 2017-02-23 | 2022-04-18 | Insulating component, semiconductor package, and semiconductor apparatus |
Publications (2)
Publication Number | Publication Date |
---|---|
US20200058578A1 true US20200058578A1 (en) | 2020-02-20 |
US11335613B2 US11335613B2 (en) | 2022-05-17 |
Family
ID=63252569
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/487,546 Active 2038-08-17 US11335613B2 (en) | 2017-02-23 | 2018-02-14 | Insulating component, semiconductor package, and semiconductor apparatus |
US17/722,529 Active US11901247B2 (en) | 2017-02-23 | 2022-04-18 | Insulating component, semiconductor package, and semiconductor apparatus |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/722,529 Active US11901247B2 (en) | 2017-02-23 | 2022-04-18 | Insulating component, semiconductor package, and semiconductor apparatus |
Country Status (5)
Country | Link |
---|---|
US (2) | US11335613B2 (en) |
EP (1) | EP3588549A4 (en) |
JP (3) | JP6829303B2 (en) |
CN (1) | CN110337718B (en) |
WO (1) | WO2018155282A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113937613A (en) * | 2021-09-22 | 2022-01-14 | 中国电子科技集团公司第十一研究所 | Satellite-borne pump LD strengthening assembly and laser |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000294667A (en) * | 1999-04-09 | 2000-10-20 | Matsushita Electronics Industry Corp | Semiconductor package and its manufacture |
JP2002141596A (en) * | 2000-10-31 | 2002-05-17 | Kyocera Corp | Package for containing optical semiconductor element |
JP2002289960A (en) | 2001-03-27 | 2002-10-04 | Kyocera Corp | Package for housing semiconductor element and semiconductor device |
JP3619473B2 (en) * | 2001-06-25 | 2005-02-09 | 京セラ株式会社 | Package for storing semiconductor elements |
JP2004228532A (en) * | 2003-01-27 | 2004-08-12 | Kyocera Corp | Input/output terminal, semiconductor element housing package, and semiconductor device |
JP2004296577A (en) * | 2003-03-26 | 2004-10-21 | Kyocera Corp | Input/output terminal and package for housing semiconductor element, and semiconductor device |
JP4594073B2 (en) | 2004-11-29 | 2010-12-08 | 京セラ株式会社 | Connection terminal and electronic component storage package and electronic device using the same |
JP2009158511A (en) | 2007-12-25 | 2009-07-16 | Sumitomo Metal Electronics Devices Inc | Input/output terminal and package for housing semiconductor device |
JP5241562B2 (en) * | 2009-02-25 | 2013-07-17 | 京セラ株式会社 | Connection device, package for storing semiconductor element with flexible substrate, and semiconductor device with flexible substrate |
WO2012057286A1 (en) * | 2010-10-27 | 2012-05-03 | 京セラ株式会社 | Wiring board |
JP5769474B2 (en) * | 2011-04-06 | 2015-08-26 | 京セラ株式会社 | Terminal structure, electronic component storage package and electronic device |
US9491873B2 (en) * | 2011-05-31 | 2016-11-08 | Kyocera Corporation | Element housing package, component for semiconductor device, and semiconductor device |
US9596747B2 (en) * | 2011-07-22 | 2017-03-14 | Kyocera Corporation | Wiring substrate and electronic device |
CN103329260B (en) * | 2011-07-26 | 2016-05-11 | 京瓷株式会社 | Semiconductor element is packaging body, the semiconductor device that possesses it and electronic installation for storage |
WO2015046292A1 (en) | 2013-09-25 | 2015-04-02 | 京セラ株式会社 | Electronic component housing package and electronic device |
JP2015103619A (en) * | 2013-11-22 | 2015-06-04 | 京セラ株式会社 | Element accommodation package and mounting structure |
-
2018
- 2018-02-14 US US16/487,546 patent/US11335613B2/en active Active
- 2018-02-14 JP JP2019501252A patent/JP6829303B2/en active Active
- 2018-02-14 WO PCT/JP2018/005080 patent/WO2018155282A1/en unknown
- 2018-02-14 CN CN201880013156.XA patent/CN110337718B/en active Active
- 2018-02-14 EP EP18757046.0A patent/EP3588549A4/en active Pending
-
2021
- 2021-01-19 JP JP2021006525A patent/JP7007502B2/en active Active
-
2022
- 2022-01-06 JP JP2022000784A patent/JP7350902B2/en active Active
- 2022-04-18 US US17/722,529 patent/US11901247B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2021064812A (en) | 2021-04-22 |
US11901247B2 (en) | 2024-02-13 |
JP7007502B2 (en) | 2022-01-24 |
CN110337718B (en) | 2023-06-16 |
JP7350902B2 (en) | 2023-09-26 |
EP3588549A1 (en) | 2020-01-01 |
CN110337718A (en) | 2019-10-15 |
EP3588549A4 (en) | 2020-12-02 |
JP6829303B2 (en) | 2021-02-10 |
JPWO2018155282A1 (en) | 2019-12-12 |
US11335613B2 (en) | 2022-05-17 |
JP2022046748A (en) | 2022-03-23 |
US20220238400A1 (en) | 2022-07-28 |
WO2018155282A1 (en) | 2018-08-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP7197647B2 (en) | High frequency substrates, high frequency packages and high frequency modules | |
CN109863591B (en) | High-frequency substrate, high-frequency package, and high-frequency module | |
US10512155B2 (en) | Wiring board, optical semiconductor element package, and optical semiconductor device | |
US9491873B2 (en) | Element housing package, component for semiconductor device, and semiconductor device | |
US11901247B2 (en) | Insulating component, semiconductor package, and semiconductor apparatus | |
US9805995B2 (en) | Element-accommodating package and mounting structure | |
JP5812671B2 (en) | Device storage package and semiconductor device including the same | |
JP7145311B2 (en) | Wiring substrates, packages for electronic components, and electronic devices | |
JP5709427B2 (en) | Device storage package and semiconductor device including the same | |
US11889618B2 (en) | Wiring board, electronic component package, and electronic apparatus | |
JP7230251B2 (en) | Wiring boards, electronic component packages and electronic devices | |
JP7254011B2 (en) | Wiring substrate, package for storing semiconductor element, and semiconductor device | |
JP4041394B2 (en) | Semiconductor element storage package and semiconductor device | |
JP2019169607A (en) | Package for semiconductor element and semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: KYOCERA CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JUTA, MASAMI;SAKUMOTO, DAISUKE;REEL/FRAME:050118/0865 Effective date: 20180511 |
|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |