US20190206628A1 - Laminated electronic component and mounting structure thereof - Google Patents
Laminated electronic component and mounting structure thereof Download PDFInfo
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- US20190206628A1 US20190206628A1 US16/175,464 US201816175464A US2019206628A1 US 20190206628 A1 US20190206628 A1 US 20190206628A1 US 201816175464 A US201816175464 A US 201816175464A US 2019206628 A1 US2019206628 A1 US 2019206628A1
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- pair
- conductors
- electronic component
- laminated electronic
- side surfaces
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- 239000004020 conductor Substances 0.000 claims abstract description 107
- 238000003475 lamination Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims description 51
- 238000011156 evaluation Methods 0.000 description 21
- 230000005534 acoustic noise Effects 0.000 description 17
- 239000003985 ceramic capacitor Substances 0.000 description 17
- 238000004088 simulation Methods 0.000 description 15
- 229910000679 solder Inorganic materials 0.000 description 12
- 239000000463 material Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 238000004364 calculation method Methods 0.000 description 5
- 238000005259 measurement Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 4
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 3
- 229910002113 barium titanate Inorganic materials 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 230000002238 attenuated effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000002847 impedance measurement Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/005—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/005—Electrodes
- H01G4/012—Form of non-self-supporting electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/252—Terminals the terminals being coated on the capacitive element
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10015—Non-printed capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2045—Protection against vibrations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- At least two types of the internal electrode layers 6 exist. That is, one is an internal electrode layer 6 including only lead-out sections 6 b ( FIG. 2A ) and the other is an internal electrode layer 6 including lead-out sections 6 a and the lead-out sections 6 b ( FIG. 2B ).
- the lead-out sections 6 a are disposed so as to be alternately exposed to any one of the pair of first side surfaces 10 and are electrically connected to the side surface sections 3 a of the first conductors 3 .
- the lead-out sections 6 b are disposed so as to be alternately exposed to any one of the pair of second side surfaces 11 and are electrically connected to the second conductors 4 .
- the internal electrode layers 6 including the lead-out sections 6 a and 6 b are disposed such that conduction is not disposed between the first conductors 3 and between the second conductors 4 .
- an exposed section of the lead-out section 6 a in the first side surface 10 is directivity connected to the first conductor 3 , from the viewpoint that symmetry of vibration is maintained and factors causing vibration of the substrate can be reduced when being mounted, it is preferable that the center portions 8 c of the long sides 8 are included.
- FIG. 3 is a sectional view illustrating a state where the laminated electronic component 1 is mounted on a substrate 12 .
- the projection sections 3 b of the first conductors 3 of the laminated electronic component 1 and land patterns 13 on the substrate 12 are joined via a conductive material such as solder.
- the laminated electronic component 1 and the substrate 12 are joined so as to be opposed with a predetermined gap between the first principal surface 7 A and a mounting surface of the substrate 12 .
- Conductive layers 14 such as solder applied on the land patterns 13 are formed between the first conductors 3 and the land patterns 13 .
- the conductive material to be used is not particularly limited as long as the conductive material has good wettability with the first conductor 3 .
- the stacked body 102 comprises a stack in which dielectric layers 105 and internal electrode layers 106 are alternately laminated.
- the internal electrode layers 106 are electrically connected to the external electrodes 103 in one of both end surfaces of the stacked body 102 .
- the second conductors 4 do not come into contact with the substrate 12 , may be disposed in positions spaced apart from the first conductors 3 on the outer surface of the stacked body 2 , and may be disposed so as to include the centers of the first and second side surfaces 10 and 11 and the vertexes V of the stacked body 2 .
- first conductors 3 are disposed so as to include center portions 9 c of short sides 9 and have side surface sections 3 a extending on second side surfaces 11 .
- Second conductors 4 are disposed on first side surfaces 10 .
- the second conductors 4 may be provided only in a part of the first side surfaces 10 in which the first conductors 3 are not provided.
- the shapes thereof are mainly formed in rectangular shapes and preferable ranges of the dimensions and ratios are described, but the shapes of the first conductor 3 and the second conductor 4 are not limited to the rectangular shape, and other various shapes and irregular shapes are acceptable.
- various changes and modifications can be made without departing from the scope of the invention based on the description regarding the vibration modes and the node-shaped sections 15 of the laminated electronic component 1 confirmed by the simulation described above.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Ceramic Capacitors (AREA)
Abstract
A laminated electronic component includes a rectangular parallelepiped shaped stacked body including dielectric layers and internal electrode layers which are alternately laminated and a pair of first conductors and a pair of second conductors which are disposed on an outer surface of the stacked body. The first conductors are disposed in portions which include centers of long sides of a first principal surface which is positioned in a direction of lamination of the dielectric layers and the internal electrode layers of the stacked body, and do not include a vertex of the stacked body so as to extend from first side surfaces to the first principal surface. The second conductors are disposed on second side surfaces, and the first conductors and the second conductors are spaced apart from each other on an outer surface and electrically connected to each other via the internal electrode layers.
Description
- This application is a divisional application of U.S. patent application Ser. No. 15/325,193, filed Jan. 10, 2017, and claims the benefit of PCT/JP2015/071365, filed Jul. 28, 2015 and JP 2014-155083, filed Jul. 30, 2014. which are incorporated by reference as if fully set forth.
- The present invention relates to a laminated electronic component and a mounting structure thereof.
- In an electronic component of laminated-type composed of a stack of dielectric layers and internal electrode layers, when a DC voltage and an AC voltage are simultaneously applied to an electronic component, distortion occurs in the dielectric layers due to an electrostriction effect by the DC voltage and the electronic component itself vibrates due to the AC voltage. A substrate on which the electronic component is mounted by solder or the like vibrates due to the vibration of the electronic component and when the substrate resonates at a resonance frequency in an audible range, a vibration sound called “acoustic noise” occurs.
- In order to reduce such “acoustic noise”, a method for reducing the vibration by suppressing distortion of the electronic component itself (for example, using a low dielectric constant material having a small electrostriction effect, suppressing the electrostriction effect by an internal electrode pattern, and the like), or a method for suppressing transmission of the vibration to the substrate by absorbing vibration of the electronic component (for example, absorbing vibration by metal terminals and leads, regulating a height of a solder fillet, and the like) has been proposed. For example, in
Patent Literature 1, a mounting structure, in which a conductive material which is a propagation medium of vibration of a capacitor is separated from the most vibrating portion of the capacitor, is provided and thereby the vibration is unlikely to transmit to a circuit substrate, is disclosed. - Patent Literature 1: Japanese Unexamined Patent Publication JP-A 2013-065820
- However, in a case where the distortion of the electronic component itself is suppressed, there is a problem that a capacity cannot be ensured, for example, in a case of a capacitor because a dielectric constant of a material is low and a capacity developing region is small. In addition, in a case where the vibration is absorbed by the metal terminals or the leads, or even in the mounting structure as described in
Patent Literature 1, there was a problem that an attenuation effect of the vibration sufficient for a complicated manufacturing process or mounting process cannot be obtained. - The invention is made in view of the problems described above, and an object thereof is to provide a laminated electronic component capable of reducing acoustic noise when mounting the laminated electronic component on a substrate, and a mounting structure thereof
- A laminated electronic component according to an embodiment of the invention includes a stacked body having a rectangular parallelepiped shape, the stacked body comprising dielectric layers and internal electrode layers which are alternately laminated; and a pair of first conductors and a pair of second conductors disposed on an outer surface of the stacked body, the stacked body comprising a pair of first and second principal surfaces which has a rectangular shape and is positioned in a direction of lamination of the dielectric layers and the internal electrode layers, a pair of first side surfaces adjacent to long sides of the pair of first and second principal surfaces, and a pair of second side surfaces adjacent to short sides of the pair of first and second principal surfaces, the pair of first conductors being disposed in portions which include centers of the long sides or the short sides of the first principal surface or the second principal surface, and do not include a vertex of the stacked body, and the pair of first conductors comprising side surface sections which extend from the long sides on the pair of first side surfaces or from the short sides on the pair of second side surfaces, and projection sections which extend from the long sides or the short sides on the first principal surface or the second principal surface, the pair of second conductors being disposed on the pair of first side surfaces or the pair of second side surfaces, and the pair of first conductors and the pair of second conductors being spaced apart from each other on the outer surface and electrically connected to each other via the internal electrode layers.
- A mounting structure according to an embodiment of the invention includes the laminated electronic component mentioned above; and a substrate which is joined with the projection sections of the pair of first conductors of the laminated electronic component.
- According to the invention, it is possible to provide the laminated electronic component and the mounting structure thereof which are capable of reducing acoustic noise when mounting the laminated electronic component on the substrate.
-
FIGS. 1A to 1C illustrate a laminated electronic component according to a first embodiment, in whichFIG. 1A is a perspective view,FIG. 1B is a sectional view taken along the line A1-A1 ofFIG. 1A , andFIG. 1C is a sectional view taken along the line A2-A2; -
FIG. 2A is a sectional view taken along the line A3-A3 ofFIG. 1A ,FIG. 2B is a sectional view on a first principal surface side compared toFIG. 2A , andFIG. 2C is a plan view ofFIG. 1A as viewed from the first principal surface side; -
FIG. 3 is a sectional view taken along the line A1-A1 ofFIG. 1A illustrating a mounting structure in which the laminated electronic component is mounted on a substrate according to the first embodiment; -
FIG. 4 is a perspective view of a calculation result of a vibration mode of the laminated electronic component at 10 kHz as viewed from a symmetry plane side in the first embodiment; -
FIGS. 5A and 5B illustrate another example of the first embodiment, in whichFIG. 5A is a perspective view andFIG. 5B is a sectional view taken along the line B1-B1 ofFIG. 5A ; -
FIGS. 6A and 6B illustrate a laminated electronic component according to a second embodiment, in whichFIG. 6A is a perspective view andFIG. 6B is a plan view as viewed from the first principal surface side ofFIG. 6A ; -
FIGS. 7A to 7C illustrate a laminated electronic component along a third embodiment, in whichFIG. 7A is a perspective view,FIG. 7B is a plan view as viewed from the first principal surface side ofFIG. 7A , andFIG. 7C is a sectional view of line C-C ofFIG. 7A ; -
FIGS. 8A to 8C illustrate a laminated electronic component of the related art, in whichFIG. 8A is a perspective view,FIG. 8B is a plan view as viewed from a z-axis direction of a coordinate axis, andFIG. 8C illustrates a mounting structure of the related art in which the laminated electronic component is mounted on a substrate, and is a sectional view of line D-D ofFIG. 8B ; -
FIG. 9 is a schematic view of a measuring device of a sound pressure level; -
FIGS. 10A and 10B illustrate a sound pressure level of a laminated ceramic capacitor in the mounting structure of the related art, in whichFIG. 10A is a graph illustrating a measured sound pressure level andFIG. 10B is a graph illustrating a sound pressure level which is obtained by simulation; -
FIG. 11 is a graph illustrating an impedance measurement result in a case where DC bias of 4V is applied to a laminated ceramic capacitor of the related art; -
FIG. 12 is a schematic view of a model of a finite element method used for simulation of impedance of the laminated ceramic capacitor of the related art; -
FIGS. 13A and 13B are perspective views illustrating a calculation result of a vibration mode of the laminated ceramic capacitor of the related art at 10 kHz, in whichFIG. 13A is a view as viewed from a symmetry plane side andFIG. 13B is a view as viewed from a surface side; and -
FIG. 14 is a perspective view schematically illustrating node-shaped sections of a vibration mode in the laminated ceramic capacitor of the related art. - A laminated electronic component and a mounting structure will be described with reference to the drawings. Moreover, in each drawing, the same reference numerals are given to the same members and portions and duplicate description will be omitted. Some of the reference numerals are omitted in some drawings. In addition, for ease of description, xyz coordinate axes are attached to each drawing.
- As illustrated in
FIGS. 1A to 1C , a laminatedelectronic component 1 according to a first embodiment includes a rectangular parallelepiped-shapedstacked body 2, a pair offirst conductors 3, and a pair ofsecond conductors 4 disposed on an outer circumferential side surface.FIG. 1B is a sectional view taken along the line A1-A1 ofFIG. 1A and as illustrated inFIG. 1B thestacked body 2, in whichdielectric layers 5 andinternal electrode layers 6 are alternately laminated in a z-axis direction of a coordinate axis, is provided. Moreover, a direction of lamination of thedielectric layers 5 and theinternal electrode layers 6 may be simply referred to as the direction of lamination. - A first
principal surface 7A and a secondprincipal surface 7B which are a pair of opposed rectangular principal surfaces are positioned in the direction of lamination of thestacked body 2 in the laminatedelectronic component 1 of the embodiment. Both of the firstprincipal surface 7A and the secondprincipal surface 7B are configured of a pair oflong sides 8 and a pair ofshort sides 9. Thestacked body 2 has a pair of opposed first side surfaces 10 adjacent to thelong sides 8 and a pair of opposed second side surfaces 11 adjacent to theshort sides 9 of the first and secondprincipal surfaces - The
first conductor 3 has aside surface section 3 a disposed on thefirst side surface 10 and aprojection section 3 b extending from theside surface section 3 a on the firstprincipal surface 7A. Theside surface section 3 a is disposed closer to the firstprincipal surface 7A than a center portion of thefirst side surface 10 in the direction of lamination. Thesecond conductor 4 is disposed on thesecond side surface 11 and is spaced apart from thefirst conductor 3. That is, thefirst conductor 3 and thesecond conductor 4 are spaced apart from each other and are not connected to each other on the outer surface of thestacked body 2. - In the embodiment, as illustrated in
FIGS. 2A and 2B , at least two types of theinternal electrode layers 6 exist. That is, one is aninternal electrode layer 6 including only lead-outsections 6 b (FIG. 2A ) and the other is aninternal electrode layer 6 including lead-outsections 6 a and the lead-outsections 6 b (FIG. 2B ). - As illustrated in
FIG. 2A , theinternal electrode layers 6 including only the lead-outsections 6 b are further composed of aninternal electrode layer 6 including the lead-outsection 6 b indicated by a solid line and aninternal electrode layer 6 including the lead-outsection 6 b indicated by a broken line. As illustrated inFIG. 1C , the former and the latterinternal electrode layers 6 are alternately laminated. The lead-outsection 6 b indicated by the solid line is exposed to thesecond side surface 11 which is positioned on a left side inFIG. 2A and the lead-outsection 6 b indicated by the broken line is exposed to thesecond side surface 11 which is positioned on a right side inFIG. 2A . - As illustrated in
FIG. 2B , theinternal electrode layers 6 including the lead-outsections 6 a and the lead-outsections 6 b are further composed of aninternal electrode layer 6 including the lead-outsections internal electrode layer 6 including the lead-outsections FIG. 2B , the lead-outsection 6 a indicated by the solid line is exposed to thefirst side surface 10 which is positioned on a lower side and the lead-outsection 6 b indicated by the solid line is exposed to thesecond side surface 11 which is positioned on the left side. The lead-outsection 6 a indicated by the broken line is exposed to thefirst side surface 10 which is positioned on an upper side and the lead-outsection 6 b indicated by the broken line is exposed to thesecond side surface 11 which is positioned on the right side. - In
FIGS. 2A and 2B , theinternal electrode layers 6 including the lead-outsections 6 b indicated by the solid lines are electrically connected to each other by thesecond conductor 4 on the left side and are further electrically connected to theside surface sections 3 a of thefirst conductors 3 on the lower side by the lead-outsections 6 a indicated by the solid lines. Theinternal electrode layers 6 including the lead-outsections 6 b indicated by the broken lines are electrically connected to each other by thesecond conductor 4 on the right side and are further electrically connected to theside surface sections 3 a of thefirst conductors 3 on the upper side by the lead-outsections 6 a indicated by the broken lines. - As described above, the lead-out
sections 6 a are disposed so as to be alternately exposed to any one of the pair of first side surfaces 10 and are electrically connected to theside surface sections 3 a of thefirst conductors 3. The lead-outsections 6 b are disposed so as to be alternately exposed to any one of the pair of second side surfaces 11 and are electrically connected to thesecond conductors 4. Theinternal electrode layers 6 including the lead-outsections first conductors 3 and between thesecond conductors 4. Moreover, inFIG. 1B , an example in which the lead-outsection 6 a of one layer of theinternal electrode layers 6 is connected to each of the pair offirst conductors 3, is illustrated, but the lead-outsections 6 a of plural layer of theinternal electrode layers 6 may be connected to each of the pair offirst conductors 3. - The internal electrode layer 6 (
FIG. 2B ) including the lead-outsections principal surface 7A than the center portion in the direction of lamination in thefirst side surface 10 and the internal electrode layer 6 (FIG. 2A ) including only the lead-outsections 6 b configures the other internal electrode layers 6. -
FIG. 2C is a plan view of the laminatedelectronic component 1 according to the embodiment as viewed from the firstprincipal surface 7A side and illustrates dimensions of each portion. As illustrated inFIG. 2C , thefirst conductors 3 includecenter portions 8 c of thelong sides 8 and are positioned at portions which do not include vertexes V of thestacked body 2. Moreover, thecenter portion 8 c of thelong side 8 is a bisecting point bisecting a length of thelong side 8. - Since an exposed section of the lead-out
section 6 a in thefirst side surface 10 is directivity connected to thefirst conductor 3, from the viewpoint that symmetry of vibration is maintained and factors causing vibration of the substrate can be reduced when being mounted, it is preferable that thecenter portions 8 c of thelong sides 8 are included. - Moreover, structures of the
dielectric layers 5 and theinternal electrode layers 6 illustrated inFIG. 1B are schematic, and actually, a laminated electronic component, in which thedielectric layers 5 and theinternal electrode layers 6 of several layers to hundreds layers are laminated, is often used. This also applies to other embodiments described later. - The dimensions of each portion will be described with reference to
FIG. 2C . InFIG. 2C , the length of thelong side 8 is L1 and a length of theshort side 9 is L2. W1 is a length of thefirst conductor 3 in a length direction (x-axis direction) of thelong side 8 and P1 is a length of theprojection section 3 b in a direction (y-axis direction) perpendicular to thelong side 8. From the viewpoint of reduction of the vibration of the substrate during being mounted on the substrate, it is preferable that a ratio (W1/L1) of W1 to L1 is equal to or less than 0.35 and, from the viewpoint of mounting reliability, is equal to or greater than 0.2. - The mounting structure of the laminated electronic component of the embodiment will be described.
FIG. 3 is a sectional view illustrating a state where the laminatedelectronic component 1 is mounted on asubstrate 12. In the mounting structure of the embodiment, as illustrated inFIG. 3 , theprojection sections 3 b of thefirst conductors 3 of the laminatedelectronic component 1 andland patterns 13 on thesubstrate 12 are joined via a conductive material such as solder. Here, the laminatedelectronic component 1 and thesubstrate 12 are joined so as to be opposed with a predetermined gap between the firstprincipal surface 7A and a mounting surface of thesubstrate 12. Conductive layers 14 such as solder applied on theland patterns 13 are formed between thefirst conductors 3 and theland patterns 13. As described above, in a case where the laminatedelectronic component 1 is mounted on thesubstrate 12 by applying the conductive material, the conductive material to be used is not particularly limited as long as the conductive material has good wettability with thefirst conductor 3. - In
FIG. 3 , H0 is a height of the laminatedelectronic component 1 in the direction of lamination (z-axis direction) of thestacked body 2, H1 is a length in the direction of lamination (z-axis direction) of theside surface section 3 a of thefirst conductor 3 on thefirst side surface 10, and C is a gap between the mounting surface of thesubstrate 12 and the laminatedelectronic component 1. - On the other hand, as illustrated in
FIG. 8A , the laminated electronic component of the related art includes a rectangular parallelepiped-shapedstacked body 102 andexternal electrodes 103 respectively disposed on outer surfaces of both end portions.FIG. 8B is a plan view as viewed from a z-axis direction ofFIG. 8A andFIG. 8C is a sectional view illustrating a mounting structure of the related art. - As illustrated in
FIG. 8C , thestacked body 102 comprises a stack in whichdielectric layers 105 and internal electrode layers 106 are alternately laminated. The internal electrode layers 106 are electrically connected to theexternal electrodes 103 in one of both end surfaces of thestacked body 102. - For example, in a laminated ceramic capacitor which is one of the laminated electronic components, as the
dielectric layer 105, a ferroelectric material such as barium titanate is used, and as theinternal electrode layer 106, a metal material such as Ni is used. In addition, usually, theexternal electrode 103 is formed by baking Cu paste as a base electrode and applying Ni and Sn plating on a surface thereof. - In the laminated electronic component of the related art, as illustrated in
FIG. 8C , theexternal electrodes 103 andland patterns 13 on asubstrate 12 are fixed in a state of being electrically connected viasolders 114. Gaps between theexternal electrodes 103 and theland patterns 13 are filled with thesolders 114, and thesolders 114 further covers theexternal electrodes 103 covering end surfaces, side surfaces, and a part of upper and lower surfaces of thestacked body 102. - When an AC voltage together with a DC voltage (DC bias) is applied to the laminated ceramic capacitor which is mounted in such a state, a piezoelectric property occurs in the
dielectric layers 105 due to the electrostriction effect by the DC voltage and piezoelectric vibration occurs due to the AC voltage. Furthermore, the piezoelectric vibration of the laminated ceramic capacitor is transmitted to thesubstrate 12 via thesolders 114, and thesubstrate 12 vibrates. When thesubstrate 12 resonates at a resonance frequency in an audible range, a vibration sound called “acoustic noise” occurs. - As an example, in a case of a mounting structure of the related art in which the laminated ceramic capacitor which is the laminated electronic component of the related art is mounted on the
substrate 12, acoustic noise was measured. For the measurement, as the laminated ceramic capacitor, Type 1005 laminated ceramic capacitor (capacity 10 μF, rated voltage 4V, hereinafter, referred to as an evaluation component) and as thesubstrate 12, a substrate formed of a FR material of 100×40 mm and thickness of 0.8 mm were used. The laminated ceramic capacitor was mounted on a center of thesubstrate 12 using solder of Sn—Ag—Cu (SAC) type. After mounting the evaluation component on thesubstrate 12, a mounting state was observed with a microscope, and it was confirmed that a fillet height of thesolder 114 was 460 μm and a gap C between thesubstrate 12 and the evaluation component was 45 μm. - As illustrated in
FIG. 9 , the measurement was performed using a measuring device of a sound pressure level. A mounting substrate 21 (hereinafter, simply referred to as the mounting substrate) in which the evaluation component is mounted on thesubstrate 12 was installed within an anechoic box 22 (inner dimensions 600×700 mm and height 600 mm) and acoustic noise was collected by asound collecting microphone 23 installed at a position away 3 mm from the center of thesubstrate 12 in a direction perpendicular to thesubstrate 12. A sound pressure level of the collected sound was measured by an amplifier 24 and a FET analyzer 25 (DS2100 manufactured by Ono Sokki Co., Ltd.). An acoustic noise measurement result is illustrated inFIG. 10A when applying the DC voltage (DC bias) of 4 V and the AC voltage of 20 Hz to 20 kHz and 1 Vp-p to the laminated ceramic capacitor. - Moreover, in
FIG. 10A , the sound pressure level is indicated by A characteristic sound pressure level (dBA) and 0 dBA corresponds to the lowest sound pressure level that a person hears as a sound. This is the sound pressure level weighted for each frequency so as to be close to hearing of a person and is described in a sound level meter (noise meter) standard (JISC 1509-1:2005). - Next, simulation of the piezoelectric vibration of the laminated ceramic capacitor was performed. First, in a state where the DC voltage (DC bias) of 4V is applied to the evaluation component, impedance is measured. A measurement result is illustrated in
FIG. 11 . - Simulation of the impedance was performed by using a model (dielectric material: barium titanate based material, internal electrode: Ni, external electrode: Cu, stacked body dimensions: 1100×620×620 μm, and
external electrode thickness 20 μm) based on the evaluation component. For piezoelectric resistance peaks existing in a frequency region of 2 GHz or more, fitting of material parameters of the evaluation component was performed so as to match an actually measured value.FIG. 12 schematically illustrates a model of a finite element method using the simulation of the impedance. This is a ⅛ model considering symmetry and two cross sections appearing on a front surface and a cross section on a lower side ofFIG. 12 are symmetrical surfaces. - The parameters (elastic stiffness cij and piezoelectric constant eij) of the
dielectric layer 105 obtained by fitting are indicated in Table 1. From Table 1, it can be seen that there is anisotropy (c11>c33 and c22>c33) in the material characteristic of thedielectric layer 105 of the evaluation component. This may be caused by a compression stress by the internal electrode layers 106. -
TABLE 1 Elastic Stiffness and Piezoelectric Constant of Dielectric Layer c11 E 281.5 × 109 N/m2 c12 E 117.2 × 109 N/m2 c13 E 57.2 × 109 N/m2 c22 E 230.8 × 109 N/m2 c23 E 57.2 × 109 N/m2 c33 E 104.3 × 109 N/m2 c44 E 30.9 × 109 N/m2 c55 E 30.9 × 109 N/m2 c66 E 68.9 × 109 N/m2 e31 −22.2 C/m2 e32 −27.8 C/m2 e33 4.75 C/m2 e15 2.94 C/m2 e24 2.94 C/m2 - A model of the mounting structure was created and simulation was performed based on the parameters of the obtained
dielectric layer 105 and the mounting substrate 21 (fillet height 460 μm and a gap between the substrate and the evaluation component 45 μm) which is used in the measurement.FIG. 10B is a graph illustrating a result which is obtained by converting a vibration amplitude of the mounting substrate 21 obtained by simulation into the A characteristic sound pressure level. The frequency characteristic of acoustic noise depends on the vibration characteristic of the evaluation component and the resonant mode of the mounting substrate 21. Therefore, results of the simulation illustrated inFIG. 10B are in good agreement with the actual measured value illustrated inFIG. 10A in the sound pressure level and the frequency characteristic particularly in a high sound pressure and a low frequency region of 10 kHz or less. Therefore, it is possible to confirm the influence on acoustic noise when changing the mounting structure or a structure of the evaluation component itself by performing the simulation using the parameters. - In addition, a vibration mode was calculated in the audible frequency region (20 Hz to 20 kHz) of the evaluation component using the obtained parameters. The ⅛ model was used in the calculation. A calculation result in 10 kHz is illustrated in
FIGS. 13A and 13B . Moreover,FIG. 13A is a view as viewed from an inner side (symmetry plane side) of the ⅛ model andFIG. 13B is a view as viewed on a side opposite toFIG. 13A , that is, from an outside (surface side) of the ⅛ model. Here, a broken line indicates a shape of the evaluation component of a state where the AC voltage is not applied and a solid line indicates a shape of the evaluation component in a state of maximum displacement by the AC voltage. From the results, it can be seen that the evaluation component in the audible frequency region performs expanding vibration in the direction of laminated surface and performs stretching vibration in a thickness direction (direction of lamination). From the results, as illustrated inFIG. 14 schematically indicating the entire evaluation component, it can be seen that regions in which the vibration amplitude is small, that is, regions 15 (hereinafter, node-shaped sections) which can be regarded as nodes of vibration exist in the center portion of each side in two principal surfaces positioned in the direction of lamination of the evaluation component. The node-shaped sections 15 also exist in the laminatedelectronic component 1 of the embodiment as in the evaluation component. Therefore, it is thought that when fixing the laminatedelectronic component 1 to thesubstrate 12 via thefirst conductors 3 and the conductive layers 14 such as solder, the laminatedelectronic component 1 is fixed in the node-shaped sections 15 and thereby propagation of the piezoelectric vibration of the laminatedelectronic component 1 to thesubstrate 12 is suppressed, and acoustic noise can be reduced. - In the embodiment, it is possible to fix the node-shaped sections 15 of the stacked body to the
substrate 12 via thefirst conductors 3 by providing thefirst conductors 3 on the node-shaped sections 15 existing in the laminatedelectronic component 1. - Even if the lead-out
sections 6 a exist only in a part of the direction of lamination, that is, in the vicinity of the firstprincipal surface 7A, simulation of acoustic noise was performed using the following model of the embodiment to confirm that the node-shaped sections 15 of the vibration exist and an effect is achieved on reduction of acoustic noise by the embodiment. External dimensions of thestacked body 2 are the same as those of the evaluation component and theinternal electrode layers 6 having the lead-outsections 6 a are disposed in a range of 90 μm the firstprincipal surface 7A in the direction of lamination. As illustrated inFIG. 2B , the lead-outsections 6 a are exposed at a width 260 μm in the vicinity of thecenter portions 8 c of thelong sides 8 in the first side surfaces 10 and are electrically connected to thefirst conductors 3. As illustrated inFIGS. 2C and 3 , in thefirst conductor 3, W1 was 280 μm, H1 was 100 μm, and P1 was 80 μm. In addition, in the mounting structure of the embodiment, C was 70 μm. Other conditions regarding the laminatedelectronic component 1 were the same as those of the simulation of acoustic noise in the evaluation component described above. -
FIG. 4 illustrates a vibration mode of the laminatedelectronic component 1 of the embodiment in 10 kHz. Moreover, in the calculation of the vibration mode, a ½ model was used in consideration of the symmetry of the laminatedelectronic component 1 of the embodiment.FIG. 4 illustrates the ½ model as viewed from the symmetry plane side. Here, a broken line indicates a shape of the laminatedelectronic component 1 of a state where the AC voltage is not applied and a solid line indicates a shape of the laminatedelectronic component 1 in a state where the laminatedelectronic component 1 is displaced to the maximum level by the AC voltage. It can be confirmed that the node-shaped sections 15 of the vibration exist in the center portion of thelong side 8 and theshort side 9 constituting the principal surface 7. Moreover, in the simulation of the vibration mode of the embodiment, a model in which P1 of thefirst conductor 3 is 0 μm was used. - If results obtained by the simulation of the sound pressure in the embodiment are averaged over a frequency region of 5 Hz to 20 kHz, an average value of the sound pressure level was reduced by 19 dBa with respect to the mounting structure of the related art.
- Moreover, in the embodiment, in the simulation described above, a ratio (W1/L1) of W1 (280 μm) to L1 (1100 μm) was set to 0.25, but even if the ratio is set to 0.35, the sound pressure level can be reduced by approximately 10 dBA with respect to that of the related art. In addition, it is preferable that W1/L1 is equal to or greater than 0.2 from the viewpoint of mountability.
- Moreover, in the mounting structure of the embodiment, the laminated
electronic component 1 does not directivity come into contact with the mounting surface of thesubstrate 12. Particularly, a ratio (C/H0) of C that is the gap between the laminatedelectronic component 1 and the mounting surface of thesubstrate 12 to H0 is equal to or greater than 0.05, particularly, is equal to or greater than 0.1. - Furthermore, according to the results of the vibration mode analysis of the evaluation component described above and the embodiment, since the vibration amplitude is large in the vicinity of the center of each surface constituting the
stacked body 2, it is preferable that a ratio (H1/H0) of H1 to H0 is equal to or less than 0.4. In addition, since the vibration amplitude is large in the vicinity of the center even in the principal surface 7, a length P1 of thefirst conductor 3 in a direction perpendicular to thelong side 8 is equal to or less than 0.25 as a ratio (P1/L2) to L2. - As described above, in the embodiment, the laminated
electronic component 1 is fixed to thesubstrate 12 by thefirst conductors 3. Therefore, thefirst conductors 3 are disposed in the node-shaped sections 15 of the laminatedelectronic component 1, that is, in portions which include thecenter portions 8 c of thelong sides 8 of the firstprincipal surface 7A and do not include the vertexes V of thestacked body 2, and thereby acoustic noise can be suppressed. On the other hand, thesecond conductors 4 are responsible for electrical connection between theinternal electrode layers 6 and do not contribute to fixation with thesubstrate 12. Therefore, thesecond conductors 4 do not come into contact with thesubstrate 12, may be disposed in positions spaced apart from thefirst conductors 3 on the outer surface of thestacked body 2, and may be disposed so as to include the centers of the first and second side surfaces 10 and 11 and the vertexes V of thestacked body 2. - As illustrated in
FIGS. 1A to 1C , for example, thesecond conductors 4 may be substantially disposed over the entire surface of the second side surfaces 11 (side surfaces on which theside surface sections 3 a of thefirst conductors 3 are not provided) or may be disposed on the second side surfaces 11 only in a part in a direction (y-axis direction) of the short side and over an entirety in the direction of lamination (z-axis direction) (across from theshort side 9 of the firstprincipal surface 7A to theshort side 9 of the secondprincipal surface 7B). It may be disposed so as to include theshort side 9 of the secondprincipal surface 7B and not to include theshort side 9 of the firstprincipal surface 7A. - Moreover, in the embodiment, the
first conductors 3 may be disposed not only on portions of the firstprincipal surface 7A side but also on the same portions of the secondprincipal surface 7B side as illustrated inFIGS. 5A and 5B . It is preferable that dispositions of thefirst conductors 3 disposed on the secondprincipal surface 7B side are symmetrical with those on the firstprincipal surface 7A side in the vertical direction. Therefore, all thefirst conductors 3 disposed on the first and secondprincipal surface - In a second embodiment, as illustrated in
FIGS. 6A and 6B ,first conductors 3 are disposed so as to includecenter portions 9 c ofshort sides 9 and haveside surface sections 3 a extending on second side surfaces 11.Second conductors 4 are disposed on first side surfaces 10. In the first embodiment, an example in which thesecond conductors 4 are disposed substantially over the entire surfaces of the second side surfaces 11 in which thefirst conductors 3 are not provided, is illustrated, but as in the second embodiment, thesecond conductors 4 may be provided only in a part of the first side surfaces 10 in which thefirst conductors 3 are not provided. In addition, thesecond conductors 4 is only required to be spaced apart from thefirst conductors 3 on an outer surface of astacked body 2 and a part thereof may go around to first and secondprincipal surfaces side surface sections 3 a of thefirst conductors 3 are provided. - In a third embodiment, as illustrated in
FIGS. 7A to 7C ,first conductors 3 are provided so as to includecenter portions 8 c oflong sides 8 and haveside surface sections 3 a extending on first side surfaces 10. In the embodiment, two pairs ofsecond conductors 4 are disposed on the first side surfaces 10 similar to thefirst conductors 3. In the embodiment,internal electrode layers 6 including lead-outsections FIG. 7C are positioned on a firstprincipal surface 7A side of a center portion in the direction of lamination. - As described above, the
second conductors 4 is only required to be spaced apart from thefirst conductors 3 in the first side surfaces 10, may be disposed on the same side surfaces as theside surface sections 3 a of thefirst conductors 3, or may be disposed on a boundary between thefirst side surface 10 and thesecond side surface 11. In addition, thesecond conductors 4 may be not only one pair but also two or more pairs. - In addition, the
internal electrode layer 6 including only the lead-outsection 6 a may be provided. That is, theinternal electrode layer 6 including only the lead-outsection 6 a may be disposed closest to the firstprincipal surface 7A of thestacked body 2, theinternal electrode layers 6 including the lead-outsection 6 a and the lead-outsection 6 b, and theinternal electrode layers 6 including only the lead-outsections 6 b may be sequentially disposed and thereby thesecond conductors 4 may be disposed spaced apart from thelong side 8 or theshort side 9. - In each embodiment described above, the shape and the disposition of the
internal electrode layers 6 may be appropriately changed according to the disposition of thefirst conductors 3 and thesecond conductors 4. - Moreover, in each embodiment described above, for the
first conductors 3 and thesecond conductors 4, the shapes thereof are mainly formed in rectangular shapes and preferable ranges of the dimensions and ratios are described, but the shapes of thefirst conductor 3 and thesecond conductor 4 are not limited to the rectangular shape, and other various shapes and irregular shapes are acceptable. In addition, various changes and modifications can be made without departing from the scope of the invention based on the description regarding the vibration modes and the node-shaped sections 15 of the laminatedelectronic component 1 confirmed by the simulation described above. - The invention is particularly suitably used in a case where, for example, a laminated ceramic capacitor, which uses a ferroelectric material such as barium titanate based material for the
dielectric layer 5 and uses a metal material such as Ni, Cu, Ag, and Ag—Pd for theinternal electrode layer 6, is the laminatedelectronic component 1. Also in other laminatedelectronic components 1, it is applicable to a case where it is necessary to suppress excitation of thesubstrate 12 on which the laminatedelectronic component 1 is mounted and the like due to the piezoelectric vibration of the laminatedelectronic component 1 itself. The invention can exert a remarkable effect particularly in the laminatedelectronic component 1 of a model of Type 1005 or larger (external dimensions of Type 1005 or larger). - The invention is applicable to various existing laminated
electronic components 1. In addition, there is also an advantage that a special jig is not required for mounting on thesubstrate 12. - Moreover, in the embodiment, although the laminated ceramic capacitor having a general shape is described as an example of the laminated
electronic component 1, in addition, it is applicable to a laminatedelectronic component 1 of a thin type or having various structures. - Furthermore, as the
first conductor 3 and thesecond conductor 4, for example, a material which is obtained by plating Ni and Sn on a base electrode made of Cu which is often used as the external electrode of the laminated ceramic capacitor, may be employed, but thefirst conductor 3 and thesecond conductor 4 which are composed only of a plating electrode without using the base electrode, can be suitably used. Since the base electrode composed of Cu is relatively soft, the piezoelectric vibration of thestacked body 2 is absorbed and attenuated to some extent, but in a case of only the plating electrode, the piezoelectric vibration of thestacked body 2 is not attenuated by thefirst conductor 3 and acoustic noise is remarkable. Therefore, it is possible to obtain a larger acoustic noise suppression effect by applying the invention. - 1: Laminated electronic component
- 2, 102: Stacked body
- 3: First conductor
- 103: External electrode
- 4: Second conductor
- 5, 105: Dielectric layer
- 6, 106: Internal electrode layer
- 7A: First principal surface
- 7B: Second principal surface
- 8: Long side
- 8 c: Center of long side
- 9: Short side
- 9 c: Center of short side
- 10: First side surface
- 11: Second side surface
- 12: Substrate
- 13: Land pattern
- 14, 114: Solder
- 15: Node-shaped section
- 21: Mounting substrate
- 22: Anechoic box
- 23: Sound collecting microphone
- 24: Amplifier
- 25: FET analyzer
Claims (8)
1. A laminated electronic component comprising:
a stacked body having a rectangular parallelepiped shape, the stacked body comprising dielectric layers and internal electrode layers which are alternately laminated; and
a pair of first conductors and a pair of second conductors disposed on an outer surface of the stacked body,
the stacked body comprising a pair of first and second principal surfaces which has a rectangular shape and is positioned in a direction of lamination of the dielectric layers and the internal electrode layers, a pair of first side surfaces adjacent to long sides of the pair of first and second principal surfaces, and a pair of second side surfaces adjacent to short sides of the pair of first and second principal surfaces,
the pair of first conductors being disposed in portions which include centers of the long sides of the first principal surface or the second principal surface, and do not include a vertex of the stacked body, and the pair of first conductors comprising side surface sections which extend from the long sides on the pair of first side surfaces, and projection sections which extend from the long sides or the short sides on the first principal surface,
the pair of second conductors being disposed on the pair of first side surfaces or the pair of second side surfaces, and
the pair of first conductors and the pair of second conductors being spaced apart from each other on the outer surface and electrically connected to each other via the internal electrode layers.
2. The laminated electronic component according to claim 1 , wherein a length in the direction of lamination of each of the side surface sections of the pair of first conductors is equal to or less than 0.4 time a length in the direction of lamination of the stacked body.
3. The laminated electronic component according to claim 1 , wherein the side surface sections of the pair of first conductors, and the pair of second conductors are respectively disposed on different side surfaces among the pair of first side surfaces and the pair of second side surfaces.
4. The laminated electronic component according to claim 3 , wherein the side surface sections of the pair of first conductors are disposed on the pair of first side surfaces, and the pair of second conductors is disposed on the pair of second side surfaces.
5. The laminated electronic component according to claim 1 , wherein the side surface sections of the pair of first conductors and the pair of second conductors are disposed on one of the pair of first side surfaces.
6. The laminated electronic component according to claim 1 , wherein the pair of second conductors is disposed over an entirety in the direction of lamination of the pair of first side surfaces or the pair of second side surfaces.
7. A mounting structure, comprising:
the laminated electronic component according to claim 1 ; and
a substrate which is joined with the projection sections of the pair of first conductors of the laminated electronic component.
8. The laminated electronic component according to claim 1 , wherein when a length of the long sides is denoted by L and a length of the pair of first conductors along the long sides is denoted by W, a ratio of W to L is equal to or less than 0.35.
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US16/175,464 US20190206628A1 (en) | 2014-07-30 | 2018-10-30 | Laminated electronic component and mounting structure thereof |
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JP2014155083 | 2014-07-30 | ||
PCT/JP2015/071365 WO2016017634A1 (en) | 2014-07-30 | 2015-07-28 | Laminated electronic component and mounting structure thereof |
US201715325193A | 2017-01-10 | 2017-01-10 | |
US16/175,464 US20190206628A1 (en) | 2014-07-30 | 2018-10-30 | Laminated electronic component and mounting structure thereof |
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PCT/JP2015/071365 Division WO2016017634A1 (en) | 2014-07-30 | 2015-07-28 | Laminated electronic component and mounting structure thereof |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060022154A1 (en) * | 2004-07-29 | 2006-02-02 | Schmitkons James W | Shuttered lamp assembly and method of cooling the lamp assembly |
JP2012069766A (en) * | 2010-09-24 | 2012-04-05 | Tdk Corp | Multilayer capacitor |
US20140041915A1 (en) * | 2012-08-10 | 2014-02-13 | Murata Manufacturing Co., Ltd. | Monolithic capacitor mounting structure and monolithic capacitor |
US20150032537A1 (en) * | 2013-07-26 | 2015-01-29 | Bank Of America Corporation | Analysis of e-receipt data for loyalty card usage |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6380619B2 (en) * | 1998-03-31 | 2002-04-30 | Tdk Corporation | Chip-type electronic component having external electrodes that are spaced at predetermined distances from side surfaces of a ceramic substrate |
JP4230469B2 (en) | 2005-03-31 | 2009-02-25 | Tdk株式会社 | Multilayer capacitor |
JP2007194312A (en) * | 2006-01-18 | 2007-08-02 | Matsushita Electric Ind Co Ltd | Multilayer ceramic capacitor |
JP2012023322A (en) * | 2010-07-13 | 2012-02-02 | Maruwa Co Ltd | Chip type laminated ceramic capacitor and method for manufacturing the same |
JP5884653B2 (en) | 2011-09-01 | 2016-03-15 | 株式会社村田製作所 | Mounting structure |
US9653212B2 (en) * | 2013-08-13 | 2017-05-16 | Samsung Electro-Mechanics Co., Ltd. | Multilayer ceramic capacitor and board for mounting thereof |
KR20140038876A (en) | 2013-08-13 | 2014-03-31 | 삼성전기주식회사 | Multi-layered ceramic capacitor and board for mounting the same |
-
2015
- 2015-07-28 US US15/325,193 patent/US10141112B2/en active Active
- 2015-07-28 JP JP2016538363A patent/JP6239764B2/en active Active
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060022154A1 (en) * | 2004-07-29 | 2006-02-02 | Schmitkons James W | Shuttered lamp assembly and method of cooling the lamp assembly |
JP2012069766A (en) * | 2010-09-24 | 2012-04-05 | Tdk Corp | Multilayer capacitor |
US20140041915A1 (en) * | 2012-08-10 | 2014-02-13 | Murata Manufacturing Co., Ltd. | Monolithic capacitor mounting structure and monolithic capacitor |
US20150032537A1 (en) * | 2013-07-26 | 2015-01-29 | Bank Of America Corporation | Analysis of e-receipt data for loyalty card usage |
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US10141112B2 (en) | 2018-11-27 |
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