JP2012023322A - Chip type laminated ceramic capacitor and method for manufacturing the same - Google Patents

Chip type laminated ceramic capacitor and method for manufacturing the same Download PDF

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JP2012023322A
JP2012023322A JP2010171102A JP2010171102A JP2012023322A JP 2012023322 A JP2012023322 A JP 2012023322A JP 2010171102 A JP2010171102 A JP 2010171102A JP 2010171102 A JP2010171102 A JP 2010171102A JP 2012023322 A JP2012023322 A JP 2012023322A
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chip
external
ceramic capacitor
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external terminal
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Yasushi Kojima
靖 小島
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Maruwa Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • H01G4/252Terminals the terminals being coated on the capacitive element
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors

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  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a chip type laminated ceramic capacitor capable of improving a mounting efficiency when leg-shaped external terminals are attached thereto, and suppressing vibration sound of a circuit board when mounted on the board.SOLUTION: A method for manufacturing a chip type laminated ceramic capacitor is provided. In the method, when leg-shaped external terminals 14a and 14b are attached to external electrodes 12a and 12b at both ends of the chip type laminated ceramic capacitor 10, first metal plating layers 13a and 13b having a melting point of 400°C or more are formed on external electrodes, respectively, and the external terminals, each having a nealy U-shaped front shape in which the center of an upper end is cut away, and having a L-shaped side surface formed by bending its lower end at a nealy right angle, are fixed to the external electrodes with spot welding via the first metal plating layers, respectively, and second metal plating layers 16a and 16b are formed on the lower ends 15d of the external terminals, respectively. Accordingly, when the external terminals are soldered on lands of a circuit board, this improves solder wettability and prevents the external terminals from removing due to heating at the time of soldering.

Description

本発明は、脚状の外部端子が外部電極に固定されたチップ型積層セラミックコンデンサ及びその製造方法に関するものである。  The present invention relates to a chip-type multilayer ceramic capacitor in which leg-shaped external terminals are fixed to external electrodes, and a method for manufacturing the same.

従来から、図17に示すように、脚状の外部端子1が外部電極2に固定されたチップ型積層セラミックコンデンサ3は公知である(特開2008−130954号公報図6)。すなわち、チップ型セラミック体4の内部に所定間隔をおいて複数層の内部電極(図示なし)が交互に両端部4a,4b寄りに積層配向されているチップ型積層セラミック体5に対して、同じく両端部4a、4bに存在する外部電極2から下方に延ばした脚状の外部端子1を介して、電子回路基板(図示なし)のランドに実装可能にした構造のチップ型積層セラミックコンデンサ3は公知である。  Conventionally, as shown in FIG. 17, a chip-type multilayer ceramic capacitor 3 in which a leg-like external terminal 1 is fixed to an external electrode 2 is known (Japanese Patent Laid-Open No. 2008-130954, FIG. 6). That is, the same applies to the chip-type multilayer ceramic body 5 in which a plurality of layers of internal electrodes (not shown) are alternately stacked near the both ends 4a and 4b with a predetermined interval inside the chip-type ceramic body 4. A chip-type multilayer ceramic capacitor 3 having a structure that can be mounted on a land of an electronic circuit board (not shown) via leg-like external terminals 1 extending downward from external electrodes 2 existing at both ends 4a and 4b is known. It is.

この公知技術によると、前記外部端子1として、上端部1aの中央が切り欠かれて正面形状がほぼU字状をなし、下端部1bがほぼ直角に曲げ加工されて側面がL字形をなす帯状金板が使用されている。そして、前記外部電極1と前記外部電極2とははんだ付けにより固定されている。  According to this known technique, as the external terminal 1, the center of the upper end portion 1a is cut out, the front shape is substantially U-shaped, and the lower end portion 1b is bent at a substantially right angle so that the side surface is L-shaped. A metal plate is used. The external electrode 1 and the external electrode 2 are fixed by soldering.

特開2008−130954号公報    JP 2008-130954 A

この公知例による前記外部端子1が特定の工程を経て製造されるので、外部電極2に対する外部端子1の振動吸収効果により、チップ型積層セラミックコンデンサ3そのものがDC−DCコンバータ等の電子回路基板に実装されたとき、誘電体セラミックの電歪効果による振動が生じ、電子回路基板に振動を伝播することによる発生する振動音、いわゆる「基板鳴き」を抑制できるという効果を発揮している。  Since the external terminal 1 according to this known example is manufactured through a specific process, the chip-type multilayer ceramic capacitor 3 itself becomes an electronic circuit board such as a DC-DC converter due to the vibration absorption effect of the external terminal 1 with respect to the external electrode 2. When mounted, the dielectric ceramic vibrates due to the electrostrictive effect, thereby exhibiting the effect of suppressing so-called “substrate squealing” generated by propagating the vibration to the electronic circuit board.

しかしながら、外部電極1に対する外部端子2に取り付け効率をさらに向上させたり、回路基板へのはんだ付け実装時の加熱による外部端子とチップ型積層セラミックコンデンサの接続部のはんだ再溶融による部品脱落を防止したりするには、前記公知技術には限度がある。従って、本発明の課題は、脚状の外部端子が外部電極に固定されたチップ型積層セラミックコンデンサを製造する過程における外部電極に対する外部端子に取り付け効率を向上させるとともに、得られたチップ型積層セラミックコンデンサを回路基板へはんだ付けして実装する際、加熱による外部端子離脱を防止し、基板鳴きをさらに抑制することにある。  However, the efficiency of attaching to the external terminal 2 with respect to the external electrode 1 can be further improved, and the component can be prevented from falling off due to the remelting of the solder between the connection portion of the external terminal and the chip-type multilayer ceramic capacitor due to heating during soldering mounting on the circuit board There is a limit to the known technology. Accordingly, an object of the present invention is to improve the efficiency of attachment to an external terminal with respect to an external electrode in the process of manufacturing a chip-type multilayer ceramic capacitor in which leg-shaped external terminals are fixed to the external electrode, and to obtain the obtained chip-type multilayer ceramic When soldering and mounting a capacitor to a circuit board, it is intended to prevent the external terminal from being detached by heating and further suppress board noise.

本発明は、前記の課題を解決するために、相対向する両端部に存在する外部電極から下方に延ばした脚状の外部端子を介して、電子回路基板に実装可能にした構造のチップ型積層セラミックコンデンサにおいて、前記外部端子として、上端部中央が切り欠かれて正面形状がほぼU字状をなし、下端部がほぼ直角に曲げ加工されて側面がL字形をなす帯状金属板を使用するとともに、外部電極の少なくとも端面に融点、400℃以上の第一金属めっき層を形成して、その金属層に前記外部端子の上端部をスポット溶接することにより、前記外部電極に対して外部端子を固定し、さらに外部端子の下端部にSn、Ag、Au、Bi、Znの1種から選ばれる金属単体又は複数種から選ばれる金属合金からなる第二金属めっき層を形成した構造のチップ型積層セラミックコンデンサにする。  In order to solve the above-described problems, the present invention provides a chip-type laminated structure that can be mounted on an electronic circuit board via leg-shaped external terminals extending downward from external electrodes present at opposite ends. In the ceramic capacitor, as the external terminal, a band-shaped metal plate is used in which the center of the upper end is notched and the front shape is substantially U-shaped, the lower end is bent at a substantially right angle, and the side surface is L-shaped. The external terminal is fixed to the external electrode by forming a first metal plating layer having a melting point of 400 ° C. or higher on at least the end surface of the external electrode and spot welding the upper end of the external terminal to the metal layer. In addition, a second metal plating layer made of a single metal selected from one of Sn, Ag, Au, Bi, and Zn or a metal alloy selected from a plurality of types is formed on the lower end of the external terminal. To flop type multilayer ceramic capacitor.

本発明の上記チップ型積層セラミックコンデンサにおいては、外部電極の端面に第一金属めっき層が所定の厚みで形成されているので、外部電極に対する外部端子のスポット溶接が可能になり、その結果、外部電極に対する外部端子に取り付け効率が向上する。また、外部端子の下端部に対して所定の高さの第二金属めっき層が形成されていので、その外部端子を介してチップ型積層セラミックコンデンサを電子回路基板のランドにはんだ付けして実装する際、外部端子の下端からはんだが這い上がる高さを第二金属めっき層の所定の高さに抑制でき、その結果、誘電体セラミックの電歪効果による振動が外部端子から電子回路基板に伝播するのを最小限に抑制できるのみならず、前記はんだ溶接時の加熱による外部端子接続部の離脱を防止することができる。  In the chip-type multilayer ceramic capacitor of the present invention, since the first metal plating layer is formed with a predetermined thickness on the end face of the external electrode, spot welding of the external terminal to the external electrode becomes possible. Mounting efficiency is improved on the external terminal with respect to the electrode. Further, since the second metal plating layer having a predetermined height is formed on the lower end portion of the external terminal, the chip type multilayer ceramic capacitor is soldered and mounted on the land of the electronic circuit board via the external terminal. In this case, the height of the solder rising from the lower end of the external terminal can be suppressed to a predetermined height of the second metal plating layer, and as a result, vibration due to the electrostrictive effect of the dielectric ceramic propagates from the external terminal to the electronic circuit board. Can be suppressed to a minimum, and separation of the external terminal connection portion due to heating during the solder welding can be prevented.

また、本発明は、前記の課題を解決するために、チップ型セラミック体の内部に所定間隔をおいて複数層の内部電極が交互に両端部寄りに積層配向されているチップ型積層セラミック体に外部電極を形成する工程と、前記外部電極の端面に融点、400℃以上の第一金属めっき層を被覆する工程と、上端部中央が切り欠かれて正面形状がほぼU字状をなし、下端部がほぼ直角に曲げ加工されて側面がL字形をなす帯状金属板からなる脚状外部端子を前記第一金属めっき層に対してスポット溶接して固定する工程とからなるチップ型積層セラミックコンデンサの製造方法を採用する。  In order to solve the above problems, the present invention provides a chip-type multilayer ceramic body in which a plurality of layers of internal electrodes are alternately stacked and oriented closer to both ends at a predetermined interval inside the chip-type ceramic body. A step of forming an external electrode, a step of coating the end surface of the external electrode with a first metal plating layer having a melting point of 400 ° C. or higher, a center of the upper end portion is notched, and the front shape is substantially U-shaped, and the lower end A chip-type multilayer ceramic capacitor comprising a step of spot-welding and fixing a leg-shaped external terminal made of a strip-shaped metal plate whose side is bent at a substantially right angle and having an L-shaped side surface to the first metal plating layer Adopt manufacturing method.

そして、この製造方法において前記外部端子は、次のステップ、すなわち(1)帯状金属板の長手方向に添う一縁側にSn、Ag、Au、Bi、Znの1種から選ばれる金属単体又は複数種から選ばれる金属合金からなる第二金属めっき層を形成するめっき金属板製造ステップと、(2)そのめっき金属板を打ち抜き加工して、めっき金属板の他の縁側に前記外部端子の上端部と下端部となる部分を有する外部端子の前駆体を複数個分枝させる前駆体製造ステップと、(3)前記前駆体において外部端子の上端部となる部分を前記チップ型積層セラミック体の第一金属めっき層にスポット溶接して固定する前駆体固定ステップと、(4)前記チップ型積層セラミック体に固定された前記前駆体を前記めっき金属板から切り落として複数個の脚状外部端子を分離するステップとを経て、外部端子が製作され、その結果、外部電極に対する外部端子の製造と固定を著しく効率化できる。  In this manufacturing method, the external terminal is a single step or a plurality of types selected from the following steps, that is, (1) Sn, Ag, Au, Bi, Zn on one edge side along the longitudinal direction of the strip-shaped metal plate. A plating metal plate manufacturing step for forming a second metal plating layer made of a metal alloy selected from: (2) punching the plating metal plate, and an upper end portion of the external terminal on the other edge side of the plating metal plate; A precursor manufacturing step of branching a plurality of precursors of external terminals having a lower end portion; and (3) a first metal of the chip-type multilayer ceramic body that is the upper end portion of the external terminal in the precursor. A precursor fixing step for fixing by spot welding to the plating layer; and (4) a plurality of legs by cutting off the precursor fixed to the chip-type multilayer ceramic body from the plated metal plate. Through and separating the external terminals are fabricated external terminal, as a result, be significantly more efficient manufacturing and fixing of the external terminals for the external electrodes.

本発明は、前述の手段を採用することにより、脚状の外部端子が外部電極に固定されたチップ型積層セラミックコンデンサを製造する過程における外部電極に対する外部端子に取り付け効率を向上させることができるとともに、得られたチップ型積層セラミックコンデンサを基板にはんだ溶接する際、加熱による外部端子接続部の離脱を防止することができ、かつ基板鳴きのさらなる抑制を可能にするという優れた効果を発揮する。  By adopting the above-mentioned means, the present invention can improve the efficiency of attaching to the external terminal with respect to the external electrode in the process of manufacturing the chip type multilayer ceramic capacitor in which the leg-shaped external terminal is fixed to the external electrode. When the obtained chip-type multilayer ceramic capacitor is solder-welded to the substrate, the external terminal connection portion can be prevented from being detached due to heating, and the excellent effect of enabling further suppression of substrate squealing is exhibited.

図1は、本発明に係るチップ型積層セラミックコンデンサの斜視図である。FIG. 1 is a perspective view of a chip type multilayer ceramic capacitor according to the present invention. 図2は、同正面図である。FIG. 2 is a front view of the same. 図3は、本発明に係るチップ型積層セラミックコンデンサの他の態様を示す正面図である。FIG. 3 is a front view showing another embodiment of the chip-type multilayer ceramic capacitor according to the present invention. 図4は、本発明に係るチップ型積層セラミックコンデンサの製造過程を示す部分破断正面図である。FIG. 4 is a partially broken front view showing the manufacturing process of the chip type multilayer ceramic capacitor according to the present invention. 図5は、本発明に係る外部端子を示す斜視図である。FIG. 5 is a perspective view showing an external terminal according to the present invention. 図6は、外部端子を製造するための帯状金属板の斜視図である。FIG. 6 is a perspective view of a band-shaped metal plate for manufacturing an external terminal. 図7は、前記金属板の第一加工ステップを示す斜視図である。FIG. 7 is a perspective view showing a first processing step of the metal plate. 図8は、前記金属板の第二加工ステップを示す斜視図である。FIG. 8 is a perspective view showing a second processing step of the metal plate. 図9は、前記金属板の第三加工ステップを示す斜視図である。FIG. 9 is a perspective view showing a third processing step of the metal plate. 図10は、本発明に係るめっき金属板を外部端子の前駆体に加工する第一ステップを示す正面図である。FIG. 10 is a front view showing a first step of processing the plated metal plate according to the present invention into a precursor of an external terminal. 図11は、同側面図である。FIG. 11 is a side view of the same. 図12は、同第二ステップを示す正面図である。FIG. 12 is a front view showing the second step. 図13は、同側面図である。FIG. 13 is a side view of the same. 図14は、チップ型積層セラミックコンデンサに対して前記前駆体をスポット溶接する状態を示す側面図である。FIG. 14 is a side view showing a state in which the precursor is spot-welded to a chip-type multilayer ceramic capacitor. 図15は、同正面図である。FIG. 15 is a front view of the same. 図16は、前記前駆体から外部端子が切り出される状態を示す側面図である。FIG. 16 is a side view showing a state in which external terminals are cut out from the precursor. 図17は、公知技術の斜視図である。FIG. 17 is a perspective view of a known technique.

次に、本発明を実施するための形態について説明すると、図1及び図2に示すように、本発明に係るチップ型積層セラミックコンデンサ(以下、「セラミックコンデンサ」という。)10は、周知のセラミック誘電体からなる直方体状のチップ型セラミック体11と、その内部に所定間隔をおいて交互に両端部11a、11b寄りに積層配向されている複数層の内部電極(図示なし)と、前記両端部11a、11bに被覆形成されている外部電極12a、12bとから構成されている。  Next, a mode for carrying out the present invention will be described. As shown in FIGS. 1 and 2, a chip-type multilayer ceramic capacitor (hereinafter referred to as “ceramic capacitor”) 10 according to the present invention is a known ceramic. A rectangular parallelepiped chip-type ceramic body 11 made of a dielectric, a plurality of layers of internal electrodes (not shown) that are alternately stacked near the both end portions 11a and 11b at a predetermined interval, and the both end portions The external electrodes 12a and 12b are formed on the 11a and 11b.

さらに、本発明に係るセラミックコンデンサ10は、外部電極12a、12bの少なくとも端面、好ましくは露出面に、Ni,Fe−Ni,Fe−Ni−Co,Fe−Ni−Cr,Cu,Cu−Sn,Cu−Sn−P,Cu−Ni,Cu−Zn,Cu−Zn−Niから選ばれる融点、400℃以上の金属、好ましくはNiからなる第一金属めっき層13a、13bが厚さ2〜20μm、好ましくは5〜15μmの厚さにめっき法により形成されている。なお、前記厚みを2μm未満であると、以降に詳述する外部端子に対してスポット溶接の強度が低下するし、逆に20μmを超えると、必要以上にめっき時間が増加してコスト高になる。  Furthermore, the ceramic capacitor 10 according to the present invention has Ni, Fe—Ni, Fe—Ni—Co, Fe—Ni—Cr, Cu, Cu—Sn, at least the end surfaces of the external electrodes 12a and 12b, preferably exposed surfaces. The first metal plating layers 13a and 13b made of a melting point selected from Cu-Sn-P, Cu-Ni, Cu-Zn, and Cu-Zn-Ni, a metal having a temperature of 400 ° C or higher, preferably Ni, have a thickness of 2 to 20 µm, Preferably, it is formed by plating to a thickness of 5 to 15 μm. In addition, if the thickness is less than 2 μm, the strength of spot welding is reduced with respect to the external terminals described in detail below. Conversely, if the thickness exceeds 20 μm, the plating time is increased more than necessary and the cost is increased. .

また、本発明に係るセラミックコンデンサ10の外部電極12a、12bの両端面には、前記第一金属めっき層13a、13bを介して、脚状の外部端子14a、14bが固着されている。外部端子14a、14bは、短尺帯状金属板を使用して後述する所定のステップを経て製作され、その上端部15uと下端部15dが特定の形状・構造を有している。すなわち、上端部15uにおいては、その中央が切り欠かれて正面形状がほぼU字状をなし、下端部15dにおいては、それがほぼ直角に外方又は内方に曲げ加工されて側面がL字形をなしている。  Further, leg-shaped external terminals 14a and 14b are fixed to both end faces of the external electrodes 12a and 12b of the ceramic capacitor 10 according to the present invention via the first metal plating layers 13a and 13b. The external terminals 14a and 14b are manufactured through a predetermined step, which will be described later, using a short belt-like metal plate, and the upper end portion 15u and the lower end portion 15d have a specific shape and structure. That is, the center of the upper end portion 15u is notched and the front shape is substantially U-shaped, and the lower end portion 15d is bent outward or inward substantially at a right angle so that the side surface is L-shaped. I am doing.

加えて、二つの外部端子14a、14bの下端部15dには、後述するように、本発明に係るセラミックコンデンサを電子回路基板のランドにはんだ付けするとき、はんだ付けを促進するために、Sn、Ag、Au、Bi、Znの1種から選ばれる金属単体又は複数種から選ばれる金属合金からなる第二金属めっき層16a、16bが下端面から高さHが0.1〜1.5mm、好ましくは0.2〜1.0mmの高さに及ぶ範囲で被覆されている。前記高さHが1.5mmより多くなると、はんだ濡れ上がりによるフィレット高さが高くなり、誘電体セラミックの電歪効果による振動が電子回路基板に伝播する割合が大きくなり、基板の鳴き抑制効果が低下する。逆に高さHが0.1未満になると、前記はんだ付けにおいて電子回路基板のランドのはんだフィレットがほとんど形成されず、その結果、はんだ接合強度の低下が生ずる。  In addition, at the lower end 15d of the two external terminals 14a and 14b, as will be described later, when soldering the ceramic capacitor according to the present invention to the land of the electronic circuit board, Sn, Second metal plating layers 16a and 16b made of a single metal selected from Ag, Au, Bi and Zn or a metal alloy selected from a plurality of types have a height H of 0.1 to 1.5 mm from the lower end surface, preferably Is coated in a range ranging from 0.2 to 1.0 mm. When the height H is more than 1.5 mm, the fillet height due to solder wetting increases, and the proportion of the vibration due to the electrostrictive effect of the dielectric ceramic propagates to the electronic circuit board increases, and the squeal suppression effect of the board is increased. descend. On the other hand, when the height H is less than 0.1, the solder fillet of the land of the electronic circuit board is hardly formed in the soldering, and as a result, the solder joint strength is lowered.

なお、上記のセラミックコンデンサ10の説明においては、それが一対の外部端子14a、14bに対して1個のセラミックコンデンサ10を取り付けた場合について説明したが、本発明は、図3に示すように、一対の外部端子14a、14bに対して複数個のセラミックコンデンサ10を取り付けた、いわゆるスタック型コンデンサに対しても適用される。  In the description of the ceramic capacitor 10 described above, the case where the single ceramic capacitor 10 is attached to the pair of external terminals 14a and 14b has been described. However, the present invention, as shown in FIG. The present invention is also applied to a so-called stack type capacitor in which a plurality of ceramic capacitors 10 are attached to a pair of external terminals 14a and 14b.

次に、上記構造のセラミックコンデンサの製造方法について説明すると、その方法は次の工程から構成される。  Next, a method for manufacturing the ceramic capacitor having the above structure will be described. The method includes the following steps.

(第一工程)最初に、公知技術に基づいて、図4に示すように、内部に所定間隔をおいて複数層の内部電極が交互に両端部11a,11b寄りに積層配向されているチップ型積層セラミック体11からなり、その前記両端部11a、11bに外部電極12a、12bが付着しているセラミックコンデンサ10をつくる。  (First Step) First, based on a known technique, as shown in FIG. 4, a chip type in which a plurality of layers of internal electrodes are alternately stacked and oriented closer to both end portions 11a and 11b with a predetermined interval inside. A ceramic capacitor 10 made of a multilayer ceramic body 11 and having external electrodes 12a and 12b attached to both end portions 11a and 11b is produced.

(第二工程)次いで、前記セラミックコンデンサ10の外部電極12a、12bの少なくとも端面、好ましくは、外部電極12a、12bの露出面に融点が400℃以上の金属、好ましくはニッケルを使用して第一金属めっき層13a、13bを被覆する。  (Second Step) Next, a metal having a melting point of 400 ° C. or higher, preferably nickel, is used on at least end surfaces of the external electrodes 12a and 12b of the ceramic capacitor 10, preferably on the exposed surfaces of the external electrodes 12a and 12b. The metal plating layers 13a and 13b are covered.

(第三工程)続いて、図5に示すように、前記外部電極12に対して、第一金属めっき層13を介して、帯状金属板からなる脚状外部端子14をスポット溶接により固定する。外部端子14は、上端部15uの中央が切り欠かれて正面形状がほぼU字形状をなし、下端部15dがほぼ直角に曲げ加工されて側面がL字形をなしている。なお、図5においては、外部電極12、第一めっき層13及び外部端子14が一つずつ描かれている態様について説明したが、図4に示したようにそれらが二つ存在する場合についても同様に適用される。(Third Step) Subsequently, as shown in FIG. 5, a leg-shaped external terminal 14 made of a strip-shaped metal plate is fixed to the external electrode 12 via a first metal plating layer 13 by spot welding. The external terminal 14 is cut out at the center of the upper end portion 15u and has a substantially U-shaped front surface, and the lower end portion 15d is bent at a substantially right angle to form an L-shaped side surface. In addition, in FIG. 5, although the aspect in which the external electrode 12, the 1st plating layer 13, and the external terminal 14 were drawn one by one was demonstrated, also when there are two of them as shown in FIG. The same applies.

なお、前記外部端子14a、14bは、次のステップからなる前駆体製造工程等を経て製作される。すなわち、まず、図6に示すように、1枚の帯状金属板20を準備する(第一ステップ)。帯状金属板20として厚みが0.05〜0.5mm、好ましくは0.05〜0.2mmのNi,Fe−Ni,Fe−Ni−Co,Fe−Ni−Cr,Cu,Cu−Sn,Cu−Sn−P,Cu−Ni,Cu−Zn,Cu−Zn−Niから選ばれる金属単体又は合金が使用される。なお、前記金属の種類によっては、スポット溶接性および表面の酸化変色などを考慮し、表面処理として融点が400℃以上の金属、好ましくはNiからなるめっきを、プレス打ち抜き前またはプレス打ち抜き後全面に0.3μm以上施すものとする。  The external terminals 14a and 14b are manufactured through a precursor manufacturing process including the following steps. That is, first, as shown in FIG. 6, one strip-shaped metal plate 20 is prepared (first step). Ni, Fe-Ni, Fe-Ni-Co, Fe-Ni-Cr, Cu, Cu-Sn, Cu having a thickness of 0.05 to 0.5 mm, preferably 0.05 to 0.2 mm, as the band-shaped metal plate 20 A single metal or an alloy selected from —Sn—P, Cu—Ni, Cu—Zn, and Cu—Zn—Ni is used. Depending on the type of the metal, in consideration of spot weldability, surface oxidative discoloration, etc., a metal having a melting point of 400 ° C. or more, preferably Ni, as the surface treatment is applied to the entire surface before press punching or after press punching. 0.3 μm or more shall be applied.

次に、図7に示すように、この帯状金属板20の長手方向に沿う一縁側20aに対して、次のステップで行うメッキ加工に備えて、マスキング21を施す(第二ステップ)。  Next, as shown in FIG. 7, masking 21 is applied to the one edge side 20 a along the longitudinal direction of the band-shaped metal plate 20 in preparation for the plating process performed in the next step (second step).

マスキング21が施された帯状金属板20の他の縁側である20bに下地材を施した後、図8に示すように、ニッケル又はそれに錫、銀若しくは金等の金属のメッキ加工を施して、帯状金属板20に第二金属めっき層16を形成する(第三ステップ)。  After applying the base material to 20b which is the other edge side of the band-shaped metal plate 20 to which the masking 21 has been applied, as shown in FIG. 8, nickel or a metal such as tin, silver or gold is plated, The second metal plating layer 16 is formed on the band-shaped metal plate 20 (third step).

続いて、マスキング21を除去して、図9に示すように、帯状金属板20の第二縁側20bに第二金属めっき層16があるめっき金属板22とする(第四ステップ)。  Subsequently, the masking 21 is removed to form a plated metal plate 22 having the second metal plating layer 16 on the second edge side 20b of the strip-shaped metal plate 20 as shown in FIG. 9 (fourth step).

この金属板22を、第10図に示すように、打ち抜いて、前記外部端子14a、14bの上端部15uと下端部15dとなる部分からなる前駆体23を成形する(第五ステップ)。すると、めっき金属板22はその第二縁側20cに外部端子14a、14bとなる前駆体23を複数個分枝させた平面形状を有するに至り、めっき金属板22をその第一縁側20aを上方にして垂直にした側面を見ると、図11に示すように、前駆体23の下端部が第二金属めっき層16で被覆された形状を呈するに至る。このようにして、少なくとも偶数枚の前駆体23を製作する(以上前駆体製造工程)。  As shown in FIG. 10, the metal plate 22 is punched to form a precursor 23 composed of the upper end portion 15u and the lower end portion 15d of the external terminals 14a, 14b (fifth step). Then, the plated metal plate 22 has a planar shape obtained by branching a plurality of precursors 23 to be the external terminals 14a and 14b on the second edge side 20c, and the plated metal plate 22 has the first edge side 20a facing upward. When the side surface made vertical is viewed, the lower end portion of the precursor 23 has a shape covered with the second metal plating layer 16 as shown in FIG. In this way, at least an even number of precursors 23 are manufactured (precursor manufacturing step).

なお、めっき金属板22の第二金属めっき層16を形成する方法としては、金属板をマスキングせずにめっき液に所定の深さで浸漬することにより形成することも可能である。また、金属板を所定の形状に打ち抜いた後、前述のめっきレジストでマスキングする方法や、マスキングせずにめっき液に所定の深さで浸漬することにより、第二金属めっき層16を形成することもできる。  In addition, as a method of forming the second metal plating layer 16 of the plated metal plate 22, it is also possible to form the metal plate by immersing it in a plating solution at a predetermined depth without masking the metal plate. In addition, after punching the metal plate into a predetermined shape, the second metal plating layer 16 is formed by masking with the above-described plating resist or immersing in a plating solution at a predetermined depth without masking. You can also.

次に、次の第六〜第九ステップからなる前記第三工程と外部端子分離工程とを同時に進行させる。まず、図12に示すめっき金属板22の前駆体23において第二金属めっき層16部分を曲げ加工して、図13に示すように、側面をほぼL字形にする(第六ステップ)。  Next, the third step consisting of the following sixth to ninth steps and the external terminal separation step are simultaneously performed. First, the second metal plating layer 16 portion is bent in the precursor 23 of the plated metal plate 22 shown in FIG. 12 to make the side surface substantially L-shaped as shown in FIG. 13 (sixth step).

このようにして得られためっき金属板22を偶数枚準備し、その金属板22にぶら下がっている前駆体23を、第一、二工程において製作されたセラミックコンデンサ10の外部電極12に対して、図14に示すように、第一金属めっき層13を介して、スポット溶接をする(第七ステップ)。1枚のめっき金属板22に存在する複数個の前駆体23の全部にセラミックコンデンサ10を固定したら、他の1枚のめっき金属板22に対してセラミックコンデンサ10の他端側の外部電極12を固定する。すると、図15に示すように、セラミックコンデンサ10がその両端部11a、11b側において2枚のめっき金属板22で挟持された半製品25ができあがる(第八ステップ)。  An even number of plated metal plates 22 obtained in this way are prepared, and the precursor 23 hanging on the metal plate 22 is applied to the external electrode 12 of the ceramic capacitor 10 manufactured in the first and second steps. As shown in FIG. 14, spot welding is performed via the first metal plating layer 13 (seventh step). When the ceramic capacitor 10 is fixed to all of the plurality of precursors 23 existing on one plated metal plate 22, the external electrode 12 on the other end side of the ceramic capacitor 10 is attached to the other one plated metal plate 22. Fix it. Then, as shown in FIG. 15, a semi-finished product 25 in which the ceramic capacitor 10 is sandwiched between the two plated metal plates 22 on the both end portions 11 a and 11 b side is completed (eighth step).

この半製品25から、図16に示すように、前駆体23をレーザー切断機等により切り離すと、図1及び図2に示すような本発明に係る脚付きセラミックコンデンサ10が出現する(第九ステップ)。  When the precursor 23 is separated from the semi-finished product 25 by a laser cutting machine or the like as shown in FIG. 16, a legged ceramic capacitor 10 according to the present invention as shown in FIGS. 1 and 2 appears (ninth step). ).

従って、このようにして得られたセラミックコンデンサ10において外部端子14a、14bの上端面15tは、外部電極12a、12bの上端面12t、好ましくは外部端子13a、13bの上端面13tよりわずかに上方に突出することは避けられず、その結果、外部電極12a、12bに対する外部負荷の軽減可能にする。  Therefore, in the ceramic capacitor 10 thus obtained, the upper end surfaces 15t of the external terminals 14a and 14b are slightly above the upper end surfaces 12t of the external electrodes 12a and 12b, preferably the upper end surfaces 13t of the external terminals 13a and 13b. The protrusion is inevitable, and as a result, the external load on the external electrodes 12a and 12b can be reduced.

また、前記外部端子13a、13bにはその下端面から所定の高さHまで第二金属めっき層16a、16bが被覆されているので、本発明に係るセラミックコンデンサ10を電子回路基板に実装する場合において外部端子13a、13bをランドにはんだ付けするとき、第二金属めっき層16a、16bは、はんだ濡れ性を高めるのみならず、外部端子の下端からはんだが這い上がる高さを第二金属めっき層の高さHで抑制でき、その結果、誘電体セラミックの電歪効果による振動が外部端子から電子回路基板に伝播するのを最小限に抑制することができ、セラミックコンデンサを電子回路基板に搭載した電子製品の基板鳴きを抑制することができる。  The external terminals 13a and 13b are covered with the second metal plating layers 16a and 16b from the lower end surface to a predetermined height H, so that the ceramic capacitor 10 according to the present invention is mounted on an electronic circuit board. When the external terminals 13a and 13b are soldered to the lands, the second metal plating layers 16a and 16b not only increase the solder wettability but also the height at which the solder rises from the lower end of the external terminals. The vibration due to the electrostrictive effect of the dielectric ceramic can be suppressed to the minimum from the external terminal to the electronic circuit board, and the ceramic capacitor is mounted on the electronic circuit board. The board noise of electronic products can be suppressed.

また、上述したように、前記上端部15uと第一金属めっき層13a、13bとは、スポット溶接により固着する手段が採用されているので、両者の固定化作業を効率化できるのみならず、基板はんだ付け時の加熱による外部端子接続部の離脱を防止することができる。  Further, as described above, since the upper end portion 15u and the first metal plating layers 13a and 13b employ means for fixing by spot welding, not only can the fixing work of both be made efficient, but also the substrate Detachment of the external terminal connection portion due to heating during soldering can be prevented.

産業上の利用分野Industrial application fields

本発明は、セラミックコンデンサを実装した電子回路基板を使用する電子機器分野に広く利用できる。  The present invention can be widely used in the field of electronic equipment using an electronic circuit board on which a ceramic capacitor is mounted.

1:外部端子、1a:上端部、1b:下端部、2:外部電極、3:チップ型積層セラミックコンデンサ、4:チップ型セラミック体、4a:一端部、4b:他端部、5:チップ型積層セラミック体、10:チップ型積層セラミックコンデンサ、11:チップ型セラミック体、11a、11b:端部、12a、12b:外部電極、13a、13b:第一金属めっき層、14a、14b:外部端子、15u:上端部、15d:下端部、16a,16b:第二金属めっき層、20:帯状金属板、20a:第一縁側、20b:第二縁側、21:マスキング、22:めっき金属板、23:前駆体、24:スポット溶接、25:半製品。  1: external terminal, 1a: upper end portion, 1b: lower end portion, 2: external electrode, 3: chip type multilayer ceramic capacitor, 4: chip type ceramic body, 4a: one end portion, 4b: other end portion, 5: chip type Multilayer ceramic body, 10: chip-type multilayer ceramic capacitor, 11: chip-type ceramic body, 11a, 11b: end, 12a, 12b: external electrode, 13a, 13b: first metal plating layer, 14a, 14b: external terminal, 15u: upper end portion, 15d: lower end portion, 16a, 16b: second metal plating layer, 20: strip metal plate, 20a: first edge side, 20b: second edge side, 21: masking, 22: plating metal plate, 23: Precursor, 24: spot welding, 25: semi-finished product.

Claims (6)

相対向する両端部に存在する外部電極(12a,12b)から下方に延ばした脚状の外部端子(14a,14b)を介して、電子回路基板に実装可能にした構造のチップ型積層セラミックコンデンサ(10)において、前記外部端子として、上端部中央が切り欠かれて正面形状がほぼU字状をなし、下端部がほぼ直角に曲げ加工されて側面がL字形をなす帯状金属板を使用するとともに、外部電極の少なくとも端面に融点、400℃以上の第一金属めっき層(13a,13b)を形成して、その金属層に前記外部端子の上端部をスポット溶接することにより、前記外部電極に対して外部端子を固定し、さらに外部端子の下端部(15d)にSn、Ag、Au、Bi、Znの1種から選ばれる金属単体又はそれらの複数種から選ばれる金属合金からなる第二金属めっき層(16a,16b)を形成したことを特徴とするチップ型積層セラミックコンデンサ。Chip-type multilayer ceramic capacitors having a structure that can be mounted on an electronic circuit board via leg-like external terminals (14a, 14b) extending downward from external electrodes (12a, 12b) existing at opposite ends. 10), as the external terminal, a band-shaped metal plate is used in which the center of the upper end is notched and the front shape is substantially U-shaped, the lower end is bent at a substantially right angle, and the side surface is L-shaped. Forming a first metal plating layer (13a, 13b) having a melting point of 400 ° C. or higher on at least an end face of the external electrode, and spot-welding the upper end of the external terminal to the metal layer; In addition, the external terminal is fixed, and the lower end (15d) of the external terminal is a single metal selected from one of Sn, Ag, Au, Bi, and Zn, or a metal alloy selected from a plurality of these. Ranaru second metal plating layer (16a, 16b) chip-type monolithic ceramic capacitor, characterized in that the formation of the. 前記外部端子をなす金属がNi,Fe−Ni,Fe−Ni−Co,Fe−Ni−Cr,Cu,Cu−Sn,Cu−Sn−P,Cu−Ni,Cu−Zn,Cu−Zn−Niから選ばれる請求項1記載のチップ型積層セラミックコンデンサ。The metal forming the external terminal is Ni, Fe-Ni, Fe-Ni-Co, Fe-Ni-Cr, Cu, Cu-Sn, Cu-Sn-P, Cu-Ni, Cu-Zn, Cu-Zn-Ni. The chip type multilayer ceramic capacitor according to claim 1, which is selected from the group consisting of: 前記第二金属めっき層(16a,16b)の高さ(H)が0.2〜1.0mmである請求項3記載のチップ型積層セラミックコンデンサ。The chip-type multilayer ceramic capacitor according to claim 3, wherein a height (H) of the second metal plating layer (16a, 16b) is 0.2 to 1.0 mm. 前記外部端子において前記第二金属めっき層(16a,16b)が形成されていない表面には、融点が400℃以上の金属めっきが厚み0.3μm以上形成されている請求項1記載のチップ型積層セラミックコンデンサ。2. The chip-type laminate according to claim 1, wherein a metal plating having a melting point of 400 ° C. or higher is formed on the surface of the external terminal where the second metal plating layer is not formed. Ceramic capacitor. チップ型セラミック体の内部に所定間隔をおいて複数層の内部電極が交互に両端部寄りに積層配向されているチップ型積層セラミック体(11)に外部電極を形成する第一工程と、前記外部電極の少なくとも端面に融点が400℃以上の第一金属めっき層(13a,13b)を被覆する第二工程と、上端部中央が切り欠かれて正面形状がほぼU字状をなし、下端部がほぼ直角に曲げ加工されて側面がL字形をなす帯状金属板からなる脚状外部端子(14a,14b)を前記第一金属めっき層に対してスポット溶接して固定する第三工程とからなるチップ型積層セラミックコンデンサの製造方法。A first step of forming an external electrode on a chip-type multilayer ceramic body (11) in which a plurality of layers of internal electrodes are alternately laminated and oriented near both ends at a predetermined interval inside the chip-type ceramic body; A second step of covering at least an end face of the electrode with a first metal plating layer (13a, 13b) having a melting point of 400 ° C. or higher, a center of the upper end portion is cut off, and the front shape is substantially U-shaped, and the lower end portion is A chip comprising a third step in which leg-shaped external terminals (14a, 14b) made of a strip-shaped metal plate bent at a substantially right angle and having an L-shaped side surface are fixed to the first metal plating layer by spot welding. Of manufacturing a multilayer ceramic capacitor. 前記外部端子(14a,14b)が次のステップを経て製作された後、チップ型積層セラミック体(11)に固定される請求項6記載のチップ型積層セラミックコンデンサの製造方法;(1)帯状金属板の長手方向に添う一縁側(20b)にめっきレジスト(21)を被覆して第二金属めっき層(16)を形成した金属板(22)を製造するめっき金属板製造ステップと、(2)そのめっき金属板を打ち抜き加工して、めっき金属板の他の縁側に前記外部端子の上端部(15u)と下端部(15d)となる部分を有する外部端子の前駆体(23)を複数個分枝させる前駆体製造ステップと、(3)前記前駆体において外部端子の上端部となる部分を前記チップ型積層セラミック体の第一金属めっき層(13a,13b)にスポット溶接して固定する前駆体固定ステップと、(4)前記チップ型積層セラミック体に固定された前記前駆体を前記めっき金属板から切り落として複数個の脚状外部端子を分離させる外部端子完成ステップ。The method for manufacturing a chip-type multilayer ceramic capacitor according to claim 6, wherein the external terminals (14a, 14b) are manufactured through the following steps and then fixed to the chip-type multilayer ceramic body (11). A plated metal plate manufacturing step for manufacturing a metal plate (22) having a second metal plating layer (16) formed by coating a plating resist (21) on one edge side (20b) along the longitudinal direction of the plate; (2) The plated metal plate is punched to separate a plurality of external terminal precursors (23) having portions that become the upper end portion (15u) and the lower end portion (15d) of the external terminal on the other edge side of the plated metal plate. A precursor manufacturing step for branching; and (3) a portion that becomes the upper end portion of the external terminal in the precursor is spot-welded to the first metal plating layer (13a, 13b) of the chip-type multilayer ceramic body and fixed. A precursor fixing step of, (4) external terminals completed step of separating a plurality of leg-like external terminals by cutting off the precursor which is fixed to the chip-type monolithic ceramic body from said plated metal plate.
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