US20180240798A1 - Semiconductor device with dummy pattern in high-voltage region and method of forming the same - Google Patents
Semiconductor device with dummy pattern in high-voltage region and method of forming the same Download PDFInfo
- Publication number
- US20180240798A1 US20180240798A1 US15/437,824 US201715437824A US2018240798A1 US 20180240798 A1 US20180240798 A1 US 20180240798A1 US 201715437824 A US201715437824 A US 201715437824A US 2018240798 A1 US2018240798 A1 US 2018240798A1
- Authority
- US
- United States
- Prior art keywords
- dummy
- semiconductor
- structures
- region
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 164
- 238000000034 method Methods 0.000 title claims description 38
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 26
- 229920005591 polysilicon Polymers 0.000 claims description 26
- 125000006850 spacer group Chemical group 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- IOVCWXUNBOPUCH-UHFFFAOYSA-M Nitrite anion Chemical compound [O-]N=O IOVCWXUNBOPUCH-UHFFFAOYSA-M 0.000 claims 2
- 239000010410 layer Substances 0.000 description 82
- 238000004519 manufacturing process Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 239000012467 final product Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/47—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a floating-gate layer also being used as part of the peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A semiconductor device includes a substrate having a high-voltage (HV) region; HV gate structures formed in the HV region of the substrate; a HV dummy pattern disposed in the HV region, and the HV dummy pattern comprising at least a semiconductor portion and a dummy HM stack disposed on the semiconductor portion, wherein a height (hS) of the semiconductor portion of the HV dummy pattern is smaller than a height (hHV-g) of a HV gate electrode of one of the HV gate structures.
Description
- The disclosure relates in general to a semiconductor device and a method of forming the same, more particularly to a semiconductor device with dummy pattern in a HV region of a substrate and a method of forming the same.
- Sizes of semiconductor devices have been decreased for these years. Reduction of feature sizes and improvements of density and cost per integrated circuit unit are important goals in the semiconductor technology. The electrical properties of devices have to be maintained even improved with the decrease of sizes to meet the requirements of commercial products in applications. For example, layers and components with damages, which have considerable effects on electrical performances, would be one of many important issues for device manufacturers. Generally, a semiconductor device with good electrical performance requires elements of complete profiles.
- According to typical manufacturing methods, different gate heights of gates in different regions of a substrate would cause damage to the gates. It is known that gate structures of a semiconductor device with flawed profiles and insufficient gate heights will cause considerable deterioration on electrical properties of the devices. It is thus desirable to conquer the gate height issue by developing a manufacturing method compatible with processes of forming different gate-height cells in different regions of a substrate.
- The disclosure relates to a semiconductor device with a dummy pattern in the high-voltage (HV) region and a method of forming the same. During formation of the semiconductor device, a dummy hardmask (HM) pattern is disposed in the HV region, and it is not necessary to form a conventional cap oxide layer in the HV region.
- According to an embodiment, a semiconductor device is provided, comprising a substrate having a high-voltage (HV) region; HV gate structures formed in the HV region of the substrate; and a HV dummy pattern disposed in the HV region, and the HV dummy pattern comprising at least a semiconductor portion and a dummy HM stack disposed on the semiconductor portion, wherein a height of the semiconductor portion of the HV dummy pattern is smaller than a height of a HV gate electrode of one of the HV gate structures.
- According to an embodiment, a method for forming a semiconductor device is provided, comprising: providing a substrate and a first semiconductor layer disposed above the substrate, and the substrate having a high-voltage (HV) region; disposing a patterned hardmask (HM) above the first semiconductor layer; defining a HV dummy pattern in the HV region by using the patterned HM, wherein the HV dummy pattern comprises at least a semiconductor portion and a dummy HM stack disposed on the semiconductor portion; disposing a second semiconductor layer; providing an etching mask in the HV region, and defining the second semiconductor layer by using the etching mask to form HV gate structures on the substrate, wherein a height of the semiconductor portion of the HV dummy pattern is smaller than a height of a HV gate electrode of one of the HV gate structures.
- According to a further embodiment, a semiconductor device is provided, comprising a substrate having a high-voltage (HV) region; HV gate structures formed in the HV region of the substrate; a HV dummy pattern disposed in the HV region. The HV dummy pattern comprises a semiconductor portion disposed above the substrate; a dummy HM stack disposed on the semiconductor portion; first spaces disposed on sidewalls of the dummy HM stack and sidewalls of the semiconductor portion; and second spacers disposed on sidewalls of the first spaces, wherein the first spaces comprise at least a dielectric material, and the second spacers comprise a semiconductor material.
- The disclosure will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
-
FIG. 1 is a simple drawing showing hardmask patterns formed above a substrate according to one embodiment of the present disclosure. -
FIG. 2 simply depicts one of the structural configurations in the HV region and the memory cell region according to one embodiment of the present disclosure. -
FIG. 3 is a top view showing a HV gate structure and a HV dummy pattern in the HV region of a semiconductor device according to the first embodiment of the disclosure. -
FIG. 4A -FIG. 4G illustrate one method for fabricating a semiconductor device according to the first embodiment of the present disclosure. -
FIG. 5 illustrates enlarging portions of theHV dummy pattern 20 and the HV gate structure GHV along a cross-sectional line 5-5 ofFIG. 3 according to the first embodiment of the present disclosure. -
FIG. 6 is a top view showing a HV gate structure and a HV dummy pattern in the HV region of a semiconductor device according to the second embodiment of the disclosure. -
FIG. 7 illustrates enlarging portions of twodummy structures 30 along a cross-sectional line 7-7 ofFIG. 6 . -
FIG. 8 is a top view showing a HV gate structure and a HV dummy pattern (comprising plural dummy structures discretely distributed) in the HV region of a semiconductor device according to the third embodiment of the disclosure. -
FIG. 9 illustrates enlarging portions of two dummy structures outside the HV gate structure and several dummy structures inside the HV gate structure along a cross-sectional line 9-9 ofFIG. 8 . -
FIG. 10 is a top view showing a HV gate structure and a HV dummy pattern in the HV region of a semiconductor device according to the fourth embodiment of the disclosure, wherein the HV dummy pattern comprises plural dummy structures discretely distributed inside the HV gate structure. -
FIG. 11 illustrates enlarging portions of a HV gate structure and a dummy structure outside the HV gate structure according to the fifth embodiment of the disclosure. - According to the embodiments of the present disclosure, a semiconductor device with dummy structures in the HV region of a substrate is provided.
FIG. 1 is a simple drawing showing hardmask patterns formed above a substrate according to one embodiment of the present disclosure. Asubstrate 10 having a logic region AL, a high-voltage (HV) region AHV and a memory cell region AC is illustrated inFIG. 1A . According to the embodiment, a patterned hardmask layer is formed above thesubstrate 10 and the patterned hardmask layer comprises dummy hardmask patterns D-HM (such as SiN hardmask patterns) formed in the HV region AHV and hardmask patterns M-HM for defining positions of floating gates (FG) of flash memory cells in the memory cell region AC. After the patterned hardmask layer is formed, the flash memory cells in the memory cell region AC can be defined and formed by several procedures (such as wordline chemical mechanical polishing (WL CMP) and WL etching back and etc.; and the details of related procedures would be described later) without forming a conventional cap oxide on the polysilicon layer (for forming the HV gate electrode) in the HV region AHV. -
FIG. 2 simply depicts one of the structural configurations in the HV region and the memory cell region according to one embodiment of the present disclosure (details of the related layers inFIG. 2 are described hereinafter). According to the embodiment, a final product of the semiconductor device comprises at least one HV dummy pattern (ex: a multilayer stack comprising a patternedfirst polysilicon layer 120′, a patternedsecond insulating layer 112′ and a dummy HM 240) and at least one HV gate structure GHV disposed in the HV region AHV, wherein the HV dummy pattern comprises asemiconductor portion 120′ and a dummy HM stack (ex: comprising the patternedsecond insulating layer 112′ and the dummy HM 240) disposed above thesemiconductor portion 120′. In one of applicable examples, the HV dummy pattern may comprise a continuous semiconductor layer (as the semiconductor portion) and a dummy HM stack disposed on the semiconductor portion, wherein in a top/layout view the HV dummy pattern is positioned at the outsides of the HV gate structures and surrounds the HV gate structures (i.e. Type 1; described in the first embodiment below). Alternatively, the HV dummy pattern may comprise a plurality of dummy structures discretely distributed in the HV region in a top/layout view, and each of the dummy structures at least comprises a semiconductor small section (ex: in form of bump or stripe or other shapes; such as a polysilicon bump in a height of about 200Λ) and a dummy HM stack disposed on the semiconductor small section (i.e. the semiconductor portion as mentioned above is comprised of several semiconductor small sections of the dummy structures in some embodiments)(i.e. Types 2-4; described in the second-fourth embodiments below). - Each of the HV gate structure comprises a HV gate electrode (such as a metal gate or a polysilicon gate in a height of about 450 Å or more) disposed above the
substrate 10. According to the embodiment, a height hS of the semiconductor portion (a continuous semiconductor layer or the semiconductor small sections) of the HV dummy pattern is smaller than a height hHV-g of a HV gate electrode of a HV gate structure in the HV region AHV. Thus, for different regions of thesubstrate 10, no gate height loss occurs at the HV gates, the flash memory cell gates and logic gates in the structure by applying the embodied designs (including the embodied structures and related fabricating method), and the structure having elements with complete profiles (such as the gates in different regions having sufficient gate heights and complete profiles) possesses good electrical properties. - Several embodiments are provided hereinafter with reference to the accompanying drawings for describing the related procedures and configurations. Related structural details such as layers and spatial arrangement are further described in the embodiments. According to the embodiments, four types of arrangements of HV dummy pattern distributed in the HV region are disclosed herein for illustration. The HV dummy pattern distributed in the HV region could be positioned outside the HV gate structures and spaced apart from the HV gate structures (Types 1 and 2; described in the first and second embodiments); or could be positioned inside (within) the HV gate structure (Type-4; described in the fourth embodiment) and spaced apart from the HV gate structure; or could be disposed in the large area of the HV region including the insides and outsides of the HV gate structures (Type 3; described in the third embodiment). However, the present disclosure is not limited to those illustrated in the drawings. It is noted that not all embodiments of the invention and the applications are shown. There may be other embodiments of the present disclosure which are not specifically illustrated. Modifications and variations can be made without departing from the spirit of the disclosure to meet the requirements of the practical applications. It is also important to point out that the illustrations may not be necessarily be drawn to scale. Thus, the specification and the drawings are to be regard as an illustrative sense rather than a restrictive sense.
- Moreover, use of ordinal terms such as “first”, “second”, etc., in the specification and claims to describe an element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having the same name (but for use of the ordinal term) to distinguish the claim elements.
- In the first embodiment, the dummy hardmask patterns D-HM (ex: SiN hardmask patterns) are disposed in the HV region during definition of the floating gate in the memory cell region, and it is not necessary to form a conventional cap oxide layer in the HV region. The method of the embodiment also leads to a HV dummy pattern remained in the HV region for the final configuration of the semiconductor device.
-
FIG. 3 is a top view showing a HV gate structure and a HV dummy pattern in the HV region of a semiconductor device according to the first embodiment of the disclosure. In the first embodiment, aHV dummy pattern 20 distributed in the HV region AHV could be positioned outside the HV gate structures GHV and spaced apart from the edges EHV-g of the HV gate structures GHV (ex: by at least 0.3 μm or other numerical values suitable for practical application) from the top view of the substrate (Types 1 and 2; first and second embodiments). In one example, aHV dummy pattern 20 of the first embodiment comprises a continuous semiconductor layer (120′ inFIG. 4G , as the semiconductor portion) positioned at the outsides of the HV gate structures GHV and surrounding the HV gate structures GHV (ex: two HV gate structures GHV are exemplified inFIG. 3 for illustration, but the actual numbers of the HV gate structures are not limited in the applications), and a dummy HM stack disposed on the continuous semiconductor layer (please also see the semiconductor portion (ex: 120′) and the dummy HM stack as shown inFIG. 4G ). According to a final product of the embodiment, as exemplified byFIG. 4G later, a height hS of the semiconductor portion (ex: 120′) is smaller than a height hHV-g of a HV gate electrode (ex: the second semiconductor layer 160) of one (/each) of the HV gate structures GHV. -
FIG. 4A -FIG. 4G illustrate one method for fabricating a semiconductor device according to the first embodiment of the present disclosure. As shown inFIG. 4A , asubstrate 10 having a logic region AL, a high-voltage (HV) region AHV and a memory cell region AC is provided, wherein a stack having a first semiconductor layer 120 (ex: polysilicon) disposed between a first insulatinglayer 110 and a second insulating layer 112 (such as the oxide layers) is formed above thesubstrate 10. Also, a combination of hardmask patterns for the different regions (ex: including the hardmask pattern L-HM in the logic region AL, the dummy hardmask patterns D-HM in the HV region AHV and the hardmask pattern M-HM in the memory cell region AC; made of silicon nitride for example) is disposed above for defining related components. Also, several shallow trench isolations (STI) are formed within thesubstrate 10 for formation of integrated circuit isolations as known in the art. InFIG. 4A , dummy hardmask patterns D-HM (ex: SiN hardmask patterns) are disposed in the HV region AHV, and a hardmask pattern M-HM is disposed in the memory cell region AC for defining position of a floating gate (FG) of a flash memory cell later. - Afterwards, definition of a WL height of the flash memory cell in the memory cell region AC is conducted. In one embodiment, during this procedure, the layers in
FIG. 4A (ex: thefirst semiconductor layer 120 and the second insulating layer 112) are patterned by the hardmasks (ex: the dummy hardmask patterns D-HM and the hardmask pattern M-HM) to form multilayer stacks, wherein one of the multilayer stacks in the HV region AHV comprises a patternedfirst polysilicon layer 120′ (as the semiconductor portion), a patterned second insulatinglayer 112′ and adummy HM 240 functions as a HV dummy pattern. Subsequently, the related spacers are formed on sidewalls of the HV dummy pattern, such as forming the first spacers (ex: oxide spacers 25) on the sidewalls of the multilayer stack (comprising 120′/112′/240), as shown inFIG. 4B . Then, another semiconductor layer (ex: polysilicon) is deposited, followed by steps of WL CMP and WL etching back until the height of the WL (ex: made by the second semiconductor layer) of the flash memory cell in the memory cell region AC is formed. After this planarization procedure, the height of WL of the flash memory cell would be determined as the height of thesecond semiconductor layer 160 shown inFIG. 4B . In one embodiment, the semiconductor layer is planarized until atop surface 160 a of the second semiconductor layer 160 (ex: polysilicon layer) is substantially aligned with atop surface 240 a of thedummy HM 240. Also, after steps of WL fabrication of the flash memory cell as shown inFIG. 4B , a HV dummy pattern in the HV region at least comprising ashort semiconductor portion 120′ and adummy HM 240 above the semiconductor portion (ex:120′) is also created. - Afterwards, an insulation stack such as an hardmask-stack 17 (ex: the
oxide layer 171, thenitride layer 172 and the oxide layer 173) is deposited in the logic region AL, the high-voltage (HV) region AHV and the memory cell region AC, as shown inFIG. 4C (blanket disposition). - Then, fabrication of logic cells in the logic region AL is performed. In one example, as shown in
FIG. 4D , all of the layers in the logic region are removed except for the first insulating layer 110 (ex: oxide layer) on thesubstrate 10. Meanwhile, the HV region AHV and the memory cell region AC are protected during fabrication of the logic cells. - Afterwards, the logic cells CL with complete profiles having the polysilicon logic gates GL with sufficient gate height are re-built, as shown in the
FIG. 4E . After fabricating the logic cells CL in the logic region AL, formation of the memory cells and a HV gate pattern are performed. - As shown in the
FIG. 4E , an etching mask such as a patterned photoresist PR layer is provided for proceeding the WL etching to define the memory cell in the memory cell region AC and define the HV gate pattern in the HV region AHV simultaneously. Noted that the logic cells CL in the logic region AL are covered (ex: by an un-patterned photoresist PR layer) during fabrications of the memory cells and the HV gate pattern. In the HV region AHV as shown inFIG. 4E , thesecond semiconductor layer 160 is etched by using the patterned photoresist PR layer to define the width (WHV-g) of the HV gate electrode of the HV gate pattern on thesubstrate 10. Also, in one embodiment, a memory cell comprising a wordline WL and an erase gate EG positioned at two sides of the floating gate FG is illustrated herein for exemplification (not for limitation). - Then, the photoresist PR layer is removed, and a blanket formation of silicides is conducted, followed by forming the nitride spacers 260 (such as SiN) on the structures formed at the logic region AL, the HV region AHV and the memory cell region AC, as shown in
FIG. 4F . - After formation of source and drain (S/D) and the
nitride spacers 260, a replacement metal gate process for replacing the polysilicon gate portions in the logic gates GL of the logic cells CL is conducted, and one of possible procedures is described below. - In one example, a contact etching stop layer CESL (such as a SiN layer; wherein the contact etching stop layer CESL and the
nitride spacers 260 could have the same material) is conformably deposited on the structures formed at the logic region AL, the HV region AHV and the memory cell region AC (as shown inFIG. 4F ), followed by depositing a thick inter-layer dielectric layer (not shown). The thick inter-layer dielectric layer and the CESL are partially removed by CMP until the polysilicon gate portions in the logic gates GL are exposed. Afterwards, the polysilicon gate portions in the logic gates GL are removed for forming the gate trenches (not shown); and then, a work-function metal layer WFM is deposited in each of the gate trenches, and a low-resistance conductive layer (ex: Al) is deposited for filling the gate trenches, followed by CMP to form the metal gates GL′ of the logic cells CL.FIG. 4G shows the metal gates GL′ of the logic cells CL, theHV dummy patterns 20 and the HV gate structures GHV, and the memory cell CM formed in the patterned thick inter-layer dielectric layer ILD′ after CMP. As shown inFIG. 4G , a height hS of thesemiconductor portion 120′ is smaller than a height hHV-g of a HV gate electrode of the HV gate structure GHV in the first embodiment, such as smaller than half of the height hHV-g of the HV gate electrode. In one example, the height hS of thesemiconductor portion 120′ (or the height hSS of the semiconductorsmall section 121 in other embodiments) is (but not limited to) about 200 Å, and the height hHV-g of the HV gate electrode is (but not limited to) about 450 Å. Also, in one example, a height hC-g of a memory cell gate and a height hHV-g of a HV gate electrode could be substantially the same. -
FIG. 5 illustrates enlarging portions of theHV dummy pattern 20 and the HV gate structure GHV along a cross-sectional line 5-5 ofFIG. 3 according to the first embodiment of the disclosure. According to the first embodiment, theHV dummy pattern 20 at least comprises a multilayer stack having a semiconductor portion (such as polysilicon portion; ex: a patternedfirst polysilicon layer 120′ as shown inFIG. 4G andFIG. 5 ) in form of a continuous layer (FIG. 3 ) and a dummy HM stack (ex: the patterned second insulatinglayer 112′ and thedummy HM 240 as shown inFIG. 4G andFIG. 5 ) disposed on the semiconductor portion. In one example, besides the multilayer stack as described above, theHV dummy pattern 20 in the HV region would further comprise theoxide spacers 25 formed on sidewalls of the multilayer stack, apatterned oxide layer 171″ on the dummy HM 240 (after forming the ILD′ as shown inFIG. 4G ), thenitride spacers 260 formed on the sidewalls of theoxide spacers 25, and the contact etching stop layer CESL formed on (sidewalls of) thenitride spacers 260. Thus, for aHV dummy pattern 20 of the first embodiment, the dummy HM stack disposed on the semiconductor portion (ex: the patternedfirst polysilicon layer 120′) may include several insulating layers, such as the patterned second insulatinglayer 112′, the dummy HM 240 (ex: SiN) and the patternedoxide layer 171″. The semiconductor portion (ex: the patternedfirst polysilicon layer 120′) of theHV dummy pattern 20 is enclosed by several insulating layers such as the oxide layers and the nitride layers; therefore, the electrical performances of the application device would not be effected by the existence of theHV dummy patterns 20 in the final product. - Noted that the memory cell region of an embodied semiconductor device may comprise plural flash memory cells, and the logic region may comprise plural logic transistors with 28 nm high-k metal gate (HKMG)), and the related cells and gates in the different regions with certain numbers of the drawings are only for illustration (not for limitation). Also, the sizes of the related elements in the drawings are not necessarily proportional to the actual product of practical applications.
-
FIG. 6 is a top view showing a HV gate structure and a HV dummy pattern in the HV region of a semiconductor device according to the second embodiment of the disclosure. Similar to the first embodiment, a plurality of HV dummy patterns of the second embodiment distributed in the HV region is also positioned outside the HV gate structure GHV (one HV gate structure GHV is exemplified for simple illustration in the second embodiment; however, a HV region in practical application comprises plural HV gate structures), and the HV dummy patterns are spaced apart from the edges EHV-g of the HV gate structure GHV. Different from a continuous semiconductor layer (as the semiconductor portion) of the HV dummy pattern as depicted in the first embodiment, the HV dummy patterns of the second embodiment are severaldummy structures 30 discretely distributed in the HV region AHV, as shown inFIG. 6 . The method for fabricating a semiconductor device according to the second embodiment is similar to that of the first embodiment. Please refer toFIG. 4A -FIG. 4G for the references, and the procedures in details are not redundantly repeated. Also, the cross-sectional views of eachdummy structure 30 and the HV gate structure GHV of the second embodiment could be identical to the configuration shown inFIG. 5 . Thus,FIG. 5 is also illustrating enlarging portions of onedummy structure 30 and one HV gate structure GHV of the second embodiment along across-sectional line 5′-5′ ofFIG. 6 . -
FIG. 7 illustrates enlarging portions of twodummy structures 30 along a cross-sectional line 7-7 ofFIG. 6 . The identical and/or similar elements of the embodiments are designated with the same and/or similar reference numerals. As shown inFIG. 7 , each of thedummy structures 30 of the second embodiment at least comprises a semiconductor small section 121 (ex: in form of a bump or strip or other shape; such as a polysilicon bump in a height of about 200 Å) and a dummy HM stack disposed on the semiconductorsmall section 121. That is, the semiconductor portion (i.e. the patternedfirst polysilicon layer 120′ as shown inFIG. 5 ) in the form of a continuous layer as described in the first embodiment can be replaced by several semiconductorsmall sections 121 of the second embodiment as shown inFIG. 7 . Also, a height hSS of the semiconductorsmall section 121 is smaller than a height hHV-g of a HV gate electrode of the HV gate structure GHV in the second embodiment. Also, the configuration of a HV gate structure GHV according to the second embodiment could be referred toFIG. 5 , and the details are not redundantly repeated. -
FIG. 8 is a top view showing a HV gate structure and a HV dummy pattern (comprising plural dummy structures discretely distributed) in the HV region of a semiconductor device according to the third embodiment of the disclosure. In the third embodiment, a HV dummy pattern comprisesplural dummy structures 30 discretely distributed in the HV region AHV, wherein thosedummy structures 30 are disposed in a large area of the HV region AHV, and include the dummy structures 30-1 disposed outside the HV gate structure(s) GHV and the dummy structures 30-2 disposed inside the HV gate structure(s) GHV, as shown inFIG. 8 . From a top view of the substrate, whether thedummy structures 30 are disposed outside or inside (within) the HV gate structure(s) GHV, all of thedummy structures 30 are spaced apart from the edges EHV-g of the HV gate structure(s) GHV. - One of the applicable methods for fabricating a semiconductor device according to the third embodiment can be obtained by slightly modifying the method of the first embodiment (
FIG. 4A -FIG. 4G ), wherein a dummy hardmask pattern D-HM (ex: a SiN hardmask pattern) as shown inFIG. 4A is designed for further including a pattern for forming the semiconductor small sections 121 (ex: short polysilicon) and the dummy HM stacks respectively disposed on the semiconductorsmall sections 121 inside the HV gate structure(s) GHV. -
FIG. 9 illustrates enlarging portions of two dummy structures 30-1 outside the HV gate structure and several dummy structures 30-2 inside the HV gate structure along a cross-sectional line 9-9 ofFIG. 8 . The identical and/or similar elements of the embodiments (ex:FIG. 9 andFIG. 7 ) are designated with the same and/or similar reference numerals for clear illustration. Please refer to the descriptions related toFIG. 7 in the second embodiment for the configuration details of the dummy structure 30-1 distributed outside the HV gate structure GHV, which are not redundantly repeated. Also, each of the dummy structures 30-2 inside the HV gate structure GHV of the third embodiment may comprise a semiconductor small section 121 (ex: in form of a bump or a strip or other shape), a patterned second insulatinglayer 112′, adummy HM 240 and theoxide spacers 25. Noted that nonitride spacers 260 and no CESL are formed on the dummy structure 30-2 inside the HV gate structure GHV since the steps of forming thenitride spacers 260 and the CESL are performed after the dummy structures 30-2 have been embedded in thesecond semiconductor layer 160 for defining the HV gate electrode (please seeFIG. 4A -FIG. 4B for the reference). - Similar to the configuration provided by the second embodiment, each of the dummy structures 30-1 and 30-2 in the third embodiment is exemplified by a combination at least having a semiconductor small section 121 (such as a polysilicon bump or strip in a height of about 200 Å) disposed above the
substrate 10 and a dummy HM stack disposed on the semiconductorsmall section 121, as shown inFIG. 9 . Also, the heights hSS of the semiconductorsmall section 121 of the dummy structures 30-1 and 30-2 are smaller than a height hHV-g of a HV gate electrode of the HV gate structure GHV according to the third embodiment. - Although there are dummy structures 30-2 formed inside the HV gate structures, the top view of the HV gate structure GHV as depicted in
FIG. 8 (as well asFIG. 10 of the fourth embodiment described later) clearly shows that the second semiconductor layer 160 (FIG. 8 ) for forming the HV gate electrode of the HV gate structure GHV is still a continuous layer, wherein the dummy structures 30-2 are isolated (and insulated) from thesecond semiconductor layer 160 by theoxide spacers 25. Since the dummy structures 30-2 of the embodiment are quite small (ex: less than 1 micrometer in width for actual applications) comparing to the large area of the HV gate structure GHV (ex: several micrometers in width for actual applications), the HV gate structure(s) GHV of the embodiment still provides good electrical characteristics. - Additionally, the distances between two adjacent dummy structures 30-1 inside the HV gate structure(s) GHV can be the same or different. Similarly, the distances between two adjacent dummy structures 30-2 outside the HV gate structure(s) GHV can be the same or different. Also, the arrangements of the dummy structures 30-1 and 30-2 can be identical, or similar or completely different, depending on actual requirements of practical applications. The disclosure has no particularly limitation thereto.
-
FIG. 10 is a top view showing a HV gate structure and a HV dummy pattern in the HV region of a semiconductor device according to the fourth embodiment of the disclosure, wherein the HV dummy pattern comprisesplural dummy structures 40 discretely distributed inside the HV gate structure(s) GHV. Please refer to the dummy structure 30-2 ofFIG. 9 for the configuration of thedummy structure 40 positioned inside (within) the HV gate structure GHV. The details are not redundantly repeated. - Due to the process variations, the configurations of the HV dummy patterns (ex: 20/30/30-1/30-2) of the embodiments can be slightly different such as addition of extra spacers comprising semiconductor material to the HV dummy patterns.
FIG. 11 illustrates enlarging portions of a HV gate structure and a dummy structure outside the HV gate structure according to the fifth embodiment of the disclosure. - Please refer back to
FIG. 4E , which illustrates thesecond semiconductor layer 160 is etched by using the patterned photoresist PR to define the width (WHV-g) of the HV gate electrode of the HV gate pattern on thesubstrate 10. If the process variation occurs in this etching step, such as the patterned photoresist PR being slightly shifted or modified, the material of thesecond semiconductor layer 160 would be remained on theoxide spacers 25 such as the semiconductor spacers 160-D shown inFIG. 11 , wherein theoxide spacers 25 can be regarded as first spacers and the semiconductor spacers 160-D can be regarded as second spacers. Accordingly, the HV dummy pattern of the semiconductor device of the fifth embodiment would comprise the first spaces having at least a dielectric material (ex: oxides), and the second spacers made by a semiconductor material (ex: polysilicon). Configurations of other related layers of the HV dummy pattern of the semiconductor device according to the fifth embodiment have been described above (ex: in the first embodiment), and the details are not redundantly described. - According to the aforementioned description, the dummy hardmask patterns D-HM (ex: SiN hardmask patterns) are disposed in the HV region during definition of the floating gates in the memory cell region, and it is no need to form an extra cap oxide layer in the HV region as taught by conventional method. The method of the embodiment also leads to a HV dummy pattern remained in the HV region for the final configuration of the semiconductor device. However, the semiconductor portion (ex: a continuous semiconductor layer in the first embodiment, or comprising plural semiconductor small sections in the second to fourth embodiments) of the HV dummy pattern is structurally and electrically isolated from the HV gate electrode of the HV gate structure (i.e. the top surface, the bottom surface and the sidewalls of the
semiconductor portion 120′/the semiconductorsmall sections 121 are covered by insulating layers), the HV gate structures GHV of the embodiments still provides good electrical characteristics. - Other embodiments with different configurations of known elements in the device/apparatus can be applicable, and the arrangement depends on the actual needs of the practical applications. It is, of course, noted that the configurations of figures are depicted only for demonstration, not for limitation. It is known by people skilled in the art that the shapes or positional relationship of the constituting elements and the procedure details could be adjusted according to the requirements and/or manufacturing steps of the practical applications.
- While the disclosure has been described by way of example and in terms of the exemplary embodiment(s), it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Claims (27)
1. A semiconductor device, comprising:
a substrate having a high-voltage (HV) region;
HV gate structures formed in the HV region of the substrate;
a HV dummy pattern disposed in the HV region, and the HV dummy pattern comprising at least a semiconductor portion and a dummy HM stack disposed on the semiconductor portion,
wherein a height (hS) of the semiconductor portion of the HV dummy pattern is smaller than a height (hHV-g) of a HV gate electrode of one of the HV gate structures.
2. The semiconductor device according to claim 1 , wherein the semiconductor portion is a continuous semiconductor layer.
3. The semiconductor device according to claim 2 , wherein the HV dummy pattern is positioned outside the HV gate structures and surrounds the HV gate structures.
4. The semiconductor device according to claim 1 , wherein the HV dummy pattern comprises plural dummy structures discretely distributed in the HV region, and each of the dummy structures at least comprises:
a semiconductor small section disposed above the substrate; and
the dummy HM stack disposed on the semiconductor small section.
5. The semiconductor device according to claim 4 , wherein the plural dummy structures are spaced apart from edges of the HV gate structures GHV from a top view of the substrate.
6. The semiconductor device according to claim 4 , wherein the plural dummy structures are discretely distributed outsides the HV gate structures and surround the HV gate structures.
7. The semiconductor device according to claim 4 , wherein the plural dummy structures are discretely distributed insides the HV gate structures.
8. The semiconductor device according to claim 4 , wherein the plural dummy structures distributed in the HV region is a dot pattern or a stripe pattern from a top view of the substrate.
9. The semiconductor device according to claim 1 , wherein one of the HV gate structures comprises:
a HV gate insulating layer disposed above the substrate; and
the HV gate electrode disposed on the HV gate insulating layer,
wherein the semiconductor portion of the HV dummy pattern and the HV gate electrode comprise the same material.
10. The semiconductor device according to claim 1 , wherein a top surface of the semiconductor portion is positioned at a lower horizontal level than a top surface of the HV gate electrode.
11. The semiconductor device according to claim 10 , wherein the substrate has a logic region comprising one logic gate, and a top surface of the logic gate is aligned with the top surface of the HV gate electrode.
12. The semiconductor device according to claim 1 , wherein the dummy HM stack is a multi-layer stack at least comprising a nitrite layer and an oxide layer disposed on the nitrite layer.
13. The semiconductor device according to claim 1 , wherein the height (hS) of the semiconductor portion is smaller than half of the height (hHV-g) of the HV gate electrode.
14. The semiconductor device according to claim 1 , wherein the HV gate electrode of each of the HV gate structures comprises metal or polysilicon.
15. The semiconductor device according to claim 1 , wherein the semiconductor portion comprises polysilicon.
16. The semiconductor device according to claim 1 , wherein the semiconductor portion of the HV dummy pattern is structurally and electrically isolated from adjacent one of the HV gate structures.
17. A method for forming a semiconductor device, comprising:
providing a substrate and a first semiconductor layer disposed above the substrate, and the substrate having a high-voltage (HV) region;
disposing a patterned hardmask (HM) above the first semiconductor layer;
defining a HV dummy pattern in the HV region by using the patterned HM, wherein the HV dummy pattern comprises at least a semiconductor portion above the substrate and a dummy HM stack disposed on the semiconductor portion;
disposing a second semiconductor layer;
providing an etching mask in the HV region, and defining the second semiconductor layer by using the etching mask to form HV gate structures on the substrate,
wherein a height (hS) of the semiconductor portion of the HV dummy pattern is smaller than a height (hHV-g) of a HV gate electrode of one of the HV gate structures.
18. The method according to claim 17 , wherein the HV dummy pattern comprises plural dummy structures discretely distributed in the HV region, and each of the dummy structures at least comprises a semiconductor small section disposed above the substrate and the dummy HM stack disposed on the semiconductor small section,
wherein the method comprises disposing the second semiconductor layer in spaces between the dummy structures.
19. The method according to claim 18 , further comprising forming oxide spacers on sidewalls of the dummy structures after defining the dummy structures.
20. The method according to claim 18 , after forming the HV gate structures using the etching mask, polysilicon spacers are further formed on sidewalls of the oxide spacers of the dummy structures.
21. The method according to claim 18 , wherein disposing the second semiconductor layer comprises:
depositing the second semiconductor layer on the dummy structures and fully filling the spaces between the dummy structures; and
planarizing the second semiconductor layer until a top surface of the second semiconductor layer substantially aligned with a top surface of the dummy HM stack.
22. The method according to claim 18 , before providing the etching mask in the HV region, the method further comprising:
providing an insulation stack on the dummy structures and the second semiconductor layer,
wherein the etching mask is disposed on the insulation stack.
23. The method according to claim 17 , wherein the substrate has a memory cell region with memory cells, wherein a memory cell gate height is substantially the same as a height of a HV gate electrode of each of the HV gate structures after planarization of the second polysilicon layer to form the HV gate structures.
24. The method according to claim 17 , wherein after forming the HV gate structures, the HV dummy pattern distributed in the HV region is spaced apart from edges of the HV gate structures from a top view of the substrate.
25. A semiconductor device, comprising:
a substrate having a high-voltage (HV) region;
HV gate structures formed in the HV region of the substrate;
a HV dummy pattern disposed in the HV region, and the HV dummy pattern comprising:
a semiconductor portion disposed above the substrate;
a dummy HM stack disposed on the semiconductor portion;
first spaces disposed on sidewalls of the dummy HM stack and sidewalls of the semiconductor portion; and
second spacers disposed on sidewalls of the first spaces,
wherein the first spaces comprise at least a dielectric material, and the second spacers comprise a semiconductor material.
26. The semiconductor device according to claim 25 , wherein a height of the semiconductor portion of the HV dummy pattern is smaller than a height of a HV gate electrode of one of the HV gate structures.
27. The semiconductor device according to claim 25 , the first spaces comprise oxide spacers, and the second spacers comprise polysilicon spacers.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/437,824 US10068900B1 (en) | 2017-02-21 | 2017-02-21 | Semiconductor device with dummy pattern in high-voltage region and method of forming the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/437,824 US10068900B1 (en) | 2017-02-21 | 2017-02-21 | Semiconductor device with dummy pattern in high-voltage region and method of forming the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20180240798A1 true US20180240798A1 (en) | 2018-08-23 |
US10068900B1 US10068900B1 (en) | 2018-09-04 |
Family
ID=63168016
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/437,824 Active 2037-04-22 US10068900B1 (en) | 2017-02-21 | 2017-02-21 | Semiconductor device with dummy pattern in high-voltage region and method of forming the same |
Country Status (1)
Country | Link |
---|---|
US (1) | US10068900B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200105764A1 (en) * | 2018-09-27 | 2020-04-02 | United Microelectronics Corp. | Method of forming layout definition of semiconductor device |
US11417735B2 (en) * | 2020-03-27 | 2022-08-16 | United Microelectronics Corp. | Method for fabricating semiconductor device |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6259115B1 (en) | 1999-03-04 | 2001-07-10 | Advanced Micro Devices, Inc. | Dummy patterning for semiconductor manufacturing processes |
US8921173B2 (en) * | 2012-05-30 | 2014-12-30 | Tower Semiconductor Ltd. | Deep silicon via as a drain sinker in integrated vertical DMOS transistor |
-
2017
- 2017-02-21 US US15/437,824 patent/US10068900B1/en active Active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200105764A1 (en) * | 2018-09-27 | 2020-04-02 | United Microelectronics Corp. | Method of forming layout definition of semiconductor device |
US10795255B2 (en) * | 2018-09-27 | 2020-10-06 | United Microelectronics Corp. | Method of forming layout definition of semiconductor device |
US11417735B2 (en) * | 2020-03-27 | 2022-08-16 | United Microelectronics Corp. | Method for fabricating semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US10068900B1 (en) | 2018-09-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9837425B2 (en) | Semiconductor device with split gate flash memory cell structure and method of manufacturing the same | |
US9349812B2 (en) | Semiconductor device with self-aligned contact and method of manufacturing the same | |
US9502286B2 (en) | Methods of forming self-aligned contact structures on semiconductor devices and the resulting devices | |
US11653491B2 (en) | Contacts and method of manufacturing the same | |
US20060017119A1 (en) | Multi-gate transistor and method of fabricating multi-gate transistor | |
US10439048B2 (en) | Photomask layout, methods of forming fine patterns and method of manufacturing semiconductor devices | |
JP2015060874A (en) | Nonvolatile semiconductor storage device | |
KR20090107707A (en) | Method of fabricating vertical transistor in high integrated semiconductor apparatus | |
KR20120126433A (en) | Semiconductor device and manufacturing method of the same | |
US10068900B1 (en) | Semiconductor device with dummy pattern in high-voltage region and method of forming the same | |
KR20120012222A (en) | Method for fabricating the semiconductor device | |
TW201924068A (en) | FDSOI semiconductor device with contact enhancement layer and method of manufacturing | |
KR101044486B1 (en) | Resistor of semiconductor device and manufacturing method of the same | |
US9196494B2 (en) | Semiconductor device and method of manufacturing the same | |
US20100148228A1 (en) | Semiconductor and manufacturing method of the same | |
US20140110773A1 (en) | Semiconductor device including line-type active region and method for manufacturing the same | |
US11665888B2 (en) | Semiconductor device and method for fabricating the same | |
US20150243669A1 (en) | Memory device | |
TWI538107B (en) | Flash memory and method of fabricating the same | |
US10566418B2 (en) | Semiconductor device | |
US20060081909A1 (en) | Semiconductor device and manufacturing method therefor | |
KR20110001136A (en) | Method for manufacturing semiconductor device | |
JP2007141962A (en) | Semiconductor storage device and its manufacturing method | |
TWI627749B (en) | Semiconductor structure and semiconductor pattern structure | |
US9437715B1 (en) | Non-volatile memory and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YANG, CHIN;CHENG, CHAO-SHENG;REEL/FRAME:041316/0873 Effective date: 20170216 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |