US20170315812A1 - Parallel instruction scheduler for block isa processor - Google Patents

Parallel instruction scheduler for block isa processor Download PDF

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Publication number
US20170315812A1
US20170315812A1 US15/224,471 US201615224471A US2017315812A1 US 20170315812 A1 US20170315812 A1 US 20170315812A1 US 201615224471 A US201615224471 A US 201615224471A US 2017315812 A1 US2017315812 A1 US 2017315812A1
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Prior art keywords
instruction
block
scheduler
instructions
ready state
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US15/224,471
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Aaron L. Smith
Jan S. Gray
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Microsoft Technology Licensing LLC
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Microsoft Technology Licensing LLC
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Priority to US15/224,471 priority Critical patent/US20170315812A1/en
Assigned to MICROSOFT TECHNOLOGY LICENSING, LLC reassignment MICROSOFT TECHNOLOGY LICENSING, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SMITH, AARON L., GRAY, JAN S.
Priority to EP17733162.6A priority patent/EP3449360A1/fr
Priority to CN201780026326.3A priority patent/CN109074259A/zh
Priority to PCT/US2017/029225 priority patent/WO2017189464A1/fr
Publication of US20170315812A1 publication Critical patent/US20170315812A1/en
Abandoned legal-status Critical Current

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    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
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    • G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Logic Circuits (AREA)
US15/224,471 2016-04-28 2016-07-29 Parallel instruction scheduler for block isa processor Abandoned US20170315812A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US15/224,471 US20170315812A1 (en) 2016-04-28 2016-07-29 Parallel instruction scheduler for block isa processor
EP17733162.6A EP3449360A1 (fr) 2016-04-28 2017-04-25 Ordonnanceur d'instructions parallèles pour processeur de bloc isa
CN201780026326.3A CN109074259A (zh) 2016-04-28 2017-04-25 用于块isa处理器的并行指令调度器
PCT/US2017/029225 WO2017189464A1 (fr) 2016-04-28 2017-04-25 Ordonnanceur d'instructions parallèles pour processeur de bloc isa

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662328976P 2016-04-28 2016-04-28
US15/224,471 US20170315812A1 (en) 2016-04-28 2016-07-29 Parallel instruction scheduler for block isa processor

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US20170315812A1 true US20170315812A1 (en) 2017-11-02

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US15/224,469 Active US11687345B2 (en) 2016-04-28 2016-07-29 Out-of-order block-based processors and instruction schedulers using ready state data indexed by instruction position identifiers
US15/224,473 Active 2037-01-17 US11106467B2 (en) 2016-04-28 2016-07-29 Incremental scheduler for out-of-order block ISA processors
US15/224,471 Abandoned US20170315812A1 (en) 2016-04-28 2016-07-29 Parallel instruction scheduler for block isa processor
US15/224,624 Active US11449342B2 (en) 2016-04-28 2016-07-31 Hybrid block-based processor and custom function blocks

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US15/224,469 Active US11687345B2 (en) 2016-04-28 2016-07-29 Out-of-order block-based processors and instruction schedulers using ready state data indexed by instruction position identifiers
US15/224,473 Active 2037-01-17 US11106467B2 (en) 2016-04-28 2016-07-29 Incremental scheduler for out-of-order block ISA processors

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US15/224,624 Active US11449342B2 (en) 2016-04-28 2016-07-31 Hybrid block-based processor and custom function blocks

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EP (4) EP3449359B1 (fr)
CN (4) CN109074259A (fr)
WO (4) WO2017189466A1 (fr)

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