US20170202080A1 - Panel with releasable core - Google Patents
Panel with releasable core Download PDFInfo
- Publication number
- US20170202080A1 US20170202080A1 US15/413,156 US201715413156A US2017202080A1 US 20170202080 A1 US20170202080 A1 US 20170202080A1 US 201715413156 A US201715413156 A US 201715413156A US 2017202080 A1 US2017202080 A1 US 2017202080A1
- Authority
- US
- United States
- Prior art keywords
- foil
- conductive foil
- outer conductive
- panel
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000011888 foil Substances 0.000 claims abstract description 293
- 239000000463 material Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 38
- 230000008878 coupling Effects 0.000 claims abstract description 20
- 238000010168 coupling process Methods 0.000 claims abstract description 20
- 238000005859 coupling reaction Methods 0.000 claims abstract description 20
- 239000011347 resin Substances 0.000 claims description 29
- 229920005989 resin Polymers 0.000 claims description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 23
- 229910052802 copper Inorganic materials 0.000 claims description 23
- 239000010949 copper Substances 0.000 claims description 23
- 239000004593 Epoxy Substances 0.000 claims description 12
- 238000003825 pressing Methods 0.000 claims description 6
- 239000004744 fabric Substances 0.000 claims 3
- 239000000758 substrate Substances 0.000 description 110
- 239000012790 adhesive layer Substances 0.000 description 42
- 239000003989 dielectric material Substances 0.000 description 25
- 238000010586 diagram Methods 0.000 description 22
- 238000004519 manufacturing process Methods 0.000 description 17
- 239000010410 layer Substances 0.000 description 13
- 230000001681 protective effect Effects 0.000 description 12
- 229910000679 solder Inorganic materials 0.000 description 9
- 239000000203 mixture Substances 0.000 description 7
- 229920001296 polysiloxane Polymers 0.000 description 7
- 230000002829 reductive effect Effects 0.000 description 7
- 238000005520 cutting process Methods 0.000 description 5
- 229920000642 polymer Polymers 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- ZWEHNKRNPOVVGH-UHFFFAOYSA-N 2-Butanone Chemical compound CCC(C)=O ZWEHNKRNPOVVGH-UHFFFAOYSA-N 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 2
- 238000005422 blasting Methods 0.000 description 2
- 229920001577 copolymer Polymers 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 230000000135 prohibitive effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- -1 Polysiloxane Polymers 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 150000001244 carboxylic acid anhydrides Chemical class 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 235000013870 dimethyl polysiloxane Nutrition 0.000 description 1
- 239000004205 dimethyl polysiloxane Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000011133 lead Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000005191 phase separation Methods 0.000 description 1
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 description 1
- 239000004848 polyfunctional curative Substances 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K1/00—Soldering, e.g. brazing, or unsoldering
- B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K1/00—Soldering, e.g. brazing, or unsoldering
- B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
- B23K1/0016—Brazing of electronic components
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
- B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/20—Layered products comprising a layer of metal comprising aluminium or copper
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B27/00—Layered products comprising a layer of synthetic resin
- B32B27/06—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material
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- B32B27/00—Layered products comprising a layer of synthetic resin
- B32B27/28—Layered products comprising a layer of synthetic resin comprising synthetic resins not wholly covered by any one of the sub-groups B32B27/30 - B32B27/42
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- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B27/00—Layered products comprising a layer of synthetic resin
- B32B27/38—Layered products comprising a layer of synthetic resin comprising epoxy resins
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B3/00—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form
- B32B3/26—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer
- B32B3/30—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer characterised by a layer formed with recesses or projections, e.g. hollows, grooves, protuberances, ribs
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
- B32B7/04—Interconnection of layers
- B32B7/12—Interconnection of layers using interposed adhesives or interposed materials with bonding properties
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/038—Textiles
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/202—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/42—Printed circuits
-
- B23K2201/42—
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2255/00—Coating on the layer surface
- B32B2255/06—Coating on the layer surface on metal layer
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2255/00—Coating on the layer surface
- B32B2255/26—Polymeric coating
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2270/00—Resin or rubber layer containing a blend of at least two different polymers
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2307/00—Properties of the layers or laminate
- B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
- B32B2307/202—Conductive
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2419/00—Buildings or parts thereof
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2457/00—Electrical equipment
- B32B2457/08—PCBs, i.e. printed circuit boards
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2607/00—Walls, panels
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09036—Recesses or grooves in insulating substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24851—Intermediate layer is discontinuous or differential
Definitions
- Examples generally relate to panel architectures and methods, such as panel architectures can facilitate the formation of a substrate thereon.
- Substrate manufacturing technology can include the use of panels to help increase the number of dies that can be manufactured at a given time. Substrate manufacturing can be inefficient, wasteful, or cost prohibitive. Such problems can be prevalent when building substrates using one or more panels.
- FIG. 1 shows a block diagram of an example of a core panel architecture.
- FIG. 2 shows a flow diagram of an example of a technique used to create the core panel architecture of FIG. 1 .
- FIG. 3 shows a flow diagram of an example of another core panel architecture.
- FIG. 4 shows a block diagram of an example of a panel according to one or more embodiments.
- FIG. 5 shows a block diagram of another example of a panel according to one or more embodiments.
- FIG. 6 shows a block diagram of yet another example of a panel according to one or more embodiments.
- FIG. 7 shows a block diagram of the panel of FIG. 6 with a fully embedded substrate built on the panel according to one or more embodiments.
- FIG. 8 shows a block diagram of the panel of FIG. 7 with edges of the panel removed.
- FIG. 9 shows a block diagram of the panel of FIG. 6 with a partially embedded substrate built on the panel according to one or more embodiments.
- FIG. 10 shows a flow diagram of an example of a technique of making a panel according to one or more embodiments.
- FIG. 11 shows a flow diagram of another example of a technique of making a panel according to one or more embodiments.
- FIG. 12 shows a block diagram of an example of a computer system.
- Examples in this disclosure relate generally to substrates or panels, such as panels that can include cureless or cored substrates built thereon, and techniques of making and using the same. Examples also relate to systems that can include one or more of the substrates or panels.
- Previous techniques for creating a releasable core panel include releasably coupling a conductive foil to a base through either vacuum pressing the conductive foil to the base or pressing the conductive into an adhesive layer on the base.
- a premature delamination of a conductive foil can cause yield loss in manufacturing a substrate on the conductive foil.
- Another problem realized in manufacturing can include a warping a conductive foil or damaging an adhesive layer that couples the conductive foil to a base of the panel.
- the adhesion strength between the conductive foil and the base can be reduced (e.g., the peel strength required to remove the conductive can be reduced), thus making it easier for the conductive foil to be delaminated.
- the adhesive layer is damaged, the adhesion strength between the conductive foil and the base can be reduced.
- a technique to reduce the risk of the conductive foil being delaminated or warped can include moving the contact area of the conductive foil inward from the edge of the panel so as to help protect the conductive foil from substrate manufacturing equipment.
- Such a panel is shown in FIG. 1 .
- FIG. 1 shows a block diagram of a panel 100 .
- the panel 100 can include a base 102 , an inner foil 104 A or 104 B, an adhesive layer 106 A or 106 B, or an outer conductive foil 108 A or 108 B.
- the outer conductive foil 108 A-B can include a width 110 A or 1108 that is smaller than a width 112 of the base 102 or the inner foil 104 A-B.
- the smaller width can provide an edge width 114 A or 114 B at which manufacturing equipment can grasp or otherwise contact the inner foil 104 A-B, such as to reduce contact with the outer conductive foil 108 A-B or the adhesive layer 106 A-B during substrate manufacturing.
- edge width 114 A-B can reduce an area on which a substrate can be manufactured (e.g., the active area).
- the edge width 114 A-B can reduce such an area by ten or more millimeters.
- a peel strength of the adhesive layer 106 A-B can be damaged by heat, bumping, or a chemical that comes into contact with the adhesive layer 106 A-B.
- FIG. 2 shows a flow diagram of a technique 200 of making the panel of FIG. 1 .
- the inner foil 104 A-B, outer conductive foil 108 A-B, and adhesive layer 106 A-B can be pressed into the base 102 .
- a masking film e.g., Dry Film Resist (DFR)
- DFR Dry Film Resist
- the panel 100 can be exposed and etched to remove the outer conductive foil at or near the edges of the panel.
- the masking film can be removed from the panel.
- a substrate can be manufactured on the outer conductive foil 108 A-B.
- edges of the panel 100 can be removed.
- DFR Dry Film Resist
- the manufactured substrate can be released from the panel 100 .
- One or more process steps can be eliminated, such as by using a different panel architecture as discussed below. Eliminating a processing step can help reduce a cost associated with manufacturing a panel on which a substrate can be built.
- FIG. 3 shows an example of a core panel 300 .
- the panel 300 can include a base 302 , an inner foil 304 A or 304 B, an outer conductive foil 306 A or 306 B, or a resin 308 A or 308 B coating on an outermost conductive foil 310 A or 310 B.
- the inner foil 304 A-B and the outer conductive foil 306 A-B can include a width 312 A or 312 B that is less than a width 314 A or 314 B of the outermost conductive foil 310 A-B and the base 302 .
- the resin 308 A-B and the outermost conductive foil 310 A can jointly comprise a resin coated conductive layer.
- the resin coated conductive layer i.e. 308 A and 310 A or 308 B and 310 B
- the base 302 can begin as a substantially rectangular structure and be processed to be generally “H” shaped, such as by forming a recess in each side of the base 302 .
- the recesses in FIG. 3 are the areas in which the inner foil 304 A-B and the outer conductive foil 306 A-B are situated.
- a substrate can be built on the outermost conductive foil 310 A-B.
- the resin coated conductive layer can be removed from the base 302 and the outer conductive foil 306 A, such as with the substrate thereon (substrate not shown in FIG. 3 ).
- the resin coated conductive layer can be removed from the substrate such as by etching, wet blasting, or a combination thereof.
- the panel 300 can be cost prohibitive. Arranging the inner foil 304 A-B and the outer conductive foil 306 A-B within a recess in the base 302 (such as shown in FIG. 3 ) can increase the cost of the panel 300 .
- the increase in cost can be due, at least in part, to extra processing that is required to arrange the inner foil 304 A-B and the outer conductive foil 306 A-B in a recess of the base 302 .
- the increase in cost can be due, at least in part, to processing conductive foil panels to be the width 312 A-B, and inserting the modified foil panels into the recess in the base 302 .
- FIG. 4 shows an example of a panel 400 according to one or more embodiments.
- the panel 400 can be configured to protect an interface between an adhesive layer 406 A or 406 B and an inner foil 404 A or 404 B or an outer conductive foil 408 A or 408 B (e.g., the area of the panel 400 covered by a protective material 412 A or 412 B).
- the panel 400 can include a base 402 , the inner foil 404 A-B, the adhesive layer 406 A-B, the outer conductive foil 408 A-B, a die 410 A or 410 B, or the protective material 412 A-B.
- the base 402 can be substantially rectangular.
- the base 402 can include a material that is rigid enough to withstand processing at a substrate manufacturing factory and retain shape.
- the base 402 can include a material impregnated with a polymer.
- the base 402 can include a carbon material impregnated with an epoxy or resin.
- the base 402 can include a metal, plastic, or other substantially rigid material.
- the base 402 can be generally rectangular and generally flat.
- the inner foil 404 A-B can be affixed to the base 402 .
- a periphery of the inner foil 404 A-B can be substantially flush with a periphery of the base 402 , such as shown in FIG. 4 .
- the inner foil 404 A-B can include a conductive material such as copper, gold, silver, aluminum, a combination thereof, or other conductive material.
- the inner foil 404 A-B can include a thickness 416 A or 416 B of between about ten and forty micrometers.
- the inner foil 404 A-B can include a thickness 416 A-B of between about fifteen and about twenty micrometers.
- the inner foil 404 A-B can include a thickness 416 A-B of about eighteen micrometers.
- the adhesive layer 406 A-B can releasably couple the outer conductive foil 408 A-B to the inner foil 404 A-B.
- the adhesive layer 406 A-B can include an epoxy, resin, a combination thereof, or other material.
- the adhesive layer 406 A-B can be pressed (e.g., hot pressed, baked with pressure, or laminated) into the inner foil 404 A-B. Such pressing can form a releasable coupling between the inner foil 404 A-B and the outer conductive foil 408 A-B, such as shown in FIG. 4 .
- the base 402 and the outer conductive foil 408 A-B can be releasably uncoupled, such as by mechanically removing (e.g., pulling) the outer conductive foil 408 A-B away from the inner foil 404 A-B.
- the outer conductive foil 408 A-B can be removed from the inner foil 404 A-B after a substrate (e.g., the die 410 A-B and associated dielectric materials, vias, traces, interconnects, or other electric or electronic circuitry) has been manufactured on the panel 400 .
- the outer conductive foil 408 A-B can be removed from the panel 400 after edges of the panel 400 have been removed. The edges of the panel 400 can be removed by cutting the panel along the dotted lines 414 A and 414 B.
- Removing the edges can expose the interface between the adhesive layer 406 A-B and the inner foil 404 A-B and the outer conductive foil 408 A-B, such as by removing the protective material 412 A-B on the edge (e.g., along the side) of the panel 400 .
- the outer conductive foil 408 A-B can then be released from the panel 400 .
- the adhesive layer 406 A-B can include a methyl ethyl ketone and toluene solvent with polydimethyl siloxane and bisphenol A based epoxy.
- An adhesive layer 406 A-B made from these materials can suffer from phase separation between the epoxy and silicone over time. Heat can cause blisters to form in the adhesive layer 406 A-B made from these materials.
- the adhesive strength of such adhesive layer 406 A-B can degrade over time.
- An adhesive layer made of these materials can have poor line yields, such as in a substrate manufacturing factory.
- releasably coupling means to couple such that a mechanical coupling through the adhesive layer 406 A-B can be broken without requiring excessive force or damaging the items mechanically coupled through the adhesive layer 406 A-B.
- the adhesive layer 406 A-B can be released from an item by exerting a relatively small amount of force, such as about five Newtons per meter to about one hundred Newtons per meter on or near the adhesive layer 406 A-B.
- the adhesive layer 406 A-B can include one or more epoxy silicone copolymers or blends of polymers, silicone, or epoxy. Different blends can be used to make adhesive layer 406 A-B with varying mechanical properties, such as depending on the volume weight percent of polymer, silicone, or epoxy used.
- the mechanical properties can include hardness, elasticity, stickiness, or other mechanical property.
- the adhesive layer 406 A-B can include an epoxy and silicone blend.
- siloxane and epoxy resin can be blended together with a carboxylic acid anhydride hardener, such as to produce a stable or well-blended adhesive layer 406 A-B.
- This blend can be used as an adhesive by controlling the siloxane to epoxy resin ratio. By increasing the proportion of siloxane, an adhesive layer 406 A-B with a reduced elastic modulus can be produced.
- the adhesive layer 406 A-B can include a blend of co-polymer, epoxy, or silicone.
- a co-polymer of siloxane and epoxy can be produced and mixed with an epoxy resin.
- Polysiloxane can have an epoxide group on a side chain thereof and can be synthesized from methylhydrosiloxane, epoxy resin.
- the outer conductive foil 408 A-B can be coupled to the inner foil 404 A-B using the adhesive layer 406 A-B.
- a periphery of the outer conductive foil 408 A-B can be substantially flush with a periphery of the base 402 or a periphery of the inner foil 404 A-B, such as shown in FIG. 4 .
- the outer conductive foil 408 A-B can include a conductive material such as copper, gold, silver, aluminum, a combination thereof, or other conductive material.
- the outer conductive foil 408 A-B can include a thickness 418 A-B that is smaller than a thickness 416 A-B of the inner foil 404 A-B.
- a yield loss realized in manufacturing a substrate onto the outer conductive foil 408 A-B can be reduced by including an outer conductive foil 408 A-B with a thickness 418 A-B that is smaller than the thickness 416 A-B of the inner foil 404 A-B.
- the thickness 418 A-B of the outer conductive foil 408 A-B can be between about one and thirty micrometers. In one or more embodiments, the thickness 418 A-B of the outer conductive foil 408 A-B can be between about two and fifteen micrometers. In one or more embodiments, the thickness 418 A-B of the outer conductive foil 408 A-B can be between about two and six micrometers.
- the thickness 418 A-B of the outer conductive foil 408 A-B can be between about three and five micrometers. In one or more embodiments, the thickness 418 A-B of the outer conductive foil 408 A-B can be about three, five, or eighteen micrometers.
- the yield loss realized in manufacturing a substrate on the outer conductive foil 408 A-B can be decreased.
- the thickness 418 A-B of the outer conductive foil is too large, delamination of the outer conductive foil 408 A-B can increase yield loss.
- the outer conductive foil 408 A-B may not be reliably releasable from the inner foil 404 A-B.
- the outer conductive foil 408 A-B can break in the separation process, or some residue from the outer conductive foil 408 A-B or the adhesive layer 406 A-B can be left on the inner foil 404 A-B in the process of separating the outer conductive foil 408 A-B from the inner foil 404 A-B.
- a periphery of the inner foil 404 A-B can be substantially flush with a periphery of the base 402 , such as shown in FIG. 4 .
- a periphery of the outer conductive foil 408 A-B can be substantially flush with a periphery of the base 402 or a periphery of the inner foil 404 A-B, such as shown in FIG. 4 .
- the protective material 412 A-B can be situated on the outer conductive foil 408 A-B or on the side of the panel 400 , such as to protect an interface between the adhesive layer 406 A-B and the outer conductive foil 408 A-B or the inner foil 404 A-B.
- the protective material 412 A-B can help protect the interface from chemicals, heat, bumping, or other external forces that can delaminate or damage the material behind the protective material 412 A-B.
- the protective material 412 A-D can include a metal, polymer, or other material that can adhere to the panel 400 , such as at the inner foil 404 A-B, the outer conductive foil 408 A-B, the adhesive layer 406 A-B, or the base 402 .
- the protective material 412 A-B can include a metal, such as copper, gold, silver, or other metal, or a polymer or plastic.
- the protective material 412 A-B can be electrolytically plated, applied in the form of a sheet, or otherwise flowed or dispensed on or mechanically coupled to the panel 400 .
- Adding the protective material 412 A-B can reduce the yield loss or other concerns realized in using an outer conductive foil 408 A-B with a thickness 418 A-B that is less than five micrometers.
- FIG. 5 shows a block diagram of an example of a panel 500 according to one or more embodiments.
- the panel 500 can include the base 402 , the inner foil 404 A-B, the outer conductive foil 408 A-B, the die 410 A-B, or a connective material 518 A, 518 B, 518 C, or 518 D situated between the outer conductive foil 408 A-B and the inner foil 404 A-B.
- the panel 500 can include an adhesive layer 406 A-B situated between the inner foil 404 A-B and the outer conductive foil 408 A-B (not shown in FIG. 5 ).
- the connective material 518 A-D can include solder paste, such as can include tin, silver, copper, lead, indium, a combination thereof, or other solder paste, or a solder thermal interface material, such as can include indium.
- the connective material 518 A-D can be placed on the inner foil 404 A-B, the outer conductive foil 408 A-B can be placed on the inner foil 404 A-B and the connective material 518 A-B, and the combination can be heat pressed to melt the connective material 518 A-D and form a mechanical connection between the inner foil 404 A-B and the outer conductive foil 408 A-B, such as to affix the inner foil 404 A-B to the outer conductive foil 408 A-B, such as at or near edges of the inner foil 404 A-B or the outer conductive foil 408 A-B.
- the connective material 518 A-D can be situated along an edge of the panel 500 , such as to protect the interface between the adhesive layer 406 A-B and the inner foil 404 A-B or the outer conductive foil 408 A-B.
- the die 410 A-B can be removed from the panel 500 , such as by removing portions of the panel 500 that include the connective material 518 A-D, such as by cutting the panel at the dotted lines 520 A-B, and releasing the outer conductive foil 408 A-B from the panel 500 .
- the outer conductive foil 408 A-B can be removed from the die 410 A-B or a substrate which the die 410 A-B is a part of, such as by etching away the outer conductive foil 408 A-B.
- FIG. 6 shows a block diagram of an example of a panel 600 according to one or more embodiments.
- the panel 600 can include the base 402 , the inner foil 404 A-B, an optional adhesive layer 406 A-B, or the outer conductive foil 408 A-B.
- the panel 600 can include one or more welds 616 affixing the inner foil 404 A-B to the outer conductive foil 408 A-B.
- the outer conductive foil 408 A-B, the inner foil 404 A-B or the base 402 can include a width 614 A-B, such as to make the outer conductive foil 408 A-B, inner foil 404 A-B, or the base 402 have substantially the same width 614 A-B.
- a width 618 of the welds 616 can be about one millimeter or less.
- FIG. 7 shows a block diagram of a panel 700 that includes the panel 600 with the die 410 A-B situated on the outer conductive foil 408 A-B and a dielectric material 712 A or 712 B over or around (e.g., encasing) the die 410 A-B.
- a dielectric material 712 A or 712 B over or around (e.g., encasing) the die 410 A-B.
- Such embodiments can be considered “fully embedded” substrate architectures, because the die 410 A-B can be fully embedded in the dielectric (e.g., buildup) layer(s).
- FIG. 8 shows a block diagram of a panel 800 that includes the panel 700 after the welds 616 have been removed from the panel 700 , such as by cutting the panel 700 at the dotted lines 714 A-B.
- the die 410 A-B and the dielectric material 712 A-B can be removed from the panel 800 , such as by releasing the outer conductive foil 408 A-B from the inner foil 404 A-B.
- the outer conductive foil 408 A-B can be removed from the dielectric material 712 A-B (e.g., an etch stop or build up material such as Ajinomoto Buildup Film (ABF)) or the die 410 A-B, such as by copper etching the outer conductive foil 408 A-B.
- ABS Ajinomoto Buildup Film
- FIG. 9 shows a block diagram of an example of a panel 900 that includes a partially embedded substrate (e.g., a conductive foil 914 A or 914 B, the die 410 A-B and the dielectric material 916 A-B).
- the panel 900 can include the base 402 , the inner foil 404 A-B, the adhesive layer 406 A-B, the outer conductive foil 408 A-B, a dielectric material 912 A or 912 B, the conductive foil 914 A-B, the die 410 A-B, or the dielectric material 916 A-B.
- the dielectric material 912 A-B and the conductive foil 914 A-B can be jointly considered a resin coated conductive foil.
- the conductive foil 914 A-B can be similar to the inner foil 404 A-B or the outer conductive foil 408 A-B.
- a recess can be formed in the conductive foil 914 A-B.
- the die 410 A-B can be situated in the recess.
- the dielectric material 916 A-B can be flowed, dispensed, or applied over the conductive foil 914 A-B and the die 410 A-B, such as to at least partially encase the die 410 A-B in the dielectric material 916 A-B.
- the dielectric material 916 A-B can be similar to the dielectric material 712 A-B.
- the substrate can be considered a partially embedded substrate because the dielectric film only covers a portion of the die, the conductive foil that the die is inserted into can help cover the remainder of the die.
- the substrate can be removed from the panel 900 by removing the edges of the panel 900 , such as to remove the weld 616 , such as by cutting the panel at the dotted lines 918 A-B.
- the outer conductive foil 408 A-B can then be released from the panel 900 , such as at an interface between the outer conductive foil 408 A-B and the adhesive layer 406 A-B or the inner foil 404 A-B.
- the outer conductive foil 408 A-B can then be removed from the partially embedded substrate, such as by etching the outer conductive foil 408 A-B from the substrate.
- the dielectric material 912 A-B can then be removed from the partially embedded substrate, such as by sand blasting, wet blasting, or cutting the dielectric material 912 A-B from the substrate.
- a fully embedded substrate or a partially embedded substrate can be built on any of the panels 400 , 500 , or 600 .
- a fully embedded substrate can include a die situated directly on the outer conductive foil and embedded in dielectric material, such as shown in FIG. 7 .
- the partially embedded substrate can include a die situated in a recess of a conductive foil that is situated on a dielectric material that is situated on the outer conductive foil. Dielectric material can be flowed over the die and the conductive foil of the partially embedded substrate.
- the partially embedded substrate or the fully embedded substrate can be BBUL substrates or cored substrates.
- a substrate may be manufactured on the panel without a die situated therein.
- Such substrates can be a cored die substrate.
- a coreless die substrate can include a substrate that is built up and a die is attached to the die substrate after the die substrate is built.
- a cored die substrate can include a substrate that includes a die arranged in the substrate and at least a portion of the substrate is built around the die.
- a BBUL die substrate can include a substrate that includes a die with one or more buildup layers built above the die to form the die substrate.
- the substrate can include a Bumpless Buildup Layer (BBUL) substrate, a Flip Chip substrate, a Surface Mount (SMT) substrate, or other type of substrate.
- BBUL Bumpless Buildup Layer
- SMT Surface Mount
- panels discussed herein are double-sided (i.e. the panels include an inner foil, adhesive layer, and outer conductive foil all situated on opposite sides of the base), the panel can be one-sided.
- One sided panels are less efficient in terms of throughput, but can include simpler processing at a manufacturing facility.
- Processing to make the panel 400 , 500 , 600 , 700 , 800 , or 900 can be simpler or cheaper than the processing to make the panel 300 or the panel 100 .
- the processing can be simpler in that the inner foil and the outer conductive foil need not be processed to fit in a recess of the base.
- the base 402 does not need to be processed to include a recess in which the inner foil or the outer conductive foil can be situated in.
- the cost of manufacturing the panel 400 , 500 , 600 , 700 , 800 , or 900 can be reduced as compared to the cost of manufacturing the panel 100 or 300 .
- Manufacturing the panel 400 , 500 , 600 , 700 , 800 , or 900 can be simpler than processing to make the panel 300 because the panel 400 , 500 , 600 , 700 , 800 , or 900 does not require the precise alignment considerations as in the manufacturing of the panel 100 or 300 .
- the active area the area on which a substrate can be built) of the panel 400 , 500 , 600 , 700 , 800 , or 900 can be larger than the active area of the panel 100 .
- FIG. 10 shows a flow diagram of an example of a technique 1000 for making a panel according to one or more embodiments.
- a panel can be pressed. Pressing the panel can include arranging a panel of inner foil on a base, optionally arranging an adhesive layer on the inner foil, optionally arranging connective material on the inner foil, arranging an outer conductive foil on the inner foil, and mechanically pressing the arranges materials, such as under heat, pressure, or in a vacuum.
- the inner and outer conductive foils can be mechanically coupled to each other.
- Mechanically coupling the inner and outer conductive foils can include melting a connective material situated between the inner and outer conductive foils, welding (e.g., laser welding) the outer conductive foil to the inner foil, or situating protective material on the edge of the inner and outer conductive foil (e.g., to protect an adhesive layer coupling the inner and outer conductive foils).
- edges of the panel can be trimmed (e.g., cut or otherwise removed), such as to remove the mechanical coupling between the inner and outer conductive foils (e.g., to remove the weld, at least a portion of the protective material, or the connective material).
- the outer conductive foil can be released from the panel.
- Building a panel using the technique 1000 can be more cost effective than building a panel using the technique 200 . This can be due to reduced number of steps in the technique 1000 as compared to the technique 200 .
- the technique 1000 there is no masking film lamination, panel expose or etch, or masking film removal process. Removing a process of the technique can reduce the cost of making a panel using the technique and increase through put by decreasing the amount of time it takes to make a panel using the technique.
- FIG. 11 shows a flow diagram of an example of a technique 1100 according to one or more embodiments.
- an inner foil can be coupled (e.g., mechanically coupled or affixed) to a substantially rectangular base.
- an outer conductive foil can be situated on or over the inner foil.
- the inner foil and the outer conductive foil can be coupled together (affixed to each other) near edges of the outer conductive foil and the inner foil, such as by using a connective material. Coupling the inner foil and the outer conductive foil can include welding the inner foil to the outer conductive foil.
- the connective material can include a solder paste and coupling the inner foil and the outer conductive foil can include reflowing the solder paste between the inner foil and the outer conductive foil.
- the technique 1100 can include situating a fully embedded substrate on the outer conductive foil.
- Situating the fully embedded substrate on the outer conductive foil can include situating a die on the outer conductive foil and situating a dielectric material over and around the die.
- Situating the fully embedded substrate on the outer conductive foil can include forming a coreless substrate, cored substrate, or a BBUL substrate on the outer conductive foil.
- the technique 1100 can include situating a partially embedded substrate on the outer conductive foil.
- Situating the partially embedded substrate on the outer conductive foil can include: (1) situating a resin coated copper on the outer conductive foil, (2) forming a recess in the resin coated copper, (3) situating a die situated in the recess, or (4) situating a dielectric material over the die and the resin coated copper.
- situating the partially embedded substrate on the outer conductive foil can include forming a coreless substrate, cored substrate, or a BBUL substrate on the outer conductive foil.
- FIG. 12 is a block diagram illustrating an example computer system 1200 machine which can include a substrate that was built on a panel as discussed herein.
- Computer system 1200 can be a computing device.
- the machine can operate as a standalone device or can be connected (e.g., via a cellular network) to other machines.
- the machine can operate in the capacity of either a server or a client machine in server-client network environments, or it can act as a peer machine in peer-to-peer (or distributed) network environments.
- the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.
- Example computer system 1200 can include a processor 1202 (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU) or both), a main memory 1204 and a static memory 1206 , which communicate with each other via an interconnect 1208 (e.g., a link, a bus, etc.).
- the computer system 1200 can further include a video display unit 1210 , an alphanumeric input device 1212 (e.g., a keyboard), and a User Interface (UI) navigation device 1214 (e.g., a mouse).
- the video display unit 1210 , input device 1212 and UI navigation device 1214 are a touch screen display.
- the computer system 1200 can additionally include a storage device 1216 (e.g., a drive unit), a signal generation device 1218 (e.g., a speaker), an output controller 1232 , a power management controller 1234 , and a network interface device 1220 (which can include or operably communicate with one or more antennas 1230 , transceivers, or other wireless communications hardware), and one or more sensors 1228 , such as a GPS sensor, compass, location sensor, accelerometer, or other sensor.
- the antennas 1230 can be coupled to a network 1226 . Any of the items of the system 1200 can include a substrate built on a panel discussed herein.
- Example 1 can include or use subject matter (such as an apparatus, a method, a means for performing acts, or a device readable memory including instructions that, when performed by the device, can cause the device to perform acts), such as can include or use a substantially rectangular base, an inner foil mechanically coupled to the base, an outer conductive foil situated over the inner foil, and connective material coupling the inner foil and the outer conductive foil near edges of the outer conductive foil and the inner foil.
- subject matter such as an apparatus, a method, a means for performing acts, or a device readable memory including instructions that, when performed by the device, can cause the device to perform acts
- Example 2 can include or use, or can optionally be combined with the subject matter of Example 1, to include or use, wherein the connective material includes a weld.
- Example 3 can include or use, or can optionally be combined with the subject matter of Example 1, to include or use, wherein the connective material includes a solder paste.
- Example 4 can include or use, or can optionally be combined with the subject matter of at least one of Examples 1-3, to include or use a fully embedded substrate situated on the outer conductive foil.
- Example 5 can include or use, or can optionally be combined with the subject matter of Example 4, to include or use, wherein the fully embedded substrate includes a die situated on the outer conductive foil and a dielectric material situated over and around the die.
- Example 6 can include or use, or can optionally be combined with the subject matter of at least one of Examples 4-5, to include or use, wherein the fully embedded substrate is a cored substrate or a Bumpless Buildup Layer (BBUL) substrate.
- BBUL Bumpless Buildup Layer
- Example 7 can include or use, or can optionally be combined with the subject matter of at least one of Examples 1-3, to include or use a partially embedded substrate situated on the outer conductive foil.
- Example 8 can include or use, or can optionally be combined with the subject matter of Example 7 to include or use, wherein the partially embedded substrate includes (1) a resin coated copper situated on the outer conductive foil, (2) a recess formed in the resin coated copper, (3) a die situated in the recess, or (4) a dielectric material situated over the die and the resin coated copper.
- the partially embedded substrate includes (1) a resin coated copper situated on the outer conductive foil, (2) a recess formed in the resin coated copper, (3) a die situated in the recess, or (4) a dielectric material situated over the die and the resin coated copper.
- Example 9 can include or use, or can optionally be combined with the subject matter of at least one of Examples 7-8 to include or use, wherein the partially embedded substrate is a cored substrate or a Bumpless Buildup Layer (BBUL) substrate.
- BBUL Bumpless Buildup Layer
- Example 10 can include or use subject matter (such as an apparatus, a method, a means for performing acts, or a device readable memory including instructions that, when performed by the device, can cause the device to perform acts), such as can include or use coupling an inner foil to a substantially rectangular base, situating an outer conductive foil situated on the inner foil, or coupling, using a connective material, the inner foil and the outer conductive foil near edges of the outer conductive foil and the inner foil.
- subject matter such as an apparatus, a method, a means for performing acts, or a device readable memory including instructions that, when performed by the device, can cause the device to perform acts
- Example 11 can include or use, or can optionally be combined with the subject matter of Example 10 to include or use, wherein coupling the inner foil and the outer conductive foil includes welding the inner foil to the outer conductive foil.
- Example 12 can include or use, or can optionally be combined with the subject matter of Example 10 to include or use, wherein the connective material includes a solder paste and coupling the inner foil and the outer conductive foil includes reflowing the solder paste between the inner foil and the outer conductive foil.
- the connective material includes a solder paste and coupling the inner foil and the outer conductive foil includes reflowing the solder paste between the inner foil and the outer conductive foil.
- Example 13 can include or use, or can optionally be combined with the subject matter of at least one of Examples 10-12 to include or use, situating a fully embedded substrate on the outer conductive foil.
- Example 14 can include or use, or can optionally be combined with the subject matter of Example 13 to include or use, wherein situating the fully embedded substrate on the outer conductive foil includes situating a die on the outer conductive foil and situating a dielectric material over and around the die.
- Example 15 can include or use, or can optionally be combined with the subject matter of at least one of Examples 13-14 to include or use, wherein situating the fully embedded substrate on the outer conductive foil includes forming a cored substrate, or a Bumpless Buildup Layer (BBUL) substrate on the outer conductive foil.
- BBUL Bumpless Buildup Layer
- Example 16 can include or use, or can optionally be combined with the subject matter of at least one of Examples 10-12 to include or use, situating a partially embedded substrate on the outer conductive foil.
- Example 17 can include or use, or can optionally be combined with the subject matter of Example 16 to include or use, wherein situating the partially embedded substrate on the outer conductive foil includes (1) situating a resin coated copper on the outer conductive foil, (2) forming a recess in the resin coated copper, (3) situating a die situated in the recess, or (4) situating a dielectric material over the die and the resin coated copper.
- Example 18 can include or use, or can optionally be combined with the subject matter of at least one of Examples 16-17 to include or use, wherein situating the partially embedded substrate on the outer conductive foil includes forming a cored substrate or a Bumpless Buildup Layer (BBUL) substrate on the outer conductive foil.
- BBUL Bumpless Buildup Layer
- Example 19 can include or use subject matter (such as an apparatus, a method, a means for performing acts, or a device readable memory including instructions that, when performed by the device, can cause the device to perform acts), such as can include or use (1) a substantially rectangular base, (2) a first inner foil mechanically coupled to a first side of the base, (3) a second inner foil mechanically coupled to a second side of the base, the second side of the base opposite the first side of the base, (4) a first outer conductive foil situated on the first inner foil, (5) a second outer conductive foil situated on the second inner foil, or (6) connective material coupling the first inner foil and the first outer conductive foil near edges of the first outer conductive foil and the first inner foil and coupling the second inner foil and the second outer conductive foil near edges of the second outer conductive foil and the second inner foil.
- subject matter such as an apparatus, a method, a means for performing acts, or a device readable memory including instructions that, when performed by the device, can cause the device to perform acts
- Example 20 can include or use, or can optionally be combined with the subject matter of Example 19 to include or use, wherein the connective material includes a weld.
- Example 21 can include or use, or can optionally be combined with the subject matter of Example 19 to include or use, wherein the connective material includes a solder paste.
- Example 22 can include or use, or can optionally be combined with the subject matter of at least one of Examples 19-21 to include or use a first fully embedded substrate situated on the first outer conductive foil and a second fully embedded substrate situated on the second outer conductive foil.
- Example 23 can include or use, or can optionally be combined with the subject matter of Example 22 to include or use, wherein the first fully embedded substrate includes a first die situated on the first outer conductive foil and a first dielectric material situated over and around the first die.
- Example 24 can include or use, or can optionally be combined with the subject matter of at least one of Examples 22-23 to include or use, wherein the first fully embedded substrate is a cored substrate or a Bumpless Buildup Layer (BBUL) substrate.
- BBUL Bumpless Buildup Layer
- Example 25 can include or use, or can optionally be combined with the subject matter of at least one of Examples 19-21 to include or use a first partially embedded substrate situated on the first outer conductive foil and a second partially embedded substrate situated on the second outer conductive foil.
- Example 26 can include or use, or can optionally be combined with the subject matter of Example 25 to include or use, wherein the first partially embedded substrate includes (1) a resin coated copper situated on the first outer conductive foil, (2) a recess formed in the resin coated copper, (3) a die situated in the recess, or (4) a dielectric material situated over the die and the resin coated copper.
- the first partially embedded substrate includes (1) a resin coated copper situated on the first outer conductive foil, (2) a recess formed in the resin coated copper, (3) a die situated in the recess, or (4) a dielectric material situated over the die and the resin coated copper.
- Example 27 can include or use, or can optionally be combined with the subject matter of at least one of Examples 25-26 to include or use, wherein the first partially embedded substrate is a cored substrate or a Bumpless Buildup Layer (BBUL) substrate.
- BBUL Bumpless Buildup Layer
- the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.”
- the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated.
- a “-” (dash) used when referring to a reference number means “or”, in the non-exclusive sense discussed in the previous paragraph, of all elements within the range indicated by the dash.
- 103 A-B means a nonexclusive “or” of the elements in the range ⁇ 103 A, 103 B ⁇ , such that 103 A- 103 B includes “ 103 A but not 103 B”, “ 103 B but not 103 A”, and “ 103 A and 103 B”.
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Abstract
Generally discussed herein are systems and apparatuses that can include a releasable core panel. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a releasable core panel can include coupling an inner foil to a substantially rectangular base, situating an outer conductive foil situated on the inner foil, or coupling, using a connective material, the inner foil and the outer conductive foil near edges of the outer conductive foil and the inner foil.
Description
- This application is a continuation of U.S. patent application Ser. No. 14/227,723, filed Mar. 27, 2014, which is a continuation-in-part to U.S. patent application Ser. No. 14/135,168, filed Dec. 19, 2013, each of which are incorporated herein by reference in their entirety.
- Examples generally relate to panel architectures and methods, such as panel architectures can facilitate the formation of a substrate thereon.
- Substrate manufacturing technology can include the use of panels to help increase the number of dies that can be manufactured at a given time. Substrate manufacturing can be inefficient, wasteful, or cost prohibitive. Such problems can be prevalent when building substrates using one or more panels.
- In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.
-
FIG. 1 shows a block diagram of an example of a core panel architecture. -
FIG. 2 shows a flow diagram of an example of a technique used to create the core panel architecture ofFIG. 1 . -
FIG. 3 shows a flow diagram of an example of another core panel architecture. -
FIG. 4 shows a block diagram of an example of a panel according to one or more embodiments. -
FIG. 5 shows a block diagram of another example of a panel according to one or more embodiments. -
FIG. 6 shows a block diagram of yet another example of a panel according to one or more embodiments. -
FIG. 7 shows a block diagram of the panel ofFIG. 6 with a fully embedded substrate built on the panel according to one or more embodiments. -
FIG. 8 shows a block diagram of the panel ofFIG. 7 with edges of the panel removed. -
FIG. 9 shows a block diagram of the panel ofFIG. 6 with a partially embedded substrate built on the panel according to one or more embodiments. -
FIG. 10 shows a flow diagram of an example of a technique of making a panel according to one or more embodiments. -
FIG. 11 shows a flow diagram of another example of a technique of making a panel according to one or more embodiments. -
FIG. 12 shows a block diagram of an example of a computer system. - Examples in this disclosure relate generally to substrates or panels, such as panels that can include cureless or cored substrates built thereon, and techniques of making and using the same. Examples also relate to systems that can include one or more of the substrates or panels.
- Previous techniques for creating a releasable core panel include releasably coupling a conductive foil to a base through either vacuum pressing the conductive foil to the base or pressing the conductive into an adhesive layer on the base.
- A premature delamination of a conductive foil can cause yield loss in manufacturing a substrate on the conductive foil. Another problem realized in manufacturing can include a warping a conductive foil or damaging an adhesive layer that couples the conductive foil to a base of the panel. When the conductive foil warps, the adhesion strength between the conductive foil and the base can be reduced (e.g., the peel strength required to remove the conductive can be reduced), thus making it easier for the conductive foil to be delaminated. Likewise, when the adhesive layer is damaged, the adhesion strength between the conductive foil and the base can be reduced.
- A technique to reduce the risk of the conductive foil being delaminated or warped can include moving the contact area of the conductive foil inward from the edge of the panel so as to help protect the conductive foil from substrate manufacturing equipment. Such a panel is shown in
FIG. 1 . -
FIG. 1 shows a block diagram of apanel 100. Thepanel 100 can include abase 102, aninner foil adhesive layer conductive foil conductive foil 108A-B can include awidth 110A or 1108 that is smaller than awidth 112 of thebase 102 or theinner foil 104A-B. The smaller width can provide anedge width inner foil 104A-B, such as to reduce contact with the outerconductive foil 108A-B or theadhesive layer 106A-B during substrate manufacturing. However, including such anedge width 114A-B can reduce an area on which a substrate can be manufactured (e.g., the active area). Theedge width 114A-B can reduce such an area by ten or more millimeters. A peel strength of theadhesive layer 106A-B can be damaged by heat, bumping, or a chemical that comes into contact with theadhesive layer 106A-B. -
FIG. 2 shows a flow diagram of atechnique 200 of making the panel ofFIG. 1 . At 202, theinner foil 104A-B, outerconductive foil 108A-B, andadhesive layer 106A-B can be pressed into thebase 102. At 204, a masking film (e.g., Dry Film Resist (DFR)) can be laminated to the outerconductive foil 108A-B. At 206, thepanel 100 can be exposed and etched to remove the outer conductive foil at or near the edges of the panel. At 208, the masking film can be removed from the panel. At 210, a substrate can be manufactured on the outerconductive foil 108A-B. At 212, edges of thepanel 100 can be removed. At 214, the manufactured substrate can be released from thepanel 100. One or more process steps can be eliminated, such as by using a different panel architecture as discussed below. Eliminating a processing step can help reduce a cost associated with manufacturing a panel on which a substrate can be built. -
FIG. 3 shows an example of a core panel 300. The panel 300 can include a base 302, an inner foil 304A or 304B, an outer conductive foil 306A or 306B, or a resin 308A or 308B coating on an outermost conductive foil 310A or 310B. The inner foil 304A-B and the outer conductive foil 306A-B can include a width 312A or 312B that is less than a width 314A or 314B of the outermost conductive foil 310A-B and the base 302. The resin 308A-B and the outermost conductive foil 310A can jointly comprise a resin coated conductive layer. The resin coated conductive layer (i.e. 308A and 310A or 308B and 310B) can be pressed into the outer conductive foil 306A-B so as to form a temporary bond or seal between the resin 308A-B and the outer conductive foil 306A-B. - The base 302 can begin as a substantially rectangular structure and be processed to be generally “H” shaped, such as by forming a recess in each side of the base 302. The recesses in
FIG. 3 are the areas in which the inner foil 304A-B and the outer conductive foil 306A-B are situated. - A substrate can be built on the outermost conductive foil 310A-B. The resin coated conductive layer can be removed from the base 302 and the outer conductive foil 306A, such as with the substrate thereon (substrate not shown in
FIG. 3 ). The resin coated conductive layer can be removed from the substrate such as by etching, wet blasting, or a combination thereof. - The panel 300 can be cost prohibitive. Arranging the inner foil 304A-B and the outer conductive foil 306A-B within a recess in the base 302 (such as shown in
FIG. 3 ) can increase the cost of the panel 300. The increase in cost can be due, at least in part, to extra processing that is required to arrange the inner foil 304A-B and the outer conductive foil 306A-B in a recess of the base 302. The increase in cost can be due, at least in part, to processing conductive foil panels to be the width 312A-B, and inserting the modified foil panels into the recess in the base 302. -
FIG. 4 shows an example of apanel 400 according to one or more embodiments. Thepanel 400 can be configured to protect an interface between anadhesive layer inner foil conductive foil panel 400 covered by aprotective material panel 400 can include abase 402, theinner foil 404A-B, theadhesive layer 406A-B, the outerconductive foil 408A-B, adie protective material 412A-B. - The base 402 can be substantially rectangular. The base 402 can include a material that is rigid enough to withstand processing at a substrate manufacturing factory and retain shape. In one or more embodiments, the base 402 can include a material impregnated with a polymer. In one or more embodiments, the base 402 can include a carbon material impregnated with an epoxy or resin. In one or more embodiments, the base 402 can include a metal, plastic, or other substantially rigid material. The base 402 can be generally rectangular and generally flat.
- The
inner foil 404A-B can be affixed to thebase 402. A periphery of theinner foil 404A-B can be substantially flush with a periphery of thebase 402, such as shown inFIG. 4 . Theinner foil 404A-B can include a conductive material such as copper, gold, silver, aluminum, a combination thereof, or other conductive material. In one or more embodiments theinner foil 404A-B can include athickness inner foil 404A-B can include athickness 416A-B of between about fifteen and about twenty micrometers. In one or more embodiments, theinner foil 404A-B can include athickness 416A-B of about eighteen micrometers. - The
adhesive layer 406A-B can releasably couple the outerconductive foil 408A-B to theinner foil 404A-B. Theadhesive layer 406A-B can include an epoxy, resin, a combination thereof, or other material. Theadhesive layer 406A-B can be pressed (e.g., hot pressed, baked with pressure, or laminated) into theinner foil 404A-B. Such pressing can form a releasable coupling between theinner foil 404A-B and the outerconductive foil 408A-B, such as shown inFIG. 4 . - The
base 402 and the outerconductive foil 408A-B can be releasably uncoupled, such as by mechanically removing (e.g., pulling) the outerconductive foil 408A-B away from theinner foil 404A-B. The outerconductive foil 408A-B can be removed from theinner foil 404A-B after a substrate (e.g., thedie 410A-B and associated dielectric materials, vias, traces, interconnects, or other electric or electronic circuitry) has been manufactured on thepanel 400. The outerconductive foil 408A-B can be removed from thepanel 400 after edges of thepanel 400 have been removed. The edges of thepanel 400 can be removed by cutting the panel along thedotted lines 414A and 414B. Removing the edges can expose the interface between theadhesive layer 406A-B and theinner foil 404A-B and the outerconductive foil 408A-B, such as by removing theprotective material 412A-B on the edge (e.g., along the side) of thepanel 400. The outerconductive foil 408A-B can then be released from thepanel 400. - The
adhesive layer 406A-B can include a methyl ethyl ketone and toluene solvent with polydimethyl siloxane and bisphenol A based epoxy. Anadhesive layer 406A-B made from these materials can suffer from phase separation between the epoxy and silicone over time. Heat can cause blisters to form in theadhesive layer 406A-B made from these materials. The adhesive strength of suchadhesive layer 406A-B can degrade over time. An adhesive layer made of these materials can have poor line yields, such as in a substrate manufacturing factory. - As used herein releasably coupling means to couple such that a mechanical coupling through the
adhesive layer 406A-B can be broken without requiring excessive force or damaging the items mechanically coupled through theadhesive layer 406A-B. Theadhesive layer 406A-B can be released from an item by exerting a relatively small amount of force, such as about five Newtons per meter to about one hundred Newtons per meter on or near theadhesive layer 406A-B. - The
adhesive layer 406A-B can include one or more epoxy silicone copolymers or blends of polymers, silicone, or epoxy. Different blends can be used to makeadhesive layer 406A-B with varying mechanical properties, such as depending on the volume weight percent of polymer, silicone, or epoxy used. The mechanical properties can include hardness, elasticity, stickiness, or other mechanical property. - The
adhesive layer 406A-B can include an epoxy and silicone blend. For example, siloxane and epoxy resin can be blended together with a carboxylic acid anhydride hardener, such as to produce a stable or well-blendedadhesive layer 406A-B. This blend can be used as an adhesive by controlling the siloxane to epoxy resin ratio. By increasing the proportion of siloxane, anadhesive layer 406A-B with a reduced elastic modulus can be produced. - The
adhesive layer 406A-B can include a blend of co-polymer, epoxy, or silicone. A co-polymer of siloxane and epoxy can be produced and mixed with an epoxy resin. Polysiloxane can have an epoxide group on a side chain thereof and can be synthesized from methylhydrosiloxane, epoxy resin. - The outer
conductive foil 408A-B can be coupled to theinner foil 404A-B using theadhesive layer 406A-B. A periphery of the outerconductive foil 408A-B can be substantially flush with a periphery of the base 402 or a periphery of theinner foil 404A-B, such as shown inFIG. 4 . The outerconductive foil 408A-B can include a conductive material such as copper, gold, silver, aluminum, a combination thereof, or other conductive material. The outerconductive foil 408A-B can include athickness 418A-B that is smaller than athickness 416A-B of theinner foil 404A-B. - A yield loss realized in manufacturing a substrate onto the outer
conductive foil 408A-B can be reduced by including an outerconductive foil 408A-B with athickness 418A-B that is smaller than thethickness 416A-B of theinner foil 404A-B. In one or more embodiments, thethickness 418A-B of the outerconductive foil 408A-B can be between about one and thirty micrometers. In one or more embodiments, thethickness 418A-B of the outerconductive foil 408A-B can be between about two and fifteen micrometers. In one or more embodiments, thethickness 418A-B of the outerconductive foil 408A-B can be between about two and six micrometers. In one more embodiments, thethickness 418A-B of the outerconductive foil 408A-B can be between about three and five micrometers. In one or more embodiments, thethickness 418A-B of the outerconductive foil 408A-B can be about three, five, or eighteen micrometers. - As the
thickness 418A-B of the outer conductive foil increases, the yield loss realized in manufacturing a substrate on the outerconductive foil 408A-B can be decreased. However, if thethickness 418A-B of the outer conductive foil is too large, delamination of the outerconductive foil 408A-B can increase yield loss. In an embodiment that includes an outerconductive foil 408A-B with athickness 418A-B that is less than five micrometers, the outerconductive foil 408A-B may not be reliably releasable from theinner foil 404A-B. The outerconductive foil 408A-B can break in the separation process, or some residue from the outerconductive foil 408A-B or theadhesive layer 406A-B can be left on theinner foil 404A-B in the process of separating the outerconductive foil 408A-B from theinner foil 404A-B. - A periphery of the
inner foil 404A-B can be substantially flush with a periphery of thebase 402, such as shown inFIG. 4 . A periphery of the outerconductive foil 408A-B can be substantially flush with a periphery of the base 402 or a periphery of theinner foil 404A-B, such as shown inFIG. 4 . - The
protective material 412A-B can be situated on the outerconductive foil 408A-B or on the side of thepanel 400, such as to protect an interface between theadhesive layer 406A-B and the outerconductive foil 408A-B or theinner foil 404A-B. Theprotective material 412A-B can help protect the interface from chemicals, heat, bumping, or other external forces that can delaminate or damage the material behind theprotective material 412A-B. Theprotective material 412A-D can include a metal, polymer, or other material that can adhere to thepanel 400, such as at theinner foil 404A-B, the outerconductive foil 408A-B, theadhesive layer 406A-B, or thebase 402. - The
protective material 412A-B can include a metal, such as copper, gold, silver, or other metal, or a polymer or plastic. Theprotective material 412A-B can be electrolytically plated, applied in the form of a sheet, or otherwise flowed or dispensed on or mechanically coupled to thepanel 400. - Adding the
protective material 412A-B can reduce the yield loss or other concerns realized in using an outerconductive foil 408A-B with athickness 418A-B that is less than five micrometers. -
FIG. 5 shows a block diagram of an example of apanel 500 according to one or more embodiments. Thepanel 500 can include thebase 402, theinner foil 404A-B, the outerconductive foil 408A-B, thedie 410A-B, or aconnective material conductive foil 408A-B and theinner foil 404A-B. Thepanel 500 can include anadhesive layer 406A-B situated between theinner foil 404A-B and the outerconductive foil 408A-B (not shown inFIG. 5 ). - The
connective material 518A-D can include solder paste, such as can include tin, silver, copper, lead, indium, a combination thereof, or other solder paste, or a solder thermal interface material, such as can include indium. Theconnective material 518A-D can be placed on theinner foil 404A-B, the outerconductive foil 408A-B can be placed on theinner foil 404A-B and theconnective material 518A-B, and the combination can be heat pressed to melt theconnective material 518A-D and form a mechanical connection between theinner foil 404A-B and the outerconductive foil 408A-B, such as to affix theinner foil 404A-B to the outerconductive foil 408A-B, such as at or near edges of theinner foil 404A-B or the outerconductive foil 408A-B. - In an embodiment that includes the
adhesive layer 406A-B, theconnective material 518A-D can be situated along an edge of thepanel 500, such as to protect the interface between theadhesive layer 406A-B and theinner foil 404A-B or the outerconductive foil 408A-B. - The die 410A-B can be removed from the
panel 500, such as by removing portions of thepanel 500 that include theconnective material 518A-D, such as by cutting the panel at thedotted lines 520A-B, and releasing the outerconductive foil 408A-B from thepanel 500. The outerconductive foil 408A-B can be removed from thedie 410A-B or a substrate which thedie 410A-B is a part of, such as by etching away the outerconductive foil 408A-B. -
FIG. 6 shows a block diagram of an example of a panel 600 according to one or more embodiments. The panel 600 can include thebase 402, theinner foil 404A-B, an optionaladhesive layer 406A-B, or the outerconductive foil 408A-B. The panel 600 can include one ormore welds 616 affixing theinner foil 404A-B to the outerconductive foil 408A-B. - The outer
conductive foil 408A-B, theinner foil 404A-B or the base 402 can include awidth 614A-B, such as to make the outerconductive foil 408A-B,inner foil 404A-B, or the base 402 have substantially thesame width 614A-B. A width 618 of thewelds 616 can be about one millimeter or less. -
FIG. 7 shows a block diagram of apanel 700 that includes the panel 600 with thedie 410A-B situated on the outerconductive foil 408A-B and adielectric material 712A or 712B over or around (e.g., encasing) thedie 410A-B. Such embodiments can be considered “fully embedded” substrate architectures, because thedie 410A-B can be fully embedded in the dielectric (e.g., buildup) layer(s). -
FIG. 8 shows a block diagram of apanel 800 that includes thepanel 700 after thewelds 616 have been removed from thepanel 700, such as by cutting thepanel 700 at thedotted lines 714A-B. The die 410A-B and thedielectric material 712A-B can be removed from thepanel 800, such as by releasing the outerconductive foil 408A-B from theinner foil 404A-B. The outerconductive foil 408A-B can be removed from thedielectric material 712A-B (e.g., an etch stop or build up material such as Ajinomoto Buildup Film (ABF)) or thedie 410A-B, such as by copper etching the outerconductive foil 408A-B. -
FIG. 9 shows a block diagram of an example of a panel 900 that includes a partially embedded substrate (e.g., a conductive foil 914A or 914B, thedie 410A-B and the dielectric material 916A-B). The panel 900 can include thebase 402, theinner foil 404A-B, theadhesive layer 406A-B, the outerconductive foil 408A-B, a dielectric material 912A or 912B, the conductive foil 914A-B, thedie 410A-B, or the dielectric material 916A-B. The dielectric material 912A-B and the conductive foil 914A-B can be jointly considered a resin coated conductive foil. The conductive foil 914A-B can be similar to theinner foil 404A-B or the outerconductive foil 408A-B. - A recess can be formed in the conductive foil 914A-B. The die 410A-B can be situated in the recess. The dielectric material 916A-B can be flowed, dispensed, or applied over the conductive foil 914A-B and the
die 410A-B, such as to at least partially encase the die 410A-B in the dielectric material 916A-B. - The dielectric material 916A-B can be similar to the
dielectric material 712A-B. The substrate can be considered a partially embedded substrate because the dielectric film only covers a portion of the die, the conductive foil that the die is inserted into can help cover the remainder of the die. - The substrate can be removed from the panel 900 by removing the edges of the panel 900, such as to remove the
weld 616, such as by cutting the panel at the dotted lines 918A-B. The outerconductive foil 408A-B can then be released from the panel 900, such as at an interface between the outerconductive foil 408A-B and theadhesive layer 406A-B or theinner foil 404A-B. The outerconductive foil 408A-B can then be removed from the partially embedded substrate, such as by etching the outerconductive foil 408A-B from the substrate. The dielectric material 912A-B can then be removed from the partially embedded substrate, such as by sand blasting, wet blasting, or cutting the dielectric material 912A-B from the substrate. - Note that a fully embedded substrate or a partially embedded substrate can be built on any of the
panels FIG. 7 . The partially embedded substrate can include a die situated in a recess of a conductive foil that is situated on a dielectric material that is situated on the outer conductive foil. Dielectric material can be flowed over the die and the conductive foil of the partially embedded substrate. The partially embedded substrate or the fully embedded substrate can be BBUL substrates or cored substrates. - A substrate may be manufactured on the panel without a die situated therein. Such substrates can be a cored die substrate. A coreless die substrate can include a substrate that is built up and a die is attached to the die substrate after the die substrate is built. A cored die substrate can include a substrate that includes a die arranged in the substrate and at least a portion of the substrate is built around the die. A BBUL die substrate can include a substrate that includes a die with one or more buildup layers built above the die to form the die substrate.
- While one die is shown in the FIGS., multiple dies can be situated on the panel. The substrate can include a Bumpless Buildup Layer (BBUL) substrate, a Flip Chip substrate, a Surface Mount (SMT) substrate, or other type of substrate.
- Note that while embodiments of panels discussed herein are double-sided (i.e. the panels include an inner foil, adhesive layer, and outer conductive foil all situated on opposite sides of the base), the panel can be one-sided. One sided panels are less efficient in terms of throughput, but can include simpler processing at a manufacturing facility.
- Processing to make the
panel panel 100. The processing can be simpler in that the inner foil and the outer conductive foil need not be processed to fit in a recess of the base. Also, thebase 402 does not need to be processed to include a recess in which the inner foil or the outer conductive foil can be situated in. By removing a processing step, the cost of manufacturing thepanel panel 100 or 300. Manufacturing thepanel panel panel 100 or 300. The active area the area on which a substrate can be built) of thepanel panel 100. -
FIG. 10 shows a flow diagram of an example of atechnique 1000 for making a panel according to one or more embodiments. At 1002, a panel can be pressed. Pressing the panel can include arranging a panel of inner foil on a base, optionally arranging an adhesive layer on the inner foil, optionally arranging connective material on the inner foil, arranging an outer conductive foil on the inner foil, and mechanically pressing the arranges materials, such as under heat, pressure, or in a vacuum. - At 1004, the inner and outer conductive foils can be mechanically coupled to each other. Mechanically coupling the inner and outer conductive foils can include melting a connective material situated between the inner and outer conductive foils, welding (e.g., laser welding) the outer conductive foil to the inner foil, or situating protective material on the edge of the inner and outer conductive foil (e.g., to protect an adhesive layer coupling the inner and outer conductive foils).
- At 1006, edges of the panel can be trimmed (e.g., cut or otherwise removed), such as to remove the mechanical coupling between the inner and outer conductive foils (e.g., to remove the weld, at least a portion of the protective material, or the connective material). At 1008, the outer conductive foil can be released from the panel.
- Building a panel using the
technique 1000 can be more cost effective than building a panel using thetechnique 200. This can be due to reduced number of steps in thetechnique 1000 as compared to thetechnique 200. In thetechnique 1000 there is no masking film lamination, panel expose or etch, or masking film removal process. Removing a process of the technique can reduce the cost of making a panel using the technique and increase through put by decreasing the amount of time it takes to make a panel using the technique. -
FIG. 11 shows a flow diagram of an example of atechnique 1100 according to one or more embodiments. At 1102, an inner foil can be coupled (e.g., mechanically coupled or affixed) to a substantially rectangular base. At 1104, an outer conductive foil can be situated on or over the inner foil. At 1106, the inner foil and the outer conductive foil can be coupled together (affixed to each other) near edges of the outer conductive foil and the inner foil, such as by using a connective material. Coupling the inner foil and the outer conductive foil can include welding the inner foil to the outer conductive foil. The connective material can include a solder paste and coupling the inner foil and the outer conductive foil can include reflowing the solder paste between the inner foil and the outer conductive foil. - The
technique 1100 can include situating a fully embedded substrate on the outer conductive foil. Situating the fully embedded substrate on the outer conductive foil can include situating a die on the outer conductive foil and situating a dielectric material over and around the die. Situating the fully embedded substrate on the outer conductive foil can include forming a coreless substrate, cored substrate, or a BBUL substrate on the outer conductive foil. - The
technique 1100 can include situating a partially embedded substrate on the outer conductive foil. Situating the partially embedded substrate on the outer conductive foil can include: (1) situating a resin coated copper on the outer conductive foil, (2) forming a recess in the resin coated copper, (3) situating a die situated in the recess, or (4) situating a dielectric material over the die and the resin coated copper. Situating the partially embedded substrate on the outer conductive foil can include forming a coreless substrate, cored substrate, or a BBUL substrate on the outer conductive foil. -
FIG. 12 is a block diagram illustrating anexample computer system 1200 machine which can include a substrate that was built on a panel as discussed herein.Computer system 1200 can be a computing device. In an example, the machine can operate as a standalone device or can be connected (e.g., via a cellular network) to other machines. In a networked deployment, the machine can operate in the capacity of either a server or a client machine in server-client network environments, or it can act as a peer machine in peer-to-peer (or distributed) network environments. Further, while only a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein. -
Example computer system 1200 can include a processor 1202 (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU) or both), amain memory 1204 and astatic memory 1206, which communicate with each other via an interconnect 1208 (e.g., a link, a bus, etc.). Thecomputer system 1200 can further include avideo display unit 1210, an alphanumeric input device 1212 (e.g., a keyboard), and a User Interface (UI) navigation device 1214 (e.g., a mouse). In an example, thevideo display unit 1210,input device 1212 andUI navigation device 1214 are a touch screen display. Thecomputer system 1200 can additionally include a storage device 1216 (e.g., a drive unit), a signal generation device 1218 (e.g., a speaker), anoutput controller 1232, apower management controller 1234, and a network interface device 1220 (which can include or operably communicate with one ormore antennas 1230, transceivers, or other wireless communications hardware), and one ormore sensors 1228, such as a GPS sensor, compass, location sensor, accelerometer, or other sensor. Theantennas 1230 can be coupled to a network 1226. Any of the items of thesystem 1200 can include a substrate built on a panel discussed herein. - The present subject matter may be described by way of several examples.
- Example 1 can include or use subject matter (such as an apparatus, a method, a means for performing acts, or a device readable memory including instructions that, when performed by the device, can cause the device to perform acts), such as can include or use a substantially rectangular base, an inner foil mechanically coupled to the base, an outer conductive foil situated over the inner foil, and connective material coupling the inner foil and the outer conductive foil near edges of the outer conductive foil and the inner foil.
- Example 2 can include or use, or can optionally be combined with the subject matter of Example 1, to include or use, wherein the connective material includes a weld.
- Example 3 can include or use, or can optionally be combined with the subject matter of Example 1, to include or use, wherein the connective material includes a solder paste.
- Example 4 can include or use, or can optionally be combined with the subject matter of at least one of Examples 1-3, to include or use a fully embedded substrate situated on the outer conductive foil.
- Example 5 can include or use, or can optionally be combined with the subject matter of Example 4, to include or use, wherein the fully embedded substrate includes a die situated on the outer conductive foil and a dielectric material situated over and around the die.
- Example 6 can include or use, or can optionally be combined with the subject matter of at least one of Examples 4-5, to include or use, wherein the fully embedded substrate is a cored substrate or a Bumpless Buildup Layer (BBUL) substrate.
- Example 7 can include or use, or can optionally be combined with the subject matter of at least one of Examples 1-3, to include or use a partially embedded substrate situated on the outer conductive foil.
- Example 8 can include or use, or can optionally be combined with the subject matter of Example 7 to include or use, wherein the partially embedded substrate includes (1) a resin coated copper situated on the outer conductive foil, (2) a recess formed in the resin coated copper, (3) a die situated in the recess, or (4) a dielectric material situated over the die and the resin coated copper.
- Example 9 can include or use, or can optionally be combined with the subject matter of at least one of Examples 7-8 to include or use, wherein the partially embedded substrate is a cored substrate or a Bumpless Buildup Layer (BBUL) substrate.
- Example 10 can include or use subject matter (such as an apparatus, a method, a means for performing acts, or a device readable memory including instructions that, when performed by the device, can cause the device to perform acts), such as can include or use coupling an inner foil to a substantially rectangular base, situating an outer conductive foil situated on the inner foil, or coupling, using a connective material, the inner foil and the outer conductive foil near edges of the outer conductive foil and the inner foil.
- Example 11 can include or use, or can optionally be combined with the subject matter of Example 10 to include or use, wherein coupling the inner foil and the outer conductive foil includes welding the inner foil to the outer conductive foil.
- Example 12 can include or use, or can optionally be combined with the subject matter of Example 10 to include or use, wherein the connective material includes a solder paste and coupling the inner foil and the outer conductive foil includes reflowing the solder paste between the inner foil and the outer conductive foil.
- Example 13 can include or use, or can optionally be combined with the subject matter of at least one of Examples 10-12 to include or use, situating a fully embedded substrate on the outer conductive foil.
- Example 14 can include or use, or can optionally be combined with the subject matter of Example 13 to include or use, wherein situating the fully embedded substrate on the outer conductive foil includes situating a die on the outer conductive foil and situating a dielectric material over and around the die.
- Example 15 can include or use, or can optionally be combined with the subject matter of at least one of Examples 13-14 to include or use, wherein situating the fully embedded substrate on the outer conductive foil includes forming a cored substrate, or a Bumpless Buildup Layer (BBUL) substrate on the outer conductive foil.
- Example 16 can include or use, or can optionally be combined with the subject matter of at least one of Examples 10-12 to include or use, situating a partially embedded substrate on the outer conductive foil.
- Example 17 can include or use, or can optionally be combined with the subject matter of Example 16 to include or use, wherein situating the partially embedded substrate on the outer conductive foil includes (1) situating a resin coated copper on the outer conductive foil, (2) forming a recess in the resin coated copper, (3) situating a die situated in the recess, or (4) situating a dielectric material over the die and the resin coated copper.
- Example 18 can include or use, or can optionally be combined with the subject matter of at least one of Examples 16-17 to include or use, wherein situating the partially embedded substrate on the outer conductive foil includes forming a cored substrate or a Bumpless Buildup Layer (BBUL) substrate on the outer conductive foil.
- Example 19 can include or use subject matter (such as an apparatus, a method, a means for performing acts, or a device readable memory including instructions that, when performed by the device, can cause the device to perform acts), such as can include or use (1) a substantially rectangular base, (2) a first inner foil mechanically coupled to a first side of the base, (3) a second inner foil mechanically coupled to a second side of the base, the second side of the base opposite the first side of the base, (4) a first outer conductive foil situated on the first inner foil, (5) a second outer conductive foil situated on the second inner foil, or (6) connective material coupling the first inner foil and the first outer conductive foil near edges of the first outer conductive foil and the first inner foil and coupling the second inner foil and the second outer conductive foil near edges of the second outer conductive foil and the second inner foil.
- Example 20 can include or use, or can optionally be combined with the subject matter of Example 19 to include or use, wherein the connective material includes a weld.
- Example 21 can include or use, or can optionally be combined with the subject matter of Example 19 to include or use, wherein the connective material includes a solder paste.
- Example 22 can include or use, or can optionally be combined with the subject matter of at least one of Examples 19-21 to include or use a first fully embedded substrate situated on the first outer conductive foil and a second fully embedded substrate situated on the second outer conductive foil.
- Example 23 can include or use, or can optionally be combined with the subject matter of Example 22 to include or use, wherein the first fully embedded substrate includes a first die situated on the first outer conductive foil and a first dielectric material situated over and around the first die.
- Example 24 can include or use, or can optionally be combined with the subject matter of at least one of Examples 22-23 to include or use, wherein the first fully embedded substrate is a cored substrate or a Bumpless Buildup Layer (BBUL) substrate.
- Example 25 can include or use, or can optionally be combined with the subject matter of at least one of Examples 19-21 to include or use a first partially embedded substrate situated on the first outer conductive foil and a second partially embedded substrate situated on the second outer conductive foil.
- Example 26 can include or use, or can optionally be combined with the subject matter of Example 25 to include or use, wherein the first partially embedded substrate includes (1) a resin coated copper situated on the first outer conductive foil, (2) a recess formed in the resin coated copper, (3) a die situated in the recess, or (4) a dielectric material situated over the die and the resin coated copper.
- Example 27 can include or use, or can optionally be combined with the subject matter of at least one of Examples 25-26 to include or use, wherein the first partially embedded substrate is a cored substrate or a Bumpless Buildup Layer (BBUL) substrate.
- The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which methods, apparatuses, and systems discussed herein can be practiced. These embodiments are also referred to herein as “examples.” Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided, Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.
- In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In this document, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.
- As used herein, a “-” (dash) used when referring to a reference number means “or”, in the non-exclusive sense discussed in the previous paragraph, of all elements within the range indicated by the dash. For example, 103A-B means a nonexclusive “or” of the elements in the range {103A, 103B}, such that 103A-103B includes “103A but not 103B”, “103B but not 103A”, and “103A and 103B”.
- The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. §1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure, This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Claims (21)
1. (canceled)
2. A device comprising:
a base including a cloth material;
a copper inner foil coupled to the base;
an outer foil situated over and releasably coupled to the inner foil; and
connective material coupling the inner foil and the outer foil, the connective material including at least one of an epoxy and a resin.
3. The device of claim 2 , wherein the connective material includes a resin.
4. The device of claim 2 , wherein the base further includes a resin.
5. The device of claim 2 , wherein the base includes a recess and the inner foil is situated, at least partially in the recess.
6. The device of claim 2 , wherein a thickness of the inner foil is between about twenty-five micrometers and about one hundred micrometers.
7. The device of claim 2 , wherein the outer foil is conductive.
8. The device of claim 7 , wherein the outer foil includes copper.
9. A device comprising:
a base including a recess;
a copper inner foil coupled to the base and situated, at least partially, in the recess;
an outer foil situated over and releasably coupled to the inner foil; and
connective material coupling the inner foil and the outer foil, the connective material including at least one of an epoxy and a resin.
10. The device of claim 9 , wherein the connective material includes a resin.
11. The device of claim 9 , wherein the base includes a cloth.
12. The device of claim 11 , wherein the base further includes a resin.
13. The device of claim 9 , wherein a thickness of the inner foil is between about twenty-five micrometers and about one hundred micrometers.
14. The device of claim 9 , wherein the outer foil is conductive.
15. The device of claim 14 , wherein the outer foil includes copper.
16. A method comprising:
situating a copper inner foil on a base, the base including at least one of a cloth and a resin:
situating a connective material over the inner foil;
situating an outer foil on the connective material; and
removing the outer foil from the base.
17. The method of claim 16 , wherein situating the inner foil on the base includes exposing the inner foil in a recess in the base.
18. The method of claim 16 , further comprising forming circuitry on the outer foil.
19. The method of claim 16 , wherein the outer foil is conductive,
20. The method of claim 19 , wherein the outer foil include copper.
21. The method of claim 16 , further comprising pressing the inner foil into the base by applying a mechanical force to the inner foil.
Priority Applications (1)
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US15/413,156 US20170202080A1 (en) | 2013-12-19 | 2017-01-23 | Panel with releasable core |
Applications Claiming Priority (3)
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US14/135,168 US9522514B2 (en) | 2013-12-19 | 2013-12-19 | Substrate or panel with releasable core |
US14/227,723 US9554472B2 (en) | 2013-12-19 | 2014-03-27 | Panel with releasable core |
US15/413,156 US20170202080A1 (en) | 2013-12-19 | 2017-01-23 | Panel with releasable core |
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US14/227,723 Continuation US9554472B2 (en) | 2013-12-19 | 2014-03-27 | Panel with releasable core |
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US15/413,156 Abandoned US20170202080A1 (en) | 2013-12-19 | 2017-01-23 | Panel with releasable core |
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Cited By (1)
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US10098233B2 (en) | 2013-12-19 | 2018-10-09 | Intel Corporation | Substrate or panel with releasable core |
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US9434135B2 (en) | 2013-12-19 | 2016-09-06 | Intel Corporation | Panel with releasable core |
US9554468B2 (en) | 2013-12-19 | 2017-01-24 | Intel Corporation | Panel with releasable core |
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US20150181717A1 (en) | 2015-06-25 |
US9554472B2 (en) | 2017-01-24 |
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