US20170200763A1

US20170200763A1 - Method for manufacturing image sensor structure having wide contact

Info

Publication number: US20170200763A1
Application number: US15/472,814
Authority: US
Inventors: Tzu-Jui WANG; Dun-Nian Yaung; Jen-Cheng Liu; Tzu-Hsuan Hsu; Yuichiro Yamashita
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2015-10-30
Filing date: 2017-03-29
Publication date: 2017-07-13
Anticipated expiration: 2035-10-30
Also published as: US9620548B1; US9978805B2; TW201727883A; US20170125473A1; CN106653780A

Abstract

Methods for forming image sensor structures are provided. The method includes forming an isolation structure in a substrate and forming a first light sensing region and a second light sensing region. The method further includes forming a first gate structure and a second gate structure, and the first gate structure and the second gate structure are positioned at a front side of the substrate. The method further includes forming a first source/drain structure adjacent to the first gate structure and a second source/drain structure adjacent to the second gate structure and forming an interlayer dielectric layer over the front side of the substrate. The method further includes forming a contact trench through the interlayer dielectric layer and forming a contact in the contact trench.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Divisional application of U.S. patent application Ser. No. 14/928,604, filed on Oct. 30, 2015, the entirety of which is incorporated by reference herein.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
However, although existing semiconductor manufacturing processes have generally been adequate for their intended purposes, as device scaling-down continues, they have not been entirely satisfactory in all respects.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a top-view representation of a pixel layout of an image sensor structure in accordance with some embodiments.

FIGS. 2A to 2L are cross-sectional representations of various stages of forming the image sensor structure illustrated along line A-A′ shown in FIG. 1 in accordance with some embodiments.

FIG. 3 is a cross-sectional representation of the image sensor structure illustrated along line B-B′ shown in FIG. 1 in accordance with some embodiments.

FIG. 4A is a top-view representation of a pixel layout of an image sensor structure in accordance with some embodiments.

FIG. 4B is a cross-sectional representations of the image sensor structure illustrated along line C-C′ shown in FIG. 4A in accordance with some embodiments.

FIG. 5 is a cross-sectional representation of an image sensor structure in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Embodiments of an integrated circuit (IC) structure and methods for forming the same are provided. In some embodiments, the IC structure includes an image sensor. The image sensor includes an isolation structure isolating two adjacent light sensing regions. Source/drain structures (in image sensor field, also called a floating node) are formed adjacent to the isolation structure. A contact is formed over the isolation structure, and the contact is wider than the isolation structure, so that the contact also covers portions of source/drain structures formed adjacent to the isolation structure. Accordingly, the source/drain structures can be electrically connected through the contact.
FIG. 1 is a pixel layout of an image sensor structure 100 a in accordance with some embodiments. FIGS. 2A to 2L are cross-sectional representations of various stages of forming image sensor structure 100 a illustrated along line A-A′ shown in FIG. 1 in accordance with some embodiments. It should be noted that image sensor structure 100 a illustrated in FIGS. 2A to 2L has been simplified for the sake of clarity so that concepts of the present disclosure can be better understood. Therefore, in some other embodiments, additional features are added in image sensor structure 100 a, and some of the elements are replaced or eliminated.
A substrate 102 is received, as shown in FIG. 1A in accordance with some embodiments. In some embodiments, substrate 102 is a semiconductor substrate including silicon. Substrate 102 may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, substrate 102 may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of the elementary semiconductor materials may be, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Examples of the compound semiconductor materials may be, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Examples of the alloy semiconductor materials may be, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP.
As shown in FIG. 2A, substrate 102 has a front side 104 and a back side 106. Isolation trenches 108 are formed in substrate 102, as shown in FIG. 2A in accordance with some embodiments. In some embodiments, isolation trenches 108 are formed by forming a hard mask structure over front side 104 of substrate 102, patterning the hard mask structure to form openings in the hard mask structure, and etching substrate 102 through the openings. As shown in FIG. 2A, isolation trenches 108 are formed from front side 104 of substrate 102.
After isolation trenches 108 are formed, liners 110 are formed on the bottom surface and the sidewalls of isolation trenches 108, as shown in FIG. 2B in accordance with some embodiments. Liners 110 may be formed by annealing, chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), spin-on coating, implantation process, and/or other applicable processes. Liners 110 may be made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or other applicable dielectric materials.
After liners 110 are formed, isolation material 111 is formed in isolation trenches 108 to form isolation structures 112, as shown in FIG. 2B in accordance with some embodiments. That is, isolation structure 112 includes liner 110 and isolation material 111 in accordance with some embodiments. However, in some other embodiments, liner 110 is not formed. In some embodiments, isolation structures 112 are deep trench isolation (DTI) structures. In some embodiments, isolation structures 112 are formed by depositing an isolation material in isolation trenches 108. The isolation materials include silicon nitride, silicon oxide, and polysilicon in accordance with some embodiments.
In some embodiments, isolation structure 112 has a thickness in a range from about 1 μm to about 4 μm. The thickness of isolation structure 112 should be thick enough so that the light sensing regions formed afterwards can be separated by isolation structure 112. In some embodiments, isolation structure 112 has a width in a range from about 0.05 μm to about 0.4 μm. If the width of isolation structure 112 is too large, the size of the light sensing regions formed afterwards may become relatively small. On the other hand, if the width of isolation structure 112 is too small, the deposition of the isolation material in isolation trench 108 may become challenging.
As shown in FIG. 2B, isolation structure 112 is formed from front side 104 of substrate 102, and substrate 102 is divided into a first region 114 and a second region 116 by isolation structure 112. After isolation structure 112 is formed, a first light sensing region 118 is formed in first region 114 of substrate 102, and a second light sensing region 120 is formed in second region 116 of substrate 102, as shown in FIG. 2C in accordance with some embodiments.
In some embodiments, the thickness of first light sensing region 118 and second light sensing region 120 are no greater than (i.e. smaller than or the same as) the thickness T₁of isolation structure 112. That is, first light sensing region 118 and second light sensing region 120 are formed from front side 104 of substrate 102, and the bottom surfaces of first light sensing region 118 and second light sensing region 120 are no lower than the bottom surface of isolation structure 112, as shown in FIG. 2C in accordance with some embodiments. Since first light sensing region 118 and second light sensing region 120 are formed at the opposite sides of isolation structure 112 and has a thickness than T₁, first light sensing region 118 and second light sensing region 120 can be isolated by isolation structure 112.
In some embodiments, first light sensing region 118 and second light sensing region 120 are configured to sense (detect) light of different wavelengths. For examples, first light sensing region 118 and second light sensing region 120 may individually correspond to a range of wavelengths of red light, green light, or blue light. First light sensing region 118 and second light sensing region 120 may be doped regions having n-type and/or p-type dopants formed in substrate 102. First light sensing region 118 and second light sensing region 120 may be formed by an ion implantation process, diffusion process, or other applicable processes.
After first light sensing region 118 and second light sensing region 120 are formed, a first gate structure 122 is formed over first region 114 of substrate 102, and a second gate structure 124 is formed over second region 116 of substrate 102, as shown in FIG. 2D in accordance with some embodiments. In some embodiments, first gate structure 122 includes a first gate dielectric layer 126 and a first gate electrode layer 128, and second gate structure 124 includes a second gate dielectric layer 130 and a second gate electrode layer 132. Spacers 134 are formed on the sidewalls of first gate structure 122 and second gate structure 124.
In some embodiments, first gate dielectric layer 126 and second gate dielectric layer 130 are made of oxide. In some embodiments, first gate dielectric layer 126 and second gate dielectric layer 130 are made of high-k dielectric materials, such as metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, or oxynitrides of metals. Examples of the high-k dielectric material include, but are not limited to, hafnium oxide (HfO₂), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO₂—Al₂O₃) alloy, or other applicable dielectric materials.
In some embodiments, first gate electrode layer 128 and second gate electrode layer 132 are made of polysilicon. In some embodiments, first gate electrode layer 128 and second gate electrode layer 132 are made of conductive materials, such as aluminum, copper, tungsten, titanium, tantalum, or other applicable materials. First gate structure 122 and second gate structure 124 may be formed by forming a gate dielectric layer and a conductive layer over front side 104 of substrate 102 and patterning the gate dielectric layer and the conductive layer.
In some embodiments, spacers 134 are made of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), silicon carbide, or other applicable dielectric materials. Spacers 134 may be formed by forming a dielectric layer over front side 104 of substrate 102 to cover first gate structure 122 and second gate structure 124 and etching the dielectric layer.
After first gate structure 122 and second gate structure 124 are formed, a first source/drain structure 136 is formed adjacent to first gate structure 122, and a second source/drain structure 138 is formed adjacent to second gate structure 124, as shown in FIG. 2E in accordance with some embodiments. In some embodiments, first source/drain structure 136 and second source/drain structure 138 are formed by implanting dopants into substrate 102 from front side 104 of substrate 102. In some embodiments, the dopants are also doped in the upper portion of isolation structure 112. In some embodiments, first source/drain structure 136 and second source/drain structure 138 are formed by recessing front side 104 of substrate 102 to form recesses and epitaxial growing strained materials in the recesses.
As shown in FIG. 2E, first source/drain structure 136 is formed in first region 114 of substrate 102 and is adjacent to one side of isolation structure 112, and second source/drain structure 138 is formed in second region 116 of substrate 102 and is adjacent to the other side of isolation structure 112. In some embodiments, the top surface of first source/drain structure 136, the top surface of isolation structure 112, and the top surface of second source/drain structure 138 are substantially level with one another.
In some embodiments, the sizes of first source/drain structure 136 and second source/drain structure 138 are relatively small since a wide contact will be formed later on. Therefore, there can be a greater spacer to form first light sensing region 118 and second light sensing region 120, and the quantum efficiency of the resulting image sensor 100 a can be improved (Details will be described later).
After first source/drain structure 136 and second source/drain structure 138 are formed, an interlayer dielectric layer 140 is formed over front side 104 of substrate 102, and first gate structure 122 and second gate structure 124 are covered by interlayer dielectric layer 140, as shown in FIG. 2F in accordance with some embodiments. Interlayer dielectric layer 140 may include multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, and/or other applicable low-k dielectric materials. Interlayer dielectric layer 140 may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), spin-on coating, or other applicable processes.
Next, a first contact trench 142, a second contact trench 144, and a wide contact trench 146 are formed through interlayer dielectric layer 140, as shown in FIG. 2G in accordance with some embodiments. First contact trench 142 is formed over first gate structure 122, second contact trench 144 is formed over second gate structure 124, and wide contact trench 146 is formed over isolation structure 112. In addition, as shown in FIG. 2G, wide contact trench 146 has a relatively great width. In some embodiments, the width of wide contact trench 146 is greater than the width of first contact trench 142 and the width of second contact trench 144.
Furthermore, the width of wide contact trench 146 is greater than the width of isolation structure 122 in accordance with some embodiments. Since wide contact trench 146 is wider than isolation structure 112, a portion of first source/drain structure 136 and a portion of second source/drain structure 138 formed adjacent to isolation structure 112 are also exposed by wide contact trench 146, as shown in FIG. 2G in accordance with some embodiments.
In some embodiments, the width of wide contact trench 146 is in a range from about 0.1 μm to about 0.5 μm. Wide contact trench 146 should be wide enough, or the contact formed in the wide contact trench afterwards will not be wide enough to connect both first source/drain structure 136 and second source/drain structure 138 (Details will be described later).
After first contact trench 142, second contact trench 144, and wide contact trench 146 are formed, a first contact 148, a second contact 150, and a wide contact 152 are formed, as shown in FIG. 2H in accordance with some embodiments. First contact 148 is formed in first contact trench 148 and is electrically contacted with first gate structure 122. Second contact 150 is formed in second contact trench 144 and is electrically contacted with second gate structure 124. Wide contact 152 is formed in wide contact trench 146 and is electrically contacted with first source/drain structure 136 and second source/drain structure 138.
Since wide contact 152 is formed in wide contact trench 146, wide contact 152 has a width substantially equal to the width of third contact trench, which is greater than the width of isolation structure 112 in accordance with some embodiments. Accordingly, wide contact 152 is formed on a portion of first source/drain structure 136, isolation structure 112, and a portion of second source/drain structure 138 in accordance with some embodiments.
As shown in FIG. 2H, wide contact 152 overlaps with isolation structure 112, a portion of first source/drain structure 136, and a portion of second source/drain structure 138. In some embodiments, wide contact 152 is in direct contact with a portion of the top surface of first source/drain structure 136, the top surface of isolation structure 112, and a portion of the top surface of second source/drain structure 138. By forming wide contact 152 having a relatively great width, first source/drain structure 136 and second source/drain structure 138 can be electrically connected without requiring additional conductive features. In some embodiments, first source/drain structure 136 and second source/drain structure 138 are electrically connected with wide contact 152 and can be seen as a floating diffusion node.
First contact 148, second contact 150, and wide contact 152 may be formed by filling first contact trench 142, second contact trench 144, and wide contact trench 146 by a conductive material. In some embodiments, the conductive material includes aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantulum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), tantulum carbide (TaC), tantulum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminide nitride (TiAlN), other applicable conductive materials, or a combination thereof.
In addition, first contact 148, second contact 150, and wide contact 152 may further include a liner and/or a barrier layer. For example, a liner (not shown) may be formed on the sidewalls and bottom of the contact trench. The liner may be silicon nitride, although any other applicable dielectric may alternatively be used. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other applicable processes, such as physical vapor deposition or a thermal process, may alternatively be used. The barrier layer (not shown) may be formed over the liner (if present) and may cover the sidewalls and bottom of the opening. The barrier layer may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition processes. The barrier layer may be made of tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, may also be used.
After first contact 148, second contact 150, and wide contact 152 are formed, an interconnect structure 154 is formed over interlayer dielectric layer 140, as shown in FIG. 2I in accordance with some embodiments. That is, interconnect structure 154 is formed over front side 104 of substrate 102. In some embodiments, interconnect structure 154 includes a dielectric layer 156 and conductive features 158 formed in dielectric layer 156.
In some embodiments, dielectric layer 156 is an inter-metal dielectric (IMD) layer. In some embodiments, dielectric layer 156 includes multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or other applicable low-k dielectric materials. Dielectric layer 156 may be formed by a chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), spin-on coating, or other applicable processes.
Conductive features 158 may be configured to connect various features or structures of image sensor structure 100 a. For example, conductive features 158 are used to interconnect first contact 148, second contact 150, and wide contact 152 formed over substrate 102. Conductive features 158 may be vertical interconnects, such as vias and contacts, and/or horizontal interconnects, such as conductive lines. In some embodiments, conductive features 158 are made of conductive materials, such as aluminum, aluminum alloy, copper, copper alloy, titanium, titanium nitride, tungsten, polysilicon, or metal silicide.
It should be noted that conductive features 158 shown in FIG. 2I are merely examples for better understanding the concept of the disclosure, and the scope of disclosure is not intended to be limiting. That is, conductive features 112 may be arranged in various ways in various embodiments.
After interconnect structure 154 is formed, a buffer layer 160 is formed over interconnect structure 154, as shown in FIG. 2J in accordance with some embodiments. In some embodiments, buffer layer 160 is made of silicon oxide, silicon nitride, or other applicable dielectric materials. Buffer layer 154 may be formed by CVD, PVD, or other applicable techniques. In some embodiments, buffer layer 160 is planarized to form a smooth surface by a chemical-mechanical-polishing (CMP) process.
Next, a carrier substrate 162 is bonded with buffer layer 160, as shown in FIG. 2J in accordance with some embodiments. Carrier substrate 162 is configured to provide mechanical strength and support for processing back side 106 of substrate 102 in subsequent processes. Carrier substrate 162 may be similar to substrate 102 or may be a glass substrate.
Afterwards, back side 106 of substrate 106 is polished to expose first light sensing region 118 and second light sensing region 120, as shown in FIG. 2K in accordance with some embodiments. Accordingly, a thinned substrate 102′ having a back side 106′ is formed. As shown in FIG. 2K, first light sensing region 118 and second light sensing region 120 are exposed from back side 106′ of substrate 102′. In some embodiments, substrate 102 is polished by a chemical mechanical polishing (CMP) process. In some embodiments, a portion of isolation structure 120 is removed during the polishing process. Accordingly, isolation structure 112 extends from front side 104 of thinned substrate 102′ to thinned back side 106′ of thinned substrate 102′, as shown in FIG. 2K.
Next, antireflective layer 164 is formed over back side 106′ of thinned substrate 102′, such that exposed first light sensing region 118 and second light sensing region 120 are covered by antireflective layer 164, as shown in FIG. 2L in accordance with some embodiments. In some embodiments, antireflective layer 164 is made of silicon carbide nitride, silicon oxide, or the like. After antireflective layer 164 is formed, a passivation layer 166 is formed over antireflective layer 164, as shown in FIG. 2L in accordance with some embodiments. In some embodiments, passivation layer 166 is made of silicon nitride or silicon oxynitride.
After passivation layer 166 is formed, color filter layer 168 is formed over passivation layer 166, and a microlens layer 170 is disposed over color filter layer 168, as shown in FIG. 2L in accordance with some embodiments. Color filter layer 168 may include more than one color filter. In some embodiments, color filter layer 168 includes a first color filter 172 and a second color filter 174. In some embodiments, first color filter 172 and second color filter 174 are respectively aligned with first light sensing region 118 and second light sensing region 120. In some embodiments, first color filter 172 and second color filter 174 are made of a dye-based (or pigment-based) polymer for filtering out a specific frequency band of radiation. In some embodiments, first color filter 172 and second color filter 174 are made of resin or other organic-based material having color pigments.
In some embodiments, microlens layer 170 disposed on color filter layer 168 includes a first microlens 176 and a second microlens 178. As shown in FIG. 2L, first microlens 176 and second microlens 178 are respectively aligned with first color filter 172 and second color filter 174 and therefore are respectively aligned with first light sensing region 118 and second light sensing region 120. However, it should be noted that microlens layer 170 may be arranged in various positions in various applications.
Referring back to FIG. 1, image sensor structure 100 a includes first region 114 and second region 116 separated by isolation structure 112 in accordance with some embodiments. First light sensing region 118 is formed in first region 114, and second light sensing region 120 is formed in second region 116. In addition, first gate structure 122 is formed over first region 114, and first source/drain structure 136 is formed adjacent to first gate structure 122. Second gate structure 124 is formed over second region 116, and second source/drain structure 138 is formed adjacent to second gate structure 124. First contact 148 is formed over first gate structure 122, and second contact 150 is formed over second gate structure 124.
As described previously, the relatively wide contact 152 is formed over isolation structure 112 and further extends over a portion of first source/drain structure 136 and a portion of second source/drain structure 138. Accordingly, first source/drain structure 136 and second source/drain structure 138 can be directly connected by wide contact 152. Additional conductive features and complicated manufacturing and aligning processes are not required.
In addition, the formation of wide contact 152 enables to save the space for forming additional conductive features. Therefore, the size of first source/drain structure 136 and second source/drain structure 138 can be relatively small. In some embodiments, a shortest distance D₁between the sidewall of first gate structure 122 and the sidewall of isolation structure 112 is smaller than 150 nm. In some embodiments, a shortest distance D₁between the sidewall of first gate structure 122 and the sidewall of isolation structure 112 is in a range from about 100 nm to about 150 nm. When the distance between first gate structure 122 (or second gate structure 124) and isolation structure 112 is reduced, the space form forming first light sensing region 118 (or second light sensing region 120) can be increased. Therefore, the performance of image sensor structure 100 a can be improved. In some embodiments, the width of first light sensing region 118 (or second light sensing region 120) is in a range from about 0.6 μm to about 0.95 μm.
Similarly, a third region 113 and a fourth region 115 are also separated by isolation structure 112, and a third light sensing region 117 is formed in third region 113 and a fourth light sensing region 119 is formed in fourth region 115 in accordance with some embodiments. In addition, a third gate structure 121 is formed over third region 113, and a third source/drain structure 135 is formed adjacent to third gate structure 121. A fourth gate structure 123 is formed over fourth region 115, and a fourth source/drain structure 137 is formed adjacent to fourth gate structure 123. In addition, a third contact 147 is formed over third gate structure 121, and a fourth contact 149 is formed over fourth gate structure 123. Similar to those described previously, wide contact 152 is formed over isolation structure 112 and further extends over a portion of third source/drain structure 135 and a portion of fourth source/drain structure 137. Accordingly, first source/drain structure 136, second source/drain structure 138, third source/drain structure 135, and fourth source/drain structure 137 are all directly connected by wide contact 152 in accordance with some embodiments.
FIG. 3 is a cross-sectional representation of image sensor structure 100 a illustrated along line B-B′ shown in FIG. 1 in accordance with some embodiments. As shown in FIG. 3, third light sensing region 117 and second light sensing region 120 are formed in thinned substrate 102′ and are separated by isolation structure 112. In addition, second gate structure 124, which includes gate dielectric layer 130 and gate electrode layer 132, and third gate structure 121, which includes a gate dielectric layer 129 and a gate electrode layer 131, are formed on front side 104 of thinned substrate 102′.
As described previously, antireflective layer 164 is formed over back side 106′ of thinned substrate 102′ to cover exposed third light sensing region 117 and second light sensing region 120, and passivation layer 166, color filter layer 168, and microlens layer 170 are formed over antireflective layer 164, as shown in FIG. 3 in accordance with some embodiments. In addition, color filter layer 168 further includes a third color filter 173, and microlens layer further includes a third microlens 177.
As shown in FIG. 3, although wide contact 152 formed over isolation structure 112 has a relatively great width, the contacts formed at other portions of image sensor structure 100 a may still remain their original widths. Therefore, the process described above may be applied to present manufacturing processes without using complicated additional processes or altering too many original processes.
FIG. 4A is a pixel layout of an image sensor structure 100 b in accordance with some embodiments. FIG. 4B is a cross-sectional representation of image sensor structure 100 b illustrated along line C-C′ shown in FIG. 4A in accordance with some embodiments. Image sensor structure 100 b is similar to image sensor structure 100 a described previously, except hard mask structures are formed over the gate structures, so that a wide contact can be self-aligned to the source/drain structures. Some processes and materials used to form image sensor structure 100 b may be similar to, or the same as, those used to form image sensor structure 100 a described previously and are not repeated herein.
Similar to image sensor structure 100 a, a thinned substrate 102 b′ is separated into a first region 114 b, a second region 116 b, a third region 113 b, and a fourth region 115 b by isolation structures 112 b. A first light sensing region 118 b, a second light sensing region 120 b, a third light sensing region 117 b, and a fourth light sensing region 119 b are formed in first region 114 b, second region 116 b, third region 113 b, and fourth region 115 b respectively. In some embodiments, isolation structure 112 b includes liners 110 b and an isolation material 111 b formed between liners 110 b.
In addition, a first gate structure 122 b, a second gate structure 124 b, a third gate structure (not shown), and a fourth gate structure (not shown) are formed over first region 114 b, second region 116 b, third region 113 b, and fourth region 115 b respectively. As shown in FIG. 4B, first gate structure 122 b includes a first gate dielectric layer 126 b and a first gate electrode layer 128 b formed over first gate dielectric layer 126 b in accordance with some embodiments. In addition, a first hard mask structure 222 is formed over first gate structure 122 b to protect first gate structure 122 b. Similarly, second gate structure 124 b includes a second gate dielectric layer 130 b and a second gate electrode layer 132 b formed over second gate dielectric layer 130 b in accordance with some embodiments. In addition, a second hard mask structure 224 is formed over second gate structure 124 b to protect second gate structure 124 b. Spacers 134 b are formed on the sidewalls of first gate structure 122 b and second gate structure 124 b.
It should be noted that, although not shown in the figures, the third gate structure and the fourth gate structure may also include the similar structures as first gate structure 122 b and second gate structure 124 b do. That is, a third hard mask structure 221 and a fourth hard mask structure 223 are formed over the third gate structure and the fourth gate structure respectively, as shown in FIG. 4A in accordance with some embodiments.
Next, a first source/drain structure 136 b, a second source/drain structure 138 b, a third source/drain structure 135 b, and a fourth source/drain structure 137 b are formed adjacent to first gate structure 122 b, second gate structure 124 b, the third gate structure, and the fourth gate structure respectively. Afterwards, an interlayer dielectric layer 140 b is formed over a front side 104 b of thinned substrate 102 b′ in accordance with some embodiments.
A first contact trench is formed over first gate structure 122 b to expose the top surface of first gate structure 122 b (e.g. the top surface of first gate electrode layer 128 b). That is, the first contact trench is formed through first hard mask structure 222. In addition, a second contact trench is formed over second gate structure 124 b to expose the top surface of second gate structure 124 b (e.g. the top surface of second gate electrode layer 132 b). That is, the second contact trench is formed through second hard mask structure 224. A third contact trench and a fourth contact trench may also be formed over the third gate structure and the fourth gate structure.
Furthermore, a wide contact trench is formed to expose isolation structure 112 and portions of first source/drain structure 136 b, second source/drain structure 138 b, third source/drain structure 135 b, and fourth source/drain structure 137 b. In addition, the wide contact trench may also be formed over portions of first gate structure 122 b, second gate structure 124 b, the third gate structure, and the fourth gate structure. However, as described above, first hard mask structure 222, second hard mask structure 224, third hard mask structure 221, and fourth hard mask structure 223 are formed, so that first gate structure 122 b, second gate structure 124 b, the third gate structure, and the fourth gate structure will not be exposed by the wide contact trench. Accordingly, the wide contact trench can be self-aligned to first source/drain structure 136 b, second source/drain structure 138 b, third source/drain structure 135 b, and fourth source/drain structure 137 b, and no complicated aligning process is required.
Next, a first contact 148 b, a second contact 150 b, a third contact 149 b, a fourth contact 149 b, and a wide contact 152 b are formed, as shown in FIG. 4A in accordance with some embodiments. As shown in FIG. 4A, wide contact 152 b is formed over first source/drain structure 136 b, second source/drain structure 138 b, third source/drain structure 135 b, and fourth source/drain structure 137 b, so that first source/drain structure 136 b, second source/drain structure 138 b, third source/drain structure 135 b, and fourth source/drain structure 137 b can be all electrically connect through wide contact 152 b. That is, additional conductive features to connect these source/drain structures are not required.
In addition, since first hard mask structure 222, second hard mask structure 224, third hard mask structure 221, and fourth hard mask structure 223 are formed, wide contact 152 b can be formed in a self-aligned etching process. Therefore, the risk of misalignment can be prevented. In some embodiments, wide contact 152 b overlaps with isolation structure 112 b, a portion of first source/drain structure 118 b, and a portion of second source/drain structure 120 b and is formed on a portion of first hard mask structure 222.
In addition, since wide contact 152 b can be self-aligned to first source/drain structure 136 b, second source/drain structure 138 b, third source/drain structure 135 b, and fourth source/drain structure 137 b, the sizes of first source/drain structure 136 b, second source/drain structure 138 b, third source/drain structure 135 b, and fourth source/drain structure 137 b can be reduced. In some embodiments, a shortest distance D₂between the sidewall of first gate structure 122 b and the sidewall of isolation structure 112 b is smaller than 100-nm. In some embodiments, a shortest distance D₂between the sidewall of first gate structure 122 b and the sidewall of isolation structure 112 b is in a range from about 50 nm to about 100 nm. When the distance between first gate structure 122 b and isolation structure 112 b is reduced, the space form forming first light sensing region 118 b can be increased. Therefore, the performance of image sensor structure 100 b can be improved.
Furthermore, as shown in FIG. 4A, since wide contact 152 b is a self-aligned contact, the size of first source/drain structure 136 b, second source/drain structure 138 b, third source/drain structure 135 b, and fourth source/drain structure 137 b can be reduced. Accordingly, the area for forming first light sensing region 118 b, second light sensing region 120 b, third light sensing region 117 b, and fourth light sensing region 119 b can be increased.
Similar to image sensor structure 100 a, image sensor structure 100 b also includes an interconnect structure 154 b, a buffer layer 160 b, and a carrier substrate 162 b formed over interlayer dielectric layer 140 b in accordance with some embodiments. Interconnect structure 154 b includes conductive features 158 b formed in a dielectric layer 156 b. In addition, an antireflective layer 164 b, a passivation layer 166 b, a color filter layer 168 b, and a microlens layer 170 b are formed over a thinned back side 106 b′ of thinned substrate 102 b′ in accordance with some embodiments. In some embodiments, color filter layer 168 b includes a first color filter 172 b and a second color filter 174 b, and microlens layer 170 b includes a first microlens 176 b and a second microlens 178 b.
FIG. 5 is a cross-sectional representation of an image sensor structure 100 c in accordance with some embodiments. Image sensor structure 100 c is similar to image sensor structure 100 a described previously, except the light sensing regions extend below the source/drain structures. Some processes and materials used to form image sensor structure 100 c may be similar to, or the same as, those used to form image sensor structure 100 a described previously and are not repeated herein.
Similar to image sensor structure 100 a, a thinned substrate 102 c′ is separated into a first region 114 c and a second region 116 c, and a first light sensing region 118 c and a second light sensing region 120 c are formed in first region 114 c and second region 116 c respectively. In some embodiments, isolation structure 112 c includes liners 110 c and an isolation material 111 c formed between liners 110 c.
In addition, a first gate structure 122 c and a second gate structure 124 c are formed over first region 114 c and second region 116 c respectively. As shown in FIG. 5, first gate structure 122 c includes a first gate dielectric layer 126 c and a first gate electrode layer 128 c formed over first gate dielectric layer 126 c in accordance with some embodiments. Similarly, second gate structure 124 c includes a second gate dielectric layer 130 c and a second gate electrode layer 132 c formed over second gate dielectric layer 130 b in accordance with some embodiments. Spacers 134 c are formed on the sidewalls of first gate structure 122 c and second gate structure 124 c.
A first source/drain structure 136 c and a second source/drain structure 138 c are formed adjacent to first gate structure 122 c and second gate structure 124 c respectively, and an interlayer dielectric layer 140 c is formed over a front side 104 c of thinned substrate 102 c′ in accordance with some embodiments. Furthermore, a first contact 148 c, a second contact 150 c, and a wide contact 152 c are formed, as shown in FIG. 5 in accordance with some embodiments.
Similar to image sensor structure 100 a, image sensor structure 100 c also includes an interconnect structure 154 c, a buffer layer 160 c, and a carrier substrate 162 c formed over interlayer dielectric layer 140 c in accordance with some embodiments. Interconnect structure 154 c includes conductive features 158 c formed in a dielectric layer 156 c. In addition, an antireflective layer 164 c, a passivation layer 166 c, a color filter layer 168 c, and a microlens layer 170 c are formed over a thinned back side 106 c′ of thinned substrate 102 c′ in accordance with some embodiments. In some embodiments, color filter layer 168 c includes a first color filter 172 c and a second color filter 174 c, and microlens layer 170 c includes a first microlens 176 c and a second microlens 178 c.
As shown in FIG. 5, first light sensing region 118 c includes an extending portion 218, and extending portion 218 overlaps with a portion of first source/drain structure 136 c. However, extending portion 218 of first light sensing region 118 c has a thickness smaller than other portions of first light sensing region 118 c, so that the extending portion 218 will not be contact with first source/drain structure 136 c.
Similarly, second light sensing region 120 c includes an extending portion 220, and extending portion 220 overlaps with a portion of second source/drain structure 138 c. However, extending portion 220 of second light sensing region 120 c has a thickness smaller than other portions of second light sensing region 120 c, so that the extending portion 220 will not be contact with second light sensing region 120 c. The formation of extending portions 218 and 220 enable to increase the size of the light sensing regions, and therefore the quantum efficient of image sensor structure 100 c may be improved.
It should be noted that the numbers of the light sensing regions, color filters, and microlens shown in FIGS. 1 to 5 are merely examples and the scope of the disclosure is not intended to be limiting. In addition, the relative size of each feature in the figures may not be changed or simplified for better understanding the concept of the disclosure, but the scope of the disclosure is not intended to be limiting.
Generally, isolation structures are used to separate neighboring light sensing regions in image sensor structures. However, as the size of the image sensor structure shrink, isolation formed by implantation may not be able to prevent cross-talk and/or blooming. Therefore, isolation structure 112 (or isolation structures 112 b and 112 c) formed by forming isolation trench 108 and depositing isolating material, such as oxide, in isolation trench 108 is formed in accordance with some embodiments. Isolation structure 112 can be seen as a deep trench isolation structure, and the risk of cross-talk and/or blooming can be reduced.
However, when isolation structure 112, which is formed by isolation material, is formed to separate first light sensing region 118 and second light sensing region 120, sharing the pixels (e.g. source/drain structures) also become difficult. For example, complicated and additional conductive features may be required. However, the space for forming these conductive features may result in smaller sensing area and higher capacitance. Therefore, in some embodiments, wide contact 152 (or wide contacts 152 b and 152 c) is formed to connect first source/drain structure 136 and second source/drain structure 138 formed at the opposite sides of isolation structure 112. That is, additional and complicated conductive features are not required, and the size of first source/drain structure 136 and second source/drain structure 138 can be reduced. Accordingly, the capacitance of the floating diffusion node may be reduced.
Furthermore, since the size of first source/drain structure 136 and second source/drain structure 138 may be reduced, the size of first light sensing region 118 and second light sensing region 120 may be enlarged. Therefore, the quantum efficiency may be increased, and the performance of image sensor structure 100 a (or image sensor structures 100 b and 100 c) may be improved.
In addition, as shown in FIG. 4B, first hard mask layer 222 is formed over first gate structure 122 b in accordance with some embodiments. Therefore, wide contact 152 b may be self-aligned to first light sensing region 136 b and second light sensing region 138 b. Accordingly, the size of first light sensing region 136 b and second light sensing region 138 b may be further reduced and the size of first light sensing region 118 b and second light sensing region 120 b may be further enlarged.
Embodiments of image sensor structures and methods for manufacturing the same are provided. The image sensor structure includes an isolation structure formed in a substrate. A first light sensing region is formed in a first region of the substrate, and a second light sensing region is formed in a second region of the substrate. A first source/drain structure is formed in the first region adjacent to one side of the isolation structure, and a second source/drain structure is formed in the second region adjacent to the other side of the isolation structure. A contact is formed over a portion of the first source/drain structure, the isolation structure, and a portion of the second source/drain structure, so that the first source/drain structure and the second source/drain structure can be electrically connected by the contact.
In some embodiments, a method for manufacturing an image sensor structure is provided. The method for manufacturing the image sensor structure includes forming an isolation structure in a substrate to divide the substrate into a first region and a second region and forming a first light sensing region in the first region and a second light sensing region in the second region. The method for manufacturing the image sensor structure further includes forming a first gate structure over the first region and a second gate structure over the second region. In addition, the first gate structure and the second gate structure are positioned at a front side of the substrate. The method for manufacturing the image sensor structure further includes forming a first source/drain structure adjacent to the first gate structure and a second source/drain structure adjacent to the second gate structure and forming an interlayer dielectric layer over the front side of the substrate to cover the first gate structure and the second gate structure. The method for manufacturing the image sensor structure further includes forming a contact trench through the interlayer dielectric layer, such that a portion of the first source/drain structure, a portion of the second source/drain structure, and the isolation structure are exposed by the contact trench. The method for manufacturing the image sensor structure further includes forming a contact in the contact trench.
In some embodiments, a method for manufacturing an image sensor structure is provided. The method for manufacturing the image sensor structure includes forming an isolation structure in a substrate and forming a first source/drain structure and a second source/drain structure at opposite sides of the isolation structure. The method for manufacturing the image sensor structure further includes forming an interlayer dielectric layer over the substrate to cover the first source/drain structure and the second source/drain structure and forming a contact trench through the interlayer dielectric layer, such that a portion of the first source/drain structure, a portion of the second source/drain structure, and the isolation structure are exposed by the contact trench. The method for manufacturing the image sensor structure further includes forming a contact in the contact trench.
In some embodiments, a method for manufacturing an image sensor structure is provided. The method for manufacturing the image sensor structure includes forming an isolation trench in a substrate and forming an isolation structure in the isolation trench. The method for manufacturing the image sensor structure further includes forming a first source/drain structure and a second source/drain structure at opposite sides of the isolation structure and . . . . The method for manufacturing the image sensor structure further includes forming a contact over a portion of the first source/drain structure, a portion of the second source/drain structure, and the isolation structure.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

What is claimed is:

1. A method for manufacturing an image sensor structure, comprising:

forming an isolation structure in a substrate to divide the substrate into a first region and a second region;

forming a first light sensing region in the first region and a second light sensing region in the second region;

forming a first gate structure over the first region and a second gate structure over the second region, wherein the first gate structure and the second gate structure are positioned at a front side of the substrate;

forming a first source/drain structure adjacent to the first gate structure and a second source/drain structure adjacent to the second gate structure;

forming an interlayer dielectric layer over the front side of the substrate to cover the first gate structure and the second gate structure;

forming a contact trench through the interlayer dielectric layer, such that a portion of the first source/drain structure, a portion of the second source/drain structure, and the isolation structure are exposed by the contact trench; and

forming a contact in the contact trench.

2. The method for manufacturing an image sensor structure as claimed in claim 1, wherein forming the isolation structure comprises:

forming an isolation trench in the substrate; and

depositing an isolation material in the isolation trench.

3. The method for manufacturing an image sensor structure as claimed in claim 2, wherein the isolation material comprises silicon nitride, silicon oxide, or polysilicon.

4. The method for manufacturing an image sensor structure as claimed in claim 1, further comprising:

forming a first hard mask structure over the first gate structure,

wherein a portion of the first hard mask structure is exposed by the contact trench.

5. The method for manufacturing an image sensor structure as claimed in claim 4, wherein a portion of the contact is overlapped with a portion of the first gate structure and is separated from the first gate structure by the first hard mask structure.

6. The method for manufacturing an image sensor structure as claimed in claim 1, further comprising:

forming an interconnect structure over the interlayer dielectric layer; and

forming a color filter layer over a back side of the substrate.

7. The method for manufacturing an image sensor structure as claimed in claim 1, further comprising:

polishing the substrate from its back side until the first light sensing region and the second light sensing region are exposed.

8. A method for manufacturing an image sensor structure, comprising:

forming an isolation structure in a substrate;

forming a first source/drain structure and a second source/drain structure at opposite sides of the isolation structure;

forming an interlayer dielectric layer over the substrate to cover the first source/drain structure and the second source/drain structure;

forming a contact in the contact trench.

9. The method for manufacturing an image sensor structure as claimed in claim 8, wherein the isolation structure comprises silicon nitride, silicon oxide, or polysilicon.

10. The method for manufacturing an image sensor structure as claimed in claim 8, further comprising:

forming a first light sensing region adjacent to the first source/drain structure and a second light sensing region adjacent to the second source/drain structure.

11. The method for manufacturing an image sensor structure as claimed in claim 8, further comprising:

forming a first gate structure adjacent to the first source/drain structure and a second gate structure adjacent to the second source/drain structure.

12. The method for manufacturing an image sensor structure as claimed in claim 11, wherein a portion of the contact overlaps with a portion of the first gate structure.

13. The method for manufacturing an image sensor structure as claimed in claim 12, wherein the contact and the first gate structure are separated by a hard mask structure.

14. The method for manufacturing an image sensor structure as claimed in claim 8, further comprising:

forming an interconnect structure over the interlayer dielectric layer; and

forming a color filter layer over a back side of the substrate.

15. A method for manufacturing an image sensor structure, comprising:

forming an isolation trench in a substrate;

forming an isolation structure in the isolation trench;

forming a first source/drain structure and a second source/drain structure at opposite sides of the isolation structure; and

forming a contact over a portion of the first source/drain structure, a portion of the second source/drain structure, and the isolation structure.

16. The method for manufacturing an image sensor structure as claimed in claim 15, further comprising:

17. The method for manufacturing an image sensor structure as claimed in claim 16, further comprising:

18. The method for manufacturing an image sensor structure as claimed in claim 15, further comprising:

forming an interlayer dielectric layer over a front side of the substrate, wherein the contact passes through the interlayer dielectric layer;

forming an interconnect structure over the interlayer dielectric layer; and

forming a color filter layer over a back side of the substrate.

19. The method for manufacturing an image sensor structure as claimed in claim 16, further comprising:

20. The method for manufacturing an image sensor structure as claimed in claim 15, further comprising:

forming a color filter layer over a back side of the substrate,

wherein the contact is formed over a front side of the substrate.