US20170149328A1 - Negative charge pump with soft start - Google Patents
Negative charge pump with soft start Download PDFInfo
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- US20170149328A1 US20170149328A1 US14/955,116 US201514955116A US2017149328A1 US 20170149328 A1 US20170149328 A1 US 20170149328A1 US 201514955116 A US201514955116 A US 201514955116A US 2017149328 A1 US2017149328 A1 US 2017149328A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- H02M2003/071—
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/071—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate a negative voltage output from a positive voltage source
Definitions
- the present invention relates to a DC-DC converter circuit and, in particular, to a negative charge pump converter circuit with a soft start operation.
- FIG. 1 showing a circuit diagram of a conventional negative charge pump circuit 10 .
- the circuit 10 includes a first CMOS switching circuit 12 and a second CMOS switching circuit 14 .
- Each switching circuit 12 and 14 is formed by a series-connected pair of MOSFETs (drive transistors) including a p-channel transistor 16 and an n-channel transistor 18 .
- the first CMOS switching circuit 12 is connected between a positive voltage supply node Vpos and a ground reference node Vgnd (with the source of transistor 16 connected to the positive voltage supply node Vpos and the source of transistor 18 connected to the ground reference node Vgnd).
- the second CMOS switching circuit 14 is connected between the ground reference node Vgnd and a negative voltage output node Vneg (with the source of transistor 16 connected to the ground reference node Vgnd and the source of transistor 18 connected to the negative voltage output node Vneg).
- the transistors 16 and 18 have their source-drain paths connected to each other at the drain terminals of the transistors 16 , 18 to define a positive node 20 for the first CMOS switching circuit 12 and a negative node 22 for the second CMOS switching circuit 14 .
- a fly capacitor Cfly is connected between the positive and negative nodes 20 and 22 , respectively.
- An output capacitor Cout is connected between the negative voltage output node Vneg and the ground reference node Vgnd.
- the gate terminals of the drive transistors within the first and second CMOS switching circuits 12 and 14 are each driven by a driver circuit 24 in response to a clock signal (clk 1 -clk 4 ) generated by a non-overlap clock generator circuit 26 .
- FIG. 2 illustrates the general shape for the waveform of the clock signals clk 1 -clk 4 .
- the p-channel transistors 16 in the first and second CMOS switching circuits 12 and 14 are each turned on and current flows from the positive voltage supply node Vpos to the ground reference node Vgnd to charge the capacitor Cfly.
- the n-channel transistors 18 in the first and second CMOS switching circuits 12 and 14 are each turned on connecting the more positive plate of the charged capacitor Cfly to ground and the more negative plate of the charged capacitor Cfly to the negative voltage output node Vneg.
- a negative voltage is eventually generated at the negative voltage output node Vneg having an absolute value equal to the voltage at the positive voltage supply node Vpos.
- the control of the charge pump circuit 10 is preferably open loop for reasons of simplicity and cost reduction. Thus, soft start control over charge pump circuit operation is typically not used.
- the duty cycle of the clock signals clk 1 -clk 4 is fixed. There is a need in the art, however, for soft start control of an open loop-type charge pump circuit.
- a circuit comprises: a charge pump circuit coupled between a positive supply node and a ground node, said charge pump circuit operating in response to a plurality of clock signals output from a clock generator to produce a negative voltage at a negative voltage output node; and a soft-start circuit for said charge pump circuit comprising a comparison circuit configured to compare an intermediate voltage between a supply voltage and the negative voltage to a falling ramp voltage during a start-up of the charge pump circuit and selectively enable to clock generator to generate said plurality of clock signals in response to said comparison.
- a circuit comprises: a charge pump circuit coupled between a positive supply node and a ground node, said charge pump circuit including a clock generator configured to generate a plurality of clock signals, the charge pump circuit responding to said plurality of clock signal to produce a negative voltage at a negative voltage output node; and a soft-start circuit for said charge pump circuit operating to cause pulse skipping of the plurality of clock signals during soft-start, said pulse skipping occurring each time an intermediate voltage that is sensed by the soft-start circuit between a supply voltage and the negative voltage crosses over a ramp voltage.
- a circuit comprises a charge pump circuit having a negative voltage output node and a soft-start circuit for said charge pump circuit.
- the charge pump circuit includes: a first CMOS switching circuit coupled between a positive supply node and a ground node and configured to receive first and second clock signals and having a first output; a second CMOS switching circuit coupled between the ground node and the negative voltage output node and configured to receive third and fourth clock signals and having a second output; wherein the first and second outputs are configured for connecting to opposite plates of a fly capacitor; and a clock generator circuit configured to generate the first through fourth clock signals.
- the soft-start circuit comprises: a resistive voltage divider having at least a first tap node, the resistive voltage divider coupled between a supply voltage node and the negative voltage output node; a ramp signal generator configured to generate a ramp signal; and a first comparator configured to compare a voltage at the first tap node to a voltage of the ramp signal to generate a first enable signal applied to control enabling of the clock generator circuit to generate the first through fourth clock signals.
- FIG. 1 is a circuit diagram for a conventional negative charge pump circuit
- FIG. 2 illustrates the waveform for clock signals driving operation of the circuit of FIG. 1 ;
- FIG. 3 is a circuit diagram for a negative charge pump circuit with soft-start operation
- FIG. 4 illustrates the waveforms for soft-start operation of the circuit of FIG. 3 ;
- FIG. 5 illustrates pulse-skipping
- the circuit 100 includes a first CMOS switching circuit 112 and a second CMOS switching circuit 114 .
- Each switching circuit 112 and 114 is formed by a series-connected pair of MOSFETs (drive transistors) including a p-channel transistor 116 and an n-channel transistor 118 .
- the first CMOS switching circuit 112 is connected between a positive voltage supply node Vpos and a ground reference node Vgnd (with the source of transistor 116 connected to the positive voltage supply node Vpos and the source of transistor 118 connected to the ground reference node Vgnd).
- the second CMOS switching circuit 114 is connected between the ground reference node Vgnd and a negative voltage output node Vneg (with the source of transistor 116 connected to the ground reference node Vgnd and the source of transistor 118 connected to the negative voltage output node Vneg).
- the transistors 116 and 118 have their source-drain paths connected to each other at the drain terminals of the transistors 116 , 118 to define a positive node 120 for the first CMOS switching circuit 112 and a negative node 122 for the second CMOS switching circuit 114 .
- a fly capacitor Cfly is connected between the positive and negative nodes 120 and 122 , respectively.
- An output capacitor Cout is connected between the negative voltage output node Vneg and the ground reference node Vgnd.
- the gate terminals of the transistors within the first and second CMOS switching circuits 112 and 114 are each driven by a driver circuit 124 in response to a clock signal (clk 1 -clk 4 ) generated by a non-overlap clock generator circuit 126 .
- the first CMOS switching circuit 112 includes a further n-channel drive transistor 128 connected in parallel with the n-channel transistor 118 so as to have common source and drain terminals but separate gate terminals.
- the transistor 128 is smaller in size than the transistor 118 (i.e., its width and/or length dimensions are smaller; for example, the ratio of transistor 118 to transistor 128 may be 10:1 in one example case, the exact ratio being determined by the in-rush current limit of capacitor Cfly.).
- the gate terminal of transistor 128 is also driven by a driver circuit 124 in response to the same clock signal clk 2 as the transistor 118 . However, the clock signal clk 2 is gated by a logic AND gate 134 before application to the gate terminal of transistor 118 .
- a first input of the AND gate 134 receives the clock signal clk 2 and a second input of the AND gate 134 receives a control signal SS_OK indicating that a soft-start period of the circuit 100 is completed.
- the AND gate 134 blocks the clock signal clk 2 from being applied to the gate terminal of transistor 118 , but the smaller parallel-connected transistor 128 is driven by the clock signal clk 2 to permit charge pump operation.
- the control signal SS_OK is asserted, the AND gate 134 passes the clock signal clk 2 , and the gate terminal of transistor 118 is then also driven by the clock signal clk 2 .
- the control signal SS_OK accordingly comprises an enable signal which blocks the clock signal clk 2 from being applied to the gate of the n-channel transistor 118 during the soft-start period, and enables the n-channel transistor 118 to receive the clock signal clk 2 through the AND gate 134 when the soft-start period ends.
- the charging current of the capacitor Cfly is limited only by the on-resistance of transistor 116 and the charging current of the capacitor Cout is limited only by the on-resistance of transistor 118 .
- the capacitor Cout will be charged very quickly because the on-resistance of transistors 116 and 118 is small, this results in a large in-rush current that could adversely affect reliability of the circuit. Soft-start is critical to proper operation of this circuit.
- transistor 128 does not have to be associated with the first CMOS switching circuit 112 .
- the transistor could instead be in the second CMOS switching circuit 114 .
- Transistor 128 is chosen for use in circuit 112 because the driver circuit is more easily implemented (ground based), but this is not a requirement.
- Transistor 128 could be placed parallel with the lower side transistor 118 of circuit 114 .
- transistor 128 could instead be a p-channel device coupled in parallel with transistor 116 in either circuit 112 or circuit 114 .
- the circuit 100 further includes a resistive divider circuit 140 comprising a plurality of resistors R 1 -R 3 connected in series between a voltage supply node (Vdd) and the negative voltage output node Vneg.
- the voltage Vdd can be a low voltage analog supply voltage or a reference voltage.
- the resistive divider circuit 140 includes a first tap node 142 between resistors R 1 and R 2 and a second tap node 144 between resistors R 2 and R 3 .
- the resistance values of the resistors R 1 -R 3 are selected such that the voltage at the second tap node 144 is greater than the ground voltage at the ground reference node Vgnd for all possible values of voltage at Vdd and Vneg, and that the voltage at the first tap node 142 is slightly greater (for example, by only tens of mV) than the voltage at the second tap node 144 .
- the control signal SS_OK is generated by a first comparator circuit 150 .
- the non-inverting input of the comparator circuit 150 is connected to the second tap node 144 .
- the inverting input of the comparator circuit 150 is configured to receive a decreasing ramp voltage Vramp.
- the comparator circuit 150 functions to compare the decreasing ramp voltage to the voltage at the second tap node 144 . It will be noted that the supply voltage Vdd is fixed as Vneg changes (i.e., falls) but is higher than the ground voltage at all times. For the duration of the soft-start period, the ramp voltage will exceed the voltage at the second tap node 144 and the comparator circuit 150 will not assert the control signal SS_OK.
- the clock signal clk 2 is blocked by the AND gate 134 from being applied to the gate terminal of transistor 118 .
- Soft-start of the circuit 100 instead utilizes the smaller transistor 128 in the first CMOS switching circuit 112 .
- the soft-start period ends when the decreasing ramp voltage falls below (crosses over) the varying voltage at the second tap node 144 .
- the output of the comparator circuit 150 changes state and the control signal SS_OK is asserted.
- the clock signal clk 2 is then passed by the AND gate 134 and applied to the gate terminal of transistor 118 .
- FIG. 2 illustrates the waveform for the clock signals clk 1 -clk 4 generated by the non-overlap clock generator circuits 26 and 126 .
- the clock signals clk 1 -clk 4 are output from the non-overlap clock generator circuits 26 and 126 when an enable signal (En) is asserted.
- the enable signal En is generated by a second comparator circuit 160 .
- the non-inverting input of the comparator circuit 160 is connected to the first tap node 142 .
- the inverting input of the comparator circuit 160 is configured to receive the decreasing ramp voltage Vramp.
- the comparator circuit 160 functions to compare the decreasing ramp voltage to the voltage at the first tap node 142 , it being understood that during the soft-start period the voltage at the first tap node 142 will vary with the supply voltage Vdd stable and as the negative output voltage at the negative voltage output node Vneg is pumped lower.
- the comparator circuit 160 asserts the enable signal En which enables the clock output by the non-overlap clock generator circuit 126 .
- the clock signals clk 1 -clk 4 are applied to the first and second CMOS switching circuits 112 and 114 .
- the comparator circuit 160 deasserts the enable signal En which disables the clock output by the non-overlap clock generator circuit 126 .
- the clock signals clk 1 -clk 4 each have a fixed logic state (for example, configured to turn off the transistors 116 , 118 and 128 ). The disabling of the non-overlap clock generator circuit 126 effectuates a pulse-skipping mode of operation with respect to the clock signals clk 1 -clk 4 and the charge pump operation (see, generally, FIG. 5 ).
- the ramp voltage Vramp signal is output by a ramp signal generator circuit 148 .
- the ramp signal generator circuit 148 comprises a digital-to-analog converter (DAC) that receives a multi-bit digital signal D defining a decreasing voltage ramp and converts that digital signal to an analog ramp referenced to a reference voltage Vref (for example, generated using band-gap circuits as known in the art).
- Vref reference voltage
- the ramp signal starts at the reference voltage Vref and progressively decreases over time until the ground voltage is reached.
- the ramp signal is enabled when the charge pump is enabled.
- FIG. 4 generally illustrates the timing of the soft-start operation for the circuit 100 of FIG. 3 .
- the soft-start operation proceeds as follows: as the supply voltage Vdd begins to rise at start-up, both the control signal SS_OK and the enable signal En are not asserted.
- the non-overlap clock generator circuit 126 is accordingly disabled, and the AND gate 134 outputs a logic low signal which ensures that transistor 128 is turned off.
- the supply voltage Vdd has already risen to a stable voltage level.
- the resistances for resistors R 1 , R 2 and R 3 are chosen so that the voltage at the first tap node 142 equals Vref when Vneg is zero. So, when Vramp begins to fall due to operation of the circuit, the comparator 160 changes state and the enable signal En is asserted (reference 202 ).
- the non-overlap clock generator circuit 126 responds to the asserted enable signal En by generating one or more cycles 42 of the clock signals clk 1 -clk 4 (as shown at reference 46 in FIG. 5 ).
- the comparator 150 does not change state because the voltage level at the second tap node 144 remains below the voltage of the ramp signal. So, the clock signal clk 2 is blocked by AND gate 134 and applied only to the transistor 128 in the first CMOS switching circuit 112 .
- the transistor 116 of the first CMOS switching circuit 112 and the transistors 116 and 118 of the second CMOS switching circuit 114 receive the clock signals clk 1 , clk 3 and clk 4 , respectively.
- the applied clock signals cause the charge pump to operate and pump the voltage at the negative voltage output node Vneg lower (reference 204 ).
- This pumping action shifts the voltages at the first and second tap nodes 142 and 144 lower and when the voltage at the first tap node is falls below voltage of the ramp signal, the comparator 160 changes state and disables the non-overlap clock generator circuit 126 (reference 206 ).
- the clock signals clk 1 -clk 4 are not supplied effectuating a form of pulse skipping as shown at reference 48 in FIG. 5 .
- the comparator 160 again changes state and the enable signal En is asserted (reference 208 ).
- the non-overlap clock generator circuit 126 responds to the asserted enable signal En by again generating one or more cycles 42 of the clock signals clk 1 -clk 4 (as shown at reference 50 in FIG. 5 ).
- the comparator 150 does not change state because the voltage level at the second tap node 144 remains below the voltage of the ramp signal. So, the clock signal clk 2 is blocked by AND gate 134 and applied only to the transistor 128 in the first CMOS switching circuit 112 .
- the transistor 116 of the first CMOS switching circuit 112 and the transistors 116 and 118 of the second CMOS switching circuit 114 receive the clock signals clk 1 , clk 3 and clk 4 , respectively.
- the applied clock signals cause the charge pump to operate and further pump the voltage at the negative voltage output node Vneg lower (reference 210 ).
- This pumping action again shifts the voltages at the first and second tap nodes 142 and 144 lower and when the voltage at the first tap node is pumped lower than the voltage of the ramp signal, the comparator 160 changes state and disables the non-overlap clock generator circuit 126 (reference 212 ).
- the clock signals clk 1 -clk 4 are not supplied effectuating a form of pulse skipping.
- the foregoing processes ( 202 / 204 / 206 and 208 / 210 / 212 ) are cyclically repeated. Each cycle is instigated when the voltage at the first tap node 142 exceeds the falling voltage of the ramp signal.
- the non-overlap clock generator circuit 126 is enabled for a short time duration 46 , 50 to perform charge pumping so as to pump the voltage at the negative voltage output node Vneg lower.
- the non-overlap clock generator circuit 126 is disabled to implement pulse skipping 48 .
- the falling of the ramp voltage causes the voltage at the first tap node 142 to shift and the cycle ends when the voltage at the first tap node 142 equals the falling voltage of the ramp signal.
- the voltage at the second tap node 144 will exceed the voltage of the ramp signal Vramp and the comparator 150 will assert the control signal SS_OK (reference 214 ). This indicates the end of the soft-start period.
- the voltage at the first tap node 142 will also exceed the voltage of the ramp signal Vramp and the comparator 160 will assert the enable signal En (reference 216 ).
- the AND gate 134 passes the clock signal clk 2 to the transistor 118 of the first CMOS switching circuit 112 . Conventional operation of the charge pump then occurs to complete pumping of the Vneg voltage to a negative voltage whose absolute magnitude substantially equals the voltage Vpos.
Abstract
Description
- This application claims priority from Chinese Application for Patent No. 201510818302.4 filed Nov. 20, 2015, the disclosure of which is incorporated by reference.
- The present invention relates to a DC-DC converter circuit and, in particular, to a negative charge pump converter circuit with a soft start operation.
- Reference is made to
FIG. 1 showing a circuit diagram of a conventional negativecharge pump circuit 10. Thecircuit 10 includes a firstCMOS switching circuit 12 and a secondCMOS switching circuit 14. Eachswitching circuit channel transistor 16 and an n-channel transistor 18. The firstCMOS switching circuit 12 is connected between a positive voltage supply node Vpos and a ground reference node Vgnd (with the source oftransistor 16 connected to the positive voltage supply node Vpos and the source oftransistor 18 connected to the ground reference node Vgnd). The secondCMOS switching circuit 14 is connected between the ground reference node Vgnd and a negative voltage output node Vneg (with the source oftransistor 16 connected to the ground reference node Vgnd and the source oftransistor 18 connected to the negative voltage output node Vneg). Thetransistors transistors positive node 20 for the firstCMOS switching circuit 12 and anegative node 22 for the secondCMOS switching circuit 14. A fly capacitor Cfly is connected between the positive andnegative nodes CMOS switching circuits driver circuit 24 in response to a clock signal (clk1-clk4) generated by a non-overlapclock generator circuit 26.FIG. 2 illustrates the general shape for the waveform of the clock signals clk1-clk4. During afirst phase 40 of eachcycle 42 of the waveform, the p-channel transistors 16 in the first and secondCMOS switching circuits second phase 44 ofcycle 42, the n-channel transistors 18 in the first and secondCMOS switching circuits - The control of the
charge pump circuit 10 is preferably open loop for reasons of simplicity and cost reduction. Thus, soft start control over charge pump circuit operation is typically not used. The duty cycle of the clock signals clk1-clk4 is fixed. There is a need in the art, however, for soft start control of an open loop-type charge pump circuit. - In an embodiment, a circuit comprises: a charge pump circuit coupled between a positive supply node and a ground node, said charge pump circuit operating in response to a plurality of clock signals output from a clock generator to produce a negative voltage at a negative voltage output node; and a soft-start circuit for said charge pump circuit comprising a comparison circuit configured to compare an intermediate voltage between a supply voltage and the negative voltage to a falling ramp voltage during a start-up of the charge pump circuit and selectively enable to clock generator to generate said plurality of clock signals in response to said comparison.
- In an embodiment, a circuit comprises: a charge pump circuit coupled between a positive supply node and a ground node, said charge pump circuit including a clock generator configured to generate a plurality of clock signals, the charge pump circuit responding to said plurality of clock signal to produce a negative voltage at a negative voltage output node; and a soft-start circuit for said charge pump circuit operating to cause pulse skipping of the plurality of clock signals during soft-start, said pulse skipping occurring each time an intermediate voltage that is sensed by the soft-start circuit between a supply voltage and the negative voltage crosses over a ramp voltage.
- In an embodiment, a circuit comprises a charge pump circuit having a negative voltage output node and a soft-start circuit for said charge pump circuit. The charge pump circuit includes: a first CMOS switching circuit coupled between a positive supply node and a ground node and configured to receive first and second clock signals and having a first output; a second CMOS switching circuit coupled between the ground node and the negative voltage output node and configured to receive third and fourth clock signals and having a second output; wherein the first and second outputs are configured for connecting to opposite plates of a fly capacitor; and a clock generator circuit configured to generate the first through fourth clock signals. The soft-start circuit comprises: a resistive voltage divider having at least a first tap node, the resistive voltage divider coupled between a supply voltage node and the negative voltage output node; a ramp signal generator configured to generate a ramp signal; and a first comparator configured to compare a voltage at the first tap node to a voltage of the ramp signal to generate a first enable signal applied to control enabling of the clock generator circuit to generate the first through fourth clock signals.
- For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:
-
FIG. 1 is a circuit diagram for a conventional negative charge pump circuit; -
FIG. 2 illustrates the waveform for clock signals driving operation of the circuit ofFIG. 1 ; -
FIG. 3 is a circuit diagram for a negative charge pump circuit with soft-start operation; -
FIG. 4 illustrates the waveforms for soft-start operation of the circuit ofFIG. 3 ; and -
FIG. 5 illustrates pulse-skipping. - Reference is now made to
FIG. 3 showing a circuit diagram for a negativecharge pump circuit 100 with soft start control. Thecircuit 100 includes a firstCMOS switching circuit 112 and a secondCMOS switching circuit 114. Eachswitching circuit channel transistor 116 and an n-channel transistor 118. The firstCMOS switching circuit 112 is connected between a positive voltage supply node Vpos and a ground reference node Vgnd (with the source oftransistor 116 connected to the positive voltage supply node Vpos and the source oftransistor 118 connected to the ground reference node Vgnd). The secondCMOS switching circuit 114 is connected between the ground reference node Vgnd and a negative voltage output node Vneg (with the source oftransistor 116 connected to the ground reference node Vgnd and the source oftransistor 118 connected to the negative voltage output node Vneg). Thetransistors transistors positive node 120 for the firstCMOS switching circuit 112 and anegative node 122 for the secondCMOS switching circuit 114. A fly capacitor Cfly is connected between the positive andnegative nodes CMOS switching circuits driver circuit 124 in response to a clock signal (clk1-clk4) generated by a non-overlapclock generator circuit 126. - The first
CMOS switching circuit 112 includes a further n-channel drive transistor 128 connected in parallel with the n-channel transistor 118 so as to have common source and drain terminals but separate gate terminals. Thetransistor 128 is smaller in size than the transistor 118 (i.e., its width and/or length dimensions are smaller; for example, the ratio oftransistor 118 totransistor 128 may be 10:1 in one example case, the exact ratio being determined by the in-rush current limit of capacitor Cfly.). The gate terminal oftransistor 128 is also driven by adriver circuit 124 in response to the same clock signal clk2 as thetransistor 118. However, the clock signal clk2 is gated by a logic ANDgate 134 before application to the gate terminal oftransistor 118. A first input of theAND gate 134 receives the clock signal clk2 and a second input of theAND gate 134 receives a control signal SS_OK indicating that a soft-start period of thecircuit 100 is completed. Thus, during soft-start theAND gate 134 blocks the clock signal clk2 from being applied to the gate terminal oftransistor 118, but the smaller parallel-connectedtransistor 128 is driven by the clock signal clk2 to permit charge pump operation. When the soft-start period is completed, the control signal SS_OK is asserted, theAND gate 134 passes the clock signal clk2, and the gate terminal oftransistor 118 is then also driven by the clock signal clk2. The control signal SS_OK accordingly comprises an enable signal which blocks the clock signal clk2 from being applied to the gate of the n-channel transistor 118 during the soft-start period, and enables the n-channel transistor 118 to receive the clock signal clk2 through theAND gate 134 when the soft-start period ends. - When the charge pump is enabled, the charging current of the capacitor Cfly is limited only by the on-resistance of
transistor 116 and the charging current of the capacitor Cout is limited only by the on-resistance oftransistor 118. The capacitor Cout will be charged very quickly because the on-resistance oftransistors - With the
smaller transistor 128 enabled during soft-start (and thetransistor 118 disabled), charge current for the capacitor Cout is now limited by the resistance oftransistor 128 which can be set much higher (for example, 10:1) and in-rush current is reduced. - It will be noted that
transistor 128 does not have to be associated with the firstCMOS switching circuit 112. The transistor could instead be in the secondCMOS switching circuit 114.Transistor 128 is chosen for use incircuit 112 because the driver circuit is more easily implemented (ground based), but this is not a requirement.Transistor 128 could be placed parallel with thelower side transistor 118 ofcircuit 114. It will further be noted thattransistor 128 could instead be a p-channel device coupled in parallel withtransistor 116 in eithercircuit 112 orcircuit 114. - The
circuit 100 further includes aresistive divider circuit 140 comprising a plurality of resistors R1-R3 connected in series between a voltage supply node (Vdd) and the negative voltage output node Vneg. In an example implementation, the voltage Vdd can be a low voltage analog supply voltage or a reference voltage. Theresistive divider circuit 140 includes afirst tap node 142 between resistors R1 and R2 and asecond tap node 144 between resistors R2 and R3. The resistance values of the resistors R1-R3 are selected such that the voltage at thesecond tap node 144 is greater than the ground voltage at the ground reference node Vgnd for all possible values of voltage at Vdd and Vneg, and that the voltage at thefirst tap node 142 is slightly greater (for example, by only tens of mV) than the voltage at thesecond tap node 144. - The control signal SS_OK is generated by a
first comparator circuit 150. The non-inverting input of thecomparator circuit 150 is connected to thesecond tap node 144. The inverting input of thecomparator circuit 150 is configured to receive a decreasing ramp voltage Vramp. Thecomparator circuit 150 functions to compare the decreasing ramp voltage to the voltage at thesecond tap node 144. It will be noted that the supply voltage Vdd is fixed as Vneg changes (i.e., falls) but is higher than the ground voltage at all times. For the duration of the soft-start period, the ramp voltage will exceed the voltage at thesecond tap node 144 and thecomparator circuit 150 will not assert the control signal SS_OK. As a result, the clock signal clk2 is blocked by the ANDgate 134 from being applied to the gate terminal oftransistor 118. Soft-start of thecircuit 100 instead utilizes thesmaller transistor 128 in the firstCMOS switching circuit 112. The soft-start period ends when the decreasing ramp voltage falls below (crosses over) the varying voltage at thesecond tap node 144. The output of thecomparator circuit 150 changes state and the control signal SS_OK is asserted. The clock signal clk2 is then passed by the ANDgate 134 and applied to the gate terminal oftransistor 118. - Reference is made to
FIG. 2 which illustrates the waveform for the clock signals clk1-clk4 generated by the non-overlapclock generator circuits clock generator circuits second comparator circuit 160. The non-inverting input of thecomparator circuit 160 is connected to thefirst tap node 142. The inverting input of thecomparator circuit 160 is configured to receive the decreasing ramp voltage Vramp. Thecomparator circuit 160 functions to compare the decreasing ramp voltage to the voltage at thefirst tap node 142, it being understood that during the soft-start period the voltage at thefirst tap node 142 will vary with the supply voltage Vdd stable and as the negative output voltage at the negative voltage output node Vneg is pumped lower. When the varying voltage at thefirst tap node 142 rises above (crosses over) the decreasing ramp voltage, thecomparator circuit 160 asserts the enable signal En which enables the clock output by the non-overlapclock generator circuit 126. As a result, the clock signals clk1-clk4 are applied to the first and secondCMOS switching circuits first tap node 142 falls below (crosses over) the decreasing ramp voltage, thecomparator circuit 160 deasserts the enable signal En which disables the clock output by the non-overlapclock generator circuit 126. In an embodiment, when the non-overlapclock generator circuit 126 is disabled, the clock signals clk1-clk4 each have a fixed logic state (for example, configured to turn off thetransistors clock generator circuit 126 effectuates a pulse-skipping mode of operation with respect to the clock signals clk1-clk4 and the charge pump operation (see, generally,FIG. 5 ). - The ramp voltage Vramp signal is output by a ramp
signal generator circuit 148. In an embodiment, the rampsignal generator circuit 148 comprises a digital-to-analog converter (DAC) that receives a multi-bit digital signal D defining a decreasing voltage ramp and converts that digital signal to an analog ramp referenced to a reference voltage Vref (for example, generated using band-gap circuits as known in the art). Thus, the ramp signal starts at the reference voltage Vref and progressively decreases over time until the ground voltage is reached. The ramp signal is enabled when the charge pump is enabled. - Reference is now additionally made to
FIG. 4 which generally illustrates the timing of the soft-start operation for thecircuit 100 ofFIG. 3 . - The soft-start operation proceeds as follows: as the supply voltage Vdd begins to rise at start-up, both the control signal SS_OK and the enable signal En are not asserted. The non-overlap
clock generator circuit 126 is accordingly disabled, and the ANDgate 134 outputs a logic low signal which ensures thattransistor 128 is turned off. Within a short delay time (reference 200), the supply voltage Vdd has already risen to a stable voltage level. The resistances for resistors R1, R2 and R3 are chosen so that the voltage at thefirst tap node 142 equals Vref when Vneg is zero. So, when Vramp begins to fall due to operation of the circuit, thecomparator 160 changes state and the enable signal En is asserted (reference 202). The non-overlapclock generator circuit 126 responds to the asserted enable signal En by generating one ormore cycles 42 of the clock signals clk1-clk4 (as shown atreference 46 inFIG. 5 ). Thecomparator 150 does not change state because the voltage level at thesecond tap node 144 remains below the voltage of the ramp signal. So, the clock signal clk2 is blocked by ANDgate 134 and applied only to thetransistor 128 in the firstCMOS switching circuit 112. Thetransistor 116 of the firstCMOS switching circuit 112 and thetransistors CMOS switching circuit 114 receive the clock signals clk1, clk3 and clk4, respectively. The applied clock signals cause the charge pump to operate and pump the voltage at the negative voltage output node Vneg lower (reference 204). This pumping action shifts the voltages at the first andsecond tap nodes comparator 160 changes state and disables the non-overlap clock generator circuit 126 (reference 206). For a period of time, the clock signals clk1-clk4 are not supplied effectuating a form of pulse skipping as shown atreference 48 inFIG. 5 . - Eventually, the voltage at the
first tap node 142 will exceed the voltage of the ramp signal. Thecomparator 160 again changes state and the enable signal En is asserted (reference 208). The non-overlapclock generator circuit 126 responds to the asserted enable signal En by again generating one ormore cycles 42 of the clock signals clk1-clk4 (as shown atreference 50 inFIG. 5 ). Thecomparator 150 does not change state because the voltage level at thesecond tap node 144 remains below the voltage of the ramp signal. So, the clock signal clk2 is blocked by ANDgate 134 and applied only to thetransistor 128 in the firstCMOS switching circuit 112. Thetransistor 116 of the firstCMOS switching circuit 112 and thetransistors CMOS switching circuit 114 receive the clock signals clk1, clk3 and clk4, respectively. The applied clock signals cause the charge pump to operate and further pump the voltage at the negative voltage output node Vneg lower (reference 210). This pumping action again shifts the voltages at the first andsecond tap nodes comparator 160 changes state and disables the non-overlap clock generator circuit 126 (reference 212). For a period of time, the clock signals clk1-clk4 are not supplied effectuating a form of pulse skipping. - The foregoing processes (202/204/206 and 208/210/212) are cyclically repeated. Each cycle is instigated when the voltage at the
first tap node 142 exceeds the falling voltage of the ramp signal. The non-overlapclock generator circuit 126 is enabled for ashort time duration first tap node 142 to fall below the voltage of the ramp signal, the non-overlapclock generator circuit 126 is disabled to implement pulse skipping 48. The falling of the ramp voltage causes the voltage at thefirst tap node 142 to shift and the cycle ends when the voltage at thefirst tap node 142 equals the falling voltage of the ramp signal. - Eventually, as a result of the cyclic pumping of the Vneg voltage lower, the stabilized supply voltage Vdd and the falling of the voltage of the ramp signal Vramp, the voltage at the
second tap node 144 will exceed the voltage of the ramp signal Vramp and thecomparator 150 will assert the control signal SS_OK (reference 214). This indicates the end of the soft-start period. The voltage at thefirst tap node 142 will also exceed the voltage of the ramp signal Vramp and thecomparator 160 will assert the enable signal En (reference 216). At this point, the ANDgate 134 passes the clock signal clk2 to thetransistor 118 of the firstCMOS switching circuit 112. Conventional operation of the charge pump then occurs to complete pumping of the Vneg voltage to a negative voltage whose absolute magnitude substantially equals the voltage Vpos. - The foregoing description has been provided by way of exemplary and non-limiting examples of a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.
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CN201510818302.4A CN106787685B (en) | 2015-11-20 | 2015-11-20 | Use the negative charge pump of soft start |
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CN114696609A (en) * | 2020-12-28 | 2022-07-01 | 圣邦微电子(北京)股份有限公司 | Charge pump circuit |
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US9653990B1 (en) | 2017-05-16 |
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