US20170032075A1 - System And Method For Discovering Unknown Problematic Patterns In Chip Design Layout For Semiconductor Manufacturing - Google Patents
System And Method For Discovering Unknown Problematic Patterns In Chip Design Layout For Semiconductor Manufacturing Download PDFInfo
- Publication number
- US20170032075A1 US20170032075A1 US14/810,428 US201514810428A US2017032075A1 US 20170032075 A1 US20170032075 A1 US 20170032075A1 US 201514810428 A US201514810428 A US 201514810428A US 2017032075 A1 US2017032075 A1 US 2017032075A1
- Authority
- US
- United States
- Prior art keywords
- circuit patterns
- problematic
- data
- statistical model
- chip design
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013461 design Methods 0.000 title claims abstract description 98
- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title abstract description 28
- 238000013179 statistical model Methods 0.000 claims abstract description 85
- 238000004088 simulation Methods 0.000 claims abstract description 29
- 238000000053 physical method Methods 0.000 claims abstract description 14
- 230000035945 sensitivity Effects 0.000 claims abstract description 4
- 230000007547 defect Effects 0.000 claims description 11
- 238000003860 storage Methods 0.000 claims description 4
- 238000012795 verification Methods 0.000 claims description 4
- 239000011159 matrix material Substances 0.000 claims description 2
- 238000002372 labelling Methods 0.000 claims 3
- 235000012431 wafers Nutrition 0.000 abstract description 19
- 238000012549 training Methods 0.000 description 13
- 238000010200 validation analysis Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 8
- 238000001459 lithography Methods 0.000 description 7
- 230000009897 systematic effect Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000013459 approach Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 239000000284 extract Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000012797 qualification Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000010978 in-process monitoring Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 238000012706 support-vector machine Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 238000007418 data mining Methods 0.000 description 1
- 238000003066 decision tree Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003064 k means clustering Methods 0.000 description 1
- 238000012417 linear regression Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000003954 pattern orientation Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Images
Classifications
-
- G06F17/5081—
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G06F17/5009—
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
Definitions
- the present invention relates generally to semiconductor device fabrication, and more specifically to a system and method for discovering unknown problematic circuit patterns in chip design layout for semiconductor device manufacturing.
- lithographic process is responsible for transferring circuit patterns created by circuit designers onto wafers.
- Photomasks/reticles with opaque and clear patterns according to the circuit patterns are used for patterning device layers on wafers. Distortion of the patterns can result from the effect of the neighboring patterns on the photomask and optical diffraction, photoresist development and etching, chemical-mechanical polishing (CMP) on adjacent layers of the wafer, and geometric and overlaying relationships between patterns of adjacent layers fabricated on the wafer.
- CMP chemical-mechanical polishing
- ICs integrated circuits
- distortion of the patterns often results in systematic defects that fail the device fabricated on the wafer or critical dimension (CD) errors that degrade the device performance.
- FIG. 1 shows a typical flow in initial setup and on-going tune-up for optimizing the lithography process of manufacturing semiconductor devices.
- Circuit patterns for manufacturing the photomask of a device layer is described in a design data file generated by the circuit designer shown in block 101 that contains design data in GDS or OASIS format.
- the design data may be random layout circuit patterns generated from a random layout generator (RLG) or product qualification vehicle (PQV) from vendors or pilot customers.
- Block 102 shows optical proximity correction (OPC) creation that generates the required OPC by using the OPC model and recipe from block 103 . After OPC creation, block 102 also performs OPC verification and lithographic process check (LPC) verification based on models of OPC and design for manufacturing (DFM).
- OPC optical proximity correction
- OPC and LPC verification also predicts potential yield limiting hot spots caused by specific layout and patterns.
- wafers manufactured by the lithography process using the OPC photomask are examined by either optical or e-beam inspection and metrology tool to detect defects and measure critical dimensions in the hot spots. Inspection and metrology data of the predicted hot spots are fed back to block 103 to tune the models and recipes of OPC and DFM.
- it is not easy to achieve perfect OPC/DFM models/recipes because the patterning errors come from various proximity and underneath effects including optical, chemical, etching, CMP and other processes as well as photomask/reticle errors. Even worse, some effects are short range and some are long range.
- OPC is effective in achieving linewidth control if optical conditions during lithography match the simulated optical conditions used to arrive at the OPC solution.
- Defocus and exposure dose variations result in linewidth variation even after OPC.
- Focus variation during lithography is caused by changes in resist thickness, wafer topography and relative distance between wafer plane and the lens system. The dose variation typically comes from the scanner or from the illumination in the optical lithography system.
- Depth of focus and exposure latitude define the process window of a lithography system.
- Latest advances in process window aware OPC guarantee acceptable lithography quality but linewidth still varies within the process window. Linewidth variation has a direct impact on timing and leakage of designs.
- Lithographic process simulation is typically used to simulate the circuit patterns and predict hot spots that are likely to cause pattern distortion. OPC and LPC are important techniques commonly used for correcting the pattern distortion. CMP simulation may also be performed on the circuit layout to determine hot spots. Alternatively, physical failure analysis (PFA) may be performed on the devices to identify hot spots. Process monitoring by sampling and inspecting wafers using the predicted or identified hot spots is necessary to ensure that systematic defects are identified and eliminated for manufacturing the semiconductor devices with high yield.
- PFA physical failure analysis
- SEM scanning electron microscopic
- a primary object of the present invention is to provide a system including a critical signature library, a statistical model creator and a statistical model based predictor for discovering unknown problematic circuit patterns.
- the critical signature library of the present invention is a storage device configured to store a library of critical signature databases.
- Each critical signature database includes a plurality of known problematic circuit patterns of a chip design layout with their corresponding physical measurement data obtained from manufacturing process and simulation data associated with the physical measurement.
- Each critical database also stores statistical models created by the statistical model creator for the corresponding chip design layout.
- the statistical model creator divides the known problematic circuit patterns stored in a critical signature database into a model training data set and a model validation data set. Each data set includes a certain amount of known problematic circuit patterns from the critical signature database.
- the statistical model creator extracts features from the known circuit patterns, creates statistical models using the model training data set and validates the statistical models with the model validation data set according to desired target specifications based on deviation between physical measurement data and simulation data or design data.
- the statistical model based predictor receives a large number of candidate circuit patterns, extracts features from them, predicts and discovers unknown problematic circuit patterns according to one or more statistical models stored in the corresponding critical signature database.
- the candidate circuit patterns may be generated by extracting design clips from the chip design layout by dividing the design layout into smaller tiles, by applying lithographic process simulation on the chip design layout to identify hot spot locations with an aggressive setting, or by finding defective locations from inspecting wafers manufactured with the chip design layout using an aggressive sensitivity setting.
- the method first preparing a critical signature library including at least one critical signature database having a plurality of known problematic circuit patterns extracted from the chip design layout.
- Each problematic circuit pattern may also have associated physical data measured from manufactured semiconductor devices and simulation data generated based on the chip design layout stored in the corresponding critical signature database.
- the method then creates one or more statistical models based on the plurality of known problematic circuit patterns according to a target specification based on deviation between the associated physical data and simulation data or design data.
- the created statistical models are saved in the corresponding critical signature database.
- a large number of candidate circuit patterns are generated from the chip design layout or inspecting wafers manufactured with the chip design layout. Each of the candidate circuit patterns is then predicted and labeled as being problematic or not according to one or more statistical models. If a candidate circuit pattern is labelled as being problematic, it is compared with the known problematic circuit patterns already stored in the corresponding critical signature database. If the candidate circuit pattern labelled as being problematic does not match any of the known problematic circuit patterns, the candidate circuit pattern is saved in the corresponding critical signature database and removed from further prediction.
- FIG. 1 shows a typical flow in initial setup and tuning for optimizing the lithography process of manufacturing semiconductor devices
- FIG. 2 shows the block diagram of a system for discovering unknown problematic circuit patterns of a chip design layout for semiconductor manufacturing according to the present invention
- FIG. 3 shows the critical signature library that stores a number of critical signature databases according to the present invention.
- FIG. 4 shows a flow chart of the method for discovering unknown problematic circuit patterns of a chip design layout for semiconductor manufacturing according to the present invention.
- FIG. 2 shows a block diagram of the system 200 for discovering problematic circuit patterns in chip design layout according to the present invention.
- the system 200 comprises a critical signature library 201 , a statistical model creator 202 , and a statistical model based predictor 203 .
- the critical signature library 201 is a storage device configured to store a library of critical signature databases 301 as shown in FIG. 3 .
- various indexes may be used to index each critical signature database 301 .
- the database may be indexed by technology nodes such as 14 nm, 10 nm or 7 nm technology node, or indexed by manufacturing lines, etc.
- Each critical signature database 301 includes a plurality of known problematic circuit patterns along with their corresponding physical measurement data such as defect image patches or critical dimension (CD) measurements acquired from manufacturing process, and the simulation data associated with the physical measurement.
- CD critical dimension
- each critical signature database 301 also includes at least one statistical model created by the statistical model creator 202 based on the plurality of known problematic circuit patterns.
- the known problematic circuit patterns are divided into a model training data set and a model validation data set. Each data set includes a certain amount of known problematic circuit patterns from the critical signature database 301 .
- a model target specification is set for the creation of the statistical mode.
- the model target specification is set based on the deviation between the physical measurement data and the simulation data or design data.
- the simulated CD data can be computed from the LP simulation using the design clip of the known problematic circuit pattern.
- a model target specification may be set as being greater than 10% in the CD deviation between the physical CD measurement and the simulated CD data or design CD data.
- an ideal statistical model created from the model training data set is that all the problematic circuit patterns in the model training data set that have more than 10% CD deviation satisfy the statistical model, and all the problematic circuit patterns in the model training data set that have less than 10% CD deviation does not satisfy the statistical model.
- a set of features are extracted from the design clip corresponding to the problematic circuit pattern.
- the features extracted from each problematic circuit pattern are pattern density, pattern perimeter, minimum or maximum linewidth, minimum or maximum spacing, pattern orientation, number of edges, inside or outside corners, spatial frequency distribution, . . . , etc.
- a statistical model can be trained using the features extracted from each problematic circuit pattern in the model training data set.
- Many model training algorithms have been widely used in statistical data analysis and data mining. For example, modeling algorithms based on decision tree, linear regression, nonlinear regression, support vector machine (SVM), k-Means clustering, hierarchical clustering, . . . , etc. All those modeling algorithms can be applied to the model training data set to establish a statistical model for the problematic circuit pattern in the model training data set.
- the statistical model is applied to the model validation data set.
- the same set of features is extracted from the design clip corresponding to each problematic circuit pattern in the model validation data set.
- the statistical model is used to predict the behavior of each problematic circuit pattern in the model validation data set.
- a statistical model can be established based on a model target specification of being greater than 10% in the CD deviation between the physical CD measurement and the simulated CD data or design CD data using the model training data set.
- model validation the predicted result of each problematic circuit pattern in the model validation data set is checked against its CD deviation of the physical CD measurement from the simulated CD data or design CD data to determine if the prediction matches the truth.
- the model accuracy can be determined based on how many problematic circuit patterns in the model validation data set have been predicted correctly.
- the robustness of a statistical model can be judged based on the model accuracy of the statistical model.
- the statistical model created for each critical signature database 301 by the statistical model creator 202 is stored in the corresponding critical signature database 301 as shown in FIG. 3 .
- Multiple statistical models may be established and saved for a corresponding critical signature database 301 by using different modeling algorithms or different sets of features extracted from the problematic circuit patterns in the critical signature database 301 .
- the statistical models for the critical signature database 301 are used by the statistical model based predictor 203 of the present invention to predict and discover unknown problematic circuit patterns 205 . As shown in FIG. 2 , the statistical model based predictor 203 predicts the unknown problematic circuit patterns 205 from candidate circuit patterns 204 based on the statistical models saved in the critical signature database 301 of the critical signature library 201 .
- the candidate circuit patterns 204 may be generated by a random layout generator (RLG) during the initial qualification of a technology node or manufacture line based on the specification of the targeted semiconductor technology such as design rules, DFM rules, process models, standard cells, . . . , etc.
- RLG random layout generator
- a large set of all possible circuit patterns can be generated from the chip design layout as the candidate circuit patterns 204 by dividing the chip design layout into many small tiles, and performing some coarse filtering to eliminate blank or non-critical areas.
- the disadvantage of this approach is that the computation required to generate all possible circuit patterns can be very expensive and the number of candidate circuit patterns may be too many to manage.
- many of the possible circuit patterns may only include trivial patterns that are unlikely to be problematic.
- the present invention provides another approach for generating the candidate circuit patterns by using LPC tools.
- the hot spot detection available in LPC tools can be used to simulate and analyze the lithographic process with the chip design layout to generate the candidate circuit patterns 204 .
- an aggressive threshold with an extended process window setting to amplify the potential systematic problems, many hot spots can be identified and their corresponding circuit patterns can be extracted from the chip design layout as the candidate circuit patterns 204 .
- the candidate circuit patterns 204 can also be generated by using wafer inspectors with an aggressive sensitivity setting to inspect wafers and detect potential systematic defect sites. Wafers with focus exposure matrix (FEM) can be particularly useful in identifying potential defect sites at various process windows. The corresponding circuit patterns of the identified potential defect sites can be extracted from the chip design layout of the semiconductor device and serve as the candidate circuit patterns 204 .
- FEM focus exposure matrix
- the statistical model based predictor 203 extracts the corresponding sets of features that have been used in creating the statistical models from all the candidate circuit patterns 204 .
- Each statistical model is applied to the corresponding set of features to predict and label each candidate circuit pattern as being problematic or not.
- the candidate circuit pattern that has been predicted as problematic is identified as a problematic circuit pattern 205 and removed from further prediction to be done by other statistical models.
- the predicted problematic circuit pattern 205 is saved in the critical signature database 301 if the same circuit pattern does not exist in the critical signature database 301 . If the predicted problematic circuit pattern is a newly discovered problematic circuit pattern, the problematic circuit pattern can be included and verified in a future test vehicle. The newly discovered problematic circuit pattern should also be fixed in the chip design layout immediately.
- statistical model based predictor 203 uses the full ensemble of the established statistical models to check the candidate circuit patterns 204 by applying each statistical model established for a given critical signature database 301 to the candidate circuit patterns 204 . It can be understood that the success of discovering unknown problematic circuit patterns relies on the accuracy and thoroughness of the established statistical models.
- the gist of the present invention resides on modeling the effect of the semiconductor manufacturing process on the circuit patterns of a chip design layout with statistical models based on features extracted from the circuit patterns. A good statistical model can be established only if the features used in the modeling can capture the effect of the semiconductor manufacturing process on the circuit patterns.
- the features used in the statistical model creator 202 of the present invention for establishing statistical models include features extracted from design clips of different sizes for the circuit patterns in the critical signature database 302 . By having different sizes of circuit patterns, the optical proximity effect can better be captured in the statistical models.
- the present invention also uses design clips of the layers underneath the current design layer for extracting features to capture the effects of multiple circuit layers.
- Boolean operators such as OR, Exclusive OR, AND, NOT, etc., can be applied to the design clips including the current layer and underneath layers to form a composite circuit pattern for feature extraction.
- FIG. 4 shows a flow chart summarizing the method for discovering unknown problematic circuit patterns according to the present invention.
- a critical signature database is prepared and stored in a critical signature library in step 401 of the method.
- the critical signature database includes a plurality of known problematic circuit patterns.
- At least a statistical model is established by dividing the known problematic circuit patterns into a model training data set and a model validation data set in step 402 .
- the established statistical model is stored in the corresponding critical signature database.
- a plurality of candidate circuit patterns are generated.
- the candidate circuit patterns may be generated from RLG, chip design layout or inspecting FEM wafers.
- the statistical models provided by the critical signature database are applied to each candidate pattern to predict if the candidate pattern is a problematic circuit pattern or not in step 404 . If a candidate pattern is predicted as being problematic, it is removed from the plurality of candidate circuit patterns and no longer applied with other statistical models for further prediction.
- step 405 a problematic circuit pattern discovered in step 404 is compared with the known problematic circuit patterns already in the corresponding critical signature database. If the discovered problematic circuit pattern does not exist in the database, the discovered problematic circuit pattern is saved in the database.
- the method of discovering unknown problematic circuit patterns can be used in the initial qualification of a new technology node or manufacturing line. It can also be used in the ramp-up stage of manufacturing a semiconductor device to uncover and fix the problematic circuit patterns in the chip design layout before starting the expensive and time-consuming manufacturing cycle.
- the method can also be used to discover unknown problematic circuit patterns if the chip design layout has a revision.
- the candidate circuit patterns can be extracted from the portion of the chip design layout that has been changed in the revision.
- the method can also help discover the unknown problematic circuit patterns that may exist in the chip design layout of the new semiconductor device.
- the statistical model creator 202 and the statistical model based predictor 203 as shown in FIG. 2 in the present invention can be implemented by a computing system that has one of more computing processors and memory devices configured to execute program instructions designed to perform the statistical modelling or prediction. They can also be dedicated hardware devices designed to deliver the required functionalities of the statistical model creator 202 and the statistical model based predictor 203 .
Abstract
Description
- 1. Field of the Invention
- The present invention relates generally to semiconductor device fabrication, and more specifically to a system and method for discovering unknown problematic circuit patterns in chip design layout for semiconductor device manufacturing.
- 2. Description of Related Art
- The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
- Semiconductor devices are manufactured by fabricating many layers of circuit patterns on wafers to form a massive number of transistors for integration as complicated circuits. In the manufacturing flow of semiconductor devices, lithographic process (LP) is responsible for transferring circuit patterns created by circuit designers onto wafers.
- Photomasks/reticles with opaque and clear patterns according to the circuit patterns are used for patterning device layers on wafers. Distortion of the patterns can result from the effect of the neighboring patterns on the photomask and optical diffraction, photoresist development and etching, chemical-mechanical polishing (CMP) on adjacent layers of the wafer, and geometric and overlaying relationships between patterns of adjacent layers fabricated on the wafer. As the component density of the integrated circuits (ICs) has increased the complexity of the IC patterns and layouts, distortion of the patterns often results in systematic defects that fail the device fabricated on the wafer or critical dimension (CD) errors that degrade the device performance.
-
FIG. 1 shows a typical flow in initial setup and on-going tune-up for optimizing the lithography process of manufacturing semiconductor devices. Circuit patterns for manufacturing the photomask of a device layer is described in a design data file generated by the circuit designer shown inblock 101 that contains design data in GDS or OASIS format. The design data may be random layout circuit patterns generated from a random layout generator (RLG) or product qualification vehicle (PQV) from vendors or pilot customers.Block 102 shows optical proximity correction (OPC) creation that generates the required OPC by using the OPC model and recipe fromblock 103. After OPC creation,block 102 also performs OPC verification and lithographic process check (LPC) verification based on models of OPC and design for manufacturing (DFM). - OPC and LPC verification also predicts potential yield limiting hot spots caused by specific layout and patterns. As shown in
block 104, wafers manufactured by the lithography process using the OPC photomask are examined by either optical or e-beam inspection and metrology tool to detect defects and measure critical dimensions in the hot spots. Inspection and metrology data of the predicted hot spots are fed back toblock 103 to tune the models and recipes of OPC and DFM. In general, it is not easy to achieve perfect OPC/DFM models/recipes because the patterning errors come from various proximity and underneath effects including optical, chemical, etching, CMP and other processes as well as photomask/reticle errors. Even worse, some effects are short range and some are long range. - OPC is effective in achieving linewidth control if optical conditions during lithography match the simulated optical conditions used to arrive at the OPC solution. Defocus and exposure dose variations result in linewidth variation even after OPC. Focus variation during lithography is caused by changes in resist thickness, wafer topography and relative distance between wafer plane and the lens system. The dose variation typically comes from the scanner or from the illumination in the optical lithography system. Depth of focus and exposure latitude define the process window of a lithography system. Latest advances in process window aware OPC guarantee acceptable lithography quality but linewidth still varies within the process window. Linewidth variation has a direct impact on timing and leakage of designs.
- Lithographic process simulation is typically used to simulate the circuit patterns and predict hot spots that are likely to cause pattern distortion. OPC and LPC are important techniques commonly used for correcting the pattern distortion. CMP simulation may also be performed on the circuit layout to determine hot spots. Alternatively, physical failure analysis (PFA) may be performed on the devices to identify hot spots. Process monitoring by sampling and inspecting wafers using the predicted or identified hot spots is necessary to ensure that systematic defects are identified and eliminated for manufacturing the semiconductor devices with high yield.
- One approach commonly used in process monitoring is to collect scanning electron microscopic (SEM) images from a significant number of hot spots by sampling dies and wafers in the manufacturing flow. The hot spots may be predicted by LPC, CMP and other experience and a priori knowledge, or identified by PFA. Ideally, the more predicted hot spots, the less chance of missing critical defects. In practice, however, the number of hot spots used in process monitoring cannot overload the wafer inspectors and many of the predicted hot spots may also turn out to be non-systematic or non-critical because of modelling errors. How to predict the hot spots with most accuracy and good thoroughness has been a big challenge to the semiconductor manufacturers.
- There is another drawback in the existing approaches to predicting the hot spots based on LP or CMP simulation of the chip design layout. Because the hot spots are predicted by applying LP or CMP model on the known chip design layout, the circuit patterns predicted as hot spots are limited within the available circuit patterns in the known chip design layout. A catastrophic systematic defect may occur in a revision of the chip design that includes new circuit patterns not covered by the hot spots. In addition, a well-qualified process line in the semiconductor fab may still run the risk of missing yield limiting defects when the semiconductor device of a new chip design is fabricated.
- The present invention has been made to overcome the above mentioned challenges and drawbacks in predicting and discovering problematic circuit patterns of a chip design layout for manufacturing semiconductor devices. Accordingly, a primary object of the present invention is to provide a system including a critical signature library, a statistical model creator and a statistical model based predictor for discovering unknown problematic circuit patterns.
- The critical signature library of the present invention is a storage device configured to store a library of critical signature databases. Each critical signature database includes a plurality of known problematic circuit patterns of a chip design layout with their corresponding physical measurement data obtained from manufacturing process and simulation data associated with the physical measurement. Each critical database also stores statistical models created by the statistical model creator for the corresponding chip design layout.
- The statistical model creator divides the known problematic circuit patterns stored in a critical signature database into a model training data set and a model validation data set. Each data set includes a certain amount of known problematic circuit patterns from the critical signature database. The statistical model creator extracts features from the known circuit patterns, creates statistical models using the model training data set and validates the statistical models with the model validation data set according to desired target specifications based on deviation between physical measurement data and simulation data or design data.
- The statistical model based predictor receives a large number of candidate circuit patterns, extracts features from them, predicts and discovers unknown problematic circuit patterns according to one or more statistical models stored in the corresponding critical signature database. The candidate circuit patterns may be generated by extracting design clips from the chip design layout by dividing the design layout into smaller tiles, by applying lithographic process simulation on the chip design layout to identify hot spot locations with an aggressive setting, or by finding defective locations from inspecting wafers manufactured with the chip design layout using an aggressive sensitivity setting.
- It is also an object of the present invention to provide a method of discovering unknown problematic circuit patterns of the chip design layout for semiconductor manufacturing. The method first preparing a critical signature library including at least one critical signature database having a plurality of known problematic circuit patterns extracted from the chip design layout. Each problematic circuit pattern may also have associated physical data measured from manufactured semiconductor devices and simulation data generated based on the chip design layout stored in the corresponding critical signature database.
- The method then creates one or more statistical models based on the plurality of known problematic circuit patterns according to a target specification based on deviation between the associated physical data and simulation data or design data. The created statistical models are saved in the corresponding critical signature database.
- A large number of candidate circuit patterns are generated from the chip design layout or inspecting wafers manufactured with the chip design layout. Each of the candidate circuit patterns is then predicted and labeled as being problematic or not according to one or more statistical models. If a candidate circuit pattern is labelled as being problematic, it is compared with the known problematic circuit patterns already stored in the corresponding critical signature database. If the candidate circuit pattern labelled as being problematic does not match any of the known problematic circuit patterns, the candidate circuit pattern is saved in the corresponding critical signature database and removed from further prediction.
- The present invention will be apparent to those skilled in the art by reading the following detailed description of preferred embodiments thereof, with reference to the attached drawings, in which:
-
FIG. 1 shows a typical flow in initial setup and tuning for optimizing the lithography process of manufacturing semiconductor devices; -
FIG. 2 shows the block diagram of a system for discovering unknown problematic circuit patterns of a chip design layout for semiconductor manufacturing according to the present invention; -
FIG. 3 shows the critical signature library that stores a number of critical signature databases according to the present invention; and -
FIG. 4 shows a flow chart of the method for discovering unknown problematic circuit patterns of a chip design layout for semiconductor manufacturing according to the present invention. -
FIG. 2 shows a block diagram of thesystem 200 for discovering problematic circuit patterns in chip design layout according to the present invention. With reference toFIG. 2 , thesystem 200 comprises acritical signature library 201, astatistical model creator 202, and a statistical model basedpredictor 203. - The
critical signature library 201 is a storage device configured to store a library ofcritical signature databases 301 as shown inFIG. 3 . In thecritical signature library 201, various indexes may be used to index eachcritical signature database 301. For example, the database may be indexed by technology nodes such as 14 nm, 10 nm or 7 nm technology node, or indexed by manufacturing lines, etc. Eachcritical signature database 301 includes a plurality of known problematic circuit patterns along with their corresponding physical measurement data such as defect image patches or critical dimension (CD) measurements acquired from manufacturing process, and the simulation data associated with the physical measurement. - In the present invention, each
critical signature database 301 also includes at least one statistical model created by thestatistical model creator 202 based on the plurality of known problematic circuit patterns. In order to validate the accuracy of the statistical model, the known problematic circuit patterns are divided into a model training data set and a model validation data set. Each data set includes a certain amount of known problematic circuit patterns from thecritical signature database 301. - In the creation of the statistical model, a model target specification is set for the creation of the statistical mode. In a preferred embodiment of the present invention, the model target specification is set based on the deviation between the physical measurement data and the simulation data or design data. For example, for a known problematic circuit pattern, the simulated CD data can be computed from the LP simulation using the design clip of the known problematic circuit pattern. A model target specification may be set as being greater than 10% in the CD deviation between the physical CD measurement and the simulated CD data or design CD data. In other words, an ideal statistical model created from the model training data set is that all the problematic circuit patterns in the model training data set that have more than 10% CD deviation satisfy the statistical model, and all the problematic circuit patterns in the model training data set that have less than 10% CD deviation does not satisfy the statistical model.
- According to the present invention, a set of features are extracted from the design clip corresponding to the problematic circuit pattern. Examples of the features extracted from each problematic circuit pattern are pattern density, pattern perimeter, minimum or maximum linewidth, minimum or maximum spacing, pattern orientation, number of edges, inside or outside corners, spatial frequency distribution, . . . , etc. These features are only examples and many others can be apparent to those skilled in the art.
- With a target specification of deviation between the associated physical measurement and simulation data or design data, a statistical model can be trained using the features extracted from each problematic circuit pattern in the model training data set. Many model training algorithms have been widely used in statistical data analysis and data mining. For example, modeling algorithms based on decision tree, linear regression, nonlinear regression, support vector machine (SVM), k-Means clustering, hierarchical clustering, . . . , etc. All those modeling algorithms can be applied to the model training data set to establish a statistical model for the problematic circuit pattern in the model training data set.
- After a statistical model for the model training data set has been established, the statistical model is applied to the model validation data set. The same set of features is extracted from the design clip corresponding to each problematic circuit pattern in the model validation data set. The statistical model is used to predict the behavior of each problematic circuit pattern in the model validation data set.
- As an example, a statistical model can be established based on a model target specification of being greater than 10% in the CD deviation between the physical CD measurement and the simulated CD data or design CD data using the model training data set. By applying the established statistical model to the set of features of a problematic circuit pattern in the model validation set, whether the CD deviation corresponding to each problematic circuit pattern should meet the target specification can be predicted.
- In the process of model validation, the predicted result of each problematic circuit pattern in the model validation data set is checked against its CD deviation of the physical CD measurement from the simulated CD data or design CD data to determine if the prediction matches the truth. The model accuracy can be determined based on how many problematic circuit patterns in the model validation data set have been predicted correctly. The robustness of a statistical model can be judged based on the model accuracy of the statistical model.
- In accordance with the present invention, the statistical model created for each
critical signature database 301 by thestatistical model creator 202 is stored in the correspondingcritical signature database 301 as shown inFIG. 3 . Multiple statistical models may be established and saved for a correspondingcritical signature database 301 by using different modeling algorithms or different sets of features extracted from the problematic circuit patterns in thecritical signature database 301. - The statistical models for the
critical signature database 301 are used by the statistical model basedpredictor 203 of the present invention to predict and discover unknownproblematic circuit patterns 205. As shown inFIG. 2 , the statistical model basedpredictor 203 predicts the unknownproblematic circuit patterns 205 fromcandidate circuit patterns 204 based on the statistical models saved in thecritical signature database 301 of thecritical signature library 201. - In order to discover unknown problematic circuit patterns, a sufficient number of the
candidate circuit patterns 204 should be provided. According to the present invention, thecandidate circuit patterns 204 may be generated by a random layout generator (RLG) during the initial qualification of a technology node or manufacture line based on the specification of the targeted semiconductor technology such as design rules, DFM rules, process models, standard cells, . . . , etc. - For the production of a given chip design layout, a large set of all possible circuit patterns can be generated from the chip design layout as the
candidate circuit patterns 204 by dividing the chip design layout into many small tiles, and performing some coarse filtering to eliminate blank or non-critical areas. The disadvantage of this approach is that the computation required to generate all possible circuit patterns can be very expensive and the number of candidate circuit patterns may be too many to manage. In addition, many of the possible circuit patterns may only include trivial patterns that are unlikely to be problematic. - The present invention provides another approach for generating the candidate circuit patterns by using LPC tools. The hot spot detection available in LPC tools can be used to simulate and analyze the lithographic process with the chip design layout to generate the
candidate circuit patterns 204. By using an aggressive threshold with an extended process window setting to amplify the potential systematic problems, many hot spots can be identified and their corresponding circuit patterns can be extracted from the chip design layout as thecandidate circuit patterns 204. - During the initial ramp-up of manufacturing a semiconductor device, the
candidate circuit patterns 204 can also be generated by using wafer inspectors with an aggressive sensitivity setting to inspect wafers and detect potential systematic defect sites. Wafers with focus exposure matrix (FEM) can be particularly useful in identifying potential defect sites at various process windows. The corresponding circuit patterns of the identified potential defect sites can be extracted from the chip design layout of the semiconductor device and serve as thecandidate circuit patterns 204. - According to the present invention, the statistical model based
predictor 203 extracts the corresponding sets of features that have been used in creating the statistical models from all thecandidate circuit patterns 204. Each statistical model is applied to the corresponding set of features to predict and label each candidate circuit pattern as being problematic or not. The candidate circuit pattern that has been predicted as problematic is identified as aproblematic circuit pattern 205 and removed from further prediction to be done by other statistical models. - The predicted
problematic circuit pattern 205 is saved in thecritical signature database 301 if the same circuit pattern does not exist in thecritical signature database 301. If the predicted problematic circuit pattern is a newly discovered problematic circuit pattern, the problematic circuit pattern can be included and verified in a future test vehicle. The newly discovered problematic circuit pattern should also be fixed in the chip design layout immediately. - In the present invention, statistical model based
predictor 203 uses the full ensemble of the established statistical models to check thecandidate circuit patterns 204 by applying each statistical model established for a givencritical signature database 301 to thecandidate circuit patterns 204. It can be understood that the success of discovering unknown problematic circuit patterns relies on the accuracy and thoroughness of the established statistical models. - It should also be noted that the gist of the present invention resides on modeling the effect of the semiconductor manufacturing process on the circuit patterns of a chip design layout with statistical models based on features extracted from the circuit patterns. A good statistical model can be established only if the features used in the modeling can capture the effect of the semiconductor manufacturing process on the circuit patterns.
- It has been well known and observed that optical proximity effect plays an important role in patterning the chip design layout. In order to improve the accuracy and thoroughness of the established statistical models, the features used in the
statistical model creator 202 of the present invention for establishing statistical models include features extracted from design clips of different sizes for the circuit patterns in the critical signature database 302. By having different sizes of circuit patterns, the optical proximity effect can better be captured in the statistical models. - Because the circuit patterns are stacked layer by layer in manufacturing the semiconductor device, in addition to using circuit patterns of different sizes for feature extraction, the present invention also uses design clips of the layers underneath the current design layer for extracting features to capture the effects of multiple circuit layers. Boolean operators such as OR, Exclusive OR, AND, NOT, etc., can be applied to the design clips including the current layer and underneath layers to form a composite circuit pattern for feature extraction.
-
FIG. 4 shows a flow chart summarizing the method for discovering unknown problematic circuit patterns according to the present invention. A critical signature database is prepared and stored in a critical signature library instep 401 of the method. The critical signature database includes a plurality of known problematic circuit patterns. At least a statistical model is established by dividing the known problematic circuit patterns into a model training data set and a model validation data set instep 402. The established statistical model is stored in the corresponding critical signature database. - In
step 403, a plurality of candidate circuit patterns are generated. The candidate circuit patterns may be generated from RLG, chip design layout or inspecting FEM wafers. The statistical models provided by the critical signature database are applied to each candidate pattern to predict if the candidate pattern is a problematic circuit pattern or not instep 404. If a candidate pattern is predicted as being problematic, it is removed from the plurality of candidate circuit patterns and no longer applied with other statistical models for further prediction. - In
step 405, a problematic circuit pattern discovered instep 404 is compared with the known problematic circuit patterns already in the corresponding critical signature database. If the discovered problematic circuit pattern does not exist in the database, the discovered problematic circuit pattern is saved in the database. - As described before, the method of discovering unknown problematic circuit patterns can be used in the initial qualification of a new technology node or manufacturing line. It can also be used in the ramp-up stage of manufacturing a semiconductor device to uncover and fix the problematic circuit patterns in the chip design layout before starting the expensive and time-consuming manufacturing cycle. The method can also be used to discover unknown problematic circuit patterns if the chip design layout has a revision. The candidate circuit patterns can be extracted from the portion of the chip design layout that has been changed in the revision. When a manufacturing line is prepared to manufacture a new semiconductor device, the method can also help discover the unknown problematic circuit patterns that may exist in the chip design layout of the new semiconductor device.
- It may be worth mentioning that the
statistical model creator 202 and the statistical model basedpredictor 203 as shown inFIG. 2 in the present invention can be implemented by a computing system that has one of more computing processors and memory devices configured to execute program instructions designed to perform the statistical modelling or prediction. They can also be dedicated hardware devices designed to deliver the required functionalities of thestatistical model creator 202 and the statistical model basedpredictor 203. - Although the present invention has been described with reference to the preferred embodiments thereof, it is apparent to those skilled in the art that a variety of modifications and changes may be made without departing from the scope of the present invention which is intended to be defined by the appended claims.
Claims (27)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/810,428 US9547745B1 (en) | 2015-07-27 | 2015-07-27 | System and method for discovering unknown problematic patterns in chip design layout for semiconductor manufacturing |
TW104130314A TWI594067B (en) | 2015-07-27 | 2015-09-14 | System and method for discovering unknown problematic patterns in chip design layout for semiconductor manufacturing |
CN201510662107.7A CN106407490B (en) | 2015-07-27 | 2015-10-15 | The System and method for of unknown problem pattern is found in chip design layout |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/810,428 US9547745B1 (en) | 2015-07-27 | 2015-07-27 | System and method for discovering unknown problematic patterns in chip design layout for semiconductor manufacturing |
Publications (2)
Publication Number | Publication Date |
---|---|
US9547745B1 US9547745B1 (en) | 2017-01-17 |
US20170032075A1 true US20170032075A1 (en) | 2017-02-02 |
Family
ID=57749314
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/810,428 Active 2035-09-20 US9547745B1 (en) | 2015-07-27 | 2015-07-27 | System and method for discovering unknown problematic patterns in chip design layout for semiconductor manufacturing |
Country Status (3)
Country | Link |
---|---|
US (1) | US9547745B1 (en) |
CN (1) | CN106407490B (en) |
TW (1) | TWI594067B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210248301A1 (en) * | 2017-12-12 | 2021-08-12 | Siemens Industry Software Inc. | Puzzle-based pattern analysis and classification |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102306558B1 (en) * | 2016-12-28 | 2021-10-05 | 에이에스엠엘 네델란즈 비.브이. | Guidance and inspection methods of process models in the manufacturing process |
KR102451504B1 (en) | 2017-04-28 | 2022-10-06 | 에이에스엠엘 네델란즈 비.브이. | Optimization of the sequence of processes for the manufacture of product units |
JP6964031B2 (en) * | 2018-03-27 | 2021-11-10 | Tasmit株式会社 | Pattern edge detection method |
KR102617197B1 (en) | 2018-12-28 | 2023-12-27 | 에이에스엠엘 네델란즈 비.브이. | Pattern ranking determination based on measurement feedback from printed boards |
US10831977B1 (en) * | 2019-06-03 | 2020-11-10 | Globalfoundries Inc. | Curvilinear mask models |
KR20210028798A (en) * | 2019-09-04 | 2021-03-15 | 삼성전자주식회사 | Manufacturing method of semiconductor device |
US11313810B2 (en) | 2019-11-14 | 2022-04-26 | International Business Machines Corporation | Secure semiconductor wafer inspection utilizing film thickness |
TWI755015B (en) * | 2020-08-11 | 2022-02-11 | 大陸商昆山吉崴微電子科技有限公司 | Signal and power integrated analog analysis system and analog analysis method for full chip system |
WO2022101051A1 (en) * | 2020-11-13 | 2022-05-19 | Asml Netherlands B.V. | Active learning-based defect location identification |
CN116888599A (en) * | 2021-05-21 | 2023-10-13 | 华为技术有限公司 | Method and device for layout of circuit units of integrated circuit |
CN113589642B (en) * | 2021-07-05 | 2024-02-27 | 广东省大湾区集成电路与系统应用研究院 | Method, device, computer equipment and medium for predicting open circuit defect of integrated circuit |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040225488A1 (en) * | 2003-05-05 | 2004-11-11 | Wen-Chuan Wang | System and method for examining mask pattern fidelity |
US7100134B2 (en) * | 2003-08-18 | 2006-08-29 | Aprio Technologies, Inc. | Method and platform for integrated physical verifications and manufacturing enhancements |
JP4768251B2 (en) * | 2004-11-01 | 2011-09-07 | 株式会社東芝 | Semiconductor integrated circuit design method, semiconductor integrated circuit design system, and semiconductor integrated circuit manufacturing method |
US7861196B2 (en) * | 2008-01-31 | 2010-12-28 | Cadence Design Systems, Inc. | System and method for multi-exposure pattern decomposition |
CN101539956A (en) * | 2008-03-20 | 2009-09-23 | 英业达股份有限公司 | System and method for arranging signal wire |
TWI421908B (en) * | 2008-09-18 | 2014-01-01 | United Microelectronics Corp | Method for constructing opc model |
CN102156760B (en) * | 2010-08-23 | 2013-05-01 | 北京航空航天大学 | Saber-based circuit failure simulation analyzing method |
US8607169B2 (en) * | 2011-12-28 | 2013-12-10 | Elitetech Technology Co., Ltd. | Intelligent defect diagnosis method |
US20140214192A1 (en) * | 2013-01-25 | 2014-07-31 | Dmo Systems Limited | Apparatus For Design-Based Manufacturing Optimization In Semiconductor Fab |
CN103246771B (en) * | 2013-05-10 | 2017-02-22 | 北京航空航天大学 | Fault-tolerant circuit fault effect analytical method based on simulation |
US9142014B2 (en) * | 2013-05-30 | 2015-09-22 | Dmo Systems Limited | System and method for identifying systematic defects in wafer inspection using hierarchical grouping and filtering |
US8938695B1 (en) * | 2014-01-09 | 2015-01-20 | Dmo Systems Limited | Signature analytics for improving lithographic process of manufacturing semiconductor devices |
-
2015
- 2015-07-27 US US14/810,428 patent/US9547745B1/en active Active
- 2015-09-14 TW TW104130314A patent/TWI594067B/en active
- 2015-10-15 CN CN201510662107.7A patent/CN106407490B/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210248301A1 (en) * | 2017-12-12 | 2021-08-12 | Siemens Industry Software Inc. | Puzzle-based pattern analysis and classification |
US11704468B2 (en) * | 2017-12-12 | 2023-07-18 | Siemens Industry Software Inc. | Puzzle-based pattern analysis and classification |
Also Published As
Publication number | Publication date |
---|---|
CN106407490A (en) | 2017-02-15 |
CN106407490B (en) | 2019-10-25 |
US9547745B1 (en) | 2017-01-17 |
TWI594067B (en) | 2017-08-01 |
TW201704849A (en) | 2017-02-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9547745B1 (en) | System and method for discovering unknown problematic patterns in chip design layout for semiconductor manufacturing | |
TWI808815B (en) | System and method of semiconductor fabrication process control and computer program product | |
US10754309B2 (en) | Auto defect screening using adaptive machine learning in semiconductor device manufacturing flow | |
US11120182B2 (en) | Methodology of incorporating wafer physical measurement with digital simulation for improving semiconductor device fabrication | |
CN110622069B (en) | Method for predicting yield of device manufacturing process | |
JP5334956B2 (en) | System and method for performing mask verification using an individual mask error model | |
US7962863B2 (en) | Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer | |
US7765515B2 (en) | Pattern match based optical proximity correction and verification of integrated circuit layout | |
US8661373B2 (en) | Method for the real-time monitoring of integrated circuit manufacture through localized monitoring structures in OPC model space | |
TW201638654A (en) | Method of detecting photolithographic hotspots | |
US20200372630A1 (en) | Computer Assisted Weak Pattern Detection and Quantification System | |
KR20210093343A (en) | In-die metrology method and system for process control | |
CN108873604B (en) | Method for inspecting hot spots of photoetching process | |
JP2012252055A (en) | Mask inspection method, mask production method and semiconductor device manufacturing method | |
Tabery et al. | SEM image contouring for OPC model calibration and verification | |
US8741511B1 (en) | Determination of lithography tool process condition | |
TW201931015A (en) | Design criticality analysis augmented process window qualification sampling | |
US8086973B2 (en) | Pattern management method and pattern management program | |
KR20100073374A (en) | Method for detecting defects of semiconductor device | |
JP2004354919A (en) | Verification method for optical proximity correction and verification apparatus | |
Yang et al. | New OPC verification method using die-to-database inspection | |
Howard et al. | Inspection of integrated circuit databases through reticle and wafer simulation: an integrated approach to design for manufacturing (DFM) | |
JP2023524095A (en) | Systems, methods, and program products for manufacturing photomasks | |
WO2023131476A1 (en) | Method and computer program for grouping pattern features of a substantially irregular pattern layout | |
KR20100076471A (en) | Method for fabricating semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: DMO SYSTEMS LIMITED, TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JUANG, SHAUH-TEH;LIN, JASON ZSE-CHERNG;REEL/FRAME:036189/0924 Effective date: 20150727 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: APPLIED MATERIALS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DMO SYSTEMS LIMITED;REEL/FRAME:049768/0076 Effective date: 20190708 |
|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |