JP2004354919A - Verification method for optical proximity correction and verification apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To significantly decrease the computer processing time and the verification time for verifying the optical proximity effect correction relating to the mask data of an LSI compared to a conventional verification method, and to realize high-accuracy verification. <P>SOLUTION: In the verification process of optical proximity correction accompanying the layout design of an LSI and the mask data making process, the layout pattern is extracted and hazardous points of the optical proximity correction are classified into errors with probability of inducing fatal problems and errors with probability of influencing the yield. The priority order of the process is determined based on the classification result. Thus, high-accuracy verification process for the optical proximity correction is performed for a specified pattern requiring high transfer accuracy. Thus, as a whole, the fast and substantial verification process for the optical proximity correction is performed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a verification method and a verification device for optical proximity effect correction for performing a layout design of a semiconductor integrated circuit and a verification process of creating mask data.
[0002]
[Prior art]
In order to prevent a decrease in fidelity of pattern transfer due to an optical proximity effect in a lithography process in a semiconductor integrated circuit (LSI) manufacturing process, an optical proximity effect correction for correcting a mask pattern at the stage of LSI layout design and mask data creation ( Optical Proximity Correction (OPC) processing is performed.
[0003]
Conventional OPC is realized by a rule-based OPC and a model-based OPC. Here, the OPC includes correction of various effects that occur throughout the wafer process, such as resist development and etching, in addition to optical effects.
[0004]
As described in Non-Patent Document 1, for example, the rule-based OPC calculates a correlation table between a line width and a space and a distortion amount due to a proximity effect for each line width and space based on an actual measurement value obtained from a transfer result of a test pattern. This is a method for creating a rule for creating and modifying a layout pattern to implement correction. This rule-based OPC excels in one-dimensionally examining and correcting a nearby figure such as a line and space pattern.
[0005]
On the other hand, the model-based OPC is a correction using a model based on a lithography simulation, in which the model is calibrated based on actual measurement values obtained from a pattern transfer result, and a more detailed complicated process is performed. This is a method that makes it possible to deal with
[0006]
This model-based OPC is good at processing for two-dimensionally examining and correcting the effect of a proximity figure, and requires a longer processing time than the rule-based OPC, but has higher overall correction accuracy. For recent advanced devices, OPC (two-dimensional OPC) for performing the above-described two-dimensional correction is required, and a model-based OPC that can realize this relatively easily is used. Further, a method of correcting by combining rule-based OPC and model-based OPC is also used.
[0007]
However, the accuracy required for OPC becomes stricter as the process generation increases, and the number of patterns that cannot be corrected correctly increases. Further, in the model-based OPC, it is not a practical method to perform all of the calibrations based on the actually measured values in that the measurement time of the actually measured values is long and it is difficult to calibrate a huge amount of data. . Therefore, the following processing method is used.
[0008]
(1) If there are regions with different required accuracy, for example, a logic circuit portion and a memory and a memory peripheral portion in a memory-embedded chip, special models or rules are created and used for each.
[0009]
(2) When a model or rule specialized for each step, such as a wafer processing process after lithography such as mask manufacturing, lithography on a wafer, and etching, can be expected to improve accuracy, for example, in etching, If the tendency of the proximity effect is different from the tendency of the proximity effect in another process, a different model or rule is created, and the correction for each process is sequentially performed according to, for example, the flowchart of the high-precision OPC process illustrated in FIG. (See Patent Document 1).
[0010]
FIG. 13 is a flowchart showing an example of an OPC process in which an etching correction portion and a lithography mask correction portion are divided.
[0011]
According to the processing methods (1) and (2), the optimum OPC is performed for each region and each process, and the accuracy is improved. However, these methods improve the average accuracy of the entire system, and some patterns cannot cope with them, and special measures are required.
[0012]
FIGS. 14A and 14B are pattern examples shown to explain an embodiment of a measure specialized for a pattern in the conventional high-precision OPC processing. FIG. 14A shows an OPC correction before the OPC processing. FIG. 14B shows an example of classification of a target edge pattern, and FIG. 14B shows an example of setting and correction of a space constraint between a line end and an external corner after OPC correction.
[0013]
As shown in FIG. 14A, examples of the classification of the OPC correction target edge include a line end, a line portion, an inner corner, an outer corner, and the like.
[0014]
As shown in FIG. 14 (B), consider a correction using a rule or a model without restrictions (or a default value) for a portion where the line end 83a of the pattern 81 and the external corner 84a of the pattern 82 approach. . In this case, the spaces between the patterns 81 and 82 tend to be too tight due to the correction portions 83b and 84b, and there is a risk that the patterns 81 and 82 may be short-circuited after transfer. Therefore, when performing the OPC process, it is necessary to give a constraint value that can secure an appropriate minimum space S to the line end 83c and the outer corner 84c, and to avoid the risk of short circuit.
[0015]
Therefore, by performing fine correction settings for each type of edge (80a, 80b, 80c, 80d, etc.) classified as shown in FIG. 14A, it is possible to take a countermeasure specialized for each pattern. However, in reality, it is difficult to flexibly respond to new pattern variations.
[0016]
For example, as shown in FIG. 14B, the correction constraint value that can secure an appropriate minimum space between the line end 83c and the outer corner 84c also differs depending on the surrounding environment and the line width of the pattern itself. May be required.
[0017]
Furthermore, for each area on the chip such as a logic section and a memory section (memory cell inside, cell end, cell peripheral section, etc.) in a memory-embedded chip or the like, or for each step of reticle manufacturing, lithography on a wafer, etching process, etc. In addition, even if the optimum OPC is performed, the average accuracy of the whole is improved, and some patterns cannot be dealt with. Therefore, a special measure is required for each pattern. The memory section is divided into the inside of a memory cell, a cell end, a cell peripheral, and the like, and different OPC is performed in each of them.
[0018]
Therefore, it is difficult to start OPC corresponding to most pattern variations at an early stage by the above-mentioned conventional method. For this reason, it is essential to verify the validity of the OPC correction results, and establishing a verification flow is the key to the early start-up of OPC.
[0019]
FIG. 15 shows an example of a flowchart and a configuration for performing a conventional high-precision OPC process and its verification process.
[0020]
In the flow shown in FIG. 15, in the layout design stage of step S1, layout verification is performed using DRC / LVS or the like. Here, DRC (Design Rule Check) is software for verifying whether a designed mask pattern conforms to a design rule (design rule check), and a violation of the design rule is found in the DRC. LVS is software for verifying a layout versus a schematic (Layout vs. Schematic), and is used to verify consistency between an original schematic and its layout. After that, the verified layout design data (Layout) is stored in the layout storage device.
[0021]
Next, in the OPC process in step S2, the OPC process is performed on the verified layout data designed in step S1. In addition to OPC, layer arithmetic processing and the like are appropriately performed. Here, as shown in FIG. 12, the OPC process includes (1) a method of using a model or the like for each area having different required accuracy, and (2) a model specialized in each of mask, lithography, and etching processes. Alternatively, a method of sequentially executing OPC corresponding to each process using a rule can be realized.
[0022]
As described above, in the pre-processing of the OPC processing, extraction and synthesis of the OPC target graphic are performed, and in the post-processing of the OPC processing, the graphic output as mask data is synthesized.
[0023]
Next, in steps S3, S4, and S6, for example, an OPC verification process is performed as shown in FIG.
[0024]
FIG. 16 shows an example of the lithography rule check process in step S4 in FIG. 15 and an example of the transfer image output in step S5.
[0025]
In the OPC rule check in step S3 in FIG. 15, the pattern validity of the pattern after the OPC is checked (whether or not the limit value in the determined mask inspection and fabrication and the limit value in the wafer process are corrected). Compare with the pattern before OPC and verify using DRC. The verification here is performed using a rule-based method, such as checking whether the width and space of the corrected figure are below the specified values, whether the pattern is broken or short-circuited, or whether the correction is extremely large. It shows what you can do.
[0026]
Next, in the lithography rule check in step S4, a pattern before and after the OPC is input, and a simple lithography simulation is performed for each edge (side of the OPC target graphic) after or before the OPC, thereby obtaining the edge of the desired pattern. The data whose deviation is larger than the specified value is output as data D of the dangerous part.
[0027]
Next, in the determination based on the output of the transfer image in step S6, first, a pattern near a dangerous portion including a dangerous portion is read, and a detailed lithography simulation is performed on the pattern near the dangerous portion to obtain a transfer image output.
[0028]
Next, a determination based on a transfer image output is performed to determine whether there is a problem with the OPC result. At this time, the results of the inspection in the mask fabrication and wafer (Wafer) fabrication in step S7 are also fed back as appropriate to determine whether there is a problem with the OPC results.
[0029]
That is, as a result of the determination in step S6, if there is a pattern in question, the process returns to step S1 or step S2, a workaround is examined, optimization such as OPC setting, layout change, etc. I do. As shown in FIG. 12, the verification process is also realized between the subdivided OPC processes.
[0030]
As a result of the determination in step S6, if there is no problem, the 0PC-verified data is converted into data for electron beam (EB) drawing, and the process proceeds to a mask (reticle) manufacturing process shown in step S7.
[0031]
A set including a plurality of photomasks manufactured in the mask manufacturing process is subjected to a mask inspection, and if there is no problem, the process proceeds to a lithography process on a wafer. In this step, a photoresist film is applied on the wafer using a spinner, and the photoresist film is exposed using a photomask (reticle) mounted on a stepper. Further, the process proceeds to a lithography inspection process through processes such as development, rinsing, post-baking, and curing. Further, as a result of the inspection of the photoresist pattern on the wafer, if there is no problem, the process proceeds to an etching process, and the photoresist film formed on the wafer by reactive ion etching (RIE) is used as an etching mask. The thin film below the film is etched. When the etching is completed, the process proceeds to the inspection of the etching shape. If there is any problem as a result of the wafer inspection such as the mask inspection and the lithography inspection and the etching shape inspection, the process returns to the previous processing to correct the OPC setting. If the layout needs to be corrected, the process returns to the previous process to perform the layout correction.
[0032]
In other words, in the flow of the conventional OPC processing and OPC verification processing described above, the lithography simulation time for acquiring a transfer image and the pattern output as a dangerous place as a result of the lithography simulation are analyzed, and the time and the number of steps for examining a countermeasure are considered. Are enormous, and there is a problem that a lot of time is required for verification.
[0033]
In addition, a flow of performing a lithography rule check after each OPC process for each region and each process, and then performing a detailed simulation of a transferred image must be repeatedly performed, which requires a great deal of time until the manufacture of a semiconductor integrated circuit. Cost me.
[0034]
Conventionally, in each process or each region, every time a pattern is determined to be non-conforming, the process returns to the beginning of the flow and changes the OPC setting or changes the layout design. Had to take a lot of time.
[0035]
Furthermore, although the OPC settings are changed based on the OPC verification results to improve the accuracy, there is a problem of accuracy deterioration due to side effects on other patterns, and it becomes difficult to optimize the OPC. I have.
[0036]
Further, in the conventional OPC and OPC verification flow represented by the flow shown in FIG. 15, it is difficult to reduce the number output as a dangerous part in the lithography check, and it takes a lot of time for verification. In particular, the time and man-hours for lithography simulation for obtaining a transfer image output and for analyzing what is output as a dangerous spot and studying countermeasures have become enormous.
[0037]
[Patent Document 1]
JP-A-11-102062
[0038]
[Non-patent document 1]
Otto et. al. , "Automated Optical Proximity Correction-A Rules-Based Approach", SPIE Optical / Laser Microlithography VII, March 1994.
[0039]
[Problems to be solved by the invention]
As described above, in order to prevent a decrease in the fidelity of pattern transfer due to an optical proximity effect in a lithography process in manufacturing an LSI, an OPC process for correcting a mask pattern is performed in a mask data creation stage. However, due to the recent miniaturization of the semiconductor process, the accuracy required for the OPC process has become severe, and there has been a problem that it takes an enormous amount of time for OPC verification.
[0040]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and significantly reduces the computer processing time and the verification time as compared with the conventional OPC verification method, and realizes the optical proximity effect that can realize high-precision OPC verification. It is an object to provide a correction verification method and a verification device.
[0041]
[Means for Solving the Problems]
The optical proximity correction verification method of the present invention extracts a layout pattern of a semiconductor integrated circuit and removes the risk of the optical proximity correction from errors and yields that may cause fatal problems. A classification step of classifying the error into a certain error; and a step of determining a priority order of processing based on a result of the classification by the classification step.
[0042]
The optical proximity correction verification apparatus of the present invention extracts a layout pattern of a semiconductor integrated circuit, and identifies a dangerous location of the optical proximity correction that may affect errors and yield that may cause a fatal problem. It is characterized by comprising classification processing means for classifying an error, and processing means for determining a priority order of processing based on a result of classification by the classification processing means.
[0043]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0044]
<First embodiment>
FIG. 1 shows a high-precision OPC according to the first embodiment of the present invention and an overall flow (flowchart) of its verification processing, and also schematically shows an OPC verification apparatus according to the first embodiment of the present invention. 1 shows the configuration.
[0045]
This high-precision OPC flow is different from the conventional high-precision OPC flow described with reference to FIG. 15 in that a dangerous part filtering process is added as a step S5 between steps S4 and S6. Others are almost the same.
[0046]
That is, in the high-precision OPC flow shown in FIG. 1, in step S1, a layout design is performed, and layout (Layout) data A is registered. In this layout design stage, a layout design is performed so that an OPC non-conforming pattern extracted by pattern matching becomes an OPC conforming pattern.
[0047]
Next, OPC processing and its verification processing are performed in steps S2 to S7. First, in the OPC processing in step S2, in addition to the OPC processing, a layer arithmetic processing and the like are appropriately performed. In the OPC process, the difference between the mask pattern and the pattern transferred onto the wafer is calculated based on the layout design data A obtained in step S1, and OPC is performed on the mask pattern data in advance. At this time, as illustrated in FIG. 12, (1) a method of using a model or the like for each region where the required accuracy is different, and (2) a model or rule specialized for each process of mask, lithography, and etching. Thus, a method of sequentially executing OPC corresponding to each step can be realized.
[0048]
Next, in steps S3 to S6, an OPC verification process is performed. First, in the OPC rule check in step S3, the validity of the pattern after OPC is compared with the pattern before OPC, and verification using DRC or the like is performed. The verification here is performed by a rule-based method, such as checking whether the width and space of the corrected figure are below the specified values, whether the pattern is broken or short-circuited, or whether the correction is extremely large. It shows what you can do.
[0049]
Next, in the lithography rule check in step S4, it is verified whether or not there is a place (dangerous place) at which there is a risk due to a defect in the pattern transferred on the wafer. That is, for example, as shown in FIG. 16, a pattern before and after the OPC is input, and a simple lithography simulation is performed for each edge after the OPC (a side of the OPC target graphic), so that the edge of the desired pattern is determined. The data whose deviation is larger than the specified value is output as the data D of the dangerous part.
[0050]
Next, in the dangerous place filtering processing in step S5, the data D of the dangerous place output in step S4 is input, and the data is reduced to the minimum necessary number using the data C of the OPC critical area group (or the degree of risk is reduced). The data is output as the data E of the dangerous part to be analyzed (weighted). As a result, the number of input data in the determination process based on the transfer image output that requires a processing time in step S6 is reduced. In addition, by using the weighted risk, a more accurate determination process is performed.
[0051]
FIG. 2 is a flowchart showing an embodiment of the processing for extracting the data C of the OPC critical area group in FIG.
[0052]
In the extraction flow shown in FIG. 2, in step S1, a related circuit pattern is extracted by extracting a critical path or the like based on the layout data A obtained in step S1 of the high-precision OPC processing flow shown in FIG. , Data B of the area relating to the critical path and the like is obtained.
[0053]
Next, in step S2, based on the layout data A, an important pattern is extracted by a graphic processing method such as DRC, and data C of an area extracted by the graphic processing method is obtained.
[0054]
Next, in step S3, based on the layout data A, by using a technique such as manual specification, an area in which OPC is to be corrected with high accuracy is extracted, and data D of the area specified manually is obtained.
[0055]
Next, in step S4, based on the layout data A, the data B, C, and D of the areas extracted in steps S1 to S3 are classified and executed as shown in FIG. Collectively register as E.
[0056]
FIG. 3 is a diagram showing an example of a pattern for explaining an embodiment of the OPC critical area classification processing in steps S1 to S3 in FIG.
[0057]
In FIG. 3, A is an OPC critical area obtained by extracting a critical path or the like, B is an OPC critical area obtained by a graphic processing method, and C (shaded area) is an area in which the two areas A and B overlap (weight). .
[0058]
FIG. 4 is a flowchart showing an embodiment of an OPC critical area extraction process by extracting a critical path or the like in step S1 in FIG.
[0059]
In the extraction flow shown in FIG. 4, in step S1, a critical path is extracted using a path extraction tool or the like, and information C such as elements of related circuits (critical configuration) and net names is registered. The information C may be obtained and registered by another method other than the path extraction.
[0060]
Next, in the LVS processing in step S2, the layout and the circuit are compared to associate them with each other. The element and the net name on the circuit diagram are compared with the corresponding portion of the layout, and the coincidence information E is obtained. register.
[0061]
Next, in step S3, a pattern (figure) on the layout constituting the critical net and the element is extracted, and its information F is registered.
[0062]
Next, in step S4, an area near the critical graphic that affects OPC is extracted, and information G of the OPC critical area is registered.
[0063]
FIG. 5A schematically shows a graphic (whole) having a critical path configuration to explain a part of the embodiment of the extraction flow shown in FIG. FIG. 5B shows an example of a pattern by extracting a part (circle part) in FIG. 5A. In FIG. 5B, reference numeral 51 denotes, for example, a Poly (polysilicon) layer wiring portion, and reference numeral 52 denotes, for example, a metal layer wiring portion.
[0064]
FIG. 5C shows a pattern constituting a critical path of the Poly layer, a figure and a critical area adjacent thereto as an example of the extraction result of the OPC critical area according to the embodiment of the extraction flow shown in FIG.
[0065]
FIG. 6 is a flowchart showing an embodiment of the OPC critical area extraction processing by a graphic processing method such as DRC in step S2 in FIG. FIG. 7 shows an example of a pattern for explaining the embodiment of the extraction flow of FIG.
[0066]
In the extraction flow shown in FIG. 6, in step S1, a wiring pattern finer than a specified value (a thin wiring pattern in which a problem such as disconnection is relatively likely to occur) is extracted, and wiring pattern group information B is registered.
[0067]
Next, in step S2, a pattern composed of a space having a large fitting residue in the OPC modeling is extracted, and the critical graphic information C is registered.
[0068]
Next, in step S3, an area near the critical graphic information C for the OPC is extracted, and the OPC critical area information D is registered.
[0069]
In step S2, a process of extracting a pitch of a pattern that is not good as OPC (which is a severe condition for OPC) may be performed.
[0070]
Further, the graphic processing method such as the DRC may be used if a graphic which is not good as OPC can be extracted by another method.
[0071]
In step S2 in FIG. 2, an OPC critical area is extracted by a graphic processing method such as DRC as described above. Apart from this, an area that does not need to be inspected as OPC (inspection unnecessary area) is also extracted. You may make it extract.
[0072]
FIG. 8 is a flowchart showing another embodiment (a flow of extracting an unnecessary inspection area) of the extraction processing of the OPC critical area by the graphic processing method such as the DRC in step S2 in FIG.
[0073]
In the extraction flow shown in FIG. 8, in step S1, a wiring pattern thicker than a specified value (a thick wiring pattern in which a problem such as disconnection is relatively unlikely to occur) is extracted, and wiring pattern group information B is registered.
[0074]
Next, in step S2, a space pattern in which the space with other wiring (space) is larger than a specified value is extracted by OPC modeling, and the non-inspection target graphic area (inspection unnecessary area) information C is registered.
[0075]
Next, in step S3, an area near the non-inspection target graphic area information C for the OPC is extracted and registered as a part of the OPC critical area information D.
[0076]
FIG. 9 shows an example of a layout on a chip for describing an embodiment of the process of extracting the OPC critical region by manual designation in step S3 in FIG.
[0077]
As shown in FIG. 9, when cell areas are arranged adjacent to each other on an LSI chip, a boundary area between adjacent cell areas is manually designated as an OPC critical area or an inspection unnecessary area. At this time, a graphic pattern overlapping with the boundary area can be extracted for each wiring layer in the cell area, and the vicinity of the graphic pattern can be designated as an OPC critical area.
[0078]
FIG. 10 is a flowchart showing an example of the dangerous part filtering (analysis target dangerous part extraction) processing in step S5 in FIG.
[0079]
In the extraction flow shown in FIG. 10, in step S1, the error amount of a dangerous place is classified according to the magnitude of a designated value, and information A1 of the dangerous place is registered.
[0080]
Next, in step S2, the presence / absence of a relationship with the OPC critical area is checked for the information A1 of the dangerous place, the related information is classified by the type of the critical area, and the information D is registered.
[0081]
Next, in step S3, a dangerous location error amount larger than the specified value and a dangerous location error amount small but related to the OPC critical area are registered as analysis-target dangerous location information E. In this case, the risk points to be analyzed relating to the OPC critical area are classified into levels according to the type of the OPC critical area, and are used as one of the judgment materials for the result judgment in step S6.
[0082]
Here, the magnitude of the dangerous location error amount will be described.
[0083]
An error with a small dangerous part error amount is not a fatal error such as a disconnection or a short circuit, but an error that may lower the yield. As shown in the error histogram of FIG. 2, the number of errors usually increases as the number of errors, and it is difficult to check all of them in time. Therefore, effective verification is performed by extracting errors to be checked from all errors using the OPC critical area.
[0084]
The one with a large dangerous part error amount is an error that may cause a fatal problem such as disconnection or short circuit. Basically, all errors must be checked, but if this number is larger than the specified value, the validity of the OPC itself will be doubted. In this case, a check is first performed from a portion related to the OPC critical area.
[0085]
FIGS. 11A and 11B show an example of a pattern for describing an embodiment of the analysis-target dangerous portion extraction processing in the embodiment shown in FIG.
[0086]
FIG. 11A shows a dangerous portion obtained by the lithography check and an OPC critical region extracted by using various methods.
[0087]
FIG. 11 (B) shows the result of filtering the dangerous locations (analytical dangerous locations). Here, in the filtering, one in which the dangerous location error amount is larger than the specified value and one in which the dangerous location error amount is smaller than the specified value but related to the OPC critical area are left. Levels (Level1, Level2,...) Indicating the degree of error importance are assigned to the analysis risk locations, and can be appropriately used in the analysis work.
[0088]
As described above with reference to FIGS. 2 to 11, after performing the dangerous part filtering processing in step S5 in FIG. 1, in the determination based on the transfer image output in step S6 in FIG. By executing a detailed lithography simulation on the other hand, a transfer image output is obtained as shown in FIG. Then, it is determined whether there is a problem in the OPC result.
[0089]
Whether or not there is a problem with the OPC result is determined by appropriately feeding back the results of the inspection in the mask fabrication and wafer fabrication shown in step S7 in FIG. As a result of the determination, if a problematic pattern exists, a countermeasure or the like is examined, and optimization such as OPC setting and layout change are dealt with. As shown in FIG. 12, the verification process is also realized between the subdivided OPC processes.
[0090]
As described above, in the high-precision OPC flow, a detailed simulation for obtaining a transfer image at the time of verifying a lithography rule check result (an OPC dangerous portion) requires a great deal of time. At this time, by classifying dangerous parts that are frequently output by the lithography rule check, and performing a check focusing on a portion related to the OPC critical area preferentially based on the classification result, it is possible to eliminate useless simulation and OPC verification. Can be reduced. Dangerous locations that may affect the yield and critical locations such as disconnection or short circuit may be classified by OPC critical area type to achieve more accurate OPC verification. can do.
[0091]
【The invention's effect】
As described above, according to the present invention, when verifying the optical proximity effect correction with respect to the LSI mask data, the computer processing time and the verification time are significantly reduced as compared with the conventional verification method, and the high-precision verification is performed. It is possible to provide a verification method and a verification apparatus for optical proximity correction that can realize the above.
[Brief description of the drawings]
FIG. 1 is a diagram showing an overall flow of a high-precision OPC and a verification process thereof according to a first embodiment of the present invention, and a schematic configuration of a verification device.
FIG. 2 is a flowchart showing an embodiment of a process for extracting data C of an OPC critical area group in FIG. 1;
FIG. 3 is a view showing an example of a pattern for explaining an embodiment of an OPC critical area classification process in steps S1 to S3 in FIG. 2;
FIG. 4 is a flowchart showing an embodiment of an OPC critical area extraction process by extracting a critical path or the like in step S1 in FIG. 2;
FIG. 5 is a view showing an example of a pattern for explaining a part of the embodiment of the extraction flow shown in FIG. 4;
FIG. 6 is a flowchart showing an embodiment of an OPC critical region extraction process by a graphic processing method such as DRC in step S2 in FIG. 2;
FIG. 7 is a view showing an example of a pattern for explaining an embodiment of the extraction flow of FIG. 6;
FIG. 8 is a flowchart showing another embodiment of an OPC critical area extraction process by a graphic processing method such as DRC in step S2 in FIG. 2;
FIG. 9 is a diagram showing an example of a layout on a chip for describing an embodiment of an OPC critical region extraction process by manual designation in step S3 in FIG. 2;
FIG. 10 is a flowchart showing an example of a dangerous part filtering process in step S5 in FIG. 1;
FIG. 11 is a view showing an example of a pattern for explaining an embodiment of a process of extracting a dangerous part to be analyzed in the embodiment shown in FIG. 10;
FIG. 12 is a flowchart showing an example of a conventional high-precision OPC process.
FIG. 13 is a flowchart showing an example of a conventional OPC process in which an etching correction portion and a lithography mask correction portion are divided.
FIG. 14 is a pattern diagram for explaining an embodiment of a measure specialized for a pattern in the conventional OPC process.
FIG. 15 is a flowchart showing an overall flow of conventional high-precision OPC and its verification processing.
FIG. 16 is a view for explaining an example of lithography rule check processing in step S4 in FIG. 15 and output of a transferred image in step S5.

Claims (10)

A layout step of extracting a layout pattern of the semiconductor integrated circuit and classifying a dangerous portion of the optical proximity correction into an error that may cause a fatal problem and an error that may affect the yield,
Determining a priority order of processing based on a result of the classification in the classification step. The method further includes a critical region extraction step of extracting a critical region of the optical proximity effect correction,
The classification step extracts a dangerous place where a fatal problem may occur, or a dangerous place which may affect the yield, and extracts the extraction result and the optical proximity extracted by the critical area extraction step. 2. The method according to claim 1, wherein errors are classified by examining the relationship between the effect correction and the critical region, and a portion where the classification is duplicated is reduced. The classifying step classifies a dangerous portion of the optical proximity correction for each type of the critical region extracted in the critical region extracting step, and a portion where the classification is duplicated and / or a portion which is less likely to affect the yield. 3. The method for verifying optical proximity effect correction according to claim 2, wherein: 4. The optical proximity method according to claim 2, wherein in the critical area extracting step, the critical area is extracted by using a critical path extraction and a circuit comparison for a pattern corresponding to an area that becomes critical in circuit operation. Verification method of effect correction. The critical region extracting step is to extract the critical region from a pattern having a space, width, or the like that is a severe condition in terms of optical proximity correction or lithography and processing, using a design rule check, a graphic processing command, and the like. The method for verifying optical proximity correction according to claim 2 or 3, wherein: 6. The optical proximity method according to claim 5, wherein the critical area extraction step extracts a wiring pattern smaller than a specified value and an area near a pattern formed by a space having a large fitting residue in modeling of optical proximity correction. Verification method of effect correction. 6. The method according to claim 5, wherein the critical area extracting step further extracts an area near a wiring pattern thicker than a specified value and a space pattern larger than the specified value as a graphic area (inspection unnecessary area) not to be inspected. The verification method of the optical proximity correction described above. 3. The critical region extracting step, wherein the critical region is extracted manually from a pattern having a space, a width, or the like, which is a severe condition in terms of optical proximity correction or lithography and processing. Or the verification method of the optical proximity effect correction according to 3. The step of extracting a pattern corresponding to an area that becomes critical in circuit operation as a critical area by using a critical path extraction and circuit comparison; and a step of optical proximity correction or lithography, a processing process. A step of extracting the critical region from a pattern having a space, width, or the like, which is a severe condition by using a design rule check, a graphic processing command, and the like, and a condition that is severe in terms of optical proximity correction or lithography and a processing process. 4. The method according to claim 2, further comprising the step of manually extracting the critical region from a pattern having a space, a width, and the like. Classification processing means for extracting a layout pattern of the semiconductor integrated circuit, and classifying a dangerous portion of the optical proximity correction into an error that may cause a fatal problem and an error that may affect the yield,
Means for determining a priority order of processing based on a result of the classification by the classification processing means.

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