CN116888599A

CN116888599A - Method and device for layout of circuit units of integrated circuit

Info

Publication number: CN116888599A
Application number: CN202180093965.8A
Authority: CN
Inventors: 陈翰轩; 王智生; 许若圣; 戴方明; 张锐
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-05-21
Filing date: 2021-05-21
Publication date: 2023-10-13
Also published as: WO2022241782A1

Abstract

The application provides a circuit unit layout method and device of an integrated circuit, which are applied to the technical field of integrated circuit layout rules. The method comprises the following steps: legal placement positions which are obtained in the current layout of the integrated circuit and can be used for placing the first circuit units are required to meet first conditions; the layout prediction model outputs a prediction result based on the current layout and legal placement positions, so that the position for placing the first circuit unit in the first area is obtained according to the prediction result; the first condition is set according to the placement rule of the circuit unit. The method obtains the legal placement position of the first circuit unit through the first condition, and can improve the layout quality of the integrated circuit.

Description

Method and device for layout of circuit units of integrated circuit

Technical Field

The present application relates to the field of integrated circuit layout planning, and in particular, to a method and apparatus for layout of circuit cells of an integrated circuit.

Background

The integrated circuit layout is a step of physical design of a very large scale integrated circuit (very large integrated circuit, VLSI), and mainly determines placement positions of circuit cells in the integrated circuit, and can be further subdivided into macro-cell layout (MP), overall layout and detailed layout, wherein MP is the first step of the layout stage, and the layout quality has a significant effect on the final physical design index.

The existing commercial MP tools are poor in placement quality, and the evaluation indexes of the layout results of the commercial MP tools cannot meet the design requirements. The exploration of an MP algorithm with automation, rapidness and high quality has great significance for shortening the physical design period and improving the development efficiency and layout quality of an integrated circuit.

Disclosure of Invention

In order to solve the above-mentioned problems, embodiments of the present application provide a method and an apparatus for layout of circuit cells of an integrated circuit, which can obtain legal placement positions of circuit cells in a layout area of the integrated circuit based on a first condition, so as to improve layout efficiency and quality of layout results of the integrated circuit.

In a first aspect, an embodiment of the present application provides a circuit cell layout method of an integrated circuit, including: acquiring the current layout of the integrated circuit; the current layout includes: a first region in which the circuit cells are not laid out; determining a plurality of legal placement positions for placing the first circuit unit in the first area; the layout prediction model outputs a prediction result based on the current layout and a plurality of legal placement positions; and determining the position for placing the first circuit unit in the first area according to the prediction result.

In the embodiment, a plurality of legal placement positions capable of placing the first circuit unit are obtained in an undeployed area, the position for placing the first circuit unit is obtained according to a layout prediction model based on the prediction results of the legal placement positions, and the first circuit unit is placed at the legal position, so that the legality of the layout of the first circuit unit can be improved, and the layout quality of an integrated circuit is improved; the plurality of legal placement positions are used as the prediction basis of the layout prediction model, compared with the position of the first circuit unit searched in the layout area, the searching range is reduced, and the layout efficiency of the integrated circuit can be improved.

In one possible embodiment, the legal placement location comprises: the legal placement position is located at an angular position of the first area and/or at an edge position of the first area.

According to the embodiment, the angular position and/or the edge position of the first area are used as legal placement positions, the purpose of placing the circuit units by side or by angle can be achieved, and the layout quality can be improved.

In a possible embodiment, the angular position comprises an angular position based on vertices of circuit cells already laid out in the current layout and/or an angular position based on vertices of the first area.

According to the embodiment, the angle position formed by the vertexes of the laid-out circuit units and/or the vertexes of the first area is used as the legal placement position, so that the purpose that the circuit units are placed according to the leaning edge or the leaning angle can be achieved, and the layout quality can be improved; the angular positions formed by the vertexes of the laid-out circuit units are used as legal placement positions, and when the angular positions formed by the vertexes of the first area are occupied, the circuit units can be placed in order, so that the quality of circuit layout is improved.

In one possible embodiment, the legal placement location further includes a location satisfying at least one of: after the first circuit unit is placed at the legal placement position, the first circuit unit is not overlapped with the circuit unit already placed in the current layout; after the first circuit unit is placed at the legal placement position, the first area does not generate a suspension area; after the first circuit unit is placed at the legal placement position, the first area does not generate a closed area; or legal placement positions are positioned in the first area and are in angular positions formed by vertexes of the laid-out circuit units which belong to the same group with the first circuit units; wherein the functions of the plurality of circuit units in the same group have a correlation.

According to the embodiment, the positions where the circuit units are not overlapped and the placing areas are not suspended and are not closed are used as legal placing positions, so that the conditions that the circuit units are overlapped, suspended areas and closed areas in the integrated circuit after layout can be avoided, and the layout quality is reduced; the angle positions formed by the vertexes of the laid-out circuit units belonging to the same group are used as legal placement positions, so that the purpose of placing the units of the same group together can be realized, and when the circuit units are grouped according to the functions of the circuit units, the circuit units can be placed more reasonably, thereby improving the quality of circuit layout.

In one possible implementation, determining, according to the prediction result, a position of the first circuit unit in the first area, where the first circuit unit is placed, includes: and determining the position of the first circuit unit in the first area according to the probability of each legal placement position in the legal placement positions.

According to the embodiment, the placement probability of each legal placement position is predicted through the layout prediction model, and the position of the first circuit unit is determined according to each probability, so that the position of the first circuit unit in the layout is more reasonable.

In one possible implementation, determining the location of the first circuit unit in the first area according to the probability of each legal placement location in the plurality of legal placement locations includes: and determining the legal placement position with the highest probability among the legal placement positions as the position for placing the first circuit unit.

According to the embodiment, the legal placement position with the highest probability is selected as the position of the first circuit unit, so that the placement position of the first circuit unit in the area is more reasonable, and the layout quality is improved.

In one possible implementation, determining the location of the first circuit unit in the first area according to the probability of each legal placement location in the plurality of legal placement locations includes: and extracting the legal placement positions according to the probability of each legal placement position in the legal placement positions to obtain the legal placement position for placing the first circuit unit.

In this embodiment, the legal placement positions are sampled based on the probability of each legal placement position, so as to obtain the position of the first circuit unit, thereby obtaining the position of the first circuit unit.

In one possible embodiment, the first circuit unit comprises a macro-unit.

In a second aspect, an embodiment of the present application further provides a circuit cell layout apparatus of an integrated circuit, the apparatus including: an acquisition module for acquiring a current layout of the integrated circuit; the current layout includes: a first region in which the circuit cells are not laid out; a first determining module, configured to determine a plurality of legal placement positions for placing the first circuit unit in the first area; the prediction module is used for outputting a prediction result based on the current layout and a plurality of legal placement positions by the layout prediction model; and the second determining module is used for determining the position for placing the first circuit unit in the first area according to the prediction result.

In one possible embodiment, the legal placement location comprises: the legal placement position is located at an angular position of the first region or at an edge position of the first region.

In one possible implementation, the layout prediction model outputs a probability of being each legal placement position of the plurality of legal placement positions, and the second determining module is specifically configured to: and determining the position of the first circuit unit in the first area according to the probability of each legal placement position in the legal placement positions.

In one possible implementation, the second determining module is specifically configured to: and determining the legal placement position with the highest probability among the legal placement positions as the position for placing the first circuit unit.

In one possible implementation, the second determining module is specifically configured to: and extracting the legal placement positions according to the probability of each legal placement position in the legal placement positions to obtain the legal placement position for placing the first circuit unit.

In one possible embodiment, the first circuit unit comprises a macro-unit.

In a third aspect, an embodiment of the present application further provides an integrated circuit layout apparatus, including: a processor and a transmission interface, the processor being configured to invoke program instructions stored in the memory to cause the integrated circuit layout apparatus to perform the method of the above-described first aspect and alternative embodiments thereof.

In a fourth aspect, embodiments of the present application also provide a computing device, the computing device comprising: the computer program product comprises a memory and a processor, the memory storing computer instructions which, when executed by the processor, implement the method of the first aspect and alternative embodiments thereof.

In a fifth aspect, embodiments of the present application also provide a computer readable storage medium storing computer program code which, when executed by a computing device, implements the method of the first aspect and alternative embodiments thereof.

In a sixth aspect, embodiments of the present application also provide a computer program product comprising instructions which, when executed by a computer or processor, cause the computer or processor to carry out the method of the first aspect and alternative embodiments thereof.

The technical effects obtained in the second to sixth aspects described above are similar to the technical effects obtained in the corresponding technical means in the first aspect, and are not described here again.

Drawings

FIG. 1 is a schematic diagram of a macro cell layout result provided by the present application;

FIG. 2 is a schematic diagram of reinforcement learning training provided by the present application;

FIG. 3 is a schematic diagram of a macro cell layout provided by the present application;

FIG. 4 is a flow chart of an integrated circuit layout method according to an embodiment of the present application;

FIG. 5 is a flow chart of a method for training a layout prediction model provided by an embodiment of the present application;

fig. 6a and fig. 6b are schematic diagrams illustrating legal placement positions located at edge positions in a blank layout according to an embodiment of the present application;

FIG. 6c is a schematic view of an angular position in a blank layout according to an embodiment of the present application;

FIG. 6d is a schematic diagram of legal placement positions at angular positions in a blank layout according to an embodiment of the present application;

FIG. 6e is a schematic diagram of angular positions in a non-blank layout according to an embodiment of the present application;

FIGS. 6f and 6g are schematic diagrams illustrating legal placement positions in a non-blank layout according to an embodiment of the present application;

FIG. 7a is a schematic diagram of a layout of macro cells without overlapping according to an embodiment of the present application;

FIG. 7b is a schematic diagram of a macro-cell overlay layout according to an embodiment of the present application;

FIG. 8 is a schematic layout of a suspended area according to an embodiment of the present application;

FIG. 9 is a schematic layout of a closed area provided by an embodiment of the present application;

FIG. 10 is a schematic diagram of a layout of two macro-cells belonging to the same group according to an embodiment of the present application;

FIG. 11a is a schematic diagram illustrating a change in elevation line before and after macro-cell placement according to an embodiment of the present application;

FIG. 11b is a schematic layout of a macro cell with a floating region according to an embodiment of the present application

FIGS. 12a and 12b are schematic diagrams illustrating layouts of two macro-cell generation enclosed areas according to embodiments of the present application;

FIG. 12c is a schematic diagram of a layout of two macro-cells without creating a closed region according to an embodiment of the present application;

FIG. 13 is a schematic illustration of marking a composite placement location provided by an embodiment of the present application;

FIG. 14 is a schematic diagram of obtaining placement positions according to probability distribution sampling provided by an embodiment of the present application;

FIG. 15 is a flowchart of a method for circuit cell layout using a layout prediction model according to an embodiment of the present application;

fig. 16 is a schematic view of a layout apparatus according to an embodiment of the present application;

FIG. 17 is a schematic diagram of a computing device according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be described below with reference to the accompanying drawings.

In describing embodiments of the present application, words such as "exemplary," "such as" or "for example" are used to mean serving as examples, illustrations or explanations. Any embodiment or design described herein as "exemplary," "such as" or "for example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "such as" or "for example," etc., is intended to present related concepts in a concrete fashion.

In the description of the embodiments of the present application, the term "and/or" is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a alone, B alone, and both A and B. In addition, unless otherwise indicated, the term "plurality" means two or more. For example, a plurality of systems means two or more systems, and a plurality of screen terminals means two or more screen terminals. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating an indicated technical feature. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

Before describing the scheme of the embodiment of the application, the netlist data, macro cells, macro cell layout, standard cells, standard cell arrangement, wire winding arrangement, evaluation indexes, neural networks and reinforcement learning which appear in the embodiment of the application are explained.

Netlist data is data describing the connections of the cells in an integrated circuit. The macro cell (macro-cell) to be placed, the standard cell (standard-cell), the connection relationship between the macro cell and the standard cell, and the layout area may be included. Optionally, the netlist data may also include information such as process parameters of the integrated circuit.

Macro-cells (macro-cells), which are predefined logic function implementing units composed of flip-flops, arithmetic logic units, hardware registers, etc. that are higher in abstraction level than logic gates, are placed on a silicon wafer as a whole in VLSI design. Each macro-cell may also correspond to a different logical function and each macro-cell may also correspond to a different size.

Macro-cell placement (MP) is a process of placing macro cells into a placement area. As shown in fig. 1, the layout area is regarded as a rectangular area including an upper edge (Top), a lower edge (Bottom), a Left edge (Left), and a Right edge (Right), and macro cells are numbered b1, b2, …, and b17, and are represented by small rectangles in the layout area. The macro cell layout is specifically understood as placing macro cells b1, b2, …, b17 in a rectangular area surrounded by Top, bottom, left and Right sides.

The standard unit is a tiny basic circuit unit, and can comprise various units such as an inverter, an AND gate, a register, a selector, a full adder and the like. Similarly, each standard cell corresponds to one or more macro cells, and it is understood that the sizes and driving capabilities of macro cells in the macro cells may be the same or different, and the sizes of macro cells may be integral multiples of the basic size or the minimum size, which means a process of placing standard cells in an area where macro is not arranged in the layout area after the macro cell layout is finished.

The wiring (routing) connects macro-cells and standard-cells by wires according to the connection relationship.

And the evaluation index is used for evaluating the layout result of the layout area. Specifically, the method comprises the following steps: wire length (wire length): refers to the total length of the line connecting macro-cells and standard-cells in the layout area; congestion degree (congestion): refers to the line density of the most dense areas in the layout area, the lines in the layout area cannot be too dense; timing (timing): after the macro and standard cells are connected, the time delay of each path comprises the maximum time delay (WNS) and the total time delay (TNS); it will be appreciated that the smaller the data values of the aforementioned metrics, the better the layout quality of the current layout.

Neural networks (neural networks), which are mathematical models, after training can output corresponding results at a given input. Neural networks are specifically a class of mathematical algorithm models that mimic the structure and function of biological neural networks (the central nervous system of animals). A neural network may include a plurality of different functional neural network layers, each layer including parameters and computational formulas. Different layers in the neural network have different names according to different calculation formulas or different functions. For example, the layer performing the convolution calculation is called a convolution layer, and the convolution layer is often used to perform feature extraction on an input signal (such as an image). A neural network model may also be composed of a combination of a plurality of existing neural network models. Neural network models of different structures may be used for different scenarios (e.g., classification, recognition, etc.) or provide different effects when used for the same scenario. The neural network model structure comprises one or more of the following: the number of layers of the network layers in the neural network model is different, the sequence of the network layers is different, and the weight, the parameters or the calculation formula in each network layer is different.

Reinforcement learning (reinforcement learning, RL), also known as re-excitation learning, evaluation learning or reinforcement learning, is a method of machine learning, and achieves maximization of return of an agent by the agent continuously learning in interaction with the environment, thereby achieving a set learning objective. Alternatively, in practical applications, the reinforcement learning algorithm may be any one of a policy gradient (policy gradient) algorithm, a Q learning (Q-learning) algorithm, a deep Q network (deep Q network) algorithm, and an actor evaluation (actor) algorithm. FIG. 2 is a schematic diagram of a reinforcement learning process provided in the present application, as shown in FIG. 2, in an interactive learning of an agent and an environment, a current state of the environment is input into a prediction model; then, the current action of the intelligent agent is obtained according to the output of the prediction model; then, updating the current state of the environment based on the current action of the intelligent agent, and completing one-time interaction between the intelligent agent and the environment; before the state is input into the prediction model, the parameters of the prediction model are updated according to the rewards of the last action of the intelligent agent and the loss functions set by reinforcement learning, so that the next action of the intelligent agent can obtain higher rewards. In one example, after the number of interactions of the agent with the environment is satisfied, the rewards of the agent are accumulated according to the rewards value fed back by the environment in each interaction, one reinforcement learning of the agent is finished, the agent performs reinforcement learning for a plurality of times, and the training of the prediction model is finished when the termination condition is satisfied.

In one example, the predictive model may be a policy network for generating an action policy of an agent according to a state of an environment, the agent selecting an action from a set of actions corresponding to the action policy; alternatively, the action policy may be a probability distribution corresponding to each action in the action set, where the agent randomly samples each action from the probability distribution, so as to obtain the current action. When the policy network outputs a probability distribution, a softmax classification layer may be included in the policy network for outputting the corresponding probability. The predictive model may also include a value network for calculating rewards for the agent to perform actions based on the status of the environment, and updating parameters of the predictive model based on the rewards of the agent after obtaining the rewards of the agent.

In one related art integrated circuit layout, a mixed-size is used for the integrated circuit layout. The method specifically converts the layout problem of the integrated circuit into a mathematical programming problem, and optimizes and solves the placement positions of the macro units and the standard units. In one example, two evaluation indexes of the line length and the line density between two circuit units are approximated as an optimization function according to a formula (1), and a random optimization algorithm is used for planning and solving, so that the placement positions of macro units and standard units meeting design conditions are obtained.

In the formula (1), WL (E, x, y) represents the length of the E-th line between the cell x and the cell y in the layout, E represents the total number of lines between x and y, D (x, y) represents the line density between the cell x and the cell y in the layout, lambda ₁ And lambda (lambda) ₂ The weights of the line length index and the line density are respectively.

The related technology is that the placement positions of macro cells and standard cells are searched and verified in the whole layout area, the search range is large, the layout efficiency is low, and the obtained layout quality is poor.

In another related art integrated circuit layout, a neural network trained by reinforcement learning is used to obtain probability distribution of placement locations to implement macro cell layout. Specifically, before each macro-unit is placed, a neural network is adopted to obtain probability distribution of the placement positions in the current layout, and the placement positions are sampled from the probability distribution to obtain the placement positions of the current macro-units. As shown in FIG. 3, a neural network is utilized to obtain a blank layout S ₀ The probability distribution of the placement positions for placing the macro cells is then sampled from the probability distribution to obtain one placement position and place the macro cells (S in FIG. 3 ₁ Black squares in the layout) such that the layout S is blank ₀ Updated immediately to the layout S ₁ Then the next macro cell is laid out by the same method to obtain a layout S ₂ The process is repeated to complete the layout of all macro cells.

Although the related technology can realize the purpose of automatically arranging macro cells, the problem of poor quality of layout results still exists when macro cell arrangement positions are extracted in the whole area.

Fig. 4 is a flowchart of an integrated circuit layout method according to an embodiment of the present application, which is applied to the layout apparatus 100. As shown in FIG. 4, the method predicts the placement positions of all circuit units in the integrated circuit through a layout prediction model, thereby realizing the layout design of the integrated circuit. Comprising the following steps S401-S403.

In step S401, netlist data of an integrated circuit is obtained.

In this embodiment, the netlist data of the integrated circuit is referred to in the foregoing description and will not be described again here; the integrated circuit may be a circuit component for integrated chip design or may be a complete integrated chip circuit. Wherein a circuit assembly or an integrated chip may comprise a plurality of circuit devices, such as transistors, resistors, capacitors, etc. The integrated circuit may be specifically a circuit implementing any kind of functional use, for example, an application specific integrated circuit for machine learning computing, video processing, encryption or other computation-intensive functions.

In step S402, a layout prediction model is trained from netlist data of an integrated circuit.

In an alternative, a layout prediction model may be obtained by training a reinforcement learning algorithm, which may be the prediction model described in the reinforcement learning section above, and the specific training process of the layout prediction model will be described in detail below in connection with fig. 5.

In step S403, the layout of the integrated circuit is determined using the trained layout prediction model.

In this embodiment, after the training of the layout prediction model is finished, the layout prediction model is used to predict the placement position of the first circuit unit in the integrated circuit, so as to implement the layout design of the integrated circuit, where the first circuit unit may be a macro unit of the integrated circuit. Specifically, the specific procedure of this step will be described in detail in the following description with reference to fig. 13.

FIG. 5 is a flowchart of a method for training a layout prediction model using a reinforcement learning algorithm, which is applied to the layout apparatus 100, according to an embodiment of the present application. The method is based on circuit units (comprising macro units and standard units), unit connection relations and layout area parameters in netlist data of an integrated circuit, and in the training process, the placement position of a first circuit unit is regarded as the action of an agent, the legal placement position in the current layout is regarded as the action set of the agent, the layout of the integrated circuit is regarded as the state of the environment, and the evaluation indexes of the layout are regarded as rewards and rewards of the agent. The model training process according to the embodiment of the present application will be described in detail below by taking the first circuit unit as an example of a macro unit.

As shown in fig. 5, the method includes the following steps S501 to S507.

In step S501, the current layout of the integrated circuit is acquired.

In this embodiment, the current layout refers to a layout result after one macro cell is placed in a layout area of the integrated circuit, where the current layout may include a first area and a second area, where the first area may be an area in which no macro cell is placed in the current layout, and the second area may be an area in which a macro cell is placed in the current layout. It can be appreciated that if the current layout is the first layout of the integrated circuit, it indicates that the current layout is a blank layout, i.e. the current layout includes only the first area; if the current layout is not the first layout of the integrated circuit, the current layout includes the first region and the second region.

In step S502, a plurality of legal placement positions are obtained as candidates in the current layout of the integrated circuit, where the legal placement positions are used for placing macro cells to be laid out.

In this embodiment, the layout apparatus 100 may determine each layout position in the first area one by one based on a preset first condition, so as to obtain a legal placement position for placing the macro cell to be laid out, where the first condition is satisfied. Specifically, the obtained legal placement position has a shape size matched with the shape size of the macro cell to be laid out. In the layout process, the macro unit is in a fixed form, namely, the shape and the size of the macro unit cannot be adjusted, and the macro unit cannot rotate, mirror deformation and the like. The macro-cell may be in the form of a rectangular area or may be in the form of a polygonal area of another type, and in the following description of the present application, the macro-cell is described as a rectangular area.

In one example, the first condition may be set according to a placement rule or a placement requirement of the macro-cells. It will be appreciated that the number of legal placement positions ultimately obtained may be one or more. In one example, when only one legal placement position is obtained, the legal placement position may be directly used as a position for placing macro-units.

Alternatively, the first condition may include at least one of the following conditions 1 to 5.

Condition 1: the legal placement position is located at an angular position of the first region or at an edge position of the first region. Wherein the angular positions may include angular positions constituted based on vertices of macro-cells already laid out in the current layout and angular positions constituted by vertices of the first region. When the legal placement position is located at an edge position, one edge of the legal placement position coincides with the edge position. When the legal placement position is located at an angular position, an apex of the legal placement position coincides with an intersection of the angular position, and at least one edge of the legal placement position coincides with an intersection line constituting the angular position. It is understood that an angular position includes an intersection point and at least two intersection lines.

It can be understood that one edge position may correspond to one legal placement position for placing a macro unit, or may correspond to a plurality of legal placement positions for placing macro units, and the specific number may be determined according to the length of the macro unit and the length of the edge position.

In one example, when the length of the macro-cell is equal to the length of the edge location, the edge location corresponds to at most one legal placement location for placing the macro-cell; as shown in fig. 6a, the current layout is a square area as shown in fig. 1, and in the current layout, when the length of the macro-cell a is equal to the length of the Top edge, the Top edge corresponds to at most one legal placement position for placing the macro-cell a.

In one example, when the length of a macro-cell is less than the length of an edge location, the edge location may correspond to a plurality of legal placement locations for the macro-cell; as shown in fig. 6b, when the length of the macro-cell a is smaller than the length of the Top edge, the Top edge may correspond to a plurality of legal placement positions (only three positions are shown in fig. 6b by way of example).

It can be understood that when the angular position is an angular position formed by the vertices of the first area, the angular position corresponds to at most one legal placement position for placing the macro-cell; when the angular position is an angular position formed by the vertexes of the laid-out macro cells of the first area, the angular position may correspond to a plurality of legal placement positions for placing macro cells. Specifically, when the current layout is a blank layout, the angular positions of the first region include only the angular positions constituted by the vertices of the first region; accordingly, when the current layout is not a blank layout, the angular position of the first area may further include the aforementioned angular position formed based on the vertices of the macro cells already laid out in the current layout and the angular position formed by the vertices of the first area.

In one example, as shown in fig. 6c, the blank layout may be a square area as previously shown in fig. 1, and when the blank layout is the current layout, the first area of the current layout may be a gray area as shown in fig. 6c, where the first area includes, in addition to four edge positions, angular positions (pentagonal marks) formed by its own four vertices, and where only one legal placement position for placing macro-cells to be laid out may exist at each angular position. Taking the example of macro cell a placement, the legal placement locations (dashed box a) at four angular positions are shown in fig. 6 d.

In one example, after one legal placement location for macro cell A is selected in FIG. 6d, the blank layout shown in FIG. 6c is updated to a non-blank layout as shown in FIG. 6 e. Compared to fig. 6c, the number of edge positions and the number of angular positions of the first region in the current layout shown in fig. 6e are changed; the edge positions include edge positions of the first area (gray area) as shown in fig. 6e, and the angular positions are increased by the angular positions formed by the vertices of the macro cell a on the basis of the positions shown in fig. 6c, that is, the angular positions marked with (1) - (7) in fig. 6 e. It will be appreciated that the lower left vertex of macro cell a in fig. 6e coincides with the lowermost vertex of the blank layout, and therefore these two vertices constitute only one angular position. Wherein macro cell B has been placed, for example, for angular positions (2) (3) (4) (6), only one legal placement position exists at each of these four angular positions, and a specific example is shown in fig. 6d; for the angular positions (1) (5), there may be two legal placement positions on each of these two angular positions, and located on both sides of the intersection point in the angular positions, for a specific example, refer to fig. f; for the angular position (7), there may be four legal placement positions on the angular position, and four directions (upper left, lower left, upper right and lower right) formed by intersecting lines of the angular position, a specific example is referred to in fig. 6g.

Condition 2: after the macro cells are placed at legal placement positions, the macro cells are not overlapped with the macro cells already placed in the current layout. This condition applies in the example of a current layout that is not blank. An exemplary description is made with reference to fig. 7a and 7 b. In fig. 7a, macro cell a is a laid-out macro cell, and the layout position (dashed box B) where macro cell B is laid out is located at an angular position (pentagonal mark in fig. 7 a) formed by one vertex of cell a, when macro cell B is laid out at the position, macro cell B does not overlap macro cell a, and therefore, the layout position (dashed box B) is a legal layout position; for fig. 7B, macro cells a and B are laid out cells, and the layout position (dashed box C) for placing macro cell C is located at an angular position (pentagonal mark in fig. 7 a) formed by one vertex of cell a, when macro cell C is placed at the layout position (dashed box C), macro cell C overlaps macro cell B, and therefore, the layout position (dashed box C) is not a legal placement position.

Condition 3: after the macro units are placed at legal placement positions, a suspension area is not generated in the first area. This condition is equally applicable in examples where the current layout is a non-blank layout. Referring to fig. 8, the layout position (dotted line box B) is located at the angular position shown in fig. 8, and after macro cell B is placed at the layout position (dotted line box B), a floating area is generated below cell B and on the right side of cell a, and therefore, the layout position (dotted line box B) is not a legal placement position.

Condition 4: after the macro units are placed at legal placement positions, no closed area is generated in the first area. This condition is equally applicable in examples where the current layout is a non-blank layout. Referring to fig. 9, the layout position (dotted line frame C) is located at the angular position shown in fig. 8, and after the macro cell C is placed at the layout position (dotted line frame C), a closed area is generated below the macro cell C and to the right of the macro cell a, and thus, the layout position (dotted line frame C) is not a legal placement position.

Condition 5: the legal placement position is located in the first area and is an angular position formed by the macro cells which belong to the same group with the macro cells to be laid out, wherein the functions of the macro cells in the same group have correlation. This condition is equally applicable in examples where the current layout is a non-blank layout. It will be appreciated that the functional presence of a macro-cell is related to the need for data or information from one of the two circuit elements to perform its own function. In one example, two macro-units in the same packet may implement the same functionality.

In one example, the groupings may be categories of macro-cells that are partitioned in terms of their functional relationship and/or their connection relationship to each other at the time of integrated circuit design. In one example, the connection relationship may include a direct connection and an indirect connection, and when two macro-units need to be directly connected, the two macro-units may be divided into one group; the direct connection means that the connection points of two macro units are directly connected and are not connected through the connection points of other macro units or other public nodes; an indirect connection is one in which two macro-cells need to be connected by other circuit elements. It will be appreciated that the macro-cells in the netlist data may be divided into a plurality of groupings, each grouping including one or more macro-cells. Referring to fig. 10, macro cell a and macro cell B have been laid out in the current layout shown in fig. 10, at the time of laying macro cell C, assuming that the obtained legal laying positions may include the three pentagonal-identified positions ((1) to (3)) shown in fig. 10, when it is determined that macro cell B and macro cell C belong to the same group, since the angular position marked by (3) is constituted by the vertex of macro cell B, the angular position marked by (3) is taken as one legal laying position.

In one example, macro cells may be grouped when designing netlist data for an integrated circuit, so that in order to improve the layout quality of the integrated circuit, angular positions of vertices of macro cells belonging to the same group are selected when legal placement positions of the layout macro cells are selected.

In one example, for condition 2, it may be determined whether two macro-cells overlap by the distance of their center points in the current layout. Specifically, the distances D of the center points of the macro cells B and C in both the macro cell length and width directions as shown in FIG. 7B can be calculated _L And D _W When D _L Less than half of the sum of two macro-cell lengths, or D _W Less than two macrocell lengthsWhen the sum is half, the macro cell B and the macro cell C are overlapped, and the position of the macro cell C is not legal. Wherein D is _L And D _W Can be obtained by calculation of coordinates of the center points of the two macro cells.

In one example, for condition 3, it may be determined whether a dangling zone is generated by determining whether one edge of the macro-cell completely coincides with the height line. Specifically, when one edge of the macro-cell is fully coincident with the altitude line, the macro-cell does not generate a suspended area, otherwise, a suspended area is generated. The height line can be determined by coordinates of two endpoints, and can be specifically determined according to four edges, partial line segments of the four edges or line segments obtained by coordinate transformation of partial line segments of the four edges in the blank layout; wherein, in the blank layout, the height line comprises four edges of the blank layout; in the non-blank layout, the height line includes a partial line segment of four sides of the blank layout and a line segment obtained by coordinate transformation of the partial line segment of the four sides.

As shown in fig. 11a, in the blank layout, a height line is included on the Bottom side (the height line is determined according to the coordinates of the two end points of the Bottom side, the thick line represents the height line), and when it is determined that the two end points of the Bottom side of the macro-cell a fall on the Bottom side after the macro-cell a is placed on the Bottom side, that is, the Bottom side of the macro-cell a coincides with the height line on the Bottom side, at this time, the Bottom side includes three height lines, and each height line may be determined by the coordinates of the two end points. With continued reference to fig. 11a, when the coordinates of points in the current layout are represented by the XY coordinate system, two end points at the lower edge of the macro cell a are respectively one end point of the left-side height line and one end point of the right-side height line, and two end points of the middle height line are determined according to the coordinates of the two end points of the macro cell a and the height of the macro cell a, that is, the height line of the overlapping portion moves up to the height of the macro cell a. Referring to fig. 11B, when the macro cell B is placed at the angular position formed by the top left vertex of the macro cell a (dashed box B), it can be seen from fig. 11B that the top edge of the macro cell B does not completely coincide with the middle height line, which indicates that the placement position (dashed box B) is not the legal placement position.

In one example, for condition 4, it may be determined whether two macro-cells constitute a closed region by depending on the solid direction or solid region of the two macro-cells. Specifically, when two macro-cells have at least one same solid direction or solid areas of the two macro-cells have a common area, the two macro-cells do not create a closed area, otherwise the two macro-cells create a closed area. The solid direction of the macro-cell refers to the direction of the edge of the macro-cell coinciding with the height line, and may include up, down, left and right; for example, when the lower side of the macro cell a is in line with the height, the solid direction of the macro cell a is down; it will be appreciated that there may be one or more solid directions for a macro-cell, up to four solid directions. The solid area of the macro unit refers to the area between the edge of the macro unit, which coincides with the height line, and the edge of the first area; for example, when the height line of the Bottom side of the macro cell a coincides with the height line of the Bottom side of the first region, the solid region of the macro cell a is the region between the Bottom side of the macro cell a and the Bottom side of the first region; it will be appreciated that a macro-cell may have one or more solid areas, up to four solid areas; in particular, the macro-cell may also be free of solid areas, i.e. one side of the macro-cell coincides with any one side of the first area. In one example, the edges of the first region may include a Top edge, a Bottom edge, a Left edge, and a Right edge as shown in fig. 1.

As shown in fig. 12a, when the solid direction of the laid-out macro cell a is downward (the area a is the solid area of the macro cell a), and the solid direction of the macro cell C is rightward (the macro cell C does not have the solid area) when the laid-out macro cell C is placed at the layout position shown by the dotted line frame C, if the solid directions of the macro cells are different, it can be determined that the macro cell a and the macro cell C form a closed area, and the layout position shown by the dotted line frame C is not the legal placement position of the macro cell C. As shown in fig. 12b, when the macro cell C to be laid out is placed at the layout position shown by the dashed frame C, the solid area C of the macro cell C is not overlapped with the laid out macro cell a, and the solid area a of the macro cell a is not overlapped with the macro cell C, it can be determined that the two macro cells generate a closed area, and the layout position shown by the dashed frame C is not the legal placement position of the macro cell C; in contrast, as shown in fig. 12C, the solid area a of the macro cell a does not overlap with the macro cell C, but the solid area C of the macro cell C (the area between the lower side of the macro cell C and the Bottom side) overlaps with the macro cell a, it can be determined that the macro cell a and the macro cell C do not generate a closed area, and the layout position shown by the dashed box C is the legal placement position of the macro cell C.

In one example, for condition 5, it may be determined whether the laid-out macro-cells and the macro-cells to be laid out belong to the same group by the number of macro-cells, and when they belong to the same group, the angular positions formed by the vertices of the laid-out macro-cells are taken as legal placement positions. For example, each macro-cell included in each group in the netlist data may be numbered, and when the number of the macro-cell to be laid out and the number of the macro-cell to be laid out are in one group, the macro-cell to be laid out and the macro-cell to be laid out may be considered to belong to the same group.

In step S503, the current layout and the plurality of legal placement positions are input into the layout prediction model, and the output of the layout prediction model is obtained.

In this embodiment, in this step, different marks may be specifically made on a plurality of legal placement positions, and then, the current layout and the marks corresponding to the plurality of legal placement positions are input into the layout prediction model, so as to obtain probability distribution of the plurality of legal placement positions output by the layout prediction model, where the probability distribution includes placement probabilities corresponding to the legal placement positions. The above step S503 will be described below with reference to fig. 13.

Referring to fig. 13, legal placement positions corresponding to 6 legal placement positions (shown by a dashed box) in the left diagram in fig. 12 are marked with different numbers, such as numbers 1 to 6 shown in the right diagram in fig. 13, and then the current layout and numbers corresponding to 6 legal placement positions are input into the layout prediction model, so as to obtain placement probabilities corresponding to the legal placement positions output by the layout prediction model, namely the probability distribution.

Optionally, the layout prediction model may include a policy network and a value network as described above, where the policy network and the value network may be specifically any type of neural network, for example, a convolutional neural network, and the type of the neural network is not specifically limited in the embodiment of the present application, so long as the function of predicting probability distribution of legal placement positions of the present application may be implemented.

Optionally, the evaluation index may include one or more of the foregoing indexes, for example, one or more of wire length (wire length), congestion degree (congestion), timing, maximum delay (WNS), and total delay (TNS), and may further include other evaluation indexes related to the integrated circuit layout, which are not disclosed in the present application, and the embodiment of the present application is not limited in particular.

In step S504, the positions of macro cells to be laid out are obtained based on the output of the layout prediction model.

In this embodiment, the agent samples a legal placement position for each legal placement position based on probability distribution corresponding to each legal placement position output by the layout prediction model, and the legal placement position is used as a position of a macro-cell to be laid out, so as to obtain a current action of the agent. The probability distribution includes a placement probability corresponding to each legal placement position, i.e., one legal placement position corresponds to one probability value.

In one example, position sampling may be implemented using the command range. Choice in the python language, the parameter position in the command range. Choice is set to a list of numbers of legal placement positions, the parameter weights is set to the probability of each legal placement position, and the number of legal placement positions acquired by executing the command may be obtained, thereby obtaining the position of the macro-cell to be laid out.

In one example, assuming that the probabilities of legal placement locations 1-6 are 0.11, 0.1, 0.13, 0.16, 0.3, 0.2, respectively, when sampling in legal placement locations 1-6, each legal placement location is different in probability of being drawn, and legal placement location 5 is the greatest in probability of being drawn, legal placement location 5 is the greatest in probability of being drawn. Referring to fig. 14, assume that a legal placement position 5 is obtained by sampling, the legal placement position 5 is taken as a position of a macro cell to be placed, and the macro cell to be placed is placed at the position. It will be appreciated that when sampling 6 legal placement locations based on the probability of the foregoing assumption, it is also possible to extract other legal placement locations than legal placement location 5.

It can be further understood that the embodiment of the application is not limited to determining the placement position of the macro unit by means of probability sampling, and can also obtain the placement position of the macro unit from legal placement positions by means of various decision methods. For example, the legal placement position with the highest probability in the probability distribution can be used as the placement position of the macro-cell to be laid out. That is, in one example, after the layout prediction model obtains probabilities corresponding to the 6 legal placement positions assumed in fig. 14, it is determined that the placement probability of the legal placement position 5 is maximum, that is, the legal placement position 5 may be selected as the placement position of the macro-unit to be laid out.

Alternatively, in step S505, it is determined whether the macro cell layout is ended, when the layout is ended, step S606 is performed, and when the layout is not ended, step S501 is performed.

In this embodiment, this step can determine whether the macro cell layout of the integrated circuit is complete by comparing the number of macro cells laid out with the number of macro cells in the netlist data. Specifically, when the number of the laid macro cells is smaller than the number of macro cells in the netlist data, it is indicated that the macro cell layout is not finished, and the rest macro cells are not laid out, and the process returns to step S501 to layout the next macro cell; when the number of the placed macro cells is equal to the number of macro cells in the netlist data, it indicates that all macro cells in the netlist data have been placed, and the macro cell placement is finished, and step S506 is performed.

Optionally, in step S506, an evaluation index of the current layout is calculated.

In this embodiment, after all the macro cells in the netlist data are placed, the current layout is subjected to index evaluation according to the set evaluation index.

In one example, after placing all the macro-cells in the netlist data, standard cell placement and wire wrapping placement are performed in the current layout according to the netlist data, and then an evaluation index of the current layout is calculated.

Optionally, in step S507, parameters of the layout prediction model are updated according to the evaluation index.

In this embodiment, the obtained evaluation index value is used as the return of the agent after multiple actions, the parameters of each node in the layout prediction model are adjusted according to the return, then the layout prediction model with updated parameters is used for the next training, and the process is repeated until the training is finished.

In one example, after a macro unit is placed, that is, after the agent makes an action, an evaluation index of the current layout is calculated and used as the reward of the agent for the action, and then the rewards of the agent after multiple actions are accumulated to obtain the rewards of the agent after the multiple actions.

In one example, the layout apparatus 100 may perform multiple training on the layout prediction model, calculate an evaluation index after each training is finished, update parameters of the layout prediction model according to the layout result of the integrated circuit obtained by the training and the evaluation index thereof, and select, when the set number of training is finished, one layout result with the best layout quality from the layout results obtained by the multiple training according to the evaluation index of each training, and output the layout with the finished integrated circuit. In one example, layout apparatus 100 may determine whether to terminate training the layout prediction model based on any one of the training termination criteria. Alternatively, the training process of the layout prediction model may be terminated by determining whether the parameter values of the respective nodes of the layout prediction model converge.

Fig. 15 is a flowchart of a method for performing circuit cell layout of an integrated circuit using a layout prediction model according to an embodiment of the present application, which is applied to a layout apparatus 100. As shown in fig. 15, the method includes steps S1501 to S1504 as follows.

In S1501, the current layout of the integrated circuit is acquired.

In S1502, in the current layout of the integrated circuit, a plurality of legal placement positions are obtained as candidates, where the legal placement positions are used to place macro cells to be laid out.

In S1503, the layout prediction model outputs a prediction result based on the current layout and the plurality of legal placement positions.

In S1504, the positions of macro cells to be laid out are obtained based on the prediction results output by the layout prediction model.

In this embodiment, the specific description of step S1501-step S1504 refers to the descriptions in the foregoing steps S501-S504, and will not be repeated here. And repeatedly executing the steps S1501-S1504 to lay out each macro cell in the netlist data, thereby completing the macro cell layout of the integrated circuit.

In addition, in the standard cell arrangement of the integrated circuit, the method steps in the foregoing method embodiments may also be adopted, where the difference is that the first condition is different, where the first condition may be set according to actual needs, and the present application is not limited to the specific content of the first condition.

In the embodiment of the method, the legal placement positions of the circuit units (such as macro units) to be placed are obtained in the placement area by adopting the first condition, the placement probability distribution corresponding to each legal placement position is obtained by utilizing the placement prediction model trained by reinforcement learning, so that one position is sampled in the legal placement positions to serve as the placement position of the current macro unit, the placement quality of the macro units in the integrated circuit can be improved, and the overall placement quality of the integrated circuit is improved.

Based on the method embodiment shown in fig. 15, the present application further provides a layout device 100, where the layout device 100 is used to implement each step in the method embodiment. The functions of the layout apparatus 100 may be implemented by a software system, a hardware device, or a combination of a software system and a hardware device.

When the layout apparatus 100 is a software apparatus, the layout apparatus 100 may be logically divided into a plurality of modules, each of which may have a different function. Referring to fig. 16, the layout apparatus 100 may include: the system comprises an acquisition module 101, a first determination module 102, a prediction module 103 and a second determination module 104. It will be appreciated that the embodiment of the present application only performs exemplary division of the structure and functional modules of the layout apparatus 100, and does not limit the specific division thereof, so that in other possible embodiments, the layout apparatus 100 may be logically divided into other numbers of modules.

The steps specifically executed by each functional module of the layout apparatus 100 are referred to in the summary of the application and the description in the foregoing method embodiments, and are not repeated herein.

The embodiment of the present application also provides another circuit cell layout apparatus of an integrated circuit, the apparatus 100 includes: one or more processors and a transmission interface; wherein the one or more processors are configured to invoke computer instructions stored in the memory to cause the apparatus to perform steps and optional steps in embodiments of the method of the present application.

When the arrangement 100 is a hardware device, the arrangement 100 may be a computing device. FIG. 17 is a schematic diagram of a computing device according to an embodiment of the present application. The computing device 200 includes: at least one central processing unit (Central Processing Unit, CPU), memory, types of Memory may include, for example, static Random-Access Memory (SRAM) and Read-Only Memory (ROM), microcontroller (Micro controller Unit, MCU), wireless local area network (Wireless Local Area Network, WLAN) subsystem, bus, transmission interface, etc. Although not shown in fig. 17, the computing device 200 may also include an application processor (Application Processor, AP), other special purpose processors such as NPUs, and other subsystems such as a power management subsystem, a clock management subsystem, and a power consumption management subsystem.

The various portions of computing device 200 are coupled by connectors, which may include, for example, various types of interfaces, transmission lines or buses, etc., which are typically electrical communication interfaces, but may also be mechanical interfaces or other forms of interfaces, as the present embodiment is not limited in this regard.

Alternatively, the CPU may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor; alternatively, the CPU may be a processor group of multiple processors coupled to each other via one or more buses. In an alternative case, the CPU implements the circuit cell layout method of the integrated circuit in the foregoing method embodiment by calling program instructions stored in the memory described above or in off-chip memory. In an alternative case, the CPU and MCU together implement a circuit cell layout method of an integrated circuit as in any of the foregoing method embodiments, e.g., the CPU performs some of the steps in the circuit cell layout method, while the MCU performs other steps in the circuit cell layout method. In an alternative case, the AP or other special purpose processor implements the circuit cell layout method of any of the previous method embodiments by invoking program instructions stored in the on-chip or off-chip memory.

The transmission interface may be an interface for receiving and transmitting data of the processor chip, and typically includes various interfaces, and in an alternative case, the transmission interface may include an Inter-Integrated Circuit (I2C) interface, a serial peripheral interface (Serial Peripheral Interface, SPI), a universal asynchronous receiver/transmitter (UART) interface, a General-purpose input/output (GPIO) interface, and the like. It should be appreciated that these interfaces may be different functions implemented by multiplexing the same physical interfaces.

In an alternative case, the transmission interface may further include a high definition multimedia interface (High Definition Multimedia Interface, HDMI), a V-By-One interface, an embedded Display Port (Embedded Display Port, eDP), a mobile industry processor interface (Mobile Industry Processor Interface, MIPI), or a Display Port (DP), etc.

In an alternative case, the above parts are integrated on the same chip; in another alternative, the memory may be a stand-alone chip.

The WLAN subsystem may include, for example, radio frequency circuitry and baseband.

The chips referred to in embodiments of the present application are systems fabricated on the same semiconductor substrate in an integrated circuit process, also known as semiconductor chips, which may be a collection of integrated circuits formed on a substrate (typically a semiconductor material such as silicon) using an integrated circuit process, the outer layers of which are typically encapsulated by a semiconductor encapsulation material. The integrated circuit may include various types of functional devices, each of which may include logic gates, metal-Oxide-Semiconductor (MOS) transistors, bipolar transistors, or diodes, and other components such as capacitors, resistors, or inductors. Each functional device can work independently or under the action of necessary driving soft parts, and can realize various functions such as communication, operation, storage and the like.

It is to be appreciated that the processor in embodiments of the application may be a central processing unit (central processing unit, CPU), other general purpose processor, digital signal processor (digital signal processor, DSP), application specific integrated circuit (application specific integrated circuit, ASIC), field programmable gate array (field programmable gate array, FPGA) or other programmable logic device, transistor logic device, hardware components, or any combination thereof. The general purpose processor may be a microprocessor, but in the alternative, it may be any conventional processor.

The method steps in the embodiments of the present application may be implemented by hardware, or may be implemented by executing software instructions by a processor. The software instructions may be comprised of corresponding software modules that may be stored in random access memory (random access memory, RAM), flash memory, read-only memory (ROM), programmable ROM (PROM), erasable programmable PROM (EPROM), electrically erasable programmable EPROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted across a computer-readable storage medium. The computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

It will be appreciated that the various numerical numbers referred to in the embodiments of the present application are merely for ease of description and are not intended to limit the scope of the embodiments of the present application.

Claims

A method of circuit cell layout for an integrated circuit, the method comprising:

acquiring the current layout of the integrated circuit; the current layout includes: a first region in which the circuit cells are not laid out;

determining a plurality of legal placement positions for placing the first circuit unit in the first area;

the layout prediction model outputs a prediction result based on the current layout and the legal placement positions;

and determining the position of the first circuit unit in the first area according to the prediction result.
The method of claim 1, wherein the legal placement location comprises: the legal placement position is located at an angular position of the first region and/or at an edge position of the first region.
The method according to claim 2, wherein the angular position comprises an angular position based on vertices of circuit cells already laid out in the current layout and/or an angular position of vertices of the first area.
A method according to any one of claims 1-3, wherein the legal placement location further comprises a location satisfying at least one of:

after the first circuit unit is placed at the legal placement position, the first circuit unit is not overlapped with the circuit unit already placed in the current layout;

after the first circuit unit is placed at the legal placement position, the first area does not generate a suspension area;

after the first circuit unit is placed at the legal placement position, the first area does not generate a closed area; or (b)

The legal placement position is positioned in the first area and is an angular position formed by vertexes of the laid-out circuit units belonging to the same group with the first circuit unit; wherein the functions of the plurality of circuit units in the same group have a correlation.
The method of any of claims 1-4, wherein the outputting of the layout prediction model is a probability of each legal placement location of the plurality of legal placement locations, and wherein determining, based on the prediction, a location in the first region where the first circuit unit is placed comprises: and determining the position of the first circuit unit in the first area according to the probability of each legal placement position in the legal placement positions.
The method of claim 5, wherein determining the location in the first area where the first circuit unit is located based on the probability of each legal placement location of the plurality of legal placement locations comprises: and determining the legal placement position with the highest probability among the legal placement positions as the position for placing the first circuit unit.
The method of claim 5, wherein determining the location in the first area where the first circuit unit is located based on the probability of each legal placement location of the plurality of legal placement locations comprises:

and extracting the legal placement positions according to the probability of each legal placement position in the legal placement positions to obtain the legal placement position for placing the first circuit unit.
The method of any of claims 1-7, wherein the first circuit unit comprises a macro-unit.
A circuit cell layout apparatus for an integrated circuit, the apparatus comprising:

an acquisition module for acquiring a current layout of the integrated circuit; the current layout includes: a first region in which the circuit cells are not laid out;

A first determining module, configured to determine a plurality of legal placement positions for placing a first circuit unit in the first area;

the prediction module is used for outputting a prediction result based on the current layout and the legal placement positions by the layout prediction model;

and the second determining module is used for determining the position of the first circuit unit in the first area according to the prediction result.
The apparatus of claim 9, wherein the legal placement location comprises: the legal placement position is located at an angular position of the first region and/or at an edge position of the first region.
The apparatus of claim 10, wherein the angular position comprises an angular position based on vertices of circuit cells already laid out in the current layout and/or an angular position of vertices of the first region.
The apparatus of any one of claims 9-11, wherein the legal placement location further comprises a location satisfying at least one of:

after the first circuit unit is placed at the legal placement position, the first circuit unit is not overlapped with the circuit unit already placed in the current layout;

After the first circuit unit is placed at the legal placement position, the first area does not generate a suspension area;

after the first circuit unit is placed at the legal placement position, the first area does not generate a closed area; or (b)

The legal placement position is positioned in the first area and is an angular position formed by vertexes of the laid-out circuit units belonging to the same group with the first circuit unit; wherein the functions of the plurality of circuit units in the same group have a correlation.
The apparatus according to any one of claims 9-12, wherein the output of the layout prediction model is a probability of each legal placement position of the plurality of legal placement positions, and the second determining module is specifically configured to:

and determining the position of the first circuit unit in the first area according to the probability of each legal placement position in the legal placement positions.
The apparatus of claim 13, wherein the second determining module is specifically configured to:

and determining the legal placement position with the highest probability among the legal placement positions as the position for placing the first circuit unit.
The apparatus of claim 13, wherein the second determining module is specifically configured to:

And extracting the legal placement positions according to the probability of each legal placement position in the legal placement positions to obtain the legal placement position for placing the first circuit unit.
The apparatus of any of claims 8-15, wherein the first circuit unit comprises a macro-unit.
An integrated circuit layout apparatus, the apparatus comprising: a processor and a transmission interface, the processor being configured to invoke program instructions stored in the memory to cause the integrated circuit layout device to implement the method of any of claims 1-8.
A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program code, which, when executed by a computer or a processor, implements the method of any of claims 1-8.
A computer program product comprising instructions which, when executed by a computer or processor, cause the computer or processor to carry out the method of any one of claims 1 to 8.