CN102156760B - Saber-based circuit failure simulation analyzing method - Google Patents
Saber-based circuit failure simulation analyzing method Download PDFInfo
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Abstract
The invention provides a Saber-based circuit failure simulation analyzing method. The method is characterized by comprising the following steps: 1, performing Saber circuit function modeling and simulation; 2, determining the failure mode of a device to be simulated; 3, modeling the failure; 4, injecting the failure; 5, simulating a failed circuit to generate a failure simulation result; 6, setting a failure criterion; and 7, giving a failure analyzing result. Regarding the problem that the conventional circuit failure simulation can be only used for digital circuits, the method provides a practical failure simulation method based on the digital-analog hybrid simulation platform Saber. Furthermore, many failure simulation models which cannot be solved by predecessors are added, and 48 failure modes can be simulated. Realization of automatic failure injection greatly improves the failure simulation efficiency. The direct interface between Saber and failure simulation is broken through, and an effective signal failure determination method is provided.
Description
(1) technical field:
The invention provides a kind of Circuit Fault Simulation analytical approach based on Saber (Saber is the hybrid system simulation software of U.S. Synopsys company), belong to the Circuit Fault Simulation analysis field.
(2) background technology:
The fault simulation technology be a kind of for analyzing system performance and functional test grow up with fault modeling, fault is injected and simulation combines analytical technology.It is take digital simulation as means, and by failure mechanism and the form of expression thereof of inner each component units of analytic system, constructing system fault simulation model on system original function model basis is realized the process that the system that has trouble unit is analyzed.
Circuit Fault Simulation is that fault injection and circuit simulation are combined, and according to the failure mechanism of device, fault is injected in the circuit, obtains the technology of circuit simulation data under fault mode, is a kind of effective householder method that realizes the circuit reliability design.Fault is injected and is referred to according to some strategy, artificially fault is introduced the process of goal systems.In fields such as Aero-Space, require high to circuit reliability, device fault may bring fatal crass's consequence, by using Circuit Fault Simulation, can find out the serious device of fault effects, as long as in the circuit design process this class device is paid close attention to, can avoid serious consequence to produce.In addition, in fault diagnosis field, the Output rusults of fault simulation is the important evidence of fault dictionary.
Before the Circuit Fault Simulation technical development, want to obtain in advance the impact behind the fault, the normal dual mode that adopts is that hardware fault is injected and the software fault injection.For circuit, hardware fault is injected and is tended to cause circuit devcie damage, inefficacy, causes very large economic loss; And the software fault injection exists the inaccessible shortcoming of some non-programmed control device.And just can well avoid this problem based on the Failure Injection Technique of emulation, and can help circuit designer to pinpoint the problems early in the design phase, help early to improve.In addition, it is low to inject cost based on the fault of emulation, and fault that can be unlimited is injected and emulation, need not to spend any hardware cost.And the mode of employing fault simulation, for hardware injected, simulation time was extremely short.
For the fault simulation of circuit, adopt exactly based on the fault of emulation and inject, the method that forefathers propose mainly contains based on the Hardware Description Language VHDL platform carries out fault modeling and emulation.The advantage of such fault simulation is to carry out fault simulation to digital circuit, and shortcoming is can't emulation to the fault of mimic channel and Digital Analog Hybrid Circuits, because VHDL platform itself can only the simulated digital circuit, and can not the analogue simulation circuit.For the problems referred to above, the present invention carries out fault simulation by third party's digital-to-analogue hybrid simulation software Saber, not only can carry out numeral, simulation, Digital Analog Hybrid Circuits fault simulation, has also guaranteed simulation accuracy and speed simultaneously.
(3) summary of the invention:
1, purpose: the purpose of this invention is to provide a kind of fault simulation analytical approach based on the Saber platform, proposed corresponding fault simulation model, the fault filling method of device fault pattern, break through the interface between Saber platform and the fault simulation.
2, technical scheme: the present invention is achieved by the following technical solutions:
A kind of Circuit Fault Simulation analytical approach based on Saber of the present invention, its step is as follows:
Step 1: carry out Saber circuit function modeling and simulation.Namely according to design requirement protracting circuit schematic diagram on the Saber platform, circuit theory diagrams debugging compiling finally meets demand, as normal circuit.With this circuit evolving net meter file, carry out direct current, Transient, obtain the normal circuit simulation result.
Step 2: the device fault pattern of determining to want emulation.Circuit designer need to determine to carry out the emulation of which class fault mode of which device.
Step 3: fault modeling.Each fault mode is corresponding to a fault simulation model, and the process of setting up fault simulation model is fault modeling, and fault modeling is a Focal point and difficult point of the present invention.The basis of fault modeling is the refinement fault mode, and the form of expression under each fault mode of device of will analyzing and researching, the final fault simulation model of setting up based on the form of expression.Setting up fault simulation model is the prerequisite of fault emulation.The fault modeling method sees below shown in the tabulation 1; Introduce the modeling method of the corresponding fault simulation model of several fault modes commonly used herein, with explanation fault modeling process:
1 " open circuit ": the fault pin is connected in series large resistance (10
10Ohm) or directly disconnect;
2 " short circuits ": parallel low resistance or direct short circuit between the fault pin;
3 " loose contacts ": selecting any termination Flash switch of defective device, connect afterwards the rear end, is that the certain proportion (such as 10%) of whole simulation time reaches the flash effect by control Flash switch periods;
4 " parameter drifts ": revise certain important electrical parameter values of device, because the many middle types of devices of this fault mode all can occur, for the different components type, the value that need to revise is different.Need to revise resistance such as resistance, electric capacity is revised the appearance value, and inductance need to be revised inductance value.Value after revising all is positive and negative drift certain proportion on the original basis;
5 " no-outputs ": defective device output head grounding;
6 " parameter is overproof ": defective device output termination gain controller changes the coefficient that gains;
Not 7 " the fuse go is not opened ": the direct short circuit in fuse two ends;
8 " the fuse go changes down ": fusting current increases 5% on original basis;
Step 4: fault is injected.It is in fact a process of fault simulation model being introduced normal circuit that fault is injected.The present invention has used two kinds of injection modes: manually inject and automatically inject.Manually injection mode is to revise schematic diagram and component parameter setting.Automatically injection mode is the modification circuits net meter file, because every class device net list language form difference is very large in the net meter file, primary fault injects needs to revise several places of net meter file content, and different faults schema modification content is different.The realization fault is injected automatically, also is the difficult point that the present invention breaks through.
Step 5: faulty circuit emulation generates the fault simulation result.After the 4th step fault was injected and finished, circuit had just become the circuit that contains fault simulation model, and this circuit simulation is faulty circuit emulation, the Output simulation result.
For circuit simulation, innovative point of the present invention directly calls exactly Saber simulation kernel (Saber emulator) and carries out emulation from the backstage, realize automatic simulation, call the emulation of corresponding number of times according to the quantity that fault mode is set, finish when carrying out next emulation after the emulation, the Saber emulator can be called again.This process adopts programmed control, the people's who breaks away from fully manual operations.
Step 6: failure criterion setting.Failure criterion is in fact to judge that the fault simulation output waveform is normal or the criterion of fault.Method of discrimination for simulating signal provides two kinds of methods: waveform diagnostic method and parameter diagnostic method.
The parameter diagnostic method will arrange judges zero-time (ms), judgement termination time (ms) and critical parameter.Critical parameter has: signal maximum, signal minimum, signal effective value, signal actual value, signal average, signal absolute mean, signal elevating time, signal fall time, signal retention time (high-low level), the signal waveform factor, the signal wave crest factor.If in the value scope of extracting the waveform parameter value (such as signal maximum) of fault simulation output and limiting, think that then waveform is normal, otherwise judge the waveform fault.
The waveform diagnostic method can be judged the similarity of two waveforms, the method that adopts waveform area to calculate.The probability that differs between the waveform is called diversity factor, if the difference of fault simulation output and normal state simulation output in the diversity factor allowed band, thinks then that this waveform is normal, otherwise judges that waveform is fault.
Fault verification method for digital signal: the main employing allows bound-time.If the bound-time section of digital signal in allowed band, judges that then waveform is normal.
Step 7: provide the fault analysis result.Judge that according to failure criterion each node signal of fault simulation output is normal or fault.Failure analysis module mainly is according to the information in the criterion file, obtains various critical parameters from simulation document, thereby carries out fault analysis.
3, advantage and effect:
The present invention is directed to the problem that existing Circuit Fault Simulation can only carry out digital circuit simulation, propose in digital-to-analogue hybrid simulation platform Saber fault simulation practical approach.In addition, increased the unsolved fault simulation model of a lot of forefathers, can 48 kinds of fault modes of emulation.The realization that fault is injected has automatically improved fault simulation efficient greatly.Break through the direct interface of Saber and fault simulation, provided the effective signal fault decision method of a cover.
(4) description of drawings:
Fig. 1 fault simulation analytical approach of the present invention process flow diagram
The amplifying circuit schematic diagram that Fig. 2 the invention process case 1 is selected
The normal state simulation output waveform of the amplifying circuit that Fig. 3 the invention process case 1 is selected
Q_3p " base stage, collector short circuit " fault simulation waveform in the selected amplifying circuit of Fig. 4 the invention process case 1
Q_3p " open base " fault simulation waveform in the selected amplifying circuit of Fig. 5 the invention process case 1
Q_3p " degeneration of the performance such as gain " fault simulation waveform in the selected amplifying circuit of Fig. 6 the invention process case 1
X1 " pp pin open circuit " fault simulation waveform in the selected amplifying circuit of Fig. 7 the invention process case 1
X1 " pp, the short circuit of pm pin " fault simulation waveform in the selected amplifying circuit of Fig. 8 the invention process case 1
X1 " parameter drift " fault simulation waveform in the selected amplifying circuit of Fig. 9 the invention process case 1
(5) embodiment:
Fault simulation analytical approach process flow diagram of the present invention as shown in Figure 1.A kind of Circuit Fault Simulation analytical approach based on Saber that the present invention proposes, its step is as follows:
Step 1: carry out Saber circuit function modeling and simulation.Namely according to design requirement protracting circuit schematic diagram on the Saber platform, circuit theory diagrams debugging compiling finally meets demand, as normal circuit.With this circuit evolving net meter file, carry out direct current, Transient, obtain the normal circuit simulation result.
Step 2: the device fault pattern of determining to want emulation.GJB299C concludes the various fault modes of variety classes device, such as resistance open circuit, short circuit, parameter drift fault mode is arranged, and the line style integrated circuit has overproof, the no-output fault mode of output.Circuit designer need to determine to carry out the emulation of which class fault mode of which device, such as the overproof fault mode of output of wanting emulation line style integrated circuit.If want that the various faults pattern of a plurality of devices of circuit is carried out emulation has just formed the fault mode collection.
Step 3: fault modeling.Each fault mode is corresponding to a fault simulation model, and the process of setting up fault simulation model is fault modeling.For making up fault simulation model, need to study first the form of expression under each fault mode of device.But fault modeling can not be directly carried out in the inadequate refinement of some fault mode, and this class fault mode need to quantize first.A part of key content of the present invention is exactly to provide fault modeling method corresponding to device fault pattern, and is as shown in table 1 below.And proposed the specific implementation process of fault modeling method under the Saber platform, enumerated shown in the part such as following table 2.
Table 1 fault modeling method
The Saber implementation (part) of table 2 fault mode
Step 4: fault is injected.It is in fact a process of fault simulation model being introduced normal circuit that fault is injected.The present invention has used two kinds of injection modes: manually inject and automatically inject.
Manually injection mode is manual modification schematic diagram and component parameter setting, and advantage is directly perceived.But because each injection all needs manually-operated, be suitable for the situation that a small amount of fault is injected.
Directly the modification circuits schematic diagram is reflected to device fault on the schematic diagram.On the one hand the device connected mode can be directly revised, the pin of device can be directly disconnected such as the device open circuit failure mode, unsettled because Saber emulation is supported.Short-circuit mode is short circuit directly.Also the fault simulation model of having built up can be injected into assigned address on the other hand, can to the connect circuit of a large resistance of device, realize disconnecting effect such as the device open circuit failure mode.The advantage of revising schematic diagram fault injection mode is more directly perceived, and shortcoming is to need manual the injection.Such injection mode mainly is applicable to pin class fault mode, such as open circuit, short circuit, break not open, lead wire fault, no-output etc. connect relevant fault mode with pin.
Directly revise the device setup of attribute, for simple discrete component, can directly revise the components and parts attribute such as resistance, electric capacity, diode etc., to reach the effect of revising device parameters.This modification attribute fault injection mode generally is only applicable to parameter class fault mode, the degeneration of performances such as parameter drift, gain etc.
Automatically injection mode is the modification circuits net meter file, is suitable for injecting in a large number the situation of fault.Automatically injection mode is wanted the modification circuits net meter file, because every class device net list language form difference is very large in the net meter file, primary fault injects needs to revise several places of net meter file content, and different faults schema modification content is different.Fault is injected realization automatically, is the difficult point that the present invention breaks through.
The net table comprises and connects design between the component parameters of element names, tie point and all non-acquiescences and the device.Because the Saber emulator is reading circuit figure directly, must show to simulate by net, this kind injection mode advantage is to have reduced fault to inject rear other operation steps, and service efficiency is high, and especially a large amount of faults are injected, and its effect is more obvious.
The net meter file form of a certain electric capacity is under the circuit normal condition:
c.cin?p:inp?m:in＝c＝33n
Under electric capacity " short circuit " fault mode, net meter file changes to:
c.cin?p:inp?m:inp＝c＝33n
Under electric capacity " parameter drift " fault mode, net meter file changes to:
c.cin?p:inp?m:in＝c＝40n
Step 5: Circuit Fault Simulation generates the fault simulation result.After the 4th step fault was injected and finished, circuit had just become the circuit that contains fault simulation model, and this circuit simulation is Circuit Fault Simulation.If only carry out the emulation of a fault mode, can adopt manual emulation, quiescent operation point analysis and the transient analysis of direct control Saber simulation software just can be finished emulation.But during to the different faults pattern emulation of each device in the circuit one time, the medium-scale circuit by tens devices just has a hundreds of fault mode, namely wants the emulation hundreds of, if at this moment according to adopting manual emulation meeting to bother very much.
For this reason, another innovative point of the present invention is exactly directly to call Saber simulation kernel (Saber emulator) to carry out emulation, according to the emulation that the quantity that fault mode is set is called corresponding number of times, to finish when carrying out next emulation after the emulation, the Saber emulator can be called again.This process adopts programmed control, the people's who breaks away from fully manual operations.
How to utilize program directly to call the Saber emulator from the backstage and become another technological breakthrough of the present invention, i.e. emulation interface between Saber and the fault simulation.
During manual emulation, then the user only need to click Transient with the circuit evolving net meter file, carries out the Transient setting; Finish as for calling by the Saber platform of emulator.And automatic simulation occurs without the need for the interface, and net meter file generation, transient analysis setting, emulator call all and directly control by program.Net meter file, suffix are .sin, and the net meter file generative process of circuit was in front portion by the agency of after fault was injected; The transient analysis setting or not at the interface of using the Saber platform to provide, and is converted into the Simulation Control order but the emulation during with normal circuit emulation arranges file, and all orders are write in the .scs file, and the .scs file layout is as follows:
dc(density?2)
tr(tend?6m，tstep?10u，monitor?100，siglist?vout，terror?1000u，density?2，method?trap，order?1，tniter?12)
stress
Emulator calls by the programmed control order, requires .scs file and .sin file under same path, and concrete call format is:
Saber installation path .sin file path-b
Step 6: failure criterion setting.Failure criterion is in fact to judge that the fault simulation output waveform is normal or the criterion of fault.Method of discrimination for simulating signal provides two kinds of methods: waveform diagnostic method and parameter diagnostic method.
The parameter diagnostic method will arrange judges zero-time (ms), judgement termination time (ms) and critical parameter.Critical parameter has: signal maximum, signal minimum, signal effective value, signal actual value, signal average, signal absolute mean, signal elevating time, signal fall time, signal retention time (high-low level), the signal waveform factor, the signal wave crest factor.If in the value scope of extracting the waveform parameter value (such as signal maximum) of fault simulation output and limiting, think that then waveform is normal, otherwise judge the waveform fault.
The waveform diagnostic method can be judged the similarity of two waveforms, the method that adopts waveform area to calculate.The probability that differs between the waveform is called diversity factor, if the difference of fault simulation output and normal state simulation output in the diversity factor allowed band, thinks then that this waveform is normal, otherwise judges that waveform is fault.
Fault verification method for digital signal: the main employing allows bound-time.If the bound-time section of digital signal in allowed band, judges that then waveform is normal.
Step 7: provide the fault analysis result.Judge that according to failure criterion each node signal of fault simulation output is normal or fault.Failure analysis module mainly is according to the information in the criterion file, obtains various critical parameters from simulation document, thereby carries out fault analysis.
Algorithm wherein is the calculating of various parameters, mainly contains:
1) obtains absolute mean
Absolute mean is the mean value of the algebraically absolute value of signal in the fixed time.Main algorithm is: the signal value of initial time in all unit interval in the fixed time is taken absolute value, then obtain mean value, be the absolute mean of signal.
Formula:
2) obtain area
Area is in the fixed time, and signal value curve and time shaft enclose the area of part, and positive and negative dividing arranged.Main algorithm is: with the division of fixed time according to the simulation data file, obtain in each minimum time unit take chronomere as wide, the size of the signal value of this chronomere's initial time (comprising sign) is long rectangular area, with all the rectangular area summations in the fixed time unit, the result who obtains is exactly the area of signal at last.
Formula:
3) obtain mean value
Mean value is the mean value of signal value in the fixed time.Main algorithm is: the size (comprising sign) to the signal value of all the least unit initial times in the fixed time is averaged, and gained is mean value.
4) picked up signal fall time
Signal fall time is in the fixed time, and signal value is from beginning for the first time to drop to the time of the last time between stopping to descend.Main algorithm is:
(1) since the initial time of fixed time, order judges that whether the signal value of each finish time unit interval is less than initial time.
(2) if the signal value of the finish time is less than the initial time signal value in the unit interval, the initial time that records this unit interval is that signal begins to descend constantly, skips to step (3); Otherwise, if should not be finish time unit interval, then skip to next unit interval finish time fixed time, continue execution in step (2), otherwise signal fall time be zero, this algorithm finishes.
(3) from this moment, order judge each finish time unit interval signal value whether more than or equal to the signal value of unit interval initial time.
(4) if the signal value of the finish time is finish time fixed time more than or equal to the signal value of this unit interval initial time or should be finish time unit interval in certain unit interval, be that signal decline stops constantly skipping to step (5) finish time of then recording this unit interval; Otherwise, skip to next unit interval, continue execution in step (4).
(5) begun to descend constantly by signal and signal descends and stops the moment and subtract each other, obtain signal fall time.Algorithm finishes.
Formula:
t
Rise=t (0.1x
Max)-t (0.9x
Max)
Annotate: this time is descending branch.
5) obtain diversity factor
In diversity factor refers at the appointed time, the absolute value of the difference of the area of signal to be declared and normal signal area and the ratio of normal signal area.Main algorithm is: calculate respectively the area of signal to be declared and normal signal in the fixed time, get the absolute value of the difference of the two, the ratio of this value and normal signal area is diversity factor.
Formula:
6) obtain maximal value
Maximal value is the maximal value of the algebraic value of signal in the fixed time.When asking this value, setting first first value constantly is maximal value, then judges each moment and current peaked magnitude relationship in the fixed time.If current maximal value is larger, then continue to judge next constantly, otherwise signal value is made as maximal value constantly.After fixed time, all judged end constantly, gained was maximal value.
7) obtain minimum value
Minimum value is the minimum value of the algebraic value of signal in the fixed time.When asking this value, setting first first value constantly is minimum value, then judge in the fixed time each constantly with the magnitude relationship of current minimum value.If current minimum value is less, then continue to judge next constantly, otherwise signal value is made as minimum value constantly.After fixed time, all judged end constantly, gained was minimum value.
8) the picked up signal rise time
Signal elevating time is in the fixed time, and signal value begins to rise to the time of nearest stopping between rising for the first time.Main algorithm is:
(1) since the initial time of fixed time, order judges that whether the signal value of each finish time unit interval is greater than initial time.
(2) if the signal value of the finish time is greater than the initial time signal value in the unit interval, the initial time that records this unit interval is that signal begins to rise constantly, skips to step (3); Otherwise, if should not be finish time unit interval, then skip to next unit interval finish time fixed time, continue execution in step (2), otherwise signal elevating time is zero, this algorithm finishes.
(3) from this moment, order judges whether the signal value of each finish time unit interval is less than or equal to the signal value of unit interval initial time.
(4) if the signal value of the interior finish time of certain unit interval is less than or equal to the signal value of this unit interval initial time or should is the finish time unit interval finish time fixed time, be that the signal rising stops constantly skipping to step (5) finish time of then recording this unit interval; Otherwise, skip to next unit interval, continue execution in step (4).
(5) begun to rise constantly by signal and signal rises and stops the moment and subtract each other, obtain signal elevating time.Algorithm finishes.
Formula:
t
Rise=t (0.9x
Max)-t (0.1x
Max)
Annotate: this time is the ascent stage
9) obtain form-factor
Form-factor is the effective value of signal in the fixed time and the ratio between the absolute mean.
Formula:
10) obtain effective value
Effective value is the square root of the mean value of signal value quadratic sum in the fixed time.Main algorithm is: since the initial time of fixed time, with initial time signal value in each unit interval square with the long-pending addition of unit interval, the result who the obtains root of making even after divided by fixed time length, acquired results is effective value.
Formula:
11) obtain crest factor
Crest factor is the maximal value of signal in the fixed time and the ratio between the effective value.
Formula:
12) the picked up signal retention time
The signal retention time is to rise for the first time from signal value in the fixed time to descend time the beginning to recent signal value after stopping.Main algorithm is:
(1) since the initial time of fixed time, order judges that whether the signal value of each finish time unit interval is greater than initial time.
(2) if the signal value of the finish time then skips to step (3) greater than the initial time signal value in the unit interval; Otherwise, if should not be finish time unit interval, then skip to next unit interval finish time fixed time, continue execution in step (2), otherwise the signal retention time be zero, this algorithm finishes.
(3) from this moment, order judges whether the signal value of each finish time unit interval is not more than initial time.
(4) if the signal value of the finish time is not more than the initial time signal value in the unit interval, the initial time that records this unit interval is that the signal rising stops constantly skipping to step (5); Otherwise, if should not be finish time unit interval, then skip to next unit interval finish time fixed time, continue execution in step (4), otherwise the signal retention time be zero, this algorithm finishes.
(5) from this moment, order judge each finish time unit interval signal value whether less than the signal value of unit interval initial time.
(6) if the signal value of the finish time is finish time fixed time less than the signal value of this unit interval initial time or should be finish time unit interval in certain unit interval, be that signal descends the zero hour finish time of then recording this unit interval, skips to step (7); Otherwise, skip to next unit interval, continue execution in step (6).
(7) risen by signal and stop constantly and signal decline is subtracted each other the zero hour, obtain signal fall time.Algorithm finishes.
Formula:
t
Keep=t1 (0.9x
Max)-t2 (0.9x
Max)
Wherein: t1 and t2 are respectively continuous ascent stage and descending branch.
Case study on implementation 1
With an amplifying circuit fault simulation analytical approach is described, this amplifying circuit schematic diagram as shown in Figure 2, the waveform of the normal state simulation of this circuit output vload as shown in Figure 3, amplitude is the sine wave about positive and negative 12v.
Case implementing procedure step is above-mentioned seven steps.For present case, the fault mode that step 2 is selected has been selected three fault modes of performance degradation such as base collector short circuit, open base, gain for bipolar transistor; Pp pin open circuit, pp, the short circuit of pm pin, three fault modes of parameter drift have been selected for transformer.After step 5, it is as shown in table 3 to have obtained each fault mode simulation result.Two kinds of method waveform diagnostic methods and parameter diagnostic method are selected in step 6 failure criterion setting.Wherein the waveform diagnostic method is set as 90% with wave-form similarity; The parameter diagnostic method set to be judged zero-time 0ms, is judged termination time 50ms, and alternative is selected three parameters: and signal maximum is set as 12v, signal minimum and is set as-and 12.5v, signal average be set as 0.By step 7, provide the fault analysis result.What two kinds of criterion methods that set provided comes to the same thing, shown in table 3 analysis result row.
Table 3 amplifying circuit fault simulation is analyzed
Claims (1)
1. one kind based on the Circuit Fault Simulation analytical approach based on Saber, it is characterized in that:
Step 1: carry out Saber circuit function modeling and simulation; Namely according to design requirement protracting circuit schematic diagram on the Saber platform, circuit theory diagrams debugging compiling finally meets demand, as normal circuit; With this circuit evolving net meter file, carry out direct current, Transient, obtain the normal circuit simulation result;
Step 2: the device fault pattern of determining to want emulation; GJB299C concludes the various fault modes of variety classes device, and resistance has open circuit, short circuit, parameter drift fault mode, and the line style integrated circuit has overproof, the no-output fault mode of output; Circuit designer need to determine to carry out the emulation of which class fault mode of which device, the overproof fault mode of output of emulation line style integrated circuit; Various faults pattern to a plurality of devices of circuit is carried out emulation, has just formed the fault mode collection;
Step 3: fault modeling; Each fault mode is corresponding to a fault simulation model, and the process of setting up fault simulation model is fault modeling; For making up fault simulation model, need to study first the form of expression under each fault mode of device; But fault modeling can not be directly carried out in the inadequate refinement of some fault mode, and this class fault mode need to quantize first; This a part of key content based on the Circuit Fault Simulation analytical approach of Saber is exactly to provide fault modeling method corresponding to device fault pattern, and has proposed the specific implementation process of fault modeling method under the Saber platform;
Table 1 fault modeling method
The Saber implementation of table 2 fault mode
Step 4: fault is injected; It is in fact a process of fault simulation model being introduced normal circuit that fault is injected; Two kinds of injection modes have been used: manually inject and automatically inject;
Manually injection mode is manual modification schematic diagram and component parameter setting, and advantage is directly perceived; But because each injection all needs manually-operated, be suitable for the situation that a small amount of fault is injected;
Directly the modification circuits schematic diagram is reflected to device fault on the schematic diagram; Directly revise on the one hand the device connected mode, the device open circuit failure mode directly disconnects the pin of device, and is unsettled because Saber emulation is supported; The direct short circuit of short-circuit mode; The fault simulation model that to build up on the other hand is injected into assigned address, and the device open circuit failure mode realizes disconnecting effect to the circuit of a large resistance of device series connection; The advantage of revising schematic diagram fault injection mode is more directly perceived, and shortcoming is to need manual the injection; Such injection mode mainly is applicable to pin class fault mode, open circuit, short circuit, break not open, lead wire fault, no-output connect relevant fault mode with pin;
Directly revise the device setup of attribute, for the simple discrete component of resistance, electric capacity and diode, directly revise the components and parts attribute, to reach the effect of revising device parameters; This modification attribute fault injection mode is only applicable to the parameter class fault mode of parameter drift, gain performance degeneration;
Automatically injection mode is the modification circuits net meter file, is suitable for injecting in a large number the situation of fault; Automatically injection mode is wanted the modification circuits net meter file, because every class device net list language form difference is very large in the net meter file, primary fault injects needs to revise several places of net meter file content, and different faults schema modification content is different; Fault is injected realization automatically, is the difficult point that breaks through;
The net table comprises and connects design between the component parameters of element names, tie point and all non-acquiescences and the device; Because the Saber emulator is reading circuit figure directly, must show to simulate by net, this kind injection mode advantage is to have reduced fault to inject rear other operation steps, and service efficiency is high, and especially a large amount of faults are injected, and its effect is more obvious;
The net meter file form of a certain electric capacity is under the circuit normal condition:
c.cin?p:inp?m:in＝c＝33n
Under electric capacity " short circuit " fault mode, net meter file changes to:
c.cin?p:inp?m:inp＝c＝33n
Under electric capacity " parameter drift " fault mode, net meter file changes to:
c.cin?p:inp?m:in＝c＝40n
Step 5: Circuit Fault Simulation generates the fault simulation result; After the 4th step fault was injected and finished, circuit had just become the circuit that contains fault simulation model, and this circuit simulation is Circuit Fault Simulation; Only carry out the emulation of a fault mode, adopt manual emulation, emulation is just finished in quiescent operation point analysis and the transient analysis of direct control Saber simulation software; But during to the different faults pattern emulation of each device in the circuit one time, the medium-scale circuit by tens devices just has a hundreds of fault mode, namely wants the emulation hundreds of, according to adopting manual emulation meeting to bother very much;
For this reason, should be exactly directly to call the Saber simulation kernel to carry out emulation based on another innovative point of Circuit Fault Simulation analytical approach of Saber, call the emulation of corresponding number of times according to the quantity that fault mode is set, finish when carrying out next emulation after the emulation, the Saber emulator can be called again; This process adopts programmed control, the people's who breaks away from fully manual operations;
How to utilize program directly to call the Saber emulator from the backstage and become the another technological breakthrough of Circuit Fault Simulation analytical approach based on Saber, i.e. emulation interface between Saber and the fault simulation;
During manual emulation, then the user only need to click Transient with the circuit evolving net meter file, carries out the Transient setting; Finish as for calling by the Saber platform of emulator; And automatic simulation occurs without the need for the interface, and net meter file generation, transient analysis setting, emulator call all and directly control by program; Net meter file, suffix are .sin, after fault is injected the net meter file generative process of circuit in step 1 to step 4 by the agency of; The interface that the transient analysis setting does not re-use the Saber platform to be provided arranges, and is converted into the Simulation Control order but the emulation during with normal circuit emulation arranges file, and all orders are write in the .scs file, and the .scs file layout is as follows:
dc(density?2)
tr(tend?6m，tstep?10u，monitor?100，siglist?vout，terror?1000u，density?2，method?trap，order1，tniter?12)stress
Emulator calls by the programmed control order, requires .scs file and .sin file under same path, and concrete call format is:
Saber installation path .sin file path-b
Step 6: failure criterion setting; Failure criterion is in fact to judge that the fault simulation output waveform is normal or the criterion of fault; Method of discrimination for simulating signal provides two kinds of methods: waveform diagnostic method and parameter diagnostic method;
The parameter diagnostic method will arrange judges zero-time, judgement termination time and critical parameter; Critical parameter has: signal maximum, signal minimum, signal effective value, signal actual value, signal average, signal absolute mean, signal elevating time, signal fall time, signal retention time, the signal waveform factor, the signal wave crest factor; If in the waveform parameter value of extraction fault simulation output and the value scope of restriction, think that then waveform is normal, otherwise judge the waveform fault;
The waveform diagnostic method is judged the similarity of two waveforms, the method that adopts waveform area to calculate; The probability that differs between the waveform is called diversity factor, if the difference of fault simulation output and normal state simulation output in the diversity factor allowed band, thinks then that this waveform is normal, otherwise judges that waveform is fault;
Fault verification method for digital signal: the main employing allows bound-time; If the bound-time section of digital signal in allowed band, judges that then waveform is normal;
Step 7: provide the fault analysis result; Judge that according to failure criterion each node signal of fault simulation output is normal or fault; Failure analysis module mainly is according to the information in the criterion file, obtains various critical parameters from simulation document, thereby carries out fault analysis;
Algorithm wherein is the calculating of various parameters, mainly contains:
1) obtains absolute mean
Absolute mean is the mean value of the algebraically absolute value of signal in the fixed time; Main algorithm is: the signal value of initial time in all unit interval in the fixed time is taken absolute value, then obtain mean value, be the absolute mean of signal;
Formula:
2) obtain area
Area is in the fixed time, and signal value curve and time shaft enclose the area of part, and positive and negative dividing arranged; Main algorithm is: with the division of fixed time according to the simulation data file, obtain in each minimum time unit take chronomere as wide, the size of the signal value of this chronomere's initial time is long rectangular area, with all the rectangular area summations in the fixed time unit, the result who obtains is exactly the area of signal at last;
Formula:
3) obtain mean value
Mean value is the mean value of signal value in the fixed time; Main algorithm is: the size to the signal value of all the least unit initial times in the fixed time is averaged, and gained is mean value;
4) picked up signal fall time
Signal fall time is in the fixed time, and signal value is from beginning for the first time to drop to the time of the last time between stopping to descend; Main algorithm is:
(1) since the initial time of fixed time, order judges that whether the signal value of each finish time unit interval is less than initial time;
(2) if the signal value of the finish time is less than the initial time signal value in the unit interval, the initial time that records this unit interval is that signal begins to descend constantly, skips to step (3); Otherwise, if should not be finish time unit interval, then skip to next unit interval finish time fixed time, continue execution in step (2), otherwise signal fall time be zero, this algorithm finishes;
(3) from this moment, order judge each finish time unit interval signal value whether more than or equal to the signal value of unit interval initial time;
(4) if the signal value of the finish time is finish time fixed time more than or equal to the signal value of this unit interval initial time or should be finish time unit interval in certain unit interval, be that signal decline stops constantly skipping to step (5) finish time of then recording this unit interval; Otherwise, skip to next unit interval, continue execution in step (4);
(5) begun to descend constantly by signal and signal descends and stops the moment and subtract each other, obtain signal fall time; Algorithm finishes;
Picked up signal formula fall time:
t
Descend=t (0.1x
Max)-t (0.9x
Max)
Annotate: this time is descending branch; X
MaxMaximal value for signal in the fixed time;
T (0.1x
Max) signal begins to descend constantly; T (0.9x
Max) signal descends and to stop constantly;
5) obtain diversity factor
In diversity factor refers at the appointed time, the absolute value of the difference of the area of signal to be declared and normal signal area and the ratio of normal signal area; Main algorithm is: calculate respectively the area of signal to be declared and normal signal in the fixed time, get the absolute value of the difference of the two, the ratio of this value and normal signal area is diversity factor;
Formula:
6) obtain maximal value
Maximal value is the maximal value of the algebraic value of signal in the fixed time; When asking this value, setting first first value constantly is maximal value, then judges each moment and current peaked magnitude relationship in the fixed time; If current maximal value is larger, then continue to judge next constantly, otherwise signal value is made as maximal value constantly; After fixed time, all judged end constantly, gained was maximal value;
7) obtain minimum value
Minimum value is the minimum value of the algebraic value of signal in the fixed time; When asking this value, setting first first value constantly is minimum value, then judge in the fixed time each constantly with the magnitude relationship of current minimum value; If current minimum value is less, then continue to judge next constantly, otherwise signal value is made as minimum value constantly; After fixed time, all judged end constantly, gained was minimum value;
8) the picked up signal rise time
Signal elevating time is in the fixed time, and signal value begins to rise to the time of nearest stopping between rising for the first time; Main algorithm is:
(1) since the initial time of fixed time, order judges that whether the signal value of each finish time unit interval is greater than initial time;
(2) if the signal value of the finish time is greater than the initial time signal value in the unit interval, the initial time that records this unit interval is that signal begins to rise constantly, skips to step (3); Otherwise, if should not be finish time unit interval, then skip to next unit interval finish time fixed time, continue execution in step (2), otherwise signal elevating time is zero, this algorithm finishes;
(3) from this moment, order judges whether the signal value of each finish time unit interval is less than or equal to the signal value of unit interval initial time;
(4) if the signal value of the interior finish time of certain unit interval is less than or equal to the signal value of this unit interval initial time or should is the finish time unit interval finish time fixed time, be that the signal rising stops constantly skipping to step (5) finish time of then recording this unit interval; Otherwise, skip to next unit interval, continue execution in step (4);
(5) begun to rise constantly by signal and signal rises and stops the moment and subtract each other, obtain signal elevating time; Algorithm finishes;
Picked up signal rise time formula:
t
Rise=t (0.9x
Max)-t (0.1x
Max)
Annotate: this time is the ascent stage; X
MaxMaximal value for signal in the fixed time;
9) obtain form-factor
Form-factor is the effective value of signal in the fixed time and the ratio between the absolute mean;
Formula:
10) obtain effective value
Effective value is the square root of the mean value of signal value quadratic sum in the fixed time; Main algorithm is: since the initial time of fixed time, with initial time signal value in each unit interval square with the long-pending addition of unit interval, the result who the obtains root of making even after divided by fixed time length, acquired results is effective value;
Formula:
11) obtain crest factor
Crest factor is the maximal value of signal in the fixed time and the ratio between the effective value;
Formula:
12) the picked up signal retention time
The signal retention time is to rise for the first time from signal value in the fixed time to descend time the beginning to recent signal value after stopping; Main algorithm is:
(1) since the initial time of fixed time, order judges that whether the signal value of each finish time unit interval is greater than initial time;
(2) if the signal value of the finish time then skips to step (3) greater than the initial time signal value in the unit interval; Otherwise, if should not be finish time unit interval, then skip to next unit interval finish time fixed time, continue execution in step (2), otherwise the signal retention time be zero, this algorithm finishes;
(3) from this moment, order judges whether the signal value of each finish time unit interval is not more than initial time;
(4) if the signal value of the finish time is not more than the initial time signal value in the unit interval, the initial time that records this unit interval is that the signal rising stops constantly skipping to step (5); Otherwise, if should not be finish time unit interval, then skip to next unit interval finish time fixed time, continue execution in step (4), otherwise the signal retention time be zero, this algorithm finishes;
(5) from this moment, order judge each finish time unit interval signal value whether less than the signal value of unit interval initial time;
(6) if the signal value of the finish time is finish time fixed time less than the signal value of this unit interval initial time or should be finish time unit interval in certain unit interval, be that signal descends the zero hour finish time of then recording this unit interval, skips to step (7); Otherwise, skip to next unit interval, continue execution in step (6);
(7) risen by signal and stop constantly and signal decline is subtracted each other the zero hour, obtain signal fall time; Algorithm finishes;
Formula:
t
Keep=t1 (0.9x
Max)-t2 (0.9x
Max)
Wherein: t1 and t2 are respectively continuous ascent stage and descending branch.
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