US20160293443A1 - Methods of forming different sized patterns - Google Patents
Methods of forming different sized patterns Download PDFInfo
- Publication number
- US20160293443A1 US20160293443A1 US14/850,419 US201514850419A US2016293443A1 US 20160293443 A1 US20160293443 A1 US 20160293443A1 US 201514850419 A US201514850419 A US 201514850419A US 2016293443 A1 US2016293443 A1 US 2016293443A1
- Authority
- US
- United States
- Prior art keywords
- forming
- openings
- layer
- pillars
- domains
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 90
- 229920001400 block copolymer Polymers 0.000 claims abstract description 129
- 238000000926 separation method Methods 0.000 claims abstract description 84
- 238000000137 annealing Methods 0.000 claims abstract description 20
- 230000000903 blocking effect Effects 0.000 claims description 49
- 229920000642 polymer Polymers 0.000 claims description 27
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 22
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 19
- BAPJBEWLBFYGME-UHFFFAOYSA-N Methyl acrylate Chemical compound COC(=O)C=C BAPJBEWLBFYGME-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 230000035515 penetration Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 249
- 239000000758 substrate Substances 0.000 description 24
- 239000004065 semiconductor Substances 0.000 description 20
- 239000011295 pitch Substances 0.000 description 15
- 239000004793 Polystyrene Substances 0.000 description 11
- 238000005191 phase separation Methods 0.000 description 10
- 238000001338 self-assembly Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000002086 nanomaterial Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000000465 moulding Methods 0.000 description 5
- 229920002717 polyvinylpyridine Polymers 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 229920001490 poly(butyl methacrylate) polymer Polymers 0.000 description 4
- 239000007795 chemical reaction product Substances 0.000 description 3
- 239000004205 dimethyl polysiloxane Substances 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 description 3
- 239000005062 Polybutadiene Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009477 glass transition Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- -1 methyl siloxane Chemical class 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920002857 polybutadiene Polymers 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920001195 polyisoprene Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 241000446313 Lamella Species 0.000 description 1
- 229920003171 Poly (ethylene oxide) Polymers 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 229920001002 functional polymer Polymers 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Definitions
- Various embodiments of the present disclosure relate to semiconductor technologies and, more particularly, to methods of forming patterns having different critical dimensions (CDs).
- CDs critical dimensions
- CD nano-scale critical dimension
- DSA direct self-assembly
- Various embodiments are directed to methods of forming different sized patterns.
- a method of forming patterns may include: forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer including first separation wall portions surrounding sidewalls of the pillars, and forming second separation wall portions covering sidewalls of the first opening trench portion; forming a block copolymer layer on the separation wall layer; forming first domains in gaps between the pillars, and forming second domains surrounding and separating the first domains by annealing the block copolymer layer; forming second openings by selectively removing the first domains; forming third openings between the second openings, and forming a fourth opening adjacent to the first isolated pattern by selectively removing the pillars and the template portion; and forming fifth openings, which extend from the second and third openings and penetrate the underlying layer, and forming a sixth opening, which extends from the fourth opening and penetrates the underlying layer.
- a method of forming patterns may include: forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer that covers the pillars, the first isolated pattern and the template portion; forming a block copolymer layer that fills gaps between the pillars and fills a gap between the first isolated pattern and the template portion; forming first domains in the gaps between the pillars, forming second domains surrounding and separating the first domains, forming a third domain in the first opening trench portion, and forming a fourth domain surrounding the third domain, by annealing the block copolymer layer, wherein the third domain is shallower than the first domains and a bottom portion of the fourth domain is thicker than bottom portions of the second domains; forming second openings by removing the first domains, and forming a seventh opening by removing the third domain; forming first extensions of the second openings, which penetrate the
- a method of forming patterns may include: forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer that covers the pillars, the first isolated pattern and the template portion; forming a block copolymer layer that fills gaps between the pillars and fills a gap between the first isolated pattern and the template portion; forming first domains in the gaps between the pillars, forming second domains surrounding and separating the first domains, forming a third domain in the first opening trench portion, and forming a fourth domain surrounding the third domain, by annealing the block copolymer layer, wherein the third domain is shallower than the first domains and a bottom portion of the fourth domain is thicker than bottom portions of the second domains; forming second openings by removing the first domains, and forming a seventh opening by removing the third domain; forming first extensions of the second openings which penetrate the bottom
- a method of forming patterns may include: forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer including separation wall portions that cover sidewalls of the pillars and sidewalls of the first openings; forming a block copolymer layer on the separation wall layer; forming first domains in gaps between the pillars, forming second domains surrounding and separating the first domains, forming third domains in the first openings, and forming fourth domains surrounding the third domains, by annealing the block copolymer layer; forming second openings in the gaps between the pillars, and forming third openings in the first openings, by selectively removing the first domains and the third domains; forming fourth openings by selectively removing the pillars; and forming fifth openings that penetrate the underlying layer and extend from the second and fourth openings, and forming sixth openings that penetrate the
- FIGS. 1 to 3 are plan views illustrating a process for obtaining a layout of a guide pattern used in a method of forming patterns according to an embodiment
- FIG. 4 is a plan view illustrating a layout of a blocking pattern used in a method of forming patterns according to an embodiment
- FIGS. 5 to 18 are cross-sectional views illustrating a method of forming patterns according to an embodiment
- FIGS. 19 to 22 are plan views illustrating a process for obtaining a layout of a guide pattern used in a method of forming patterns according to another embodiment
- FIGS. 23 to 48 are cross-sectional views illustrating a method of forming patterns according to another embodiment
- FIGS. 49 and 50 are plan views illustrating a process for obtaining a layout of a guide pattern used in a method of forming patterns according to still another embodiment.
- FIGS. 51 to 53 are schematic views illustrating phase separations of block copolymer (BCP) layers used in exemplary embodiments.
- the term “dense patterns” may be used to describe patterns having a relatively small pitch size and a relatively short distance therebetween, and the term “isolated patterns” may be used to describe patterns having a relatively large pitch size and a relatively long distance therebetween.
- the term “regularly arrayed patterns” may be used to describe patterns arrayed to have a uniform pitch size and substantially the same distance therebetween, and the term “irregularly arrayed patterns” may be used to describe patterns arrayed to have non-uniform pitch sizes or different distances therebetween.
- the term “irregularly arrayed patterns” may also be used to describe patterns randomly arrayed without any regularity.
- Exemplary embodiments of the present disclosure may provide methods of forming fine patterns through a phase separation of a block copolymer (BCP) layer so that the patterns have a line width less than a resolution limit of exposure apparatuses.
- BCP block copolymer
- exemplary embodiments of the present disclosure may provide methods of forming an array of contact holes or an array of cutting holes for cutting line-shaped patterns through a direct self-assembly (DSA) technique of the BCP layer.
- DSA direct self-assembly
- Specific polymer blocks included in the BCP layer may be ordered and phase-separated from a matrix material to form domain portions under a specific condition, and the phase-separated domain portions may be selectively removed to form spaces or patterns having a nano-scaled feature size.
- the nano-scaled feature size may range from a few nanometers to several tens of nanometers.
- a self-assembled structure of the BCP layer may have a cylindrical shape or a lamellar shape according to a volume ratio of two or more distinct polymer blocks included in the BCP layer, an annealing temperature for the phase separation of the BCP layer, a molecule size of the polymer blocks included in the BCP layer, and a molecular weight of the polymer blocks included in the BCP layer. That is, the phase-separated domain portions of the polymer blocks may have a cylindrical shape or a lamellar shape.
- the self-assembled structure of the BCP layer has a cylindrical shape
- the BCP layer may be used to form a hole array pattern.
- the self-assembled structure of the BCP layer may be used to form a line and space pattern.
- DRAM dynamic random access memory
- PcRAM phase changeable random access memory
- ReRAM resistive random access memory
- SRAM static random access memory
- MRAM magnetic random access memory
- FeRAM ferroelectric random access memory
- logic devices such as control devices, central processing units (CPU) or arithmetic logic units (ALU).
- FIGS. 1 to 3 are plan views illustrating a process for obtaining a layout of a guide pattern used in a method of forming patterns according to an embodiment.
- a layout 10 of a target feature may include a layout 11 having an array of first target features 12 that are to be transferred onto a substrate to form fifth openings, and may include a layout 19 having a second target feature 18 that is to be transferred onto the substrate to form a second isolated pattern.
- the layout 11 of the first target features 12 and the layout 19 of the second target feature 18 may be located at different regions. For example, the layout 11 and the layout 19 may be adjacent to each other.
- the first target features 12 may be disposed in a dense pattern region such as a cell region, and the second target feature 18 may be disposed in an isolated pattern region such as a peripheral region.
- the second target feature 18 may have a line shape or a polygonal shape.
- the first target features 12 may include pillar features 13 for portions of guide patterns, and first domain features 14 between the pillar features 13 .
- the first domain features 14 may be surrounded by four adjacent pillar features 13 during phase separation of the BCP material. Accordingly, the pillar features 13 may be separated from the first domain features 14 according to the phase separation of the BCP material.
- a layout 20 may include a layout 21 having pillar features 23 and a layout 29 having a first isolated pattern 28 and a first opening trench.
- the layout 21 having the pillar features 23 may be obtained by separating the first domain features 14 from the layout 11 of the first target features 12 .
- the layout of the first isolated pattern 28 may be obtained by resizing the second target feature 18 corresponding to the second isolated pattern.
- the layout of the first isolated pattern 28 may be obtained by two-dimensionally shrinking the second target feature 18 by “R1” as shown in FIG. 2 .
- the layout of the first opening trench portion 27 may be obtained by removing the layout of the first isolated pattern 28 from the second target feature 18 .
- a layout 30 of guide patterns may include pillar features 33 arrayed in a region 31 , a template portion 39 exposing the region 31 , and a first isolated pattern 38 disposed in the template portion 39 spaced apart from the template portion 39 .
- the pillar features 33 may correspond to the pillar features 23 of FIG. 2
- the first isolated pattern 38 may correspond to the first isolated pattern 28 of FIG. 2 .
- a region 37 between the template portion 39 and the first isolated pattern 38 may correspond to a first opening trench portion 27 of FIG. 2 . That is, the first isolated pattern 38 may be surrounded by the first opening trench portion 37 in the template portion 39 .
- FIG. 4 is a plan view illustrating a layout 40 of a blocking pattern 48 .
- the layout 40 may include the blocking pattern 48 that is transferred onto the first isolated pattern 38 to form a mask pattern covering the first isolated pattern 38 .
- the mask pattern formed by the blocking pattern 48 may remain to protect the first isolated pattern 38 while the template portion 39 is selectively removed.
- the first isolated pattern 38 may still remain due to the presence of the mask pattern formed by the blocking pattern 48 during removal of the template portion 39 .
- the blocking pattern 48 may be obtained by two-dimensionally enlarging the first isolated pattern 38 .
- the blocking pattern 48 may have a layout of the second isolated pattern 18 .
- the blocking pattern 48 may be formed by two-dimensionally enlarging the second isolated pattern 18 to overlap with a portion of the template portion 39 adjacent to the second isolated pattern 18 .
- FIGS. 5 to 18 are cross-sectional views taken along a line C 1 -C 1 ′ of FIGS. 1 to 3 to illustrate a method of forming patterns according to an embodiment.
- FIG. 5 illustrates a step of forming mask patterns 633 , 638 and 639 on a guide layer 500 .
- the mask patterns 633 , 638 and 639 may be formed on the guide layer 500 .
- the mask patterns 633 , 638 and 639 may serve as etch masks when the guide layer 500 is etched in a subsequent process.
- the mask patterns 633 , 638 and 639 may include first patterns 633 corresponding to the pillars 33 , a second pattern 638 corresponding to the first isolated pattern 38 , and a third pattern 639 corresponding to the template portion 39 .
- a space region 637 between the second pattern 638 and the third pattern 639 may have substantially the same shape as the first opening trench portion 37 .
- the mask patterns 633 , 638 and 639 may include a photoresist material.
- the guide layer 500 may be patterned in a subsequent process to form guide patterns, which are described with reference to FIGS. 1 to 3 and define positions of the domains in the phase-separated BCP layer.
- the guide layer 500 may be formed on a semiconductor substrate 100 .
- the semiconductor substrate 100 may include a first region 131 on which the pillars 33 are disposed with high density, and may include a second region 139 on which the second isolated pattern 18 is disposed.
- the second region 139 may be distinct from and adjacent to the first region 131 .
- the guide layer 500 may include a spin-on-carbon (SOC) layer 501 disposed on an underlying layer 400 .
- the SOC layer 501 may have a thickness ranging from about 700 to about 800 angstroms.
- the guide layer 500 may further include a capping layer 503 disposed on the SOC layer 501 .
- the capping layer 503 may be formed of a silicon oxynitride (SION) layer having a thickness of about 300
- the underlying layer 400 may be used to pattern a part of or an entire hard mask in a subsequent patterning process.
- the underlying layer 400 may serve as one of multi-layers in a hard mask system.
- a second etch target layer 300 may be formed between the underlying layer 400 and the semiconductor substrate 100 .
- a first etch target layer 200 may be formed between the second etch target layer 300 and the semiconductor substrate 100 .
- the first or second etch target layer 200 or 300 may be one of the hard mask system, or may be selectively etched using the hard mask system as an etch mask in a subsequent process.
- the first etch target layer 200 may be formed of an interlayer insulation layer including a silicon oxide layer such as a tetra-ethyl-ortho-silicate (TEOS) layer having a thickness of about 2200 angstroms.
- TEOS tetra-ethyl-ortho-silicate
- the first etch target layer 200 may be formed of a conductive layer such as a doped polysilicon layer.
- the second etch target layer 300 may be formed by depositing an amorphous SOC layer having a thickness ranging from about 730 to about 1000 angstroms on the first etch target layer 200 .
- the underlying layer 400 may be formed on the second etch target layer 300 and may include a silicon oxynitride (SION) layer having a thickness ranging from about 300 to about 350 angstroms.
- SION silicon oxynitride
- FIG. 6 illustrates a step of forming an array of pillars 530 , a first isolated pattern 580 and a template portion 590 .
- the guide layer 500 may be etched using the mask patterns 633 , 638 and 639 as etch masks, thereby forming the array of the pillars 530 , the first isolated pattern 580 and the template portion 590 .
- the array of the pillars 530 may be formed on the first region 131 of the semiconductor substrate 100
- the first isolated pattern 580 and the template portion 590 may be formed on the second region 139 of the semiconductor substrate 100 .
- a space region between the first isolated pattern 580 and the template portion 590 may correspond to a first opening trench portion 570 .
- the pillars 530 may be arrayed so that four adjacent pillars 530 are positioned to form a rectangular shape. Alternatively, the pillars 530 may be arrayed so that three adjacent pillars 530 are positioned to form a triangular shape.
- the pillars 530 may be arrayed to have a gap 531 between two adjacent pillars 530 which are disposed on the line C 1 -C 1 ′. As illustrated in FIG. 3 , a gap between two adjacent pillars 33 which are arrayed on a horizontal line may be narrower than the gap between two adjacent pillars 33 which are arrayed on the diagonal portion of the line C 1 -C 1 ′.
- the pillars 530 may serve as guide patterns that induce self-assembly of the BCP layer which is formed in a subsequent process.
- the first isolated pattern 580 and the template portion 590 may serve as guide patterns that prevent the self-assembly of the BCP layer on the second region 139 .
- FIG. 7 illustrates a step of forming a separation wall layer 600 .
- the separation wall layer 600 may include first separation wall portions 602 A covering sidewalls of the pillars 530 , and second separation wall portions 602 B covering sidewalls of the first opening trench portion 570 .
- the separation wall layer 600 may include first extensions 601 A extending from the first separation wall portions 602 A to cover portions of the underlying layer 400 exposed by the gaps 531 , and second extensions 603 A extending from the first separation wall portions 602 A to cover top surfaces of the pillars 530 .
- the separation wall layer 600 may further include third extensions 601 B extending from the second separation wall portions 602 B to cover portions of the underlying layer 400 exposed by the first opening trench portion 570 , and fourth extensions 6038 extending from the second separation wall portions 602 B to cover top surfaces of the first isolated pattern 580 and the template portion 590 .
- the separation wall layer 600 may provide recessed regions defined by gaps 631 between the pillars 530 , and a recessed region defined by a gap 637 between the first isolated pattern 580 and the template portion 590 .
- the separation wall layer 600 may be formed of an insulation layer having an etch selectivity with respect to the pillars 530 and the underlying layer 400 .
- the separation wall layer 600 may be formed of an ultra-low temperature oxide (ULTO) layer having a thickness of about 200 angstroms.
- ULTO ultra-low temperature oxide
- FIG. 8 illustrates a step of forming the BCP layer 700 .
- the BCP layer 700 may be formed on the separation wall layer 600 to fill the gaps 631 and 637 which are provided by the pillars 530 , the first isolated pattern 580 and the template portion 590 .
- the BCP layer 700 may include a polystyrene-poly (meta methyl acrylate) block copolymer (PS-b-PMMA) material or a polystyrene-poly (di methyl siloxane) (PS-PDMS) block copolymer material.
- PS-b-PMMA polystyrene-poly (meta methyl acrylate) block copolymer
- PS-PDMS polystyrene-poly (di methyl siloxane)
- the volume ratio of the PS blocks to the PMMA blocks or molecular weights of the PS block and the PMMA block may be appropriately controlled according to a process scheme.
- the PS-b-PMMA material may have a PS block content of about 60 vol. % to about 80 vol. % and a PMMA block content of about 20 vol. % to about 40 vol. %.
- FIGS. 51 to 53 are schematic views illustrating the phase separation of the BCP layer 700 for exemplary embodiments.
- the BCP layer 700 may be a functional polymer material made by combining polymer blocks having two or more distinct structures into a single block copolymer material through a covalent bond, as illustrated in FIG. 51 .
- the BCP layer 700 may have a chain shape including polymer blocks ‘A’ and ‘B’, which are connected to each other by a covalent bond through a link point.
- the BCP layer 700 may be coated to have a homogeneous phase. Referring to FIG.
- the polymer blocks having distinct structures in the BCP layer 700 may have different miscibility and different solubility from each other due to different chemical structures thereof. That is, the polymer blocks having distinct structures are immiscible with each other at a certain temperature.
- the BCP layer 700 may be phase-separated through an annealing process to provide a self-aligned structure.
- the BCP layer 700 having a homogeneous phase may be phase-separated into a domain ‘A’ in which polymer blocks ‘A’ are ordered and a domain ‘B’ in which polymer blocks ‘B’ are ordered, through an annealing process.
- polymer blocks of the BCP layer 700 may be phase-separated or selectively dissolved in a liquid state or in a solid state to form a self-assembled structure.
- a nano-scale structure having a specific shape through the self-assembly of the BCP layer 700 may be affected by a physical property and/or a chemical property of the polymer blocks of the BCP layer 700 .
- the self-assembled structure of the BCP layer may have a three dimensional cubic shape, a three dimensional double helix shape, a two dimensional hexagonal packed column shape, a two dimensional lamella shape and so forth according to a volume ratio of the polymer blocks included in the BCP layer, an annealing temperature for phase separation of the BCP layer, and a molecule size of the polymer blocks included in the BCP layer.
- the BCP layer 700 may be formed of polybutadiene-polybutylmethacrylate block copolymer, polybutadiene-polydimethylsiloxane block copolymer, polybutadiene-polymethylmethacrylate block copolymer, polybutadienepolyvinylpyridine block copolymer, polybutylacrylate-polymethylmethacrylate block copolymer, polybutylacrylate-polyvinylpyridine block copolymer, polyisoprene-polyvinylpyridine block copolymer, polyisoprene-polymethylmethacrylate block copolymer, polyhexylacrylatepolyvinylpyridine block copolymer, polyisobutylene-polybutylmethacrylate block copolymer, polyisobutylene-polymethylmethacrylate block copolymer, polyisobutylene-polybutylmethacrylate block copolymer, poly
- FIG. 9 illustrates a step of phase-separating the BCP layer 700 .
- the BCP layer 700 may be phase-separated through an annealing process into first domains 710 respectively located at central portions of the gaps 631 between the pillars 530 arrayed on the line C 1 -C 1 ′, and a second domain 730 disposed between the pillars 530 to surround the first domains 710 and to isolate the first domains 710 from each other.
- the first domains 710 may fill recessed regions provided by the second domain 730 .
- the first domains 710 may have post shapes and may be surrounded by the second domain 730 .
- a portion of the BCP layer 700 filling the gap 637 provided by the separation wall layer 600 on the second region 139 may be phase-separated into a third domain 750 and a fourth domain 770 surrounding the third domain 750 in the gap 637 .
- the third domain 750 may insufficiently expand toward a bottom surface of the gap 637 to have a smaller depth than the first domains 710 . This is due to the gap 637 having a smaller width than the gaps 631 . Since the third domain 750 does not sufficiently expand toward the bottom surface of the gap 637 , a bottom surface D 1 of the third domain 750 may be located adjacent to an entrance of the gap 637 .
- the bottom surface D 1 of the third domain 750 may be located at a higher level than bottom surfaces D 2 of the first domains 710 . Accordingly, a bottom portion 771 of the fourth domain 770 surrounding the bottom surface D 1 and sidewalls of the third domain 750 may be thicker than bottom portions 731 of the second domain 730 .
- the gap 637 may have an insufficient space to accommodate two different domains 750 and 770 . In such a case, a portion of the BCP layer 700 filling the gap 637 may not be phase-separated even though the BCP layer 700 is annealed.
- the phase separation of the BCP layer 700 may be achieved by annealing the BCP layer 700 at a temperature exceeding a glass transition temperature Tg of the BCP layer 700 to rearrange the polymer blocks of the BCP layer 700 .
- the BCP layer 700 may be annealed at a temperature ranging from about 100 to about 190 degrees Celsius for a time ranging from about six minutes to about twenty four hours.
- FIG. 10 illustrates a step of forming a plurality of second openings 701 and a seventh opening 705 .
- the first domains 710 may be selectively removed to form the plurality of second openings 701 located between the pillars 530 . While the first domains 710 are selectively removed, the third domain 750 may also be removed to form the seventh opening 705 in the first opening trench portion 570 . In such a case, the seventh opening 705 may be shallower than the second openings 701 .
- FIG. 11 illustrates a step of forming second extensions 701 B of the second openings 701 .
- the bottom portions 731 of the second domain 730 exposed by the second openings 701 may be selectively removed to form first extensions 701 A of the second openings 701 extending from the second openings 701 . While the bottom portions 731 of the second domain 730 are selectively removed, the bottom portion 771 of the fourth domain 770 exposed by the seventh opening 705 may be partially removed to form an extension 705 B of the seventh opening 705 . However, the extension 705 B of the seventh opening 705 may be formed not to penetrate the bottom portion 771 of the fourth domain 770 . As a result, a feature of the seventh opening 705 may not be transferred into the bottom portion 771 of the fourth domain 770 .
- the first extensions 601 A of the separation wall layer 600 exposed by the first extensions 701 A of the second openings 701 may be selectively removed to form the second extensions 701 B of the second openings 701 extending from the second openings 701 .
- the second extensions 603 A of the separation wall layer 600 covering the top surfaces of the pillars 530 and the template portion 590 may also be removed to expose the top surfaces of the pillars 530 and the template portion 590 .
- FIG. 12 illustrates a step of forming a blocking pattern 848 .
- the blocking pattern 848 may cover the first isolated pattern 580 .
- residues of the BCP layer 700 including the second domain 730 and the fourth domain 770 may be removed.
- a sacrificial layer 810 may be formed on the pillars 530 , the first isolated pattern 580 and the template portion 590 to fill the second extensions 701 B of the second openings 701 , the gaps between the pillars 530 , and the gap between the first isolated pattern 580 and the template portion 590 .
- the blocking pattern 848 may extend to cover the second separation wall portions 602 B adjacent to the first isolated pattern 580 .
- the blocking pattern 848 may be formed by transferring a layout feature of the blocking pattern 848 .
- the blocking pattern 848 may cover all of the first isolated pattern 580 , the second separation wall portions 602 B and the third extensions 601 B.
- the blocking pattern 848 may be laterally shifted from an expected position due to an overlay shift during an alignment and exposure process. Even though the blocking pattern 848 is laterally shifted, the first isolated pattern 580 may still be sealed with the second separation wall portions 602 B and the blocking pattern 848 as far as the first isolated pattern 580 is laterally shifted within an allowable overlay range since the second separation wall portions 602 B and the blocking pattern 848 are disposed around the first isolated pattern 580 .
- FIG. 13 is a cross-sectional view illustrating a blocking pattern 848 A which is laterally shifted.
- the blocking pattern 848 A may cover a portion of the template portion 590 . Nevertheless, the blocking pattern 848 A may have an alignment margin of about “R2” corresponding to a width of the first opening trench portion 570 . That is, even though the blocking pattern 848 A is shifted so that an edge of the blocking pattern 848 A is disposed in the first opening trench portion 570 , the first isolated pattern 580 may still be sealed with the second separation wall portions 602 B and the third extensions 601 B.
- FIG. 14 illustrates a step of selectively removing the pillars 530 and the template portion 590 .
- the pillars 530 and the template portion 590 may be selectively etched and removed using the planarized sacrificial layer 810 , the first and second separation wall portions 602 A and 602 B, the first and third extensions 601 A and 6018 , and the blocking pattern 848 as etch masks.
- the pillars 530 may be removed to form third openings 633
- the template portion 590 may be removed to form a fourth opening 639 .
- FIG. 15 illustrates a step of removing the blocking pattern 848 .
- the blocking pattern 848 and the planarized sacrificial layer 810 may be selectively removed to expose the second extensions 701 B of the second openings 701 extending from the second openings 701 .
- FIG. 16 illustrates a step of forming fifth openings 402 and a sixth opening 439 .
- the underlying layer 400 on the first region 131 may be etched using the first separation wall portions 602 A and the first extensions 601 A as etch masks, thereby forming the fifth openings 402 that extend from the second extensions 701 B of the second openings 701 and extend from the third openings 633 . While the fifth openings 402 are formed, the underlying layer 400 may be patterned to include a first pattern 410 that provides the fifth openings 402 . In addition, the underlying layer 400 on the second region 139 may be etched using the first isolated pattern 580 , and the second separation wall portion 602 B and the third extension 601 B as etch masks, thereby forming the sixth opening 439 that extends from the fourth opening 639 . Accordingly, the underlying layer 400 may be patterned to include a second pattern 418 that provides the sixth opening 439 . The second pattern 418 may correspond to the second isolated pattern. The fifth openings 402 and the sixth opening 439 may be simultaneously formed.
- FIGS. 17 and 18 illustrate a step of forming extensions 202 of the fifth openings 402 and an extension 239 of the sixth opening 439 .
- the second etch target layer 300 and the first etch target layer 200 may be etched using the first pattern 410 and the second isolated pattern 418 as etch masks, thereby forming the extensions 202 of the fifth openings 402 and the extension 239 of the sixth opening 439 that penetrate the first and second etch target layers 200 and 300 .
- a second pattern 318 of the second etch target layer 300 and a second pattern 218 of the first etch target layer 200 may be provided by the extension 239 of the sixth opening 439 on the second region 139
- a first pattern 310 of the second etch target layer 300 and a first pattern 210 of the first etch target layer 200 may be provided by the extensions 202 of the fifth opening 402 on the first region 131 .
- the first pattern 410 of the underlying layer 400 , the second isolated pattern 418 , and the first and second patterns 310 and 318 of the second etch target layer 300 may be removed to leave the second pattern 218 having a planar shape of the second isolated pattern 418 and the first pattern 210 providing the extensions 202 of the fifth opening 402 .
- FIGS. 19 to 22 are plan views illustrating a process for obtaining a layout of a guide pattern used in a method of forming patterns according to another embodiment.
- a layout 2011 may include an array of first target features 2015 which are to be transferred onto the substrate to form patterns.
- the first target features 2015 may form fifth openings that penetrate a material layer disposed on the substrate.
- the first target features 2015 may be regularly and repeatedly arrayed to have a certain pitch, for example a first pitch P 1 .
- the first target features 2015 may include pillar features 2012 arrayed in a diagonal direction and first domain features 2014 disposed between the pillar features 2012 .
- a layout 2019 may include an array of second target features 2018 .
- the layout 2011 of the first target features 2015 shown in FIG. 19 and the layout 2019 of the second target features 2018 shown in FIG. 20 may be located at two different regions.
- the second target features 2018 may provide sixth openings that penetrate a material layer disposed on the substrate.
- Each of the second target features 2018 may have a size which is the same as or different from a size of each of the first target features 2015 .
- the first target features 2015 are arrayed to have the first pitch P 1
- the second target features 2018 may be arrayed to have a second pitch P 2 .
- the second pitch P 2 may be greater than the first pitch P 1 .
- the second pitch P 2 may be twice or more of the first pitch P 1 .
- a layout 2021 may be obtained by separating the pillar features 2012 from the layout 2011 of the first target features 2015 . That is, the layout 2021 may include pillar features 2022 corresponding to the pillar features 2012 without first domain features 2024 corresponding to the first domain features 2014 .
- a layout 2029 may correspond to a layout of first opening features 2028 obtained by resizing the second target features 2018 .
- Each of the first opening features 2028 may provide a space in which a third domain 2078 is induced.
- the second target features 2018 may be located at the positions of the third domains 2078 , respectively.
- FIGS. 23 to 50 are cross-sectional views and plan views illustrating a method of forming patterns according to another embodiment.
- FIGS. 23 and 24 illustrate a step of forming mask patterns 2622 and 2627 on a guide layer 2500 .
- FIG. 23 is a cross-sectional view taken along a line C 21 -C 21 ′ of FIG. 21
- FIG. 24 is a cross-sectional view taken along a line C 22 -C 22 ′ of FIG. 22 .
- a semiconductor substrate 2100 may have a first region 2121 and a second region 2129 that are distinct from each other, and the guide layer 2500 may be formed by sequentially stacking a SOC layer 2501 and a capping layer 2503 on an entire surface of the semiconductor substrate 2100 .
- the capping layer 2503 may be formed of a silicon oxynitride (SiON) layer.
- the pillar features 2022 of the layout 2021 may be transferred onto the semiconductor substrate 2100 to realize the first mask patterns 2622 providing openings 2623 on the first region 2121
- the first opening features 2028 of the layout 2029 may be transferred onto the semiconductor substrate 2100 to realize the second mask patterns 2627 providing openings 2628 on the second region 2129 .
- the first and second mask patterns 2622 and 2627 may include a photoresist material.
- the guide layer 2500 may be patterned in a subsequent process to form guide patterns that define positions of domains in a phase-separated BCP layer.
- the guide layer 2500 may be formed on an underlying layer 2400 and may include an SOC layer having a thickness ranging from about 700 to about 800 angstroms.
- a capping layer (not shown) may be additionally formed on the SOC layer.
- the capping layer may be formed of a silicon oxynitride (SION) layer having a thickness of about 300 angstroms.
- the underlying layer 2400 may be used to pattern a portion or an entire hard mask in a subsequent patterning process.
- the underlying layer 2400 may serve as one of multi-layers in a hard mask system.
- a second etch target layer 2300 may be formed between the underlying layer 2400 and the semiconductor substrate 2100 .
- a first etch target layer 2200 may be formed between the second etch target layer 2300 and the semiconductor substrate 2100 .
- the first or second etch target layer 2200 or 2300 may be one of the hard mask system, or may be selectively etched using the hard mask system as an etch mask in a subsequent process.
- the first etch target layer 2200 may be formed of an interlayer insulation layer including a silicon oxide layer such as a tetra-ethyl-ortho-silicate (TEOS) layer having a thickness of about 2200 angstroms.
- TEOS tetra-ethyl-ortho-silicate
- the first etch target layer 2200 may be formed of a conductive layer such as a doped polysilicon layer.
- the second etch target layer 2300 may be formed by depositing an amorphous SOC layer having a thickness ranging from about 730 to about 1000 angstroms on the first etch target layer 2200 .
- the underlying layer 2400 may be formed on the second etch target layer 2300 and may include a silicon oxynitride (SION) layer having a thickness ranging from about 300 to about 350 angstroms.
- SION silicon oxynitride
- FIGS. 25 and 26 illustrate a step of forming an array of pillars 2530 and a template portion 2570 .
- FIG. 25 is a cross-sectional view taken along a line C 21 -C 21 ′ of FIG. 21
- FIG. 26 is a cross-sectional view taken along a line C 22 -C 22 ′ of FIG. 22 .
- the guide layer 2500 may be etched using the mask patterns 2622 and 2627 as etch masks, thereby forming the array of the pillars 2530 having the same shape as the pillar features 2022 and the template portion 2570 providing first openings 2578 having the same shape as the first opening features 2028 .
- the array of the pillars 2530 may be formed on the first region 2121 of the semiconductor substrate 2100
- the template portion 2570 may be formed on the second region 2129 of the semiconductor substrate 2100 .
- the pillars 2530 may be arrayed so that four adjacent pillars 2530 are positioned to form a rectangle shape. Alternatively, the pillars 2530 may be arrayed so that three adjacent pillars 2530 are positioned to form a triangular shape.
- the pillars 2530 may be arrayed to have a gap 2533 between two adjacent ones of the pillars 2530 which are disposed on a diagonal portion of the line C 21 -C 21 ′. As illustrated in FIG. 21 , a gap between two adjacent pillar features 2022 which are arrayed on a horizontal line may be narrower than the gap between two adjacent pillar features 2022 which are arrayed on the diagonal portion of the line C 21 -C 21 ′.
- the pillars 2530 may serve as guide patterns that induce self-assembly of the BCP layer which is formed in a subsequent process.
- the first openings 2578 in the template portion 2570 may have a pitch which is greater than a pitch of the pillars 2530 .
- the template portion 2570 may also serve as a guide pattern that induces self-assembly of the BCP layer which is formed in a subsequent process.
- FIGS. 27 and 28 illustrate a step of forming a separation wall layer 2600 .
- FIG. 27 is a cross-sectional view taken along a line C 21 -C 21 ′ of FIG. 21
- FIG. 28 is a cross-sectional view taken along a line C 22 -C 22 ′ of FIG. 22 .
- the separation wall layer 2600 may cover sidewalls of the pillars 2530 , and sidewalls of the first openings 2578 .
- the separation wall layer 2600 may include first separation wall portions 2602 A covering sidewalls of the pillars 2530 , a first extension 2601 A extending from the first separation wall portions 2602 A to cover a portion of the underlying layer 2400 exposed by the gaps 2533 , and second extensions 2603 A extending from the first separation wall portions 2602 A to cover top surfaces of the pillars 2530 .
- the separation wall layer 2600 may further include second separation wall portions 2602 B covering sidewalls of the first openings 2578 , third extensions 2601 B extending from the second separation wall portions 2602 B to cover portions of the underlying layer 2400 exposed by the first openings 2578 , and a fourth extension 2603 B extending from the second separation wall portions 2602 B to cover a top surface of the template portion 2570 .
- the separation wall layer 2600 may provide recessed regions defined by gaps 2631 between the pillars 2530 and recessed regions defined by gaps 2637 in the first openings 2578 .
- the separation wall layer 2600 may be formed of an insulation layer having an etch selectivity with respect to the pillars 2530 and the underlying layer 2400 .
- the separation wall layer 2600 may be formed of an ultra-low temperature oxide (ULTO) layer having a thickness of about 200 angstroms.
- ULTO ultra-low temperature oxide
- FIGS. 29 and 30 illustrate a step of forming the BCP layer 2700 .
- FIG. 29 is a cross-sectional view taken along a line C 21 -C 21 ′ of FIG. 21
- FIG. 30 is a cross-sectional view taken along a line C 22 -C 22 ′ of FIG. 22 .
- the BCP layer 2700 may be formed on the separation wall layer 2600 to fill the gaps 2631 and 2637 which are provided by the pillars 2530 and the template portion 2570 .
- the BCP layer 2700 may include a polystyrene-poly(meta methyl acrylate) block copolymer (PS-b-PMMA) material or a polystyrene-poly(di methyl siloxane) (PS-PDMS) block copolymer material.
- PS-b-PMMA polystyrene-poly(meta methyl acrylate) block copolymer
- PS-PDMS polystyrene-poly(di methyl siloxane)
- the volume ratio of the PS blocks to the PMMA blocks or molecular weights of the PS block and the PMMA block may be appropriately controlled according to a process scheme.
- the PS-b-PMMA material may have a PS block content of about 60 vol. % to about 80 vol. % and a PMMA block content of about 20 vol. % to about 40 vol. %.
- FIGS. 31 and 32 illustrate a step of phase-separating the BCP layer 2700 .
- FIG. 31 is a cross-sectional view taken along a line C 21 -C 21 ′ of FIG. 21
- FIG. 32 is a cross-sectional view taken along a line C 22 -C 22 ′ of FIG. 22 .
- the BCP layer 2700 may be phase-separated through an annealing process into first domains 2710 respectively located at central portions of the gaps 2631 between the pillars 2530 arrayed on the line C 21 -C 21 ′, and a second domain 2730 disposed between the pillars 2530 to surround the first domains 2710 and to isolate the first domains 2710 from each other.
- the first domains 2710 may fill recessed regions provided by the second domain 2730 .
- the first domains 2710 may have post shapes and may be surrounded by the second domain 2730 .
- portions of the BCP layer 700 filling the gaps 2637 provided by the separation wall layer 2600 on the second region 2129 may be phase-separated into third domains 2750 located at central portions of the gaps 2637 and fourth domains 2770 surrounding the third domain 2750 in the gap 2637 .
- the third domains 2750 may be respectively located at the central portions of the gaps 2637
- the fourth domains 2770 may cover sidewalls of the first openings 2578 .
- the phase separation of the BCP layer 2700 may be achieved by annealing the BCP layer 2700 at a temperature exceeding a glass transition temperature Tg of the BCP layer 2700 to rearrange the polymer blocks of the BCP layer 2700 .
- the BCP layer 2700 may be annealed at a temperature ranging from about 100 to about 190 degrees Celsius for a time ranging from about six minutes to about twenty four hours to rearrange the polymer blocks of the BCP layer 2700 .
- FIGS. 33 and 34 illustrate a step of forming a plurality of second openings 2701 and a plurality of third openings 2705 .
- FIG. 33 is a cross-sectional view taken along a line C 21 -C 21 ′ of FIG. 21
- FIG. 34 is a cross-sectional view taken along a line C 22 -C 22 ′ of FIG. 22 .
- the first domains 2710 may be selectively removed to form the plurality of second openings 2701 located between the pillars 2530 .
- the third domain 2750 may also be removed to form the third openings 2705 in the first openings 2578 .
- FIGS. 35 and 36 illustrate a step of forming first extensions 2701 A of the second openings 2701 and first extensions 2705 A of the third openings 2705 .
- FIG. 35 is a cross-sectional view taken along a line C 21 -C 21 ′ of FIG. 21
- FIG. 36 is a cross-sectional view taken along a line C 22 -C 22 ′ of FIG. 22 .
- bottom portions 2731 of the second domains 2730 exposed by the second openings 2701 may be selectively removed to form the first extensions 2701 A of the second openings 2701 extending from the second openings 2701 .
- bottom portions 2771 of the fourth domains 2770 exposed by the third opening 2705 may be also removed to form the first extensions 2705 A of the third openings 2705 .
- FIGS. 37 and 38 illustrate a step of forming second extensions 2701 B of the second openings 2701 and second extensions 2705 B of the third openings 2705 .
- FIG. 37 is a cross-sectional view taken along a line C 21 -C 21 ′ of FIG. 21
- FIG. 38 is a cross-sectional view taken along a line C 22 -C 22 ′ of FIG. 22 .
- the first extensions 2601 A of the separation wall layer 2600 exposed by the first extensions 2701 A of the second openings 2701 may be selectively removed to form the second extensions 2701 B of the second openings 2701 extending from the second openings 2701 .
- the third extensions 2601 B of the separation wall layer 2600 may also be removed to form the second extensions 2705 B of the third openings 2705 .
- the second and fourth extensions 2603 A and 2603 B of the separation wall layer 2600 may also be removed to expose the top surfaces of the pillars 2530 and the template portion 2570 .
- FIGS. 39 and 40 illustrate a step of forming a blocking pattern 2827 .
- FIG. 39 is a cross-sectional view taken along a line C 21 -C 21 ′ of FIG. 21
- FIG. 40 is a cross-sectional view taken along a line C 22 -C 22 ′ of FIG. 22 .
- the blocking pattern 2827 may cover the template portion 2570 and the second extensions 2705 B of the third openings 2705 .
- the blocking pattern 2827 may correspond to a mask that opens the first region 2121 on which the pillars 2530 are arrayed and covers the second region 2129 on which the template portion 2570 is disposed. Before the blocking pattern 2827 is formed, residues of the BCP layer 2700 including the second domains 2730 and the fourth domains 2770 may be removed.
- a sacrificial layer 2810 may be formed on the pillars 2530 and the template portion 2570 to fill the second extensions 2701 B of the second openings 2701 and the second extensions 2705 B of the third openings 2705 . Subsequently, the sacrificial layer 2810 may be patterned to form the blocking pattern 2827 on the second region 2129 as well as a planarized sacrificial layer 2810 on the first region 2121 . In some other embodiments, the blocking pattern 2827 may be formed of a different material from the planarized sacrificial layer 2810 after the planarized sacrificial layer 2810 is formed.
- the blocking pattern 2827 may include a photoresist material
- the planarized sacrificial layer 2810 may include a bottom antireflective coating (BARC) material.
- BARC bottom antireflective coating
- the blocking pattern 2827 and the planarized sacrificial layer 2810 may be formed of two different dielectric layers having an etch selectivity with each other.
- FIGS. 41 and 42 illustrate a step of exposing the top surfaces of the pillars 2530 .
- FIG. 41 is a cross-sectional view taken along a line C 21 -C 21 ′ of FIG. 21
- FIG. 42 is a cross-sectional view taken along a line C 22 -C 22 ′ of FIG. 22 .
- the planarized sacrificial layer 2810 exposed by the blocking pattern 2827 may be partially etched to expose the top surfaces of the pillars 2530 . Subsequently, capping patterns 2503 on the pillars 2530 may be removed to expose the pillars 2530 .
- FIGS. 43 and 44 illustrate a step of removing the pillars 2530 .
- FIG. 43 is a cross-sectional view taken along a line C 21 -C 21 ′ of FIG. 21
- FIG. 44 is a cross-sectional view taken along a line C 22 -C 22 ′ of FIG. 22 .
- the pillars 2530 may be selectively etched and removed using the planarized sacrificial layer 2810 , the first separation wall portions 2602 A, the first extensions 2601 A, and the blocking pattern 2827 as etch mask.
- the pillars 2530 may be removed to form fourth openings 2703 .
- the blocking pattern 2827 and the planarized sacrificial layer 2810 may be selectively removed.
- FIGS. 45 and 46 illustrate a step of forming fifth openings 2415 and sixth openings 2418 .
- FIG. 45 is a cross-sectional view taken along a line C 21 -C 21 ′ of FIG. 21
- FIG. 46 is a cross-sectional view taken along a line C 22 -C 22 ′ of FIG. 22 .
- the underlying layer 2400 on the first region 2121 may be etched using the first separation wall portions 2602 A and the first extensions 2601 A as etch masks, thereby forming the fifth openings 2415 that extend from the second extensions 2701 B of the second openings 701 and extend from the fourth openings 2703 .
- the underlying layer 2400 may be patterned to include a first pattern 2410 that provides the fifth openings 2415 .
- the underlying layer 2400 on the second region 2129 may be etched using the template portion 2570 , the second separation wall portion 2602 B and the third extension 2601 B as etch masks, thereby forming the sixth openings 2418 that extend from the second extensions 2705 B of the third openings 2705 .
- the underlying layer 2400 may be patterned to include a second pattern 2480 that provides the sixth openings 2418 .
- the fifth openings 2415 and the sixth opening 2418 may be simultaneously formed.
- FIGS. 47 and 48 illustrate a step of forming extensions 2215 of the fifth openings 2415 and extensions 2218 of the sixth openings 2418 .
- FIG. 47 is a cross-sectional view taken along a line C 21 -C 21 ′ of FIG. 21
- FIG. 48 is a cross-sectional view taken along a line C 22 -C 22 ′ of FIG. 22 .
- the second etch target layer 2300 and the first etch target layer 2200 may be etched using the first pattern 2410 and the second pattern 2480 as etch masks, thereby forming the extensions 2215 of the fifth openings 2415 and the extensions 2218 of the sixth openings 2418 that penetrate the first and second etch target layers 2200 and 2300 .
- a first pattern 2320 of the second etch target layer 2300 and a first pattern 2220 of the first etch target layer 2200 may be provided by the extensions 2215 of the fifth openings 2415 on the first region 2121
- a second pattern 2380 of the second etch target layer 2300 and a second pattern 2280 of the first etch target layer 2200 may be provided by the extensions 2218 of the sixth openings 2418 on the second region 2129 .
- each of the extensions 2215 of the fifth openings 2415 may penetrate the first and second etch target layers 2200 and 2300 and have the same shape as the first target feature 2015
- each of the extensions 2218 of the sixth openings 2418 may penetrate the first and second etch target layers 2200 and 2300 and have the same shape as the second target feature 2018 .
- FIGS. 49 and 50 are plan views illustrating a process for obtaining a layout of a guide pattern used in a method of forming patterns according to still another embodiment.
- a layout 3019 may be set to include an array of third target features 3018 . While the second target features 2018 are regularly arrayed, the third target features 3018 may be irregularly arrayed.
- a layout 3029 of FIG. 50 may correspond to a layout of first opening features 3028 that are obtained by resizing the third target features 3018 of FIG. 49 .
- Each of the first opening features 3028 may provide a space in which a third domain 3078 is induced.
- the third target features 3018 may be located at the positions of the third domains 3078 , respectively.
- the method of forming patterns described with reference to FIGS. 23 to 48 may also be used in realization of the third target features 3018 which are irregularly arrayed.
- nano-scale structures or nano structures can be fabricated on a large-sized substrate through a phase separation technique of a BCP layer.
- the nano-scale structures may be used in fabrication of polarizing plates or in formation of reflective lens of reflective liquid crystal display (LCD) units.
- the nano structures may also be used in fabrication of separate polarizing plates as well as in formation of polarizing parts including display panels.
- the nano structures may be used in fabrication of array substrates including thin film transistors or in processes for directly forming the polarizing parts on color filter substrates.
- the nano structures may be used in molding processes for fabricating nanowire transistors or memories, molding processes for fabricating electronic/electric components such as nano-scaled interconnections, molding process for fabricating catalysts of solar cells and fuel cells, molding process for fabricating etch masks and organic light emitting diodes (OLEDs), and molding process for fabricating gas sensors.
- molding processes for fabricating nanowire transistors or memories molding processes for fabricating electronic/electric components such as nano-scaled interconnections
- molding process for fabricating catalysts of solar cells and fuel cells molding process for fabricating etch masks and organic light emitting diodes (OLEDs)
- OLEDs organic light emitting diodes
- the methods according to the aforementioned embodiments and structures formed thereby may be used in fabrication of integrated circuit (IC) chips.
- the IC chips may be supplied to users in a raw wafer form, in a bare die form or in a package form.
- the IC chips may also be supplied in a single package form or in a multi-chip package form.
- the IC chips may be integrated in intermediate products such as mother boards or end products to constitute signal processing devices.
- the end products may include toys, low end application products, or high end application products such as computers.
- the end products may include display units, keyboards, or central processing units (CPUs).
Abstract
Description
- The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2015-0048672, filed on Apr. 6, 2015, which is herein incorporated by reference in its entirety as set forth in full.
- 1. Technical Field
- Various embodiments of the present disclosure relate to semiconductor technologies and, more particularly, to methods of forming patterns having different critical dimensions (CDs).
- 2. Related Art
- To increase integration density of semiconductor devices comprised of integrated circuits, it may be necessary to reduce an area occupied by a unit cell of the semiconductor devices and to increase the number of discrete devices such as transistors, resistors, capacitors or the like, integrated in a limited area of a semiconductor substrate. Various techniques have been attempted to realize fine pattern structures having a nano-scale critical dimension (CD), that is, a size ranging from a few nanometers to several tens of nanometers.
- It is difficult to form nano-scale fine patterns of the semiconductor devices only with a photolithography process. Image resolution limits of lithography apparatuses for the photolithography process may be caused by the nature of optical systems for the photolithography process and wavelengths of lights generated from light sources of the optical systems. Methods of forming the fine patterns through a self-assembly of polymer molecules may be considered as a candidate for overcoming the image resolution limits. However, it is difficult to merely apply a direct self-assembly (DSA) of polymer molecules to methods of forming a plurality of patterns having different pitches for example, different widths or different spaces. Accordingly, it is necessary to further develop the methods of forming fine patterns using DSA of the polymer molecules to overcome the limitations of DSA technology.
- Various embodiments are directed to methods of forming different sized patterns.
- According to an embodiment, there is provided a method of forming patterns. The method may include: forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer including first separation wall portions surrounding sidewalls of the pillars, and forming second separation wall portions covering sidewalls of the first opening trench portion; forming a block copolymer layer on the separation wall layer; forming first domains in gaps between the pillars, and forming second domains surrounding and separating the first domains by annealing the block copolymer layer; forming second openings by selectively removing the first domains; forming third openings between the second openings, and forming a fourth opening adjacent to the first isolated pattern by selectively removing the pillars and the template portion; and forming fifth openings, which extend from the second and third openings and penetrate the underlying layer, and forming a sixth opening, which extends from the fourth opening and penetrates the underlying layer.
- According to another embodiment, there is provided a method of forming patterns. The method may include: forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer that covers the pillars, the first isolated pattern and the template portion; forming a block copolymer layer that fills gaps between the pillars and fills a gap between the first isolated pattern and the template portion; forming first domains in the gaps between the pillars, forming second domains surrounding and separating the first domains, forming a third domain in the first opening trench portion, and forming a fourth domain surrounding the third domain, by annealing the block copolymer layer, wherein the third domain is shallower than the first domains and a bottom portion of the fourth domain is thicker than bottom portions of the second domains; forming second openings by removing the first domains, and forming a seventh opening by removing the third domain; forming first extensions of the second openings, which penetrate the bottom portions of the second domains, and an extension of the seventh opening in the fourth domain without penetration of the bottom portion of the fourth domain, by etching the second and fourth domains; forming second extensions of the second openings, and exposing top surfaces of the pillars, a top surface of the first isolated pattern and a top surface of the template portion, by selectively removing portions of the separation wall layer exposed by the first extensions of the second openings; forming third openings by selectively removing the pillars, and forming a fourth opening by selectively removing the template portion; and forming fifth openings that penetrate the underlying layer and extend from the second and third openings, and forming a sixth opening that penetrates the underlying layer and extends from the fourth opening.
- According to another embodiment, there is provided a method of forming patterns. The method may include: forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer that covers the pillars, the first isolated pattern and the template portion; forming a block copolymer layer that fills gaps between the pillars and fills a gap between the first isolated pattern and the template portion; forming first domains in the gaps between the pillars, forming second domains surrounding and separating the first domains, forming a third domain in the first opening trench portion, and forming a fourth domain surrounding the third domain, by annealing the block copolymer layer, wherein the third domain is shallower than the first domains and a bottom portion of the fourth domain is thicker than bottom portions of the second domains; forming second openings by removing the first domains, and forming a seventh opening by removing the third domain; forming first extensions of the second openings which penetrate the bottom portions of the second domains, and an extension of the seventh opening in the fourth domain without penetration of the bottom portion of the fourth domain, by etching the second and fourth domains; forming second extensions of the second openings, and exposing top surfaces of the pillars, a top surface of the first isolated pattern and a top surface of the template portion, by selectively removing portions of the separation wall layer exposed by the first extensions of the second openings; forming a blocking pattern that covers the first isolated pattern and a portion of the template portion adjacent to the first isolated pattern; forming third openings by selectively removing the pillars using the blocking pattern as an etch mask, and forming a fourth opening by selectively removing the template portion; and forming fifth openings that penetrate the underlying layer and extend from the second and third openings, and forming a sixth opening that penetrates the underlying layer and extends from the fourth opening.
- According to another embodiment, there is provided a method of forming patterns. The method may include: forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer including separation wall portions that cover sidewalls of the pillars and sidewalls of the first openings; forming a block copolymer layer on the separation wall layer; forming first domains in gaps between the pillars, forming second domains surrounding and separating the first domains, forming third domains in the first openings, and forming fourth domains surrounding the third domains, by annealing the block copolymer layer; forming second openings in the gaps between the pillars, and forming third openings in the first openings, by selectively removing the first domains and the third domains; forming fourth openings by selectively removing the pillars; and forming fifth openings that penetrate the underlying layer and extend from the second and fourth openings, and forming sixth openings that penetrate the underlying layer and extend from the third openings.
- Various embodiments of the present disclosure will become more apparent in view of the attached drawings and accompanying detailed description, in which:
-
FIGS. 1 to 3 are plan views illustrating a process for obtaining a layout of a guide pattern used in a method of forming patterns according to an embodiment; -
FIG. 4 is a plan view illustrating a layout of a blocking pattern used in a method of forming patterns according to an embodiment; -
FIGS. 5 to 18 are cross-sectional views illustrating a method of forming patterns according to an embodiment; -
FIGS. 19 to 22 are plan views illustrating a process for obtaining a layout of a guide pattern used in a method of forming patterns according to another embodiment; -
FIGS. 23 to 48 are cross-sectional views illustrating a method of forming patterns according to another embodiment; -
FIGS. 49 and 50 are plan views illustrating a process for obtaining a layout of a guide pattern used in a method of forming patterns according to still another embodiment; and -
FIGS. 51 to 53 are schematic views illustrating phase separations of block copolymer (BCP) layers used in exemplary embodiments. - It will be understood that although the terms first, second, third etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in exemplary embodiments could be termed a second element in other embodiments without departing from the teachings of the present disclosure.
- It will also be understood that when an element is referred to as being located “under”, “beneath,” “below”, “lower,” “on”, “over”, “above,” “upper”, “side” or “aside” another element, it can be directly contact the other element, or at least one intervening element may also be present therebetween. Accordingly, the terms such as “under”, “beneath,” “below”, “lower,”, “on”, “over”, “above,” “upper”, “side”, “aside” and the like which are used herein are for the purpose of describing particular embodiments only and are not intended to limit the scope of the present disclosure. Other words used to describe the relationship between elements or layers should be interpreted in a like fashion for example, “between” versus “directly between” or “adjacent” versus “directly adjacent”.
- In the following embodiments, the term “dense patterns” may be used to describe patterns having a relatively small pitch size and a relatively short distance therebetween, and the term “isolated patterns” may be used to describe patterns having a relatively large pitch size and a relatively long distance therebetween. In addition, the term “regularly arrayed patterns” may be used to describe patterns arrayed to have a uniform pitch size and substantially the same distance therebetween, and the term “irregularly arrayed patterns” may be used to describe patterns arrayed to have non-uniform pitch sizes or different distances therebetween. The term “irregularly arrayed patterns” may also be used to describe patterns randomly arrayed without any regularity.
- Exemplary embodiments of the present disclosure may provide methods of forming fine patterns through a phase separation of a block copolymer (BCP) layer so that the patterns have a line width less than a resolution limit of exposure apparatuses. For example, exemplary embodiments of the present disclosure may provide methods of forming an array of contact holes or an array of cutting holes for cutting line-shaped patterns through a direct self-assembly (DSA) technique of the BCP layer. Specific polymer blocks included in the BCP layer may be ordered and phase-separated from a matrix material to form domain portions under a specific condition, and the phase-separated domain portions may be selectively removed to form spaces or patterns having a nano-scaled feature size. The nano-scaled feature size may range from a few nanometers to several tens of nanometers.
- A self-assembled structure of the BCP layer may have a cylindrical shape or a lamellar shape according to a volume ratio of two or more distinct polymer blocks included in the BCP layer, an annealing temperature for the phase separation of the BCP layer, a molecule size of the polymer blocks included in the BCP layer, and a molecular weight of the polymer blocks included in the BCP layer. That is, the phase-separated domain portions of the polymer blocks may have a cylindrical shape or a lamellar shape. When the self-assembled structure of the BCP layer has a cylindrical shape, the BCP layer may be used to form a hole array pattern. When the self-assembled structure of the BCP layer has a lamellar shape, the BCP layer may be used to form a line and space pattern.
- Various embodiments of the present disclosure may be applied to fabrication of highly integrated semiconductor devices, for example, dynamic random access memory (DRAM) devices, phase changeable random access memory (PcRAM) devices or resistive random access memory (ReRAM) devices. In addition, the following embodiments may be applied to fabrication of memory devices such as static random access memory (SRAM) devices, flash memory devices, magnetic random access memory (MRAM) devices or ferroelectric random access memory (FeRAM) devices. The following embodiments may also be applied to fabrication of logic devices, such as control devices, central processing units (CPU) or arithmetic logic units (ALU).
-
FIGS. 1 to 3 are plan views illustrating a process for obtaining a layout of a guide pattern used in a method of forming patterns according to an embodiment. - Referring to
FIG. 1 , alayout 10 of a target feature may include a layout 11 having an array offirst target features 12 that are to be transferred onto a substrate to form fifth openings, and may include a layout 19 having asecond target feature 18 that is to be transferred onto the substrate to form a second isolated pattern. The layout 11 of the first target features 12 and the layout 19 of thesecond target feature 18 may be located at different regions. For example, the layout 11 and the layout 19 may be adjacent to each other. Thefirst target features 12 may be disposed in a dense pattern region such as a cell region, and thesecond target feature 18 may be disposed in an isolated pattern region such as a peripheral region. Thesecond target feature 18 may have a line shape or a polygonal shape. - In the layout 11, the
first target features 12 may include pillar features 13 for portions of guide patterns, and first domain features 14 between the pillar features 13. The first domain features 14 may be surrounded by four adjacent pillar features 13 during phase separation of the BCP material. Accordingly, the pillar features 13 may be separated from the first domain features 14 according to the phase separation of the BCP material. - Referring to
FIGS. 1 and 2 , alayout 20 may include alayout 21 having pillar features 23 and alayout 29 having a firstisolated pattern 28 and a first opening trench. Thelayout 21 having the pillar features 23 may be obtained by separating the first domain features 14 from the layout 11 of the first target features 12. The layout of the firstisolated pattern 28 may be obtained by resizing thesecond target feature 18 corresponding to the second isolated pattern. For example, the layout of the firstisolated pattern 28 may be obtained by two-dimensionally shrinking thesecond target feature 18 by “R1” as shown inFIG. 2 . In such a case, the layout of the firstopening trench portion 27 may be obtained by removing the layout of the firstisolated pattern 28 from thesecond target feature 18. - Referring to
FIG. 3 , alayout 30 of guide patterns may include pillar features 33 arrayed in aregion 31, atemplate portion 39 exposing theregion 31, and a firstisolated pattern 38 disposed in thetemplate portion 39 spaced apart from thetemplate portion 39. The pillar features 33 may correspond to the pillar features 23 ofFIG. 2 , and the firstisolated pattern 38 may correspond to the firstisolated pattern 28 ofFIG. 2 . Aregion 37 between thetemplate portion 39 and the firstisolated pattern 38 may correspond to a firstopening trench portion 27 ofFIG. 2 . That is, the firstisolated pattern 38 may be surrounded by the firstopening trench portion 37 in thetemplate portion 39. -
FIG. 4 is a plan view illustrating alayout 40 of a blockingpattern 48. - Referring to
FIGS. 1 to 4 , thelayout 40 may include the blockingpattern 48 that is transferred onto the firstisolated pattern 38 to form a mask pattern covering the firstisolated pattern 38. The mask pattern formed by the blockingpattern 48 may remain to protect the firstisolated pattern 38 while thetemplate portion 39 is selectively removed. Thus, the firstisolated pattern 38 may still remain due to the presence of the mask pattern formed by the blockingpattern 48 during removal of thetemplate portion 39. The blockingpattern 48 may be obtained by two-dimensionally enlarging the firstisolated pattern 38. For example, the blockingpattern 48 may have a layout of the secondisolated pattern 18. In exemplary embodiments, the blockingpattern 48 may be formed by two-dimensionally enlarging the secondisolated pattern 18 to overlap with a portion of thetemplate portion 39 adjacent to the secondisolated pattern 18. -
FIGS. 5 to 18 are cross-sectional views taken along a line C1-C1′ ofFIGS. 1 to 3 to illustrate a method of forming patterns according to an embodiment. -
FIG. 5 illustrates a step of formingmask patterns - Referring to
FIGS. 1 to 5 , themask patterns mask patterns mask patterns first patterns 633 corresponding to thepillars 33, asecond pattern 638 corresponding to the firstisolated pattern 38, and athird pattern 639 corresponding to thetemplate portion 39. Thus, aspace region 637 between thesecond pattern 638 and thethird pattern 639 may have substantially the same shape as the firstopening trench portion 37. Themask patterns - The guide layer 500 may be patterned in a subsequent process to form guide patterns, which are described with reference to
FIGS. 1 to 3 and define positions of the domains in the phase-separated BCP layer. The guide layer 500 may be formed on asemiconductor substrate 100. Thesemiconductor substrate 100 may include afirst region 131 on which thepillars 33 are disposed with high density, and may include asecond region 139 on which the secondisolated pattern 18 is disposed. Thesecond region 139 may be distinct from and adjacent to thefirst region 131. The guide layer 500 may include a spin-on-carbon (SOC)layer 501 disposed on anunderlying layer 400. TheSOC layer 501 may have a thickness ranging from about 700 to about 800 angstroms. The guide layer 500 may further include acapping layer 503 disposed on theSOC layer 501. Thecapping layer 503 may be formed of a silicon oxynitride (SION) layer having a thickness of about 300 angstroms. - The
underlying layer 400 may be used to pattern a part of or an entire hard mask in a subsequent patterning process. For example, theunderlying layer 400 may serve as one of multi-layers in a hard mask system. A secondetch target layer 300 may be formed between theunderlying layer 400 and thesemiconductor substrate 100. In addition, a firstetch target layer 200 may be formed between the secondetch target layer 300 and thesemiconductor substrate 100. The first or secondetch target layer - The first
etch target layer 200 may be formed of an interlayer insulation layer including a silicon oxide layer such as a tetra-ethyl-ortho-silicate (TEOS) layer having a thickness of about 2200 angstroms. Alternatively, the firstetch target layer 200 may be formed of a conductive layer such as a doped polysilicon layer. The secondetch target layer 300 may be formed by depositing an amorphous SOC layer having a thickness ranging from about 730 to about 1000 angstroms on the firstetch target layer 200. Theunderlying layer 400 may be formed on the secondetch target layer 300 and may include a silicon oxynitride (SION) layer having a thickness ranging from about 300 to about 350 angstroms. -
FIG. 6 illustrates a step of forming an array ofpillars 530, a firstisolated pattern 580 and atemplate portion 590. - Referring to
FIG. 6 , the guide layer 500 may be etched using themask patterns pillars 530, the firstisolated pattern 580 and thetemplate portion 590. The array of thepillars 530 may be formed on thefirst region 131 of thesemiconductor substrate 100, and the firstisolated pattern 580 and thetemplate portion 590 may be formed on thesecond region 139 of thesemiconductor substrate 100. A space region between the firstisolated pattern 580 and thetemplate portion 590 may correspond to a firstopening trench portion 570. - The
pillars 530 may be arrayed so that fouradjacent pillars 530 are positioned to form a rectangular shape. Alternatively, thepillars 530 may be arrayed so that threeadjacent pillars 530 are positioned to form a triangular shape. Thepillars 530 may be arrayed to have a gap 531 between twoadjacent pillars 530 which are disposed on the line C1-C1′. As illustrated inFIG. 3 , a gap between twoadjacent pillars 33 which are arrayed on a horizontal line may be narrower than the gap between twoadjacent pillars 33 which are arrayed on the diagonal portion of the line C1-C1′. Thepillars 530 may serve as guide patterns that induce self-assembly of the BCP layer which is formed in a subsequent process. The firstisolated pattern 580 and thetemplate portion 590 may serve as guide patterns that prevent the self-assembly of the BCP layer on thesecond region 139. -
FIG. 7 illustrates a step of forming aseparation wall layer 600. - Referring to
FIGS. 6 and 7 , theseparation wall layer 600 may include firstseparation wall portions 602A covering sidewalls of thepillars 530, and second separation wall portions 602B covering sidewalls of the firstopening trench portion 570. Theseparation wall layer 600 may includefirst extensions 601A extending from the firstseparation wall portions 602A to cover portions of theunderlying layer 400 exposed by the gaps 531, andsecond extensions 603A extending from the firstseparation wall portions 602A to cover top surfaces of thepillars 530. Theseparation wall layer 600 may further include third extensions 601B extending from the second separation wall portions 602B to cover portions of theunderlying layer 400 exposed by the firstopening trench portion 570, andfourth extensions 6038 extending from the second separation wall portions 602B to cover top surfaces of the firstisolated pattern 580 and thetemplate portion 590. - The
separation wall layer 600 may provide recessed regions defined bygaps 631 between thepillars 530, and a recessed region defined by agap 637 between the firstisolated pattern 580 and thetemplate portion 590. Theseparation wall layer 600 may be formed of an insulation layer having an etch selectivity with respect to thepillars 530 and theunderlying layer 400. For example, theseparation wall layer 600 may be formed of an ultra-low temperature oxide (ULTO) layer having a thickness of about 200 angstroms. -
FIG. 8 illustrates a step of forming theBCP layer 700. - Referring to
FIG. 8 , theBCP layer 700 may be formed on theseparation wall layer 600 to fill thegaps pillars 530, the firstisolated pattern 580 and thetemplate portion 590. TheBCP layer 700 may include a polystyrene-poly (meta methyl acrylate) block copolymer (PS-b-PMMA) material or a polystyrene-poly (di methyl siloxane) (PS-PDMS) block copolymer material. When theBCP layer 700 is formed of the PS-b-PMMA material including PS blocks and PMMA blocks, a volume ratio of the PS blocks to the PMMA blocks may be controlled to be within the range from about 7:3 to about 5:5. The volume ratio of the PS blocks to the PMMA blocks or molecular weights of the PS block and the PMMA block may be appropriately controlled according to a process scheme. For example, the PS-b-PMMA material may have a PS block content of about 60 vol. % to about 80 vol. % and a PMMA block content of about 20 vol. % to about 40 vol. %. -
FIGS. 51 to 53 are schematic views illustrating the phase separation of theBCP layer 700 for exemplary embodiments. TheBCP layer 700 may be a functional polymer material made by combining polymer blocks having two or more distinct structures into a single block copolymer material through a covalent bond, as illustrated inFIG. 51 . As illustrated inFIG. 51 , theBCP layer 700 may have a chain shape including polymer blocks ‘A’ and ‘B’, which are connected to each other by a covalent bond through a link point. Referring toFIG. 52 , theBCP layer 700 may be coated to have a homogeneous phase. Referring toFIG. 53 , the polymer blocks having distinct structures in theBCP layer 700 may have different miscibility and different solubility from each other due to different chemical structures thereof. That is, the polymer blocks having distinct structures are immiscible with each other at a certain temperature. Thus, theBCP layer 700 may be phase-separated through an annealing process to provide a self-aligned structure. Accordingly, theBCP layer 700 having a homogeneous phase may be phase-separated into a domain ‘A’ in which polymer blocks ‘A’ are ordered and a domain ‘B’ in which polymer blocks ‘B’ are ordered, through an annealing process. As such, polymer blocks of theBCP layer 700 may be phase-separated or selectively dissolved in a liquid state or in a solid state to form a self-assembled structure. - A nano-scale structure having a specific shape through the self-assembly of the
BCP layer 700 may be affected by a physical property and/or a chemical property of the polymer blocks of theBCP layer 700. When a BCP layer including two distinct polymer blocks is self-assembled on the substrate, the self-assembled structure of the BCP layer may have a three dimensional cubic shape, a three dimensional double helix shape, a two dimensional hexagonal packed column shape, a two dimensional lamella shape and so forth according to a volume ratio of the polymer blocks included in the BCP layer, an annealing temperature for phase separation of the BCP layer, and a molecule size of the polymer blocks included in the BCP layer. - In exemplary embodiments, the
BCP layer 700 may be formed of polybutadiene-polybutylmethacrylate block copolymer, polybutadiene-polydimethylsiloxane block copolymer, polybutadiene-polymethylmethacrylate block copolymer, polybutadienepolyvinylpyridine block copolymer, polybutylacrylate-polymethylmethacrylate block copolymer, polybutylacrylate-polyvinylpyridine block copolymer, polyisoprene-polyvinylpyridine block copolymer, polyisoprene-polymethylmethacrylate block copolymer, polyhexylacrylatepolyvinylpyridine block copolymer, polyisobutylene-polybutylmethacrylate block copolymer, polyisobutylene-polymethylmethacrylate block copolymer, polyisobutylene-polybutylmethacrylate block copolymer, polyisobutylenepolydimethylsiloxane block copolymer, polybutylmethacrylatepolybutylacrylate block copolymer, polyethylethylene-polymethylmethacrylate block copolymer, polystyrene-polybutylmethacrylate block copolymer, polystyrene-polybutadiene block copolymer, polystyrene-polyisoprene block copolymer, polystyrene-polydimethylsiloxane block copolymer, polystyrene-polyvinylpyridine block copolymer, polyethylethylene-polyvinylpyridine block copolymer, polyethylene-polyvinylpyridine block copolymer, polyvinylpyridinepolymethylmethacrylate block copolymer, polyethyleneoxide-polyisoprene block copolymer, polyethyleneoxide-polybutadiene block copolymer, polyethyleneoxide-polystyrene block copolymer, polyethyleneoxidepolymethylmethacrylate block copolymer, polyethyleneoxide-polydimethylsiloxane block copolymer, polystyrene-polyethyleneoxide block copolymer and so forth. -
FIG. 9 illustrates a step of phase-separating theBCP layer 700. - Referring to
FIGS. 6 to 9 , theBCP layer 700 may be phase-separated through an annealing process intofirst domains 710 respectively located at central portions of thegaps 631 between thepillars 530 arrayed on the line C1-C1′, and asecond domain 730 disposed between thepillars 530 to surround thefirst domains 710 and to isolate thefirst domains 710 from each other. Thefirst domains 710 may fill recessed regions provided by thesecond domain 730. Thus, thefirst domains 710 may have post shapes and may be surrounded by thesecond domain 730. - While the
BCP layer 700 is phase-separated through an annealing process, a portion of theBCP layer 700 filling thegap 637 provided by theseparation wall layer 600 on thesecond region 139 may be phase-separated into athird domain 750 and afourth domain 770 surrounding thethird domain 750 in thegap 637. In such a case, thethird domain 750 may insufficiently expand toward a bottom surface of thegap 637 to have a smaller depth than thefirst domains 710. This is due to thegap 637 having a smaller width than thegaps 631. Since thethird domain 750 does not sufficiently expand toward the bottom surface of thegap 637, a bottom surface D1 of thethird domain 750 may be located adjacent to an entrance of thegap 637. That is, the bottom surface D1 of thethird domain 750 may be located at a higher level than bottom surfaces D2 of thefirst domains 710. Accordingly, a bottom portion 771 of thefourth domain 770 surrounding the bottom surface D1 and sidewalls of thethird domain 750 may be thicker thanbottom portions 731 of thesecond domain 730. In exemplary embodiments, thegap 637 may have an insufficient space to accommodate twodifferent domains BCP layer 700 filling thegap 637 may not be phase-separated even though theBCP layer 700 is annealed. - The phase separation of the
BCP layer 700 may be achieved by annealing theBCP layer 700 at a temperature exceeding a glass transition temperature Tg of theBCP layer 700 to rearrange the polymer blocks of theBCP layer 700. For example, to rearrange the polymer blocks of theBCP layer 700, theBCP layer 700 may be annealed at a temperature ranging from about 100 to about 190 degrees Celsius for a time ranging from about six minutes to about twenty four hours. -
FIG. 10 illustrates a step of forming a plurality of second openings 701 and aseventh opening 705. - Referring to
FIGS. 6 to 10 , thefirst domains 710 may be selectively removed to form the plurality of second openings 701 located between thepillars 530. While thefirst domains 710 are selectively removed, thethird domain 750 may also be removed to form theseventh opening 705 in the firstopening trench portion 570. In such a case, theseventh opening 705 may be shallower than the second openings 701. -
FIG. 11 illustrates a step of forming second extensions 701B of the second openings 701. - Referring to
FIGS. 6 to 11 , thebottom portions 731 of thesecond domain 730 exposed by the second openings 701 may be selectively removed to formfirst extensions 701A of the second openings 701 extending from the second openings 701. While thebottom portions 731 of thesecond domain 730 are selectively removed, the bottom portion 771 of thefourth domain 770 exposed by theseventh opening 705 may be partially removed to form an extension 705B of theseventh opening 705. However, the extension 705B of theseventh opening 705 may be formed not to penetrate the bottom portion 771 of thefourth domain 770. As a result, a feature of theseventh opening 705 may not be transferred into the bottom portion 771 of thefourth domain 770. - Subsequently, the
first extensions 601A of theseparation wall layer 600 exposed by thefirst extensions 701A of the second openings 701 may be selectively removed to form the second extensions 701B of the second openings 701 extending from the second openings 701. While thefirst extensions 601A of theseparation wall layer 600 are selectively removed, thesecond extensions 603A of theseparation wall layer 600 covering the top surfaces of thepillars 530 and thetemplate portion 590 may also be removed to expose the top surfaces of thepillars 530 and thetemplate portion 590. -
FIG. 12 illustrates a step of forming ablocking pattern 848. - Referring to
FIGS. 4 to 12 , the blockingpattern 848 may cover the firstisolated pattern 580. Before theblocking pattern 848 is formed, residues of theBCP layer 700 including thesecond domain 730 and thefourth domain 770 may be removed. After the residues of theBCP layer 700 are removed, asacrificial layer 810 may be formed on thepillars 530, the firstisolated pattern 580 and thetemplate portion 590 to fill the second extensions 701B of the second openings 701, the gaps between thepillars 530, and the gap between the firstisolated pattern 580 and thetemplate portion 590. The blockingpattern 848 may extend to cover the second separation wall portions 602B adjacent to the firstisolated pattern 580. The blockingpattern 848 may be formed by transferring a layout feature of theblocking pattern 848. The blockingpattern 848 may cover all of the firstisolated pattern 580, the second separation wall portions 602B and the third extensions 601B. However, in exemplary embodiments, the blockingpattern 848 may be laterally shifted from an expected position due to an overlay shift during an alignment and exposure process. Even though theblocking pattern 848 is laterally shifted, the firstisolated pattern 580 may still be sealed with the second separation wall portions 602B and theblocking pattern 848 as far as the firstisolated pattern 580 is laterally shifted within an allowable overlay range since the second separation wall portions 602B and theblocking pattern 848 are disposed around the firstisolated pattern 580. -
FIG. 13 is a cross-sectional view illustrating a blocking pattern 848A which is laterally shifted. - Referring to
FIGS. 6 to 13 , in the event that the blocking pattern 848A is laterally shifted by “S”, the blocking pattern 848A may cover a portion of thetemplate portion 590. Nevertheless, the blocking pattern 848A may have an alignment margin of about “R2” corresponding to a width of the firstopening trench portion 570. That is, even though the blocking pattern 848A is shifted so that an edge of the blocking pattern 848A is disposed in the firstopening trench portion 570, the firstisolated pattern 580 may still be sealed with the second separation wall portions 602B and the third extensions 601B. -
FIG. 14 illustrates a step of selectively removing thepillars 530 and thetemplate portion 590. - Referring to
FIGS. 6 to 14 , thepillars 530 and thetemplate portion 590 may be selectively etched and removed using the planarizedsacrificial layer 810, the first and secondseparation wall portions 602A and 602B, the first andthird extensions blocking pattern 848 as etch masks. Thepillars 530 may be removed to formthird openings 633, and thetemplate portion 590 may be removed to form afourth opening 639. -
FIG. 15 illustrates a step of removing theblocking pattern 848. - Referring to
FIGS. 14 and 15 , the blockingpattern 848 and the planarizedsacrificial layer 810 may be selectively removed to expose the second extensions 701B of the second openings 701 extending from the second openings 701. -
FIG. 16 illustrates a step of formingfifth openings 402 and asixth opening 439. - Referring to
FIGS. 6 to 16 , theunderlying layer 400 on thefirst region 131 may be etched using the firstseparation wall portions 602A and thefirst extensions 601A as etch masks, thereby forming thefifth openings 402 that extend from the second extensions 701B of the second openings 701 and extend from thethird openings 633. While thefifth openings 402 are formed, theunderlying layer 400 may be patterned to include afirst pattern 410 that provides thefifth openings 402. In addition, theunderlying layer 400 on thesecond region 139 may be etched using the firstisolated pattern 580, and the second separation wall portion 602B and the third extension 601B as etch masks, thereby forming thesixth opening 439 that extends from thefourth opening 639. Accordingly, theunderlying layer 400 may be patterned to include asecond pattern 418 that provides thesixth opening 439. Thesecond pattern 418 may correspond to the second isolated pattern. Thefifth openings 402 and thesixth opening 439 may be simultaneously formed. -
FIGS. 17 and 18 illustrate a step of formingextensions 202 of thefifth openings 402 and anextension 239 of thesixth opening 439. - Referring to
FIGS. 17 and 18 , the secondetch target layer 300 and the firstetch target layer 200 may be etched using thefirst pattern 410 and the secondisolated pattern 418 as etch masks, thereby forming theextensions 202 of thefifth openings 402 and theextension 239 of thesixth opening 439 that penetrate the first and second etch target layers 200 and 300. As a result, asecond pattern 318 of the secondetch target layer 300 and asecond pattern 218 of the firstetch target layer 200 may be provided by theextension 239 of thesixth opening 439 on thesecond region 139, and afirst pattern 310 of the secondetch target layer 300 and afirst pattern 210 of the firstetch target layer 200 may be provided by theextensions 202 of thefifth opening 402 on thefirst region 131. Subsequently, thefirst pattern 410 of theunderlying layer 400, the secondisolated pattern 418, and the first andsecond patterns etch target layer 300 may be removed to leave thesecond pattern 218 having a planar shape of the secondisolated pattern 418 and thefirst pattern 210 providing theextensions 202 of thefifth opening 402. -
FIGS. 19 to 22 are plan views illustrating a process for obtaining a layout of a guide pattern used in a method of forming patterns according to another embodiment. - Referring to
FIG. 19 , alayout 2011 may include an array of first target features 2015 which are to be transferred onto the substrate to form patterns. The first target features 2015 may form fifth openings that penetrate a material layer disposed on the substrate. The first target features 2015 may be regularly and repeatedly arrayed to have a certain pitch, for example a first pitch P1. The first target features 2015 may include pillar features 2012 arrayed in a diagonal direction and first domain features 2014 disposed between the pillar features 2012. - Referring to
FIGS. 19 and 20 , alayout 2019 may include an array of second target features 2018. Thelayout 2011 of the first target features 2015 shown inFIG. 19 and thelayout 2019 of the second target features 2018 shown inFIG. 20 may be located at two different regions. For example, thelayout 2011 and thelayout 2019 may be adjacent to each other. The second target features 2018 may provide sixth openings that penetrate a material layer disposed on the substrate. Each of the second target features 2018 may have a size which is the same as or different from a size of each of the first target features 2015. While the first target features 2015 are arrayed to have the first pitch P1, the second target features 2018 may be arrayed to have a second pitch P2. The second pitch P2 may be greater than the first pitch P1. For example, the second pitch P2 may be twice or more of the first pitch P1. - Referring to
FIGS. 19 to 21 , alayout 2021 may be obtained by separating the pillar features 2012 from thelayout 2011 of the first target features 2015. That is, thelayout 2021 may include pillar features 2022 corresponding to the pillar features 2012 without first domain features 2024 corresponding to the first domain features 2014. - Referring to
FIGS. 20 to 22 , alayout 2029 may correspond to a layout of first opening features 2028 obtained by resizing the second target features 2018. Each of the first opening features 2028 may provide a space in which athird domain 2078 is induced. As a result, the second target features 2018 may be located at the positions of thethird domains 2078, respectively. -
FIGS. 23 to 50 are cross-sectional views and plan views illustrating a method of forming patterns according to another embodiment. -
FIGS. 23 and 24 illustrate a step of formingmask patterns guide layer 2500.FIG. 23 is a cross-sectional view taken along a line C21-C21′ ofFIG. 21 , andFIG. 24 is a cross-sectional view taken along a line C22-C22′ ofFIG. 22 . - Referring to
FIGS. 21 to 24 , asemiconductor substrate 2100 may have afirst region 2121 and asecond region 2129 that are distinct from each other, and theguide layer 2500 may be formed by sequentially stacking aSOC layer 2501 and acapping layer 2503 on an entire surface of thesemiconductor substrate 2100. Thecapping layer 2503 may be formed of a silicon oxynitride (SiON) layer. The pillar features 2022 of thelayout 2021 may be transferred onto thesemiconductor substrate 2100 to realize thefirst mask patterns 2622 providingopenings 2623 on thefirst region 2121, and the first opening features 2028 of thelayout 2029 may be transferred onto thesemiconductor substrate 2100 to realize thesecond mask patterns 2627 providingopenings 2628 on thesecond region 2129. The first andsecond mask patterns - The
guide layer 2500 may be patterned in a subsequent process to form guide patterns that define positions of domains in a phase-separated BCP layer. Theguide layer 2500 may be formed on anunderlying layer 2400 and may include an SOC layer having a thickness ranging from about 700 to about 800 angstroms. A capping layer (not shown) may be additionally formed on the SOC layer. The capping layer may be formed of a silicon oxynitride (SION) layer having a thickness of about 300 angstroms. - The
underlying layer 2400 may be used to pattern a portion or an entire hard mask in a subsequent patterning process. For example, theunderlying layer 2400 may serve as one of multi-layers in a hard mask system. A secondetch target layer 2300 may be formed between theunderlying layer 2400 and thesemiconductor substrate 2100. In addition, a firstetch target layer 2200 may be formed between the secondetch target layer 2300 and thesemiconductor substrate 2100. The first or secondetch target layer - The first
etch target layer 2200 may be formed of an interlayer insulation layer including a silicon oxide layer such as a tetra-ethyl-ortho-silicate (TEOS) layer having a thickness of about 2200 angstroms. Alternatively, the firstetch target layer 2200 may be formed of a conductive layer such as a doped polysilicon layer. The secondetch target layer 2300 may be formed by depositing an amorphous SOC layer having a thickness ranging from about 730 to about 1000 angstroms on the firstetch target layer 2200. Theunderlying layer 2400 may be formed on the secondetch target layer 2300 and may include a silicon oxynitride (SION) layer having a thickness ranging from about 300 to about 350 angstroms. -
FIGS. 25 and 26 illustrate a step of forming an array ofpillars 2530 and atemplate portion 2570.FIG. 25 is a cross-sectional view taken along a line C21-C21′ ofFIG. 21 , andFIG. 26 is a cross-sectional view taken along a line C22-C22′ ofFIG. 22 . - Referring to
FIGS. 21 to 26 , theguide layer 2500 may be etched using themask patterns pillars 2530 having the same shape as the pillar features 2022 and thetemplate portion 2570 providingfirst openings 2578 having the same shape as the first opening features 2028. The array of thepillars 2530 may be formed on thefirst region 2121 of thesemiconductor substrate 2100, and thetemplate portion 2570 may be formed on thesecond region 2129 of thesemiconductor substrate 2100. - The
pillars 2530 may be arrayed so that fouradjacent pillars 2530 are positioned to form a rectangle shape. Alternatively, thepillars 2530 may be arrayed so that threeadjacent pillars 2530 are positioned to form a triangular shape. Thepillars 2530 may be arrayed to have agap 2533 between two adjacent ones of thepillars 2530 which are disposed on a diagonal portion of the line C21-C21′. As illustrated inFIG. 21 , a gap between two adjacent pillar features 2022 which are arrayed on a horizontal line may be narrower than the gap between two adjacent pillar features 2022 which are arrayed on the diagonal portion of the line C21-C21′. Thepillars 2530 may serve as guide patterns that induce self-assembly of the BCP layer which is formed in a subsequent process. - The
first openings 2578 in thetemplate portion 2570 may have a pitch which is greater than a pitch of thepillars 2530. Thetemplate portion 2570 may also serve as a guide pattern that induces self-assembly of the BCP layer which is formed in a subsequent process. -
FIGS. 27 and 28 illustrate a step of forming aseparation wall layer 2600.FIG. 27 is a cross-sectional view taken along a line C21-C21′ ofFIG. 21 , andFIG. 28 is a cross-sectional view taken along a line C22-C22′ ofFIG. 22 . - Referring to
FIGS. 25 to 28 , theseparation wall layer 2600 may cover sidewalls of thepillars 2530, and sidewalls of thefirst openings 2578. Theseparation wall layer 2600 may include firstseparation wall portions 2602A covering sidewalls of thepillars 2530, afirst extension 2601A extending from the firstseparation wall portions 2602A to cover a portion of theunderlying layer 2400 exposed by thegaps 2533, andsecond extensions 2603A extending from the firstseparation wall portions 2602A to cover top surfaces of thepillars 2530. Theseparation wall layer 2600 may further include second separation wall portions 2602B covering sidewalls of thefirst openings 2578, third extensions 2601B extending from the second separation wall portions 2602B to cover portions of theunderlying layer 2400 exposed by thefirst openings 2578, and a fourth extension 2603B extending from the second separation wall portions 2602B to cover a top surface of thetemplate portion 2570. - The
separation wall layer 2600 may provide recessed regions defined bygaps 2631 between thepillars 2530 and recessed regions defined bygaps 2637 in thefirst openings 2578. Theseparation wall layer 2600 may be formed of an insulation layer having an etch selectivity with respect to thepillars 2530 and theunderlying layer 2400. For example, theseparation wall layer 2600 may be formed of an ultra-low temperature oxide (ULTO) layer having a thickness of about 200 angstroms. -
FIGS. 29 and 30 illustrate a step of forming theBCP layer 2700.FIG. 29 is a cross-sectional view taken along a line C21-C21′ ofFIG. 21 , andFIG. 30 is a cross-sectional view taken along a line C22-C22′ ofFIG. 22 . - Referring to
FIGS. 29 and 30 , theBCP layer 2700 may be formed on theseparation wall layer 2600 to fill thegaps pillars 2530 and thetemplate portion 2570. TheBCP layer 2700 may include a polystyrene-poly(meta methyl acrylate) block copolymer (PS-b-PMMA) material or a polystyrene-poly(di methyl siloxane) (PS-PDMS) block copolymer material. When theBCP layer 2700 is formed of the PS-b-PMMA material including PS blocks and PMMA blocks, a volume ratio of the PS blocks to the PMMA blocks may be controlled to be within the range from about 7:3 to about 5:5. The volume ratio of the PS blocks to the PMMA blocks or molecular weights of the PS block and the PMMA block may be appropriately controlled according to a process scheme. For example, the PS-b-PMMA material may have a PS block content of about 60 vol. % to about 80 vol. % and a PMMA block content of about 20 vol. % to about 40 vol. %. -
FIGS. 31 and 32 illustrate a step of phase-separating theBCP layer 2700.FIG. 31 is a cross-sectional view taken along a line C21-C21′ ofFIG. 21 , andFIG. 32 is a cross-sectional view taken along a line C22-C22′ ofFIG. 22 . - Referring to
FIGS. 26 to 32 , theBCP layer 2700 may be phase-separated through an annealing process intofirst domains 2710 respectively located at central portions of thegaps 2631 between thepillars 2530 arrayed on the line C21-C21′, and asecond domain 2730 disposed between thepillars 2530 to surround thefirst domains 2710 and to isolate thefirst domains 2710 from each other. Thefirst domains 2710 may fill recessed regions provided by thesecond domain 2730. Thus, thefirst domains 2710 may have post shapes and may be surrounded by thesecond domain 2730. - When the
BCP layer 2700 is phase-separated through an annealing process, portions of theBCP layer 700 filling thegaps 2637 provided by theseparation wall layer 2600 on thesecond region 2129 may be phase-separated intothird domains 2750 located at central portions of thegaps 2637 andfourth domains 2770 surrounding thethird domain 2750 in thegap 2637. Thethird domains 2750 may be respectively located at the central portions of thegaps 2637, and thefourth domains 2770 may cover sidewalls of thefirst openings 2578. - The phase separation of the
BCP layer 2700 may be achieved by annealing theBCP layer 2700 at a temperature exceeding a glass transition temperature Tg of theBCP layer 2700 to rearrange the polymer blocks of theBCP layer 2700. For example, theBCP layer 2700 may be annealed at a temperature ranging from about 100 to about 190 degrees Celsius for a time ranging from about six minutes to about twenty four hours to rearrange the polymer blocks of theBCP layer 2700. -
FIGS. 33 and 34 illustrate a step of forming a plurality of second openings 2701 and a plurality ofthird openings 2705. FIG. 33 is a cross-sectional view taken along a line C21-C21′ ofFIG. 21 , andFIG. 34 is a cross-sectional view taken along a line C22-C22′ ofFIG. 22 . - Referring to
FIGS. 26 to 34 , thefirst domains 2710 may be selectively removed to form the plurality of second openings 2701 located between thepillars 2530. When thefirst domains 2710 are selectively removed, thethird domain 2750 may also be removed to form thethird openings 2705 in thefirst openings 2578. -
FIGS. 35 and 36 illustrate a step of formingfirst extensions 2701A of the second openings 2701 and first extensions 2705A of thethird openings 2705.FIG. 35 is a cross-sectional view taken along a line C21-C21′ ofFIG. 21 , andFIG. 36 is a cross-sectional view taken along a line C22-C22′ ofFIG. 22 . - Referring to
FIGS. 35 and 36 ,bottom portions 2731 of thesecond domains 2730 exposed by the second openings 2701 may be selectively removed to form thefirst extensions 2701A of the second openings 2701 extending from the second openings 2701. When thebottom portions 2731 of thesecond domains 2730 are selectively removed, bottom portions 2771 of thefourth domains 2770 exposed by thethird opening 2705 may be also removed to form the first extensions 2705A of thethird openings 2705. -
FIGS. 37 and 38 illustrate a step of forming second extensions 2701B of the second openings 2701 and second extensions 2705B of thethird openings 2705.FIG. 37 is a cross-sectional view taken along a line C21-C21′ ofFIG. 21 , andFIG. 38 is a cross-sectional view taken along a line C22-C22′ ofFIG. 22 . - Referring to
FIGS. 27 to 38 , thefirst extensions 2601A of theseparation wall layer 2600 exposed by thefirst extensions 2701A of the second openings 2701 may be selectively removed to form the second extensions 2701B of the second openings 2701 extending from the second openings 2701. When thefirst extensions 2601A of theseparation wall layer 2600 are selectively removed, the third extensions 2601B of theseparation wall layer 2600 may also be removed to form the second extensions 2705B of thethird openings 2705. When thefirst extensions 2601A and the third extensions 2601B of theseparation wall layer 2600 are selectively removed, the second andfourth extensions 2603A and 2603B of theseparation wall layer 2600 may also be removed to expose the top surfaces of thepillars 2530 and thetemplate portion 2570. -
FIGS. 39 and 40 illustrate a step of forming ablocking pattern 2827.FIG. 39 is a cross-sectional view taken along a line C21-C21′ ofFIG. 21 , andFIG. 40 is a cross-sectional view taken along a line C22-C22′ ofFIG. 22 . - Referring to
FIGS. 39 and 40 , theblocking pattern 2827 may cover thetemplate portion 2570 and the second extensions 2705B of thethird openings 2705. Theblocking pattern 2827 may correspond to a mask that opens thefirst region 2121 on which thepillars 2530 are arrayed and covers thesecond region 2129 on which thetemplate portion 2570 is disposed. Before theblocking pattern 2827 is formed, residues of theBCP layer 2700 including thesecond domains 2730 and thefourth domains 2770 may be removed. After the residues of theBCP layer 2700 are removed, asacrificial layer 2810 may be formed on thepillars 2530 and thetemplate portion 2570 to fill the second extensions 2701B of the second openings 2701 and the second extensions 2705B of thethird openings 2705. Subsequently, thesacrificial layer 2810 may be patterned to form theblocking pattern 2827 on thesecond region 2129 as well as a planarizedsacrificial layer 2810 on thefirst region 2121. In some other embodiments, theblocking pattern 2827 may be formed of a different material from the planarizedsacrificial layer 2810 after the planarizedsacrificial layer 2810 is formed. In such a case, theblocking pattern 2827 may include a photoresist material, and the planarizedsacrificial layer 2810 may include a bottom antireflective coating (BARC) material. In exemplary embodiments, theblocking pattern 2827 and the planarizedsacrificial layer 2810 may be formed of two different dielectric layers having an etch selectivity with each other. -
FIGS. 41 and 42 illustrate a step of exposing the top surfaces of thepillars 2530.FIG. 41 is a cross-sectional view taken along a line C21-C21′ ofFIG. 21 , andFIG. 42 is a cross-sectional view taken along a line C22-C22′ ofFIG. 22 . - Referring to
FIGS. 41 and 42 , the planarizedsacrificial layer 2810 exposed by theblocking pattern 2827 may be partially etched to expose the top surfaces of thepillars 2530. Subsequently, cappingpatterns 2503 on thepillars 2530 may be removed to expose thepillars 2530. -
FIGS. 43 and 44 illustrate a step of removing thepillars 2530.FIG. 43 is a cross-sectional view taken along a line C21-C21′ ofFIG. 21 , andFIG. 44 is a cross-sectional view taken along a line C22-C22′ ofFIG. 22 . - Referring to
FIGS. 43 and 44 , thepillars 2530 may be selectively etched and removed using the planarizedsacrificial layer 2810, the firstseparation wall portions 2602A, thefirst extensions 2601A, and theblocking pattern 2827 as etch mask. Thepillars 2530 may be removed to form fourth openings 2703. Subsequently, theblocking pattern 2827 and the planarizedsacrificial layer 2810 may be selectively removed. -
FIGS. 45 and 46 illustrate a step of formingfifth openings 2415 andsixth openings 2418.FIG. 45 is a cross-sectional view taken along a line C21-C21′ ofFIG. 21 , andFIG. 46 is a cross-sectional view taken along a line C22-C22′ ofFIG. 22 . - Referring to
FIGS. 45 and 46 , theunderlying layer 2400 on thefirst region 2121 may be etched using the firstseparation wall portions 2602A and thefirst extensions 2601A as etch masks, thereby forming thefifth openings 2415 that extend from the second extensions 2701B of the second openings 701 and extend from the fourth openings 2703. Theunderlying layer 2400 may be patterned to include afirst pattern 2410 that provides thefifth openings 2415. - In addition, the
underlying layer 2400 on thesecond region 2129 may be etched using thetemplate portion 2570, the second separation wall portion 2602B and the third extension 2601B as etch masks, thereby forming thesixth openings 2418 that extend from the second extensions 2705B of thethird openings 2705. Accordingly, theunderlying layer 2400 may be patterned to include asecond pattern 2480 that provides thesixth openings 2418. Thefifth openings 2415 and thesixth opening 2418 may be simultaneously formed. -
FIGS. 47 and 48 illustrate a step of formingextensions 2215 of thefifth openings 2415 andextensions 2218 of thesixth openings 2418.FIG. 47 is a cross-sectional view taken along a line C21-C21′ ofFIG. 21 , andFIG. 48 is a cross-sectional view taken along a line C22-C22′ ofFIG. 22 . - Referring to
FIGS. 19 to 48 , the secondetch target layer 2300 and the firstetch target layer 2200 may be etched using thefirst pattern 2410 and thesecond pattern 2480 as etch masks, thereby forming theextensions 2215 of thefifth openings 2415 and theextensions 2218 of thesixth openings 2418 that penetrate the first and secondetch target layers first pattern 2320 of the secondetch target layer 2300 and afirst pattern 2220 of the firstetch target layer 2200 may be provided by theextensions 2215 of thefifth openings 2415 on thefirst region 2121, and asecond pattern 2380 of the secondetch target layer 2300 and a second pattern 2280 of the firstetch target layer 2200 may be provided by theextensions 2218 of thesixth openings 2418 on thesecond region 2129. Accordingly, each of theextensions 2215 of thefifth openings 2415 may penetrate the first and secondetch target layers first target feature 2015, and each of theextensions 2218 of thesixth openings 2418 may penetrate the first and secondetch target layers second target feature 2018. -
FIGS. 49 and 50 are plan views illustrating a process for obtaining a layout of a guide pattern used in a method of forming patterns according to still another embodiment. - Referring to
FIGS. 20 to 50 , alayout 3019 may be set to include an array of third target features 3018. While the second target features 2018 are regularly arrayed, the third target features 3018 may be irregularly arrayed. A layout 3029 ofFIG. 50 may correspond to a layout of first opening features 3028 that are obtained by resizing the third target features 3018 ofFIG. 49 . Each of the first opening features 3028 may provide a space in which athird domain 3078 is induced. As a result, the third target features 3018 may be located at the positions of thethird domains 3078, respectively. The method of forming patterns described with reference toFIGS. 23 to 48 may also be used in realization of the third target features 3018 which are irregularly arrayed. - According to the embodiments described above, nano-scale structures or nano structures can be fabricated on a large-sized substrate through a phase separation technique of a BCP layer. The nano-scale structures may be used in fabrication of polarizing plates or in formation of reflective lens of reflective liquid crystal display (LCD) units. The nano structures may also be used in fabrication of separate polarizing plates as well as in formation of polarizing parts including display panels. For example, the nano structures may be used in fabrication of array substrates including thin film transistors or in processes for directly forming the polarizing parts on color filter substrates. Furthermore, the nano structures may be used in molding processes for fabricating nanowire transistors or memories, molding processes for fabricating electronic/electric components such as nano-scaled interconnections, molding process for fabricating catalysts of solar cells and fuel cells, molding process for fabricating etch masks and organic light emitting diodes (OLEDs), and molding process for fabricating gas sensors.
- The methods according to the aforementioned embodiments and structures formed thereby may be used in fabrication of integrated circuit (IC) chips. The IC chips may be supplied to users in a raw wafer form, in a bare die form or in a package form. The IC chips may also be supplied in a single package form or in a multi-chip package form. The IC chips may be integrated in intermediate products such as mother boards or end products to constitute signal processing devices. The end products may include toys, low end application products, or high end application products such as computers. For example, the end products may include display units, keyboards, or central processing units (CPUs).
- The embodiments of the present disclosure have been disclosed above for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions, and substitutions are possible, without departing from the scope and spirit of the present disclosure as disclosed in the accompanying claims.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/242,903 US9691614B2 (en) | 2015-04-06 | 2016-08-22 | Methods of forming different sized patterns |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2015-0048672 | 2015-04-06 | ||
KR1020150048672A KR102358710B1 (en) | 2015-04-06 | 2015-04-06 | Method of forming different sized patterns |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/242,903 Continuation US9691614B2 (en) | 2015-04-06 | 2016-08-22 | Methods of forming different sized patterns |
Publications (2)
Publication Number | Publication Date |
---|---|
US9449840B1 US9449840B1 (en) | 2016-09-20 |
US20160293443A1 true US20160293443A1 (en) | 2016-10-06 |
Family
ID=56896186
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/850,419 Active US9449840B1 (en) | 2015-04-06 | 2015-09-10 | Methods of forming different sized patterns |
US15/242,903 Active US9691614B2 (en) | 2015-04-06 | 2016-08-22 | Methods of forming different sized patterns |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/242,903 Active US9691614B2 (en) | 2015-04-06 | 2016-08-22 | Methods of forming different sized patterns |
Country Status (3)
Country | Link |
---|---|
US (2) | US9449840B1 (en) |
KR (1) | KR102358710B1 (en) |
CN (1) | CN106057651B (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170294354A1 (en) * | 2016-04-07 | 2017-10-12 | Globalfoundries Inc. | Integration of nominal gate width finfets and devices having larger gate width |
US9799514B1 (en) | 2016-04-07 | 2017-10-24 | Globalfoundries Inc. | Protecting, oxidizing, and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines |
US10068766B2 (en) | 2016-04-07 | 2018-09-04 | Globalfoundries Inc. | Oxidizing and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines |
US11676816B2 (en) * | 2018-11-12 | 2023-06-13 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102358710B1 (en) * | 2015-04-06 | 2022-02-08 | 에스케이하이닉스 주식회사 | Method of forming different sized patterns |
KR102317785B1 (en) * | 2015-05-12 | 2021-10-26 | 삼성전자주식회사 | Method of forming pattern and method of manufacturing integrated circuit device using the same |
CN108400085B (en) * | 2017-02-06 | 2019-11-19 | 联华电子股份有限公司 | The method for forming semiconductor element pattern |
US10312435B1 (en) * | 2018-01-09 | 2019-06-04 | Spin Memory, Inc. | Method for manufacturing high density magnetic tunnel junction devices using photolithographic VIAS and chemically guided block copolymer self assembly |
CN110634733A (en) * | 2018-06-22 | 2019-12-31 | 长鑫存储技术有限公司 | Method for preparing semiconductor memory capacitor hole |
US11069693B2 (en) * | 2018-08-28 | 2021-07-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for improving control gate uniformity during manufacture of processors with embedded flash memory |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8610262B1 (en) * | 2005-02-18 | 2013-12-17 | Utac Hong Kong Limited | Ball grid array package with improved thermal characteristics |
US8557128B2 (en) * | 2007-03-22 | 2013-10-15 | Micron Technology, Inc. | Sub-10 nm line features via rapid graphoepitaxial self-assembly of amphiphilic monolayers |
KR20090050735A (en) * | 2007-11-16 | 2009-05-20 | 주식회사 하이닉스반도체 | Method for repairing critical dimension of pattarn in photomask |
US8114306B2 (en) | 2009-05-22 | 2012-02-14 | International Business Machines Corporation | Method of forming sub-lithographic features using directed self-assembly of polymers |
JP2011129874A (en) * | 2009-11-19 | 2011-06-30 | Toshiba Corp | Pattern forming method and pattern forming apparatus |
US9233840B2 (en) * | 2010-10-28 | 2016-01-12 | International Business Machines Corporation | Method for improving self-assembled polymer features |
WO2013158527A1 (en) * | 2012-04-16 | 2013-10-24 | Brewer Science Inc. | Silicon hardmask layer for directed self-assembly |
US9005877B2 (en) * | 2012-05-15 | 2015-04-14 | Tokyo Electron Limited | Method of forming patterns using block copolymers and articles thereof |
JP5537628B2 (en) | 2012-10-09 | 2014-07-02 | 株式会社東芝 | Method for forming self-organized pattern |
US9581899B2 (en) * | 2012-11-27 | 2017-02-28 | International Business Machines Corporation | 2-dimensional patterning employing tone inverted graphoepitaxy |
JP2014192400A (en) * | 2013-03-27 | 2014-10-06 | Nikon Corp | Mark forming method, mark detecting method, and device manufacturing method |
KR20150014009A (en) * | 2013-07-25 | 2015-02-06 | 에스케이하이닉스 주식회사 | Method for fabricating fine pattern |
KR102105196B1 (en) | 2013-07-25 | 2020-04-29 | 에스케이하이닉스 주식회사 | Method for fabricating semiconductor device |
KR102166523B1 (en) | 2013-12-02 | 2020-10-16 | 에스케이하이닉스 주식회사 | Structure and Method of fabricating nano scale features and structure including the features |
KR102358710B1 (en) * | 2015-04-06 | 2022-02-08 | 에스케이하이닉스 주식회사 | Method of forming different sized patterns |
-
2015
- 2015-04-06 KR KR1020150048672A patent/KR102358710B1/en active IP Right Grant
- 2015-09-10 US US14/850,419 patent/US9449840B1/en active Active
- 2015-11-20 CN CN201510812017.1A patent/CN106057651B/en active Active
-
2016
- 2016-08-22 US US15/242,903 patent/US9691614B2/en active Active
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170294354A1 (en) * | 2016-04-07 | 2017-10-12 | Globalfoundries Inc. | Integration of nominal gate width finfets and devices having larger gate width |
US9799514B1 (en) | 2016-04-07 | 2017-10-24 | Globalfoundries Inc. | Protecting, oxidizing, and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines |
US10068766B2 (en) | 2016-04-07 | 2018-09-04 | Globalfoundries Inc. | Oxidizing and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines |
US11676816B2 (en) * | 2018-11-12 | 2023-06-13 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US9449840B1 (en) | 2016-09-20 |
US9691614B2 (en) | 2017-06-27 |
US20160358771A1 (en) | 2016-12-08 |
KR102358710B1 (en) | 2022-02-08 |
CN106057651B (en) | 2020-08-14 |
CN106057651A (en) | 2016-10-26 |
KR20160119940A (en) | 2016-10-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9691614B2 (en) | Methods of forming different sized patterns | |
US9721795B2 (en) | Methods of forming patterns having different shapes | |
US8999862B1 (en) | Methods of fabricating nano-scale structures and nano-scale structures fabricated thereby | |
US9840059B2 (en) | Fine pattern structures having block co-polymer materials | |
US9202744B1 (en) | Methods of fabricating interconnection structures | |
US9190274B2 (en) | Methods of fabricating fine patterns | |
KR102105196B1 (en) | Method for fabricating semiconductor device | |
US9666448B2 (en) | Methods of forming patterns | |
US9911605B2 (en) | Methods of forming fine patterns | |
US10504726B2 (en) | Nano-scale structures | |
US9640399B2 (en) | Methods of forming patterns with block copolymer | |
US10056257B2 (en) | Methods for forming fine patterns using spacers | |
US9478436B1 (en) | Methods for forming patterns in honeycomb array | |
KR20180026157A (en) | Method of fabricating interconnection structure by using dual damascene process |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SK HYNIX INC., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BAN, KEUN DO;PARK, JONG CHEON;HEO, JUNG GUN;AND OTHERS;REEL/FRAME:036534/0772 Effective date: 20150826 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |