KR20180026157A - Method of fabricating interconnection structure by using dual damascene process - Google Patents

Abstract

Provided is a method for forming a wiring structure, which comprises the steps of: forming a line pattern template which provides a via pattern template layer and a trench on a substrate; applying a block copolymer layer; annealing the block copolymer layer to induce a polymeric matrix and polymer domains; selectively removing the polymer domains to form cavities; forming a via blocking pattern for blocking a part of the cavities; and forming a via hole by extending the other parts of the exposed cavities into the via pattern template layer.

Description

TECHNICAL FIELD [0001] The present invention relates to a method of forming a wiring structure using a dual damascene process,

The present application relates to a method of forming an interconnection structure using a dual damascene process.

The semiconductor industry is rapidly growing, and efforts are being made to realize integrated circuits with higher device densities. In order to integrate a larger number of devices into a limited area, efforts are being made to reduce the area occupied by unit cells in a planar manner. Various techniques have been attempted to realize the structure of fine patterns having a nanoscale line width (CD: critical dimension or pitch) of several nm to several tens nm.

A process of forming a metal interconnection structure by a dual damascene process has been applied. However, the pattern size of a conductive via, which is greatly reduced, . Due to the exposure resolution limitations of lithography systems, it becomes increasingly more difficult to pattern conductive vias of finer sizes, making it difficult to form metal wiring structures with a dual damascene process.

This application proposes a method of forming a metal wiring structure having a conductive via by applying a phase coherence of a block co-polymer to a dual damascene process.

One aspect of the present application includes a method of fabricating a semiconductor device, comprising: forming a via pattern template layer on a substrate; Forming a line pattern template that provides a trench on the via patterned template layer; Applying a block copolymer layer filling the trench; Annealing the block copolymer layer to induce a polymeric matrix and polymer domains; Selectively removing the polymer domains to form cavities; Forming a via blocking pattern to block a portion of the cavities; And forming via holes by extending other portions of the cavities exposed by the via blocking pattern into the via pattern template layer.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: sequentially forming a via pattern template layer and a line pattern template layer on a substrate; Forming first trenches in the line pattern template layer; Forming second trenches in the line pattern template layer; Applying a block copolymer layer filling the first and second trenches; Annealing the block copolymer layer to induce a polymeric matrix and polymer domains; Selectively removing the polymer domains to form cavities; Forming a via blocking pattern to block a portion of the cavities; And forming via holes by extending other portions of the cavities exposed by the via blocking pattern into the via pattern template layer.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: sequentially forming a via pattern template layer and a line pattern template layer on a substrate; Forming first trenches in the line pattern template layer; Applying a first block copolymer layer filling the first trenches; Annealing the first block copolymer layer to induce a polymeric first matrix polymer domain and polymeric first domains; Selectively removing the polymer first domains to form first cavities; Forming second trenches in the line pattern template layer; Applying a second block copolymer layer filling the second trenches; Annealing the second block copolymer layer to induce a polymeric second matrix polymer domain and polymer domain second polymer domains; Selectively removing the polymer second domains to form second cavities; Forming a via blocking pattern to block a portion of the first and second cavities; And forming via holes by extending other portions of the first and second cavities exposed by the via-blocking pattern into the via patterned template layer. .

According to embodiments of the present application, a method of forming a connection wiring structure having conductive vias by applying a phase coherence of a block co-polymer to a dual damascene process can be presented.

1 to 15 are views showing a method of forming a metal wiring structure according to an example of the present application.
16 to 21 are views showing a method of forming a metal wiring structure according to an example of the present application.
22 to 36 are views showing a method of forming a metal wiring structure according to an example of the present application.
37 to 39 are diagrams showing phase separation of a block copolymer.

The terms used in describing the example of the present application are selected in consideration of the functions in the illustrated embodiments, and the meaning of the terms may be changed according to the intentions or customs of the user, the operator in the technical field, and so on. The meaning of the term used is in accordance with the defined definition when specifically defined in this specification and can be interpreted in a sense generally recognized by those skilled in the art without specific definition. In the description of the examples of the present application, a substrate such as "first" and "second", "top" and "bottom" It is not meant to be taken to be a meaning but to mean a relative positional relationship and not to a specific case in which the member is directly contacted or further members are introduced into the interface between the members. The same interpretation can be applied to other expressions that describe the relationship between the components.

A method of applying a phase separation process of a block co-polymer to a process of forming a damascene metallization structure having vias can be suggested. Directly self-aligned block domains are induced by phase separation of the block copolymer, and via holes can be formed through which the conductive vias are formed by selectively removing the block domains. Thereby, a separate additional lithography process for the conductive vias can be omitted, and also the exposure resolution limit of the lithography process can be overcome.

The specific polymer blocks of the block copolymer (BCP) are ordered so that the domains of the polymer blocks are phase separated from the matrix and the phase separated domains are selectively removed to form a nanoscale-sized shape features can be derived. Since the block domain can have a nanoscale size ranging from several nanometers to several tens nanometers, the line width size of the conductive vias can be realized with a very small nanoscale line width size.

Embodiments of the present application can be applied to the integration of PcRAM devices, memory devices such as ReRAM, SRAM, FLASH, MRAM, or FeRAM, or logic devices in which logic integrated circuits are integrated. Embodiments of the present application can be applied to form a logic circuit interconnection structure comprising conductive vias spaced apart or arranged in a mutually non-regular manner and conductive lines interconnecting these conductive vias.

Like reference characters throughout the specification may refer to the same elements. The same reference numerals or similar reference numerals can be described with reference to other drawings, even if they are not mentioned or described in the drawings. Further, even if the reference numerals are not shown, they can be described with reference to other drawings.

1 to 15 show a method of forming a metal wiring structure according to an example of the present application.

FIG. 1 is a layout showing a planar arrangement shape of a trench 410 of a line pattern template 400. 2 is a view showing a cross-sectional shape along the cutting line A1-A1 'in FIG.

Referring to FIGS. 1 and 2, a first dielectric layer 120 is formed on a semiconductor substrate 100 (FIG. 2), and a lower conductive line 210 is formed on a first dielectric layer 120 as a conductive element. Respectively. The lower conductive lines 210 may be provided as a first metal line Ml in the multilayer wiring structure. The lower conductive lines 210 may be formed to include a copper (Cu) layer having a lower resistance for improving the operating speed of the device.

The semiconductor substrate 100 may be provided with electronic elements such as transistors structures including gates 113 and 114 and junctions 111 and 112. The junctions 111 and 112 may be provided as a drain region or a source region of the transistor. The first lower conductive line 218 is connected to the first junction 111 of the first transistor including the first junction 111 and the first gate 113 by a conductive plug 121 Or may be electrically connected by a conductive contact. The second lower conductive line 217 is connected to the second junction 113 of the second transistor including the second junction 113 and the second gate 114 by a connection pattern such as the second conductive plug 122 And can be electrically connected. The first and second transistors may be electronic elements forming a logic circuit.

A second dielectric layer 200 isolating and insulating the lower conductive lines 210 may be formed on the first dielectric layer 120. A first dielectric layer 120 may comprise a layer of dielectric material of the silicone base (silicon base), such as a silicon oxide (SiO _2), silicon nitride (Si ₃ N _4). A second dielectric layer 200 may comprise a layer of dielectric material of a silicone base such as a silicon oxide (SiO _2), silicon nitride (Si ₃ N _4). The first dielectric layer 120 or the second dielectric layer 200 may be formed of a stack of a single dielectric material or a plurality of multilayer dielectric layers.

A template layer for via pattern 300 covering the lower conductive lines 210 may be formed on the second dielectric layer 200. [ The via patterned template layer 300 may be an interlayered layer or a multilayered wiring layer structure that isolates the upper conductive lines (not shown) to be provided on the lower conductive lines 210 and the via patterned template layer 300 May be formed of an intermetallic dielectric layer (IMD). Via pattern template layer 300 may be formed of a single layer or multiple layers, including a layer of dielectric material of a silicone base such as a layer of dielectric material, e.g., silicon oxide (SiO _2), silicon nitride (Si ₃ N ₄₎ .

A template for line pattern 400 may be formed on the via patterned template layer 300 to provide a pattern shape of the upper conductive line. The line pattern template 400 may be formed as a layer that provides a pattern shape of the upper conductive line to be electrically connected to the lower conductive lines 210 by the via pattern. The line pattern template 400 may include a trench 410 to provide a patterned top conductive line with a recessed opening region.

After forming a layer for the line pattern template 400 on the via patterned template layer 300, a mask pattern 700 for patterning the line patterned template layer may be formed. The mask pattern 700 may be formed by forming a photoresist layer on the line pattern template layer, and then performing a lithography process including exposure and development. The line pattern template 400 having the trenches 410 can be formed by selectively etching and removing the line pattern template layer exposed by the mask pattern 700. [ The trenches 410 may be formed to overlap at least two lower conductive lines 210, for example, the first lower conductive line 218 and the second lower conductive line 217. The surface of the via pattern template layer 300 may be exposed at the bottom of the trench 410. Line pattern templates 400 may be formed as a single layer or multiple layers, including a layer of dielectric material of a silicone base such as a layer of dielectric material, e.g., silicon oxide (SiO _2), silicon nitride (Si ₃ N _4).

The trenches 410 of the line pattern template 400 may be patterned in a line shape extending in the X-axis direction orthogonal to each other or extending in the Y-axis direction, as shown in Fig. Or may be patterned into a shape that extends in the X-axis direction and then bends to extend again in the Y-axis direction.

3 is a layout showing a planar arrangement shape of the polymer matrix part 520. In FIG. FIGS. 4 to 6 illustrate a process of forming the polymer matrix portion 520 and show cross-sectional shapes along the cutting line A1-A1 'of FIG.

Referring to FIGS. 3 and 4, a block copolymer layer 500 filling the trenches 410 is coated in the trenches 410 of the line pattern template 400. The block copolymer layer 500 may be formed by coating a polystyrene-polymethylmethacrylate (PS-PMMA) block copolymer. Or the block copolymer layer 500 may utilize a polystyrene-polydimethylsiloxane (PS-PDMS) block copolymer. When the block copolymer layer 500 is formed of a polystyrene-polymethylmethacrylate block copolymer of PS and PMMA, the volume ratio of PS and PMMA can be adjusted to approximately 70:30. This volume ratio, the molecular weight of each polymer block component, and the like can be adjusted to match the process.

The block copolymer (BCP) is a functional polymer in which polymer blocks having two or more different structures are combined with one polymer through covalent bonding as shown in FIG. As shown in FIG. 37 showing a single block copolymer, the polymer block component A and the polymer block component B may have a chain polymer shape connected to a covalent bond point. The block copolymer may be coated in a homogenous phase in a mixed state as shown in FIG.

Each of the polymer blocks constituting the block copolymer may have different mixing characteristics and different selective solubilities due to differences in their chemical structures. The polymer block components are chemically immiscible and can be phase-separated by annealing, and a self-aligned structure can be realized using such phase separation. As shown in Fig. 39 showing the phase separation phenomenon, a homogeneous monolayer coated block copolymer is obtained by annealing a domain A in which polymer blocks A are ordered and a domain B in which polymer blocks B are aligned, . Alternatively, the polymer blocks A may be phase-separated into domains A in a matrix portion containing polymer blocks B. As such, the block copolymer can provide phase separation or selective solubility in solution or solid phase, thereby forming a self-assembled structure.

It is possible that the block copolymer constituting the microstructure of a specific shape through self-assembly may be influenced by the physical or / or chemical properties of each block polymer. When a block copolymer composed of two different polymers is self-assembled on a substrate, the self-assembled structure of the block copolymer is determined by the volume ratio of each polymer block constituting the block copolymer, the annealing temperature for phase separation, A hexagonal packed column structure and a lamella structure, which are three-dimensional structures, such as a cubic structure and a double helix structure, and a two-dimensional structure, depending on the size of the substrate.

The block copolymer may be selected from the group consisting of a polybutadiene-polybutylmethacrylate block copolymer, a polybutadiene-polydimethylsiloxane block copolymer, a polybutadiene-polymethylmethacrylate block Polybutadienepolyvinylpyridine block copolymers, polybutylacrylate-polymethylmethacrylate block copolymers, polybutylacrylate-polyvinylpyridine block copolymers, polybutadiene-polyvinylpyridine block copolymers, Polymer, polyisoprene-polyvinylpyridine block copolymer, polyisoprene-polymethylmethacrylate block copolymer, polyhexylacrylatepolyvinylpyridine block copolymer, poly Polyisobutylene-polybutylmethacrylate block copolymer, polyisobutylene-polymethylmethacrylate block copolymer, polyisobutylene-polybutylmethacrylate block copolymer, polyisobutylene- polybutylmethacrylate block copolymers, polyisobutylenepolydimethylsiloxane block copolymers, polybutylmethacrylatepolybutylacrylate block copolymers, polyethylethylene-polymethyl methacrylate block copolymers, polymethylmethacrylate block copolymer, polystyrene-polybutylmethacrylate block copolymer, polystyrene-polybutadiene block copolymer, polystyrene-polyisoprene block copolymer, polystyrene- Polymethylsiloxane ( polystyrene-polydimethylsiloxane block copolymers, polystyrene-polyvinylpyridine block copolymers, polyethylethylene-polyvinylpyridine block copolymers, polyethylene-polyvinylpyridine block copolymers, Polymer, polyvinylpyridinepolymethylmethacrylate block copolymer, polyethyleneoxide-polyisoprene block copolymer, polyethyleneoxide-polybutadiene block copolymer, polyethylene oxide-polystyrene (polyvinylpyridinepolymethylmethacrylate) polyethyleneoxide-polystyrene block copolymer, polyethylene oxide-polymethylmethacrylate block copolymer, polyethylene oxide-polydimethylsiloxane block copolymer, polystyrene - it may be used polyethylene oxide (polyethyleneoxide-polystyrene) block copolymer and the like.

5, a block copolymer layer 500 filling the trenches 410 of the line pattern template 400 is annealed to form a polymer domain 510 in the shape of a cylinder and a polymer matrix part 500 in the shape of a cylinder. (520). The block copolymer layer 500 can be formed by mixing a first polymer block, such as a PMMA polymer block component and a second polymer block, such as PS polymer block components, as shown in Figure 38, to form a homogenous homogeneous phase The polymer domain 510, which may be the domain A portion, may be phase separated into the polymer matrix portion 520, which may be a portion of the domain B, as shown in Figure 38 by annealing. The annealing process may be performed by thermal annealing, for example, at a temperature of about 200 캜 to 300 캜 for a time of less than about 1 hour to about 100 hours. The first polymer block component and the second polymer block components may be rearranged to order the first polymer block components so that the domains 510 are phase-separated as shown in FIG.

Each of the polymer domains 510 may be formed in a shape surrounded by the polymer matrix portion 520 in a cylindrical shape. A portion of the polymer matrix portion 520 may be located between the polymer domain 510 and the domain portion 510 to isolate the individual polymer domains 510. The polymer domains 510 may be phase separated from the polymer matrix portion 520 such that a plurality of the polymer domains 510 are aligned in the direction of the length of the trenches 410 (L in FIG. 5). The position of the phase separated polymer domain 510 can be adjusted depending on the length L of the trench 410 and the volume ratio of the first polymer block, e.g., PMMA polymer block component. The number of polymer domains 510 that may be formed in the trenches 410 may be adjusted depending on the length L of the trenches 410 and the volume ratio of the first polymer block, e.g., PMMA polymer block component. A plurality of polymer domains 510 may be formed in the trenches 410 depending on the length L of the trenches 410. [

6 and 3, the polymer domains 510 are selectively removed from the polymer matrix portion 520. [ The polymer domains 510 are removed and cavities 510V for the via holes can be formed at positions where the polymer domains 510 are located. The polymer domains 510 may be etched using a solvent capable of dissolving the PMMA block polymer component constituting the polymer domain 510, for example, leaving the polymer matrix portion 520 containing the PS block polymer component. By selectively removing the polymer domain 510, a cylinder-shaped concave cavity (510 V) can be induced. Cylindrical cavities 510V may be formed in the polymer matrix portion 520 in the trenches 410 in a plurality of self-aligned shapes.

FIG. 7 is a layout showing a planar layout shape of a via blocking pattern 750. FIGS. 8 and 9 illustrate the process of forming the via interconnection pattern 750 and show cross-sectional shapes along the cut line A1-A1 'of FIG.

Referring to FIG. 8 together with FIG. 7, a blocking layer 751 covering the polymer matrix portion 520 formed with the cavities 510V is formed. The barrier layer 751 may be formed to fill the cavities 510V formed in the concave shape in the polymer matrix portion 520. The barrier layer 751 may be formed of a layer of a material having an etch selectivity with the polymer matrix portion 520. The barrier layer 751 may be formed of a layer of material that may have an etch selectivity with the line pattern template 400. The barrier layer 751 may be formed of a layer of material that may have an etch selectivity with the via patterned template layer 300. The barrier layer 751 may be selected from layers of various dielectric materials, but may be formed of a spin on carbon (SOC) layer or a photoresist layer.

Referring to FIG. 9 together with FIG. 7, a barrier layer 751 is patterned to form a via isolation pattern 750. The via cutoff pattern 750 may be patterned to expose the first cavities 510V-1 located overlying the portion where the actual conductive via will be located. The first cavities 510V-1 may be extended or pattern-transferred as a via hole to the lower via pattern template layer 300 in a subsequent process. The via cutoff pattern 750 may be patterned to fill and block the second cavities 510V-2 located overlying the portion where the conductive vias would not be located. The second cavities 510V-2 may be blocked so as not to extend as via holes in the lower via pattern template layer 300 in the subsequent process.

The polymer domains (510 in FIG. 5) leading to the cavities (510V) can be phase separated within the polymer matrix portion (520 in FIG. 5) to lie side by side. Accordingly, some of the cavities 510V are not useful for forming the conductive vias, and must not be pattern-transferred to the via pattern template layer 300. [ The via blocking pattern 750 may be introduced to block the second cavities 510V-2 that are not useful for forming the conductive vias that are part of the cavities 510V.

10 is a layout showing a planar arrangement shape of a via hole 310. FIG. FIGS. 11 and 12 illustrate a process of forming the via hole 310, and show cross-sectional shapes along the cutting line A1-A1 'of FIG.

11, the first cavity 510V-1 is extended and extended to the via pattern template layer 300 to form a via hole 310 in the via pattern template layer 300. Referring to FIG. The via hole 310 may be formed in an extended shape so as to be aligned with the first cavity 510V-1. The line pattern template 400, the polymer matrix portion 520 and the via cut-off pattern 750 are used as an etch mask assembly to form the line pattern template 400, the polymer matrix portion 520, The bottom portion of the first cavity 510V-1 exposed to the combination of the first cavity 510 and the second cavity 500 is selectively etched and removed. By selectively removing the bottom portion of the first cavity 510V-1, the portion of the via pattern template layer 300 exposed to the bottom portion of the first cavity 510V-1 is gradually removed. Accordingly, a via hole 310 aligned with the first cavity 510V-1 can be formed in a concave shape penetrating the via pattern layer 300. [ Since the via hole 310 is formed extending from the first cavity 510V-1, the via hole 310 can be self-aligned to the trench 410. [ The first cavities 510V-1 and the via holes 310 derived from the polymer domain 510 are self-aligned to the trenches 410 because the polymer domains 510 are formed by self- . Accordingly, the via hole 310 may have a line width size smaller than the line width of the trench 410.

The via hole 310 may be formed to completely penetrate the via patterning layer 300 to expose the underlying lower conductive line 210. Nevertheless, the portion of the via pattern 310 located at the bottom of the via pattern layer 300 remains in the passivation portion 310B covering the surface of the lower conductive line 210, The etching process to be performed can be stopped in the middle. The via hole 310 may be formed to partially penetrate the via patterning layer 300 without completely penetrating it. The portion of the via pattern template layer 300 remaining in the bottom portion of the via hole 310 to a certain thickness remains in the passivation portion 310B so that the passivation portion 310B contacts the portion of the lower conductive line 210 So that it is not exposed to the outside.

The lower conductive line 210 may be formed to include a copper layer for improving the operation speed of the semiconductor device or the logic device. When the portion of the lower conductive line 210 aligned with the via hole 310 is exposed at the bottom of the via hole 310, the copper layer constituting the lower conductive line 210 may be exposed to the external environment. If the copper layer is exposed to external defects, copper contamination of the process equipment may result. Or that the copper layer surface exposed to the external environment is oxidized to undesirably increase the electrical resistance between the lower conductive line 210 and the conductive vias to be connected thereto. The via hole 310 is etched so that the bottom portion of the via hole 310 remains in the passivation portion 310B covering the lower conductive line 210 in order to prevent the copper layer of the lower conductive line 210 from being damaged. Can be performed.

Since the second cavities 510V-2 are shielded by the via-intercepting pattern 750, the lower cavity pattern layer (the lower cavity pattern layer) may be formed in the etching process of forming the via hole 310 by extending the first cavity 510V- 300). ≪ / RTI > Accordingly, although the polymer matrix portion 520 is formed to have the second cavities 510V-2, only the first cavities 510V-1 at a desired position can be selected by introducing the via- 310, respectively. The via holes 310 may be formed with holes aligned with the lower conductive lines 210, respectively.

Referring to FIG. 12 together with FIG. 10, after the via hole 310 is formed, the via blocking pattern 750 may be selectively removed. In addition, the polymer matrix portion 520 can be selectively removed. The template structure in which the via hole 310 is formed in the bottom portion of the trench 410 of the line pattern template 400 is formed for the damascene process by selectively removing the polymer matrix portion 520 and the via interception pattern 750 .

Figure 13 is a layout showing the top conductive layer 600 including the conductive vias 630 and the top conductive lines 650. [ FIGS. 14 and 15 illustrate a process of forming the conductive via 630 and the upper conductive line 650, and show cross-sectional shapes along the cutting line A1-A1 'of FIG.

Referring to FIG. 14 together with FIG. 13, the passivation portion (310B in FIG. 12) remaining in the bottom portion of the via hole 310 is etched and removed to form the bottom conductive line 210 in the bottom portion of the via hole 310 Expose the surface portion. At this time, the surface of the via pattern template layer 300 exposed by the line pattern template 400 may be removed together with some thickness during the process of removing the passivation part 310B.

15, the via hole 310 exposed at the surface portion of the lower conductive line 210 may be filled in the bottom portion and the upper conductive layer 600 filling the trench 410 may be formed. The process of forming the upper conductive layer 600 may include a process of etching and removing the passivation portion 310B remaining in the bottom portion of the via hole 310 and an insitu process . ≪ / RTI > The process of forming the upper conductive layer 600 may be performed by plating a copper layer. The etching process for removing the passivation portion 310B may be performed in situ just before performing the deposition process for forming the plating seed layer (not shown) required in the process of plating the copper layer. The bottom portion of the trench 410 may be recessed to some thickness in the etching process to remove the passivation portion 310B. The surface of the via pattern template layer 300 exposed at the bottom of the trench 410 may be partially recessed and removed. The copper layer can be formed to fill the trenches 410 and the via holes 310 and the copper layer can be planarized and confined within the trenches 410 to form the upper conductive layer 600. [ The process of planarizing the copper layer can be performed by chemical mechanical polishing (CMP).

The top conductive layer 600 patterned in a pattern filling the trench 410 may include a portion of the top conductive line 650 located in the trench 410 and a portion of the conductive via 630 filling the via hole 310 . The via pattern 310 formed in the via pattern 310 induces the conductive via 630 to be formed along the via hole 310 and the line pattern template 400 is formed along the shape of the trench 410, (650) may be patterned.

Since the via hole 310 for the conductive via 630 is induced by the polymer domain due to the phase separation of the block copolymer, it can be formed to have a very small linewidth size at the nanoscale level. Each of the conductive vias 630 is connected to a first lower conductive line 218 and a second lower conductive line 217 and a wiring structure may be formed in which the upper conductive lines 650 interconnect the conductive vias 630 have.

16 to 21 show a method of forming a metal wiring structure according to an example of the present application. In this embodiment, the trenches 410 of the line pattern template 400 may be formed by applying a double patterning technique.

16 is a target layout 410T showing a planar arrangement shape of the trench 410 of the line pattern template 400. As shown in FIG. 17 and 18 are sub-layouts 410T-1 and 410T-2 obtained by dividing the target layout 410T of FIG. 16 for double patterning. Figs. 19 and 20 are views showing cross-sectional shapes along cutting lines A1-A1 'and A2-A2' in Figs. 16 to 18. Fig.

Referring to FIG. 16 together with FIG. 19, the trenches 410 of the line pattern template 400 may be arranged in an irregularly mixed manner in portions extending in the X-axis direction and portions extending in the Y-axis direction. If the target layout 410T of such a trench 410 is implemented in one photomask and trenches 410 are to be formed in the line pattern template 400 (Fig. 19) in a single photolithography process, Can be difficult. In order to overcome this, the trenches 410 can be formed into more precise and precise patterns by using a double patterning technique.

The target layout 410T of the trenches 410 designed and arranged as shown in Fig. 16 is divided into a first sub-layout 410T-1 of the first trenches 410-1 of Fig. 17 and a second sub- 410-2 of the first sub-layout 410-2. The first trenches 410-1 redesigned in the first sub-layout 410T-1 may have a larger pitch than the trenches 410 disposed in the target layout 410T and may exhibit the arranged geometry . The second trenches 410-2 redesigned in the second sub-layout 410T-2 may show a shape that is arranged with a larger pitch than the trenches 410 disposed in the target layout 410T . Thus, by implementing the first sub-layout 410T-1 and the second sub-layout 410T-2 respectively with photomasks and performing two photolithography processes, the entire trenches 410 are formed in a more elaborate pattern can do.

Referring to Fig. 19, a first mask pattern 710 having a pattern shape of a first sub-layout (410T-1 in Fig. 17) is formed on a layer for a line pattern template 400. Fig. A first trench 410-1 is formed in the line pattern template layer 400L by performing selective etching using the first mask pattern 710 as an etch mask.

20, a second mask pattern 730 having a pattern shape of the second sub-layout (410T-2 in FIG. 18) is formed on the line pattern template layer 400L on which the first trenches 410-1 are formed . A second trench 410-2 is formed in the line pattern template layer 400L by performing selective etching using the second mask pattern 730 as an etching mask. In this manner, the line pattern template 400 having the first and second trenches 410-1 and 410-2 can be patterned using double patterning. The second trenches 410-2B of some of the second trenches 410-2 have a first trench 410-1A arranged to extend in parallel with the first trench 410-1A and another first trench 410-1B As shown in FIG. As depicted in FIG. 16, the second trench (410-2B of FIG. 16) may have a line shape extending in the Y-axis direction in parallel with the first trench 410-1A. The second trench (410-2B of FIG. 16) may have a line shape extending in the X-axis direction so as to connect the first trench 140-1C extending in the Y-axis direction and the other first trench 140-1D have.

21, a block copolymer layer 500 filling the trenches 410 including the first and second trenches 410-1 and 410-2 of the line pattern template 400 can be formed . The process of forming the block copolymer layer 500 can be performed by the process described with reference to FIG. Thereafter, the conductive vias (630 in FIG. 15) and the upper conductive line 650 can be patterned by applying the process described with reference to FIGS. 5 to 15.

22 to 36 are views showing a method of forming a metal wiring structure according to an example of the present application.

22 is a layout showing the planar arrangement shape of the polymer first matrix portion 2512. [ FIGS. 23 to 26 illustrate the process of forming the polymer first matrix portion 2512 and show cross-sectional shapes along the cutting lines A1-A1 'and A2-A2' in FIG.

Referring to FIG. 23 together with FIG. 22, first trenches 2410-1 are formed in the line pattern template layer 2400L. The layout of the first trenches 2410-1 is the same as the layout of the first sub-layouts (Fig. 16) separated from the target layout of the trenches 410 (Fig. 16D) 17, 410T-1). The first trenches 2410-1 may be preferentially formed by first patterning using a double patterning technique. The first trench 2410-1 may be formed in the line pattern template layer 2400L by performing selective etching using the first mask pattern 2710 as an etching mask. The planar shape of the first mask pattern 2710 may follow the first sub-layout (410T-1 in FIG. 17) separated from the target layout (410T in FIG. 16) of the trenches (410 in FIG. 16).

The first mask pattern 2710 may be formed including a photoresist material. The first mask pattern 2710 may be selected from a dielectric material having an etch selectivity with the line pattern template layer 2400L, such as silicon oxynitride (SiON) or silicon oxide.

The first dielectric layer 2120 may be provided on the semiconductor substrate 2100 and the lower conductive lines 2210 may be provided on the first dielectric layer 2120. [ Electronic elements such as a transistor structure including a gate 2115 and a junction 2113 may be provided on the semiconductor substrate 2100. [ The lower conductive lines 2210 may be electrically connected to the junction 2113 by a connection pattern or a conductive contact such as the conductive plug 2125. [ A second dielectric layer 2200 may be formed on the first dielectric layer 2120 to isolate and isolate between the lower conductive lines 2210. [

A via patterning layer 2300 covering the lower conductive lines 2210 may be formed on the second dielectric layer 2200. [ A line pattern template layer 2400L may be formed on the via pattern template layer 2300 to provide a pattern shape of the upper conductive line.

Referring to FIG. 24, a first block copolymer layer 2510 filling the first trench 2410-1 is coated in the first trench 2410-1 of the line pattern template layer 2400L. The first block copolymer layer 2510 may be formed by coating a polystyrene-polymethylmethacrylate (PS-PMMA) block copolymer. The process of coating the block copolymer can be performed by the process described with reference to FIG.

25, the first block copolymer layer 2510 is first annealed to phase-separate the polymer first domain 2511 and the polymer first matrix portion 2512. The phase separation process can be performed by the process described with reference to FIG.

Referring to FIG. 26, the polymer first domains 2511 are selectively removed from the polymer first matrix portion 2512. The polymer first domains 2511 are removed and first cavities 2511V for via holes may be formed at positions where the polymer first domains 2511 are located.

27 is a layout showing a planar arrangement shape of the polymer second matrix portion 2522. Fig. FIGS. 28 to 33 illustrate the process of forming the polymer second matrix portion 2522 and show cross-sectional shapes along the cutting lines A1-A1 'and A2-A2' of FIGS. 22 and 27. FIG.

28, the first trenches 2410-1 are covered with the line pattern template layer 2400L, and the second trenches 2410-2 covering the second trenches 2410-2 A mask pattern 2730 is formed. The second mask pattern 2730 may be formed to cover and cover the first cavities 2511V and the polymer first matrix portion 2512 formed in the first trench 2410-1. The planar shape of the second mask pattern 2730 may follow the second sub-layout (410T-2 in FIG. 18) separated from the target layout (410T in FIG. 16) of the trenches (410 in FIG. 16). The second mask pattern 2730 may be formed including a photoresist material. The second mask pattern 2730 may include a polymeric first matrix portion 2512 and a dielectric material having an etch selectivity. The second mask pattern 2730 may be selected from a dielectric material having an etch selectivity with the line pattern template layer 2400L, such as silicon oxynitride (SiON) or silicon oxide.

Referring to FIG. 29, a second trench 2410-2 may be formed in the line pattern template 2400 by performing selective etching using the second mask pattern 2730 as an etch mask. The etching process using the second mask pattern 2730 may be a second patterning process of double patterning. The arrangement shape of the second trenches 2410-2 to be formed can follow the second sub-layout (410T-2 in Fig. 18) separated from the target layout (410T in Fig. 16) of the trenches .

30, a second block copolymer layer 2410-2 filling the second trench 2410-2 is formed in the second trench 2410-2 of the line pattern template 2400 exposed by the second mask pattern 2730, (2520). The second block copolymer layer 2520 may be formed by coating a polystyrene-polymethylmethacrylate (PS-PMMA) block copolymer. The process of coating the block copolymer can be performed by the process described with reference to FIG.

Referring to FIG. 31, the second block copolymer layer 2520 is second annealed to phase-separate the polymer second domain 2521 and the polymer second matrix portion 2522. The phase separation process can be performed by the process described with reference to FIG.

Referring to FIG. 32, the polymer second domains 2521 are selectively removed from the polymer second matrix portion 2522. The polymer second domains 2521 are removed, and the second cavities 2521V for via holes are formed at positions where the polymer second domains 2521 are located.

Referring to FIG. 33, the second mask pattern 2730 may be selectively removed to expose the polymer first matrix portion 2512 and the first cavities 2511V. In the process of removing the second mask pattern 2730, the upper part of the polymer first matrix portion 2512 may be removed together to lower the height.

34 is a layout showing a planar arrangement shape of the via interception pattern 2750. Fig. 35 is a view showing a process of forming a via hole 2310 and showing a cross-sectional shape along the cutting lines A1-A1 'and A2-A2' in FIG.

35, the third cavities 2511V-1 overlapping the portion of the first cavities 2511V where the actual conductive vias are to be positioned, and the third cavities 2511V- A via cut-off pattern 2750 is formed to expose the fourth cavities 2521 V-1 overlapping the portion where the conductive vias will be located. The process of forming the via intercept pattern 2750 can be performed by the process described with reference to FIGS. 8 and 9. The third cavities 2511V-1 and the fourth cavities 2521V-1 may extend to the via hole 2310 in the lower via pattern template layer 2300 in a subsequent process. The via cutoff pattern 2750 is formed by the fifth cavities 2511V-2 in which the conductive vias are not located among the first cavities 2511V and the fifth cavities 2511V-2 in which the conductive vias among the second cavities 2521V are located May be patterned to fill and block the sixth cavities 2521 V-2 which are overlapped with portions not to be formed. The fifth cavities 2511V-2 and the sixth cavities 2521V-2 may be blocked so as not to extend as via holes in the lower via pattern template layer 2300 in a subsequent process.

The third cavities 2511V-1 and fourth cavities 2521V-1 are extended and extended to the via pattern template layer 2300 to form via holes 2310 in the via pattern template layer 2300. [ Using the line pattern template 2400, the polymer first and second matrix portions 2512 and 2522 and the via cut-off pattern 2750 as an etch mask assembly, the third cavity 2511V- 4 cavities 2521V-1 are selectively etched and removed. The process of forming the via holes 2310 can be performed by the process described with reference to FIG. The via holes 2310 allow the bottom portion to remain in the passivation portion 2310B without completely penetrating the via pattern template layer 2300 so that the passivation portion 2310B covers the portion of the lower conductive line 2210, As shown in FIG.

36 shows the process of forming the conductive vias 2630 and the upper conductive line 2650.

Referring to FIG. 36, after selectively removing the line pattern template 2400, the polymer first and second matrix portions 2512 and 2522, and the via cutoff pattern 2750, the upper conductive layer 2600 filling the via holes 2310 ) Can be formed. The passivation portion (2310B in Fig. 35) remaining in the bottom portion of the via hole 2310 is etched and removed to expose the surface portion of the lower conductive line 2210 to the bottom portion of the via hole 3210. It is possible to fill the via hole 2310 exposed at the surface portion of the lower conductive line 2210 in the bottom portion and to form the upper conductive layer 2600 filling the first and second trenches 2410-1 and 2410-2 have. The process of forming the upper conductive layer 2600 can be performed by the process described with reference to FIGS. The via pattern 2300 formed with the via hole 2310 induces the conductive vias 2630 to be formed along the shape of the via hole 2310 and the line pattern template 2400 forms the first and second trenches 2410- 1, 2410-2), the upper conductive line 2650 may be patterned.

According to the present application, a nanoscale structure or nanostructure can be formed on a large-area substrate. The nanostructure can be used for the production of a polarizing plate including a line grating and the formation of a reflection lens of a reflection type liquid crystal display device. The nanostructure can be used not only for the production of independent polarizing plates but also for the formation of polarizing portions integral with the display panel. For example, it can be used for an array substrate including a thin film transistor or a process for forming a polarizing portion directly on a color filter substrate. The nanostructures can be used in various applications including nanowire transistors, templates for memory fabrication, molds for electrical and electronic components such as nanostructures for nanoscale patterning of leads, templates for catalysts for solar cells and fuel cells, etch masks and organic diodes ) Can be used for molds for making molds and gas sensors for cell fabrication.

The methods and structures according to the present application described above can be used in the manufacture of integrated circuit chips. The resulting integrated circuit chip may be distributed by the manufacturer in a raw wafer form, a bare die, or a package form. The chip may be provided in the form of a single chip package or a multi-chip package chip package. In addition, one chip may be integrated into another integrated circuit chip or integrated into a discrete circuit element. One chip may be integrated to form another signal processing device as a part in the form of an intermediate product such as a mother board or an end product. The final product may be any product including an integrated circuit chip and may be a high performance computer product from a toy or low performance application and may be a display or keyboard or other input device, And a central processor.

Although the embodiments of the present application as described above illustrate and describe the drawings, it is intended to illustrate what is being suggested in the present application and is not intended to limit what is presented in the present application in a detailed form. Various other modifications will be possible as long as the technical ideas presented in this application are reflected.

300: Via pattern template layer,
400: line pattern template layer,
500: block copolymer layer,
750: Via blocking pattern.

Claims (28)

Forming a via pattern template layer on the substrate;
Forming a line pattern template that provides a trench on the via patterned template layer;
Applying a block copolymer layer filling the trench;
Annealing the block copolymer layer to induce a polymeric matrix and polymer domains;
Selectively removing the polymer domains to form cavities;
Forming a via blocking pattern to block a portion of the cavities; And
And forming via holes by extending other portions of the cavities exposed by the via cutoff pattern into the via patterned template layer. The method according to claim 1,
Between the substrate and the via pattern template layer
Further comprising forming lower conductive lines,
And each of the via holes is aligned with each of the lower conductive lines. 3. The method of claim 2,
The trench
Wherein the lower conductive lines are disposed to overlap at least two of the lower conductive lines. 3. The method of claim 2,
The via-
By partially penetrating the via pattern template layer,
And a portion of the via pattern template layer overlapping the lower conductive lines is formed to remain in a passivation portion for protecting the lower conductive lines by remaining a part of the thickness. 5. The method of claim 4,
Forming a via hole and a conductive layer filling the trench; And
Before forming the conductive layer
And selectively removing the passivation portion. 5. The method of claim 4,
The step of forming the conductive layer
Removing the passivation portion and performing a vacuum break. The method according to claim 1,
The step of forming the via holes
The via pattern template layer is exposed using the line pattern template, the polymeric matrix and the via blocking pattern as an etch mask. And removing portions overlapping the cavities. The method according to claim 1,
The block copolymer layer
A method of forming a wiring structure comprising a first polymer block component and a second polymer block component that can be chemically immiscible and phase-separated. 9. The method of claim 8,
The polymer domain
Said first polymer block component,
The polymer matrix portion
And the second polymer block component. The method according to claim 1,
The polymer domains
Wherein the polymer matrix portion is phase-separated so as to be arranged in a row in the longitudinal direction of the trench. The method according to claim 1,
The via-
And filling a part of the cavities. Sequentially forming a via pattern template layer and a line pattern template layer on a substrate;
Forming first trenches in the line pattern template layer;
Forming second trenches in the line pattern template layer;
Applying a block copolymer layer filling the first and second trenches;
Annealing the block copolymer layer to induce a polymeric matrix and polymer domains;
Selectively removing the polymer domains to form cavities;
Forming a via blocking pattern to block a portion of the cavities; And
And forming via holes by extending other portions of the cavities exposed by the via cutoff pattern into the via patterned template layer. 13. The method of claim 12,
The step of forming the first trenches
Forming a first mask pattern on the line pattern template layer; And
And performing an etching process using the first mask pattern as an etching mask,
The forming of the second trenches
Forming a second mask pattern on the line pattern template layer; And
And performing an etching process using the second mask pattern as an etching mask. 13. The method of claim 12,
One of the second trenches
The second trenches are formed so as to be located between the first trenches. 13. The method of claim 12,
One of the second trenches
Wherein the first trenches are formed to interconnect the two first trenches spaced apart from each other. 13. The method of claim 12,
One of the second trenches
The first trench extends in a direction perpendicular to a direction in which the first trench extends. Sequentially forming a via pattern template layer and a line pattern template layer on a substrate;
Forming first trenches in the line pattern template layer;
Applying a first block copolymer layer filling the first trenches;
Annealing the first block copolymer layer to induce a polymeric first matrix polymer domain and polymeric first domains;
Selectively removing the polymer first domains to form first cavities;
Forming second trenches in the line pattern template layer;
Applying a second block copolymer layer filling the second trenches;
Annealing the second block copolymer layer to induce a polymeric second matrix polymer domain and polymer domain second polymer domains;
Selectively removing the polymer second domains to form second cavities;
Forming a via blocking pattern to block a portion of the first and second cavities; And
And forming via holes by extending other portions of the first and second cavities exposed by the via cut-off pattern into the via pattern template layer. 18. The method of claim 17,
The step of forming the first trenches
Forming a first mask pattern on the line pattern template layer; And
And performing an etching process using the first mask pattern as an etching mask. 19. The method of claim 18,
The forming of the second trenches
Forming a second mask pattern that fills the first cavities on the line pattern template layer and exposes a portion of the line pattern template layer; And
And performing an etching process using the second mask pattern as an etching mask. 20. The method of claim 19,
The second mask pattern
And extends to cover and block the polymer first matrix portion. 18. The method of claim 17,
One of the second trenches
The second trenches are formed so as to be located between the first trenches. 18. The method of claim 17,
One of the second trenches
Wherein the first trenches are formed to interconnect the two first trenches spaced apart from each other. 18. The method of claim 17,
One of the second trenches
The first trench extends in a direction perpendicular to a direction in which the first trench extends. 18. The method of claim 17,
Between the substrate and the via pattern template layer
Further comprising forming lower conductive lines,
And each of the via holes is aligned with each of the lower conductive lines. 25. The method of claim 24,
The trench
Wherein the lower conductive lines are disposed to overlap at least two of the lower conductive lines. 25. The method of claim 24,
The via-
By partially penetrating the via pattern template layer,
And a portion of the via pattern template layer overlapping the lower conductive lines is formed to remain in a passivation portion for protecting the lower conductive lines by remaining a part of the thickness. 27. The method of claim 26,
Forming a via hole and a conductive layer filling the trench; And
Before forming the conductive layer
And selectively removing the passivation portion. 18. The method of claim 17,
The step of forming the via holes
The via patterning layer (or the via patterning layer) may be formed using a line pattern template layer, polymer first and second polymeric matrices, and a via blocking pattern as an etch mask. and removing a portion overlapping the exposed first and second cavities of the via pattern template layer.

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