US20160247735A1 - Semiconductor package with elastic coupler and related methods - Google Patents
Semiconductor package with elastic coupler and related methods Download PDFInfo
- Publication number
- US20160247735A1 US20160247735A1 US14/626,758 US201514626758A US2016247735A1 US 20160247735 A1 US20160247735 A1 US 20160247735A1 US 201514626758 A US201514626758 A US 201514626758A US 2016247735 A1 US2016247735 A1 US 2016247735A1
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- US
- United States
- Prior art keywords
- pin
- housing
- substrate
- spring
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims description 33
- 239000000758 substrate Substances 0.000 claims abstract description 102
- 230000008878 coupling Effects 0.000 claims description 13
- 238000010168 coupling process Methods 0.000 claims description 13
- 238000005859 coupling reaction Methods 0.000 claims description 13
- 230000006835 compression Effects 0.000 claims description 9
- 238000007906 compression Methods 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 17
- 239000010949 copper Substances 0.000 description 17
- 229910052802 copper Inorganic materials 0.000 description 15
- 229910000679 solder Inorganic materials 0.000 description 13
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 230000007246 mechanism Effects 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 229910000881 Cu alloy Inorganic materials 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000007788 roughening Methods 0.000 description 4
- 238000009434 installation Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000851 Alloy steel Inorganic materials 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 229910000952 Be alloy Inorganic materials 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910000599 Cr alloy Inorganic materials 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 229910000639 Spring steel Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- QRJOYPHTNNOAOJ-UHFFFAOYSA-N copper gold Chemical compound [Cu].[Au] QRJOYPHTNNOAOJ-UHFFFAOYSA-N 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000010309 melting process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H01L23/041—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction having no base used as a mounting for the semiconductor body
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- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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- H01R4/00—Electrically-conductive connections between two or more conductive members in direct contact, i.e. touching one another; Means for effecting or maintaining such contact; Electrically-conductive connections having two or more spaced connecting locations for conductors and using contact members penetrating insulation
- H01R4/28—Clamped connections, spring connections
- H01R4/48—Clamped connections, spring connections utilising a spring, clip, or other resilient member
- H01R4/4854—Clamped connections, spring connections utilising a spring, clip, or other resilient member using a wire spring
- H01R4/4863—Coil spring
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- H01R4/00—Electrically-conductive connections between two or more conductive members in direct contact, i.e. touching one another; Means for effecting or maintaining such contact; Electrically-conductive connections having two or more spaced connecting locations for conductors and using contact members penetrating insulation
- H01R4/28—Clamped connections, spring connections
- H01R4/48—Clamped connections, spring connections utilising a spring, clip, or other resilient member
- H01R4/489—Clamped connections, spring connections utilising a spring, clip, or other resilient member spring force increased by screw, cam, wedge, or other fastening means
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Definitions
- aspects of this document relate generally to semiconductor device packages. Particular aspects of this document relate to power semiconductor device packages, such as power integrated modules (PIMs).
- PIMs power integrated modules
- Semiconductor devices are often encased within (or partly within) a package prior to use. Some packages contain a single die while others contain multiple die. The package offers protection to the die, such as from corrosion, impact and other damage, and often also includes electrical leads or other components which connect the electrical contacts of the die with a motherboard. The package may also include components configured to dissipate heat from the die into a motherboard, a heat sink, or otherwise away from the package. Some conventional semiconductor power packages have included springs exterior to the package for contact with external elements, and some of these may have included double-spring designs.
- Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.
- Implementations of semiconductor packages may include one, all, or any of the following:
- a base of the pin may be coupled to the substrate with a spring.
- the pin may be fixedly coupled in a top of the housing and may be configured to be coupled with the substrate by lowering the housing towards the substrate.
- the pin may include two rigid portions coupled together only with a spring.
- One of the rigid portions may include a flat plate.
- the reversibly elastically deformable lower portion may include a spring.
- the spring may include a coil spring.
- Implementations of semiconductor packages may include: at least one die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the at least one die within a cavity of the housing, and; a plurality of pins fixedly coupled in a top of the housing, each of the plurality of pins electrically coupled with one of the at least one die through a connection trace of the substrate, each of the plurality of pins including a spring, wherein the spring of each pin biases an upper portion of the pin towards the housing.
- Implementations of semiconductor packages may include one, all, or any of the following:
- the spring of each pin may be positioned between two rigid portions of the pin.
- the spring of each pin may bias the two rigid portions of the pin away from one another.
- the spring of each pin may be compressed along a direction substantially parallel with a longest length of the pin.
- the spring of each pin may be configured to prevent a contact surface of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered towards the substrate.
- the spring may include a helical spring.
- Implementations of methods of forming a semiconductor package may include: securing a pin to a housing, the pin including a spring; lowering the housing relative to a substrate having a semiconductor die (die) coupled thereon to at least partially enclose the die within a cavity of the housing, and; while lowering the housing, compressing the spring so that a lower end of the pin does not lower beyond a predetermined point relative to the substrate and so that an upper portion of the pin is biased towards the housing, wherein lowering the housing includes electrically coupling the pin with the die.
- Implementations of methods of forming a semiconductor package may include one, all, or any of the following:
- the housing may be secured to the substrate.
- Securing the housing to the substrate may include maintaining compression of the spring.
- the lower end of the pin may be included in a flat plate of the pin and, prior to lowering the housing, the flat plate may be coupled to the upper portion of the pin through only the spring.
- Compressing the spring may include compressing the spring between two rigid portions of the pin.
- Compressing the spring may include biasing the two rigid portions of the pin away from one another.
- Compressing the spring may include compressing the spring along a direction substantially parallel with a longest length of the pin.
- FIG. 1 is a perspective view of an implementation of a semiconductor package
- FIG. 2 is a perspective view of another implementation of a semiconductor package
- FIG. 3 is a cross-section view of the semiconductor package of FIG. 4 in an open configuration
- FIG. 4 is a cross-section view of the semiconductor package of FIG. 1 taken along line A-A;
- FIG. 5 is a cross-section view of the semiconductor package of FIG. 6 in an open configuration
- FIG. 6 is a cross-section view of the semiconductor package of FIG. 2 taken along line B-B;
- FIG. 7 is a top view of a plurality of substrates, a baseplate, and other elements of a conventional semiconductor package
- FIG. 8 is a top view of a plurality of substrates, a baseplate, and other elements of a semiconductor package.
- FIG. 9 is a perspective view of another implementation of a semiconductor package.
- Top side and bottom side are terms used in the industry to refer to sides of semiconductor die and sometimes relate to the nature of the electrical contacts on the side being referenced.
- a side having one or more electrical contacts not intending to be only used as a ground is sometimes called a “top side.”
- a side having only electrical contacts which are intended to be used as an electrical ground is sometimes called a “bottom side.”
- bottom side refers to the side of a die that is facing towards a bottom of a drawing page
- top side when used herein refers to the side of a die that is facing towards a top of a drawing page.
- a semiconductor package (package) 2 includes one or more die 4 coupled to a substrate 6 .
- a housing 24 has one or more pins 38 fixedly coupled thereto and at least one of the pins is electrically coupled to one of the die 4 .
- the package 2 in implementations is a power semiconductor device such as, by non-limiting example, a power integrated module (PIM), an integrated power module (IPM) or intelligent power module, and the like, and may include one or more power metal-oxide-semiconductor field-effect transistors (power MOSFETs), insulated gate bipolar transistors (IGBTs), and the like.
- PIM power integrated module
- IPM integrated power module
- IGBTs insulated gate bipolar transistors
- the package 2 may be used, for example, for power applications in the auto industry, in industrial machines, in power generation, in household appliances, and so forth.
- the package examples shown in the drawings are power semiconductor devices, in other applications similar pins and other packaging elements and methods disclosed herein may be used for packages which are not power semiconductor packages.
- the package 2 may include, by non-limiting example, one or more insulated gate bipolar transistor (IGBT) die electrically coupled, such as through a wirebond, clip or the like, with one or more diode rectifier die.
- IGBT insulated gate bipolar transistor
- Substrate 6 in implementations is a power electronic substrate and may include, by non-limiting example, a direct bonded copper (DBC) substrate, an active metal brazed (AMB) substrate, an insulated metal substrate (IMS), a ceramic substrate, and the like. Other types of substrates could be used.
- DBC substrate may have a copper layer only on one side of the DBC substrate (a side that includes connection traces) or, in other implementations, it may include a first copper layer on a first side of a ceramic layer and a second copper layer on a second side of the ceramic layer so that the ceramic layer is sandwiched between two copper layers.
- Substrate 6 is a direct bonded copper (DBC) substrate 8 having a ceramic layer 10 sandwiched between a first copper layer 12 and second copper layer 18 , and the first copper layer 12 includes connection traces 14 .
- DBC direct bonded copper
- Other metallic and/or non-metallic layers may be included on the first and/or second copper layers 12 , 18 in various implementations.
- one or more DBC substrates each having two copper layers, and each having connection traces in each copper layer, could be used.
- the wirebonds 22 could be excluded and instead a second DBC substrate having connection traces on both sides (each in a copper layer) could be coupled to the die 4 , the connection traces in a bottom side of the second DBC electrically coupling to the electrical contacts on a top side of the die 4 (“top side” meaning facing a top of the page in the drawings).
- a second layer of die 4 may then be placed atop the connection traces on the upper side of the second DBC substrate, and then further connections may be made with electrical contacts on a top side of the second layer of die 4 , such as using electrical couplers 20 , which may be wirebonds 22 , conductive clips, or the like, and then further packaging may be done to achieve a structure similar to structures shown in the drawings but having a stacked configuration with multiple layers of die 4 .
- Other stacking mechanisms and methods may be used, and those given here are just representative examples.
- one or more or all of the die 4 could be coupled with the connection traces 14 using a flip-chip process using die bumps so that no wirebonds or conductive clips are needed.
- connection traces 14 route and electrically couple electrical contacts on the die 4 with other elements, such as the pins, other die 4 , power sources, electrical grounds, other devices within or without the package 2 , and the like.
- the connection traces to which the bottom side of each die 4 is coupled (“bottom side” referring to the sides of the die 4 facing a bottom of the page in the drawings) may connect conductive pads on the bottom sides of those die with electrical ground, while the electrical couplers 20 (such as wirebonds 22 or conductive clips) which are electrically coupled to pins 38 through other connection traces 14 may couple electrical contacts on the top sides of the die 4 with power sources.
- the electrical couplers 20 such as wirebonds 22 or conductive clips
- connection traces 14 may be used to couple one or more electrical contacts on the bottom side of the die 4 with electrical ground and one or more other connection traces 14 may be used to couple one or more other electrical contacts on the bottom side of the die 4 with one or more power sources through the pins, one or more other die 4 , one or more other electrical devices within or without the package 2 , and so forth.
- the housing 24 in implementations is formed of a polymer, such as a thermoset, thermosoftening (thermopolymer), or other type of polymer or plastic—though in implementations it could also be formed of a composite material.
- Elastic couplers 36 are formed of an electrically conductive material, such as a metal, and are used to electrically and/or mechanically couple one or more electrical contacts of the die 4 with items outside the package 2 , such as with a motherboard or printed circuit board (PCB), a power source, an electrical ground, other devices external to the package 2 , and so forth.
- the motherboard/PCB may include pin receivers, such as an array of cylindrical cavities, each pin receiver designed to receive one pin 38 and thereby electrically and mechanically couple thereto.
- the motherboard/PCB may further route the pins to other electric devices, power sources, electrical ground, other die 4 , and so forth.
- one or more packages 2 may be coupled to a single motherboard/PCB and the multiple packages 2 may or may not be electrically interconnected through the motherboard/PCB.
- the elastic couplers 36 are fixedly attached to the housing 24 . This may be accomplished in a variety of ways. In the implementations illustrated in the drawings, the elastic couplers 36 have been integrated into a top 26 of the housing 24 by placing the elastic couplers 36 and housing 24 in the configuration shown while the housing 24 is in a liquid state and then allowing or causing the housing 24 to solidify. For example this may be done through a melting process, or a resin may be used which may be cured to form a solid phase, and so forth. In other implementations the same structure shown in FIGS. 3-4 may be accomplished by forming the housing 24 with portions configured to receive the pins 38 and then gluing, welding, or otherwise adhering the pins 38 to the portions of the housing 24 configured to receive them.
- the housing 24 may have female threads and the pins 38 may have male threads and the two may be joined by coupling the threads together.
- Other coupling mechanisms may be used.
- the pins 38 at a point in the fabrication of the package 2 prior to coupling the pins with the connection traces 14 , are fixedly coupled to the housing 24 and, therefore, generally not free to move relative to the housing 24 while the housing 24 is being lowered towards the substrate 6 to couple thereto.
- the housing 24 includes a cavity 28 configured to receive the die 4 and other elements therein.
- the cavity at least partially encloses the die within the cavity.
- the housing includes a ledge 30 which rests atop the substrate 6 , and which may be adhered thereto such as using an adhesive, though the ledge 30 may also just rest atop the substrate 6 without any adhesive and the substrate 6 may have one or more other coupling mechanisms such as screw holes so that the housing 24 may be coupled thereto by inserting screws into the openings 32 of housing 24 and screwing screws into screw holes of the substrate 6 .
- Other coupling mechanisms such as clips, a friction fit, and the like are possible.
- an area proximate the ledge 30 and or including the ledge 30 may be roughened prior to coupling the housing and substrate together, such as with the use of an abrasive, in order to ensure a better bond when an adhesive is applied therebetween.
- a similar roughening operation may be done in order to form a better or stronger fit therebetween, or in other words a fit having greater friction.
- this roughening may be done with physical abrasion such as through sanding or blasting with a fluid having a grit element therein.
- the roughening may be done through chemical means such as through an etching process or the like, though other mechanisms may also be used for roughening these surfaces.
- coupling structures may be included in the location of the housing 24 proximate the ledge 30 or including the ledge 30 to aid in establishing a friction fit, including, by non-limiting example projections, flanges, pin-like structures, bumps, and other structures that can couple against the edge of the substrate 6 .
- the elastic couplers 36 are pins 38 configured to electrically couple with the die 4 through the connection traces 14 and to electrically couple with a motherboard, PCB or other element external to package 2 .
- Pin 38 has an upper portion 40 , which includes a rigid portion 42 , and a reversibly elastically deformable lower portion (lower portion) (elastic portion) 44 .
- elastic portion 44 includes a spring 46 and a rigid portion 50 .
- the rigid portion 50 forms a base 54 of the pin 38 and includes a flat plate 56 having a contact surface 58 on its underside configured to electrically couple with a connection trace 14 .
- a lower end 52 of the pin 38 is a rigid portion 50 , so that the elastic portion 44 includes both a spring 46 and a rigid portion 50 .
- the elastic portion 44 in the implementations of FIGS. 3-4 has a portion which is reversibly elastically deformable and another portion which is not. Those portions that are not reversibly elastically deformable may be plastically deformable and/or non-reversibly elastically deformable.
- all of the elastic portion 44 could be reversibly elastically deformable.
- the rigid portion 50 could be omitted entirely, so that the elastic portion 44 only includes spring 46 .
- the lower end 52 of the pin 38 would be the bottom of the spring 46 , not the bottom of the flat plate 56 , since the flat plate 56 would be excluded.
- the spring is a coil spring, such as a helical coil spring 48 .
- the elastic section 44 in implementations is formed entirely in: the bottom half; the bottom third; the bottom fourth; the bottom fifth; the bottom sixth; the bottom seventh; the bottom eighth; the bottom ninth; the bottom tenth; the bottom eleventh; the bottom twelfth; the bottom thirteenth; the bottom fourteenth; the bottom fifteenth; the bottom sixteenth; and so forth, of the pin 38 .
- the pin 38 may have a longest length 60 of, or of about, 14 mm
- the spring 46 may have a length, measured along the same direction of the longest length 60 , of, or of about, 1 mm.
- the spring 46 may be configured to compress from a length of, or of about, 1 mm to a length of, or of about: 0.9 mm; 0.8 mm; 0.7 mm, 0.6 mm, 0.5 mm, 0.4 mm, 0.3 mm; and so forth. Accordingly, spring material and spring constants for the spring 46 may be selected according to the desired compression characteristics. In implementations of springs herein the spring may have a length, parallel with a longest length of the pin, of greater than 1 mm.
- the spring 46 is formed of, by non-limiting example: a high carbon spring steel; a stainless steel, a steel alloy having one or more of chromium, vanadium, nickel, molybdenum, and/or aluminum; a bronze alloy; an alloy of beryllium and copper; an alloy of nickel and copper; an alloy of iron, chromium and nickel; and the like.
- the springs 46 shown in the drawings have a straight cylindrical profile (i.e., the coils are of the same diameter), in other implementations the springs may have a conical profile with decreasing coil diameters (going in either direction) such that the individual coils are not forced against one another, or not as much, in compression, thus allowing greater overall compression of the spring 46 .
- the spring 46 may be coupled to the rigid portions using, by non-limiting example: a solder; a conductive adhesive; a weld; and the like.
- the entirety of each pin, including the rigid portion(s) and the spring could be integrally formed from a single piece of material so that the spring is integrally attached to the rigid portion(s).
- the relaxed, non-compressed length of the spring in a direction parallel with longest length 60 is one of: less than half, less than a third, less than a fourth, less than a fifth, less than a sixth, less than a seventh, less than an eighth, less than a ninth, less than a tenth, less than an eleventh, less than a twelfth, less than a thirteenth, less than a fourteenth, less than a fifteenth, and so forth, the length of longest length 60 .
- the rigid portion 50 when included, is formed of an electrically conductive metal.
- the metal for the rigid portions 42 and 50 may be, by non-limiting example: copper; a copper alloy; a copper-gold alloy; and the like or any of the spring material times disclosed herein.
- the spring could be a type of compression spring other than a coil spring such as, by non-limiting example: a flat spring; a machined spring (which may or may not include the rigid portions of the pin); a volute spring; a Belleville spring; and the like.
- the elastic coupler 36 is configured so that, when the housing 24 is lowered towards the substrate 6 , the lower end 52 of the pin stops at a predetermined point 16 and travels no farther downwards.
- the spring of each pin is configured to prevent a contact surface of the pin from lowering beyond the predetermined point relative to the substrate when the housing is lowered towards the substrate.
- the lower end 52 may be the rigid portion 42 or, in implementations in which rigid portion 42 is excluded, it may be a lower end of the spring 46 . This allows electrical and/or mechanical communication to be formed between each pin and the connection traces by the act of lowering the housing onto the substrate.
- the pins may be coupled with the connection traces without the use of solder, conductive adhesive, a press-fit, and so forth. Additionally, as the coupling of the pins with the connection traces is formed by virtue of the elastic portion 44 , the housing 24 could be raised and the pins would lift off the communication traces without needing to sever the pins or melt solder, or the like, for the removal.
- the pin When the spring is compressed, which occurs as the housing is lowered towards the substrate and the base 54 contacts the substrate, the pin then biases the lower end or base 54 of the pin towards the substrate and, at the same time, biases an upper portion of the pin (in other words, the portion of the pin between the spring and the top of the housing) towards the top of the housing.
- the spring when compressed, also biases the two rigid portions away from one another, and it could also be said that the spring, when compressed, biases the lower rigid portion 50 downwards while biasing the upper rigid portion 42 upwards.
- Each pin, when compressed, is compressed along a direction that is parallel, or substantially parallel, with a longest length 60 of the pin.
- the act of lowering the housing electrically couples the pin with the die by contacting the lower end of the pin with a connection trace of the substrate, the connection trace of the substrate being electrically coupled with an electrical contact of the die.
- the housing may be secured to the substrate, or relative to the substrate, such as with a friction fit, a glue, screws, a clamping mechanism, and the like, and securing the housing to or with the substrate maintains compression of the spring.
- the two rigid portions are directly coupled together only with the spring.
- the pin consists of two rigid portions coupled together with a spring. Compressing the spring in various implementations includes compressing the spring between the two rigid portions of the pin.
- Pins 38 may have various shapes, for instance they may have cylindrical or rounded shapes when viewed perpendicular to the longest length 60 , or they may have rectangular or square shapes when viewed from that direction. In various implementations each pin 38 may have a smallest diameter, taken perpendicular to a longest length 60 of the pin, of, or of about, 0.64 mm. In implementations in which the pin 38 has a rectangular shape where it exits the top 26 , the pin 38 may have a cross section taken perpendicular to the longest length 60 having a rectangular shape with a first side ranging between 1.12 mm and 1.18 mm and a second side ranging between 0.77 mm and 0.83 mm.
- the rectangular shape may have a first side of 1.15 mm and a second side of 1.8 mm.
- the packages shown in FIGS. 1, 2 and 9 may each have a rectangular footprint having a first side of, or of about, 66 mm and another side of, or of about, 32.5 mm.
- the packages may each have a rectangular footprint having a first side ranging between 107 mm to 108 nun and a second side ranging between 44.5 mm and 45.5 mm.
- the packages may each have a rectangular footprint having a first side of 107.5 mm and a second side of 45 mm.
- the packages 2 shown in the figures do not include a baseplate below the substrate 6 .
- a baseplate may be used, and in such implementations the baseplate may couple directly to the substrate 6 such as with an adhesive or using screws, or the like, and/or may be coupled directly to the housing 24 and pressed against substrate 6 thereby, and so forth.
- the baseplate may be metallic and may assist in the extraction of heat away from the die 4 .
- Package 2 may further include one or more couplers 34 to couple the package 2 to a heat spreader, heat pipes, heat sink, and/or to an electrical ground, and the like.
- a semiconductor package (package) 62 includes a housing 64 having a top 66 , the housing forming a cavity 68 configured to receive and/or enclose one or more die 4 therein.
- Package 62 includes a baseplate 78 and a plurality of substrates 6 are coupled to the baseplate.
- Baseplate 78 may be formed of a metallic material and may be used to extract heat or assist in extracting heat away from the die 4 .
- the baseplate could be formed of steel, aluminum or an aluminum alloy, copper or a copper alloy, an alloy containing molybdenum and/or tungsten, and the like.
- the substrates 6 may be coupled to the baseplate 78 such as with a solder, an adhesive, screws, a friction fit, or the like.
- Housing 64 includes openings 70 and baseplate 78 includes corresponding openings 80 for a coupler 72 , such as screw 74 , to couple the housing 64 to the baseplate 78 .
- coupler 72 such as screw 74
- Other coupling mechanisms could be used such as glue, a friction fit, and so forth.
- FIGS. 7-8 show examples of assemblies 76 and 116 .
- Assembly 76 includes the baseplate 78 and substrates 6 , along with die 4 and electrical couplers 20 , of FIGS. 5-6 . Some of the electrical couplers 20 are coupled to pads 82 of the die 4 , the pads 82 being electrical contacts on a face of the die 4 .
- Assembly 116 differs from assembly 76 in that assembly 116 includes pin receiving members 118 .
- Assembly 116 is a conventional assembly that is used with conventional pins. Conventional pins do not include an elastic portion and, furthermore, with packages that use a baseplate, the pins in some cases are not coupled directly to the substrate(s) atop the baseplate for a variety of reasons.
- pin receiving members 118 may be placed atop the baseplate and contacts of the pin receiving members may be electrically coupled to contacts of elements atop the substrate 6 using electrical couplers 20 , which in implementations may be aluminum wires.
- electrical couplers 20 which in implementations may be aluminum wires.
- the housing is placed atop the assembly 116 , and when the package is installed, such as using a press-fit method with a motherboard or printed circuit board (PCB), or the like
- the forces of press-fit installation will push down on the conventional pins but will not push down directly on the substrate 6 because the pins are positioned over the pin receiving members 118 instead of over the substrate.
- the conventional pins will thus press down instead on the baseplate 78 . This may reduce the likelihood of damage to the substrate 6 during press-fit installation of the package with a motherboard, PCB or the like.
- the pin receiving members 118 may not be needed since during press-fit installation of the package 62 the pins 86 , if they are pressed down, the members 118 do not impart undue pressure onto the substrate 6 because of the reversibly elastically deformable lower portion (elastic portion) (lower portion) 92 which includes spring 94 .
- package 62 may be formed with the pins 86 landing directly on the substrate 6 instead of on pin receiving members 118 of the baseplate 78 . Accordingly, pin receiving members 118 may be excluded, and thus assembly 76 may be used instead of assembly 116 .
- the package may be reduced in size because of this, with the baseplate 78 and the housing 64 having a smaller area and/or footprint, due to the lack of need to use pin receiving members 118 .
- Package implementations in which pin receiving members 118 are excluded may also have improved operation and/or life by eliminating aluminum wirebonds.
- the same size housing 64 and baseplate 78 could be used and one or more of the pins 86 are formed with a horizontal section 112 so that the pins 86 , instead of landing on the baseplate 78 , extend inwards to land on the substrate 6 .
- a perimeter defined by a plurality of elastic couplers 84 outside the package such as shown with semiconductor package (package) 120 of FIG. 9 , may be smaller than a perimeter formed by the same plurality of elastic couplers 84 within the package.
- the housing 122 may be used with assembly 76 , but an outer perimeter defined by the elastic couplers 84 , as seen in FIG.
- packages 9 may be larger than an outer perimeter formed by a plurality of substrates 6 . Additionally some packages, such as package 120 , may have pins only along a single rectangular perimeter, while others, as packages 2 and 62 , may have pins not only along a rectangular perimeter but also within the rectangle defined by that perimeter.
- the cavity of package 120 may be partially or fully filled with an encapsulant through an opening in the housing 122 (which in FIG. 9 is rectangular) which is later covered with cover 124 .
- the pins 86 include, along with the horizontal section 112 , a first vertical section 110 and a second vertical section 114 . Furthermore, an upper portion 88 of the pin 86 includes a rigid portion 90 , and the spring 94 in implementations includes a helical coil spring 96 . The spring 94 couples the rigid portion 90 with rigid portion 98 . A lower end 100 of the pin 86 is defined as a lower end of the rigid portion 98 , if rigid portion 98 is included, or the lower end of spring 94 if rigid portion 98 is excluded, similar to pin 38 .
- the rigid portion 98 in implementations includes a flat plate 104 having a contact surface 106 on a base 102 of the flat plate 104 .
- the pin 86 has a longest length 108 that is substantially parallel, or parallel, with a direction of compression of spring 94 .
- wires of aluminum or another metal may be used to electrically couple one or more connection traces of the substrate with one or more pins of the package.
- Implementations of semiconductor packages 2 , 62 , 120 disclosed herein allow electrical interconnection between the die and pins of the package without the use of wirebonds or wire connections between the substrate and pins.
- Conventional packages use soldering to electrically and mechanically couple pins of the package with connection traces of the substrate, and thereafter a housing (such as a polymer case) is coupled to the substrate and/or a baseplate coupled to the substrate.
- the conventional housing has openings for the pins to pass through as the housing is being lowered towards the substrate and, therefore, the pins are not fixedly coupled to the housing.
- an encapsulant such as silicone potting
- the pins are nevertheless not generally fixedly coupled to the housing itself
- the housing cannot be lifted without twisting the pin to reverse the locking procedure, and the pin is fixedly coupled to the substrate with solder, such that the housing could not be lifted relative to the substrate, without twisting the pin to the open position, without fracturing the solder connection of the pin with the substrate.
- the pin is only temporarily fixedly coupled to the housing.
- the pins are permanently fixedly coupled to the housing by being at least partially encapsulated within the housing during formation of the housing.
- the housing after the pins have been at least partially encapsulated therein, is not free to move without moving the pins as well.
- the pins could be only temporarily fixedly coupled to the housing, such as with threads, a friction fit, or the like.
- the plastic injection mold chase may be designed to arrange the pins before plastic injection.
- Each spring as disclosed herein is integrated with one of the pins in the longitudinal direction.
- pressure between the individual pins and the substrate is maintained by virtue of the plastic case being coupled with the substrate.
- the pins as described herein may be configured to be press-fit pins, such as to be press fit into hollow pin receivers of a motherboard or PCB, or they may be solder pins, configured to be soldered to connection traces or other elements of a motherboard, PCB or the like.
- the pins are press fit pins they may have a press fit portion proximate a distal end (opposite the end closest to the elastic portion or spring).
- the press fit portion may include elements such as, by non-limiting example, a compressible section that is configured to compress along a direction perpendicular with the direction of insertion of the pin into a pin receiver, which compression may comprise only elastic or may comprise elastic and plastic deformation.
- the compressible section may include an opening passing through the pin along a direction perpendicular with a longest length of the pin, though in implementations the compressible section may include other elements and/or the press fit portion may exclude an opening.
- a wide variety of other type of press-fit sections and designs may be utilized and selected by those of ordinary skill in the art using the principles disclosed herein.
- the flat plate 56 , 104 shown in the drawings has a width, substantially parallel with a longest length 60 , 108 of the pin 38 , 86 , that is greater than a height of the flat plate 56 , 104 —the height being substantially parallel with a longest length 60 , 108 of the pin 38 , 86 —in other implementations the flat plate 56 , 104 could have a height greater than its width.
- pins 38 , 86 remove the potential for such damage due to the lack of a solder connection between the pin and substrate and due to the elastic portions 44 , 92 .
- soldering process there is no soldering process to couple the pins to the substrate, and there is no wirebond connection between the substrate and the pins.
- the lack of a solder connection between the pins and the substrate may eliminate a second solder reflow process for the assembly of the package, as a first solder reflow may have occurred when coupling the die to the substrate. This can reduce other problems, such as movement or float of the die during the second solder reflow.
- the pins 38 , 86 may increase a contact area, and otherwise improve electrical contact, between the pin and the substrate as compared with conventional pins.
- the housings disclosed herein may be laser marked, or the like, at any point in the assembly process.
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Abstract
Description
- 1. Technical Field
- Aspects of this document relate generally to semiconductor device packages. Particular aspects of this document relate to power semiconductor device packages, such as power integrated modules (PIMs).
- 2. Background Art
- Semiconductor devices are often encased within (or partly within) a package prior to use. Some packages contain a single die while others contain multiple die. The package offers protection to the die, such as from corrosion, impact and other damage, and often also includes electrical leads or other components which connect the electrical contacts of the die with a motherboard. The package may also include components configured to dissipate heat from the die into a motherboard, a heat sink, or otherwise away from the package. Some conventional semiconductor power packages have included springs exterior to the package for contact with external elements, and some of these may have included double-spring designs.
- Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.
- Implementations of semiconductor packages may include one, all, or any of the following:
- A base of the pin may be coupled to the substrate with a spring.
- The pin may be fixedly coupled in a top of the housing and may be configured to be coupled with the substrate by lowering the housing towards the substrate.
- The pin may include two rigid portions coupled together only with a spring.
- One of the rigid portions may include a flat plate.
- The reversibly elastically deformable lower portion may include a spring.
- The spring may include a coil spring.
- Implementations of semiconductor packages may include: at least one die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the at least one die within a cavity of the housing, and; a plurality of pins fixedly coupled in a top of the housing, each of the plurality of pins electrically coupled with one of the at least one die through a connection trace of the substrate, each of the plurality of pins including a spring, wherein the spring of each pin biases an upper portion of the pin towards the housing.
- Implementations of semiconductor packages may include one, all, or any of the following:
- The spring of each pin may be positioned between two rigid portions of the pin.
- The spring of each pin may bias the two rigid portions of the pin away from one another.
- The spring of each pin may be compressed along a direction substantially parallel with a longest length of the pin.
- The spring of each pin may be configured to prevent a contact surface of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered towards the substrate.
- The spring may include a helical spring.
- Implementations of methods of forming a semiconductor package may include: securing a pin to a housing, the pin including a spring; lowering the housing relative to a substrate having a semiconductor die (die) coupled thereon to at least partially enclose the die within a cavity of the housing, and; while lowering the housing, compressing the spring so that a lower end of the pin does not lower beyond a predetermined point relative to the substrate and so that an upper portion of the pin is biased towards the housing, wherein lowering the housing includes electrically coupling the pin with the die.
- Implementations of methods of forming a semiconductor package may include one, all, or any of the following:
- The housing may be secured to the substrate.
- Securing the housing to the substrate may include maintaining compression of the spring.
- The lower end of the pin may be included in a flat plate of the pin and, prior to lowering the housing, the flat plate may be coupled to the upper portion of the pin through only the spring.
- Compressing the spring may include compressing the spring between two rigid portions of the pin.
- Compressing the spring may include biasing the two rigid portions of the pin away from one another.
- Compressing the spring may include compressing the spring along a direction substantially parallel with a longest length of the pin.
- The foregoing and other aspects, features, and advantages will be apparent to those artisans of ordinary skill in the art from the DESCRIPTION and DRAWINGS, and from the CLAIMS.
- Implementations will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements, and:
-
FIG. 1 is a perspective view of an implementation of a semiconductor package; -
FIG. 2 is a perspective view of another implementation of a semiconductor package; -
FIG. 3 is a cross-section view of the semiconductor package ofFIG. 4 in an open configuration; -
FIG. 4 is a cross-section view of the semiconductor package ofFIG. 1 taken along line A-A; -
FIG. 5 is a cross-section view of the semiconductor package ofFIG. 6 in an open configuration; -
FIG. 6 is a cross-section view of the semiconductor package ofFIG. 2 taken along line B-B; -
FIG. 7 is a top view of a plurality of substrates, a baseplate, and other elements of a conventional semiconductor package; -
FIG. 8 is a top view of a plurality of substrates, a baseplate, and other elements of a semiconductor package; and -
FIG. 9 is a perspective view of another implementation of a semiconductor package. - This disclosure, its aspects and implementations, are not limited to the specific components, assembly procedures or method elements disclosed herein. Many additional components, assembly procedures and/or method elements known in the art consistent with the intended semiconductor packages with elastic couplers and related methods will become apparent for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, and/or the like as is known in the art for such semiconductor packages with elastic couplers and related methods, and implementing components and methods, consistent with the intended operation and methods.
- “Top side” and “bottom side” are terms used in the industry to refer to sides of semiconductor die and sometimes relate to the nature of the electrical contacts on the side being referenced. A side having one or more electrical contacts not intending to be only used as a ground is sometimes called a “top side.” A side having only electrical contacts which are intended to be used as an electrical ground is sometimes called a “bottom side.” Nevertheless, for ease of explanation, as used herein the term “bottom side” in this document refers to the side of a die that is facing towards a bottom of a drawing page, while the term “top side” when used herein refers to the side of a die that is facing towards a top of a drawing page.
- Referring now to
FIGS. 1, 3 and 4 , as illustrated, a semiconductor package (package) 2 includes one ormore die 4 coupled to asubstrate 6. Ahousing 24 has one ormore pins 38 fixedly coupled thereto and at least one of the pins is electrically coupled to one of the die 4. Thepackage 2 in implementations is a power semiconductor device such as, by non-limiting example, a power integrated module (PIM), an integrated power module (IPM) or intelligent power module, and the like, and may include one or more power metal-oxide-semiconductor field-effect transistors (power MOSFETs), insulated gate bipolar transistors (IGBTs), and the like. Thepackage 2 may be used, for example, for power applications in the auto industry, in industrial machines, in power generation, in household appliances, and so forth. - Although the package examples shown in the drawings are power semiconductor devices, in other applications similar pins and other packaging elements and methods disclosed herein may be used for packages which are not power semiconductor packages. In implementations in which the
package 2 is a power semiconductor device thepackage 2 may include, by non-limiting example, one or more insulated gate bipolar transistor (IGBT) die electrically coupled, such as through a wirebond, clip or the like, with one or more diode rectifier die. By non-limiting example, referring to the package ofFIG. 3 , one of the die shown may be an IGBT while the other may be a diode rectifier. -
Substrate 6 in implementations is a power electronic substrate and may include, by non-limiting example, a direct bonded copper (DBC) substrate, an active metal brazed (AMB) substrate, an insulated metal substrate (IMS), a ceramic substrate, and the like. Other types of substrates could be used. In implementations in which a DBC substrate is used the DBC substrate may have a copper layer only on one side of the DBC substrate (a side that includes connection traces) or, in other implementations, it may include a first copper layer on a first side of a ceramic layer and a second copper layer on a second side of the ceramic layer so that the ceramic layer is sandwiched between two copper layers.Substrate 6, for example, is a direct bonded copper (DBC)substrate 8 having aceramic layer 10 sandwiched between afirst copper layer 12 andsecond copper layer 18, and thefirst copper layer 12 includes connection traces 14. Other metallic and/or non-metallic layers may be included on the first and/or second copper layers 12, 18 in various implementations. - In some implementations one or more DBC substrates each having two copper layers, and each having connection traces in each copper layer, could be used. For example, although the implementation in
FIG. 3 useselectrical couplers 20 that are wirebonds 22 to electrically couple electrical contacts of thedie 4 with the connection traces 14, in other implementations thewirebonds 22 could be excluded and instead a second DBC substrate having connection traces on both sides (each in a copper layer) could be coupled to thedie 4, the connection traces in a bottom side of the second DBC electrically coupling to the electrical contacts on a top side of the die 4 (“top side” meaning facing a top of the page in the drawings). A second layer ofdie 4 may then be placed atop the connection traces on the upper side of the second DBC substrate, and then further connections may be made with electrical contacts on a top side of the second layer ofdie 4, such as usingelectrical couplers 20, which may be wirebonds 22, conductive clips, or the like, and then further packaging may be done to achieve a structure similar to structures shown in the drawings but having a stacked configuration with multiple layers ofdie 4. Other stacking mechanisms and methods may be used, and those given here are just representative examples. In some implementations one or more or all of thedie 4 could be coupled with the connection traces 14 using a flip-chip process using die bumps so that no wirebonds or conductive clips are needed. - The connection traces 14 route and electrically couple electrical contacts on the
die 4 with other elements, such as the pins,other die 4, power sources, electrical grounds, other devices within or without thepackage 2, and the like. By non-limiting example, the connection traces to which the bottom side of each die 4 is coupled (“bottom side” referring to the sides of thedie 4 facing a bottom of the page in the drawings) may connect conductive pads on the bottom sides of those die with electrical ground, while the electrical couplers 20 (such aswirebonds 22 or conductive clips) which are electrically coupled topins 38 through other connection traces 14 may couple electrical contacts on the top sides of thedie 4 with power sources. These are just representative examples, and one or more electrical contacts on the top sides of die may be coupled to electrical ground through the pins. Naturally, in cases in which flip chip packaging is used, one or more connection traces 14 may be used to couple one or more electrical contacts on the bottom side of thedie 4 with electrical ground and one or more other connection traces 14 may be used to couple one or more other electrical contacts on the bottom side of thedie 4 with one or more power sources through the pins, one or moreother die 4, one or more other electrical devices within or without thepackage 2, and so forth. - Referring still to
FIGS. 1, 3 and 4 , thehousing 24 in implementations is formed of a polymer, such as a thermoset, thermosoftening (thermopolymer), or other type of polymer or plastic—though in implementations it could also be formed of a composite material.Elastic couplers 36 are formed of an electrically conductive material, such as a metal, and are used to electrically and/or mechanically couple one or more electrical contacts of thedie 4 with items outside thepackage 2, such as with a motherboard or printed circuit board (PCB), a power source, an electrical ground, other devices external to thepackage 2, and so forth. In cases in which a motherboard or PCB is used, the motherboard/PCB may include pin receivers, such as an array of cylindrical cavities, each pin receiver designed to receive onepin 38 and thereby electrically and mechanically couple thereto. The motherboard/PCB may further route the pins to other electric devices, power sources, electrical ground,other die 4, and so forth. In implementations one ormore packages 2 may be coupled to a single motherboard/PCB and themultiple packages 2 may or may not be electrically interconnected through the motherboard/PCB. - The
elastic couplers 36 are fixedly attached to thehousing 24. This may be accomplished in a variety of ways. In the implementations illustrated in the drawings, theelastic couplers 36 have been integrated into a top 26 of thehousing 24 by placing theelastic couplers 36 andhousing 24 in the configuration shown while thehousing 24 is in a liquid state and then allowing or causing thehousing 24 to solidify. For example this may be done through a melting process, or a resin may be used which may be cured to form a solid phase, and so forth. In other implementations the same structure shown inFIGS. 3-4 may be accomplished by forming thehousing 24 with portions configured to receive thepins 38 and then gluing, welding, or otherwise adhering thepins 38 to the portions of thehousing 24 configured to receive them. In other implementations thehousing 24 may have female threads and thepins 38 may have male threads and the two may be joined by coupling the threads together. Other coupling mechanisms may be used. In general thepins 38, at a point in the fabrication of thepackage 2 prior to coupling the pins with the connection traces 14, are fixedly coupled to thehousing 24 and, therefore, generally not free to move relative to thehousing 24 while thehousing 24 is being lowered towards thesubstrate 6 to couple thereto. - The
housing 24 includes acavity 28 configured to receive thedie 4 and other elements therein. The cavity at least partially encloses the die within the cavity. In the implementation shown inFIGS. 3-4 the housing includes aledge 30 which rests atop thesubstrate 6, and which may be adhered thereto such as using an adhesive, though theledge 30 may also just rest atop thesubstrate 6 without any adhesive and thesubstrate 6 may have one or more other coupling mechanisms such as screw holes so that thehousing 24 may be coupled thereto by inserting screws into theopenings 32 ofhousing 24 and screwing screws into screw holes of thesubstrate 6. Other coupling mechanisms such as clips, a friction fit, and the like are possible. In implementations an area proximate theledge 30 and or including the ledge 30 (particularly the bottom face of the ledge 30), the vertical inner portion of thehousing 24 below theledge 30 and/or the portion of thesubstrate 6 that contacts these areas of thehousing 24 may be roughened prior to coupling the housing and substrate together, such as with the use of an abrasive, in order to ensure a better bond when an adhesive is applied therebetween. In implementations in which a friction fit is used a similar roughening operation may be done in order to form a better or stronger fit therebetween, or in other words a fit having greater friction. In some implementations this roughening may be done with physical abrasion such as through sanding or blasting with a fluid having a grit element therein. In other implementations the roughening may be done through chemical means such as through an etching process or the like, though other mechanisms may also be used for roughening these surfaces. In other implementations, coupling structures may be included in the location of thehousing 24 proximate theledge 30 or including theledge 30 to aid in establishing a friction fit, including, by non-limiting example projections, flanges, pin-like structures, bumps, and other structures that can couple against the edge of thesubstrate 6. - The
elastic couplers 36 arepins 38 configured to electrically couple with thedie 4 through the connection traces 14 and to electrically couple with a motherboard, PCB or other element external topackage 2.Pin 38 has anupper portion 40, which includes arigid portion 42, and a reversibly elastically deformable lower portion (lower portion) (elastic portion) 44. In some implementations all of the elastic portion 44 is reversibly elastically deformable, while in other implementations only a portion of the elastic portion 44 is reversibly elastically deformable. Referring toFIGS. 3-4 , for instance, elastic portion 44 includes aspring 46 and arigid portion 50. Therigid portion 50 forms abase 54 of thepin 38 and includes aflat plate 56 having acontact surface 58 on its underside configured to electrically couple with aconnection trace 14. Thus, in the implementation ofFIGS. 3-4 alower end 52 of thepin 38 is arigid portion 50, so that the elastic portion 44 includes both aspring 46 and arigid portion 50. Thus, the elastic portion 44 in the implementations ofFIGS. 3-4 has a portion which is reversibly elastically deformable and another portion which is not. Those portions that are not reversibly elastically deformable may be plastically deformable and/or non-reversibly elastically deformable. - In other implementations all of the elastic portion 44 could be reversibly elastically deformable. For example, in some cases the
rigid portion 50 could be omitted entirely, so that the elastic portion 44 only includesspring 46. In such cases, thelower end 52 of thepin 38 would be the bottom of thespring 46, not the bottom of theflat plate 56, since theflat plate 56 would be excluded. In various implementations, the spring is a coil spring, such as ahelical coil spring 48. - The elastic section 44 in implementations is formed entirely in: the bottom half; the bottom third; the bottom fourth; the bottom fifth; the bottom sixth; the bottom seventh; the bottom eighth; the bottom ninth; the bottom tenth; the bottom eleventh; the bottom twelfth; the bottom thirteenth; the bottom fourteenth; the bottom fifteenth; the bottom sixteenth; and so forth, of the
pin 38. In implementations thepin 38 may have alongest length 60 of, or of about, 14 mm, and thespring 46 may have a length, measured along the same direction of thelongest length 60, of, or of about, 1 mm. Thespring 46 may be configured to compress from a length of, or of about, 1 mm to a length of, or of about: 0.9 mm; 0.8 mm; 0.7 mm, 0.6 mm, 0.5 mm, 0.4 mm, 0.3 mm; and so forth. Accordingly, spring material and spring constants for thespring 46 may be selected according to the desired compression characteristics. In implementations of springs herein the spring may have a length, parallel with a longest length of the pin, of greater than 1 mm. - In implementations the
spring 46 is formed of, by non-limiting example: a high carbon spring steel; a stainless steel, a steel alloy having one or more of chromium, vanadium, nickel, molybdenum, and/or aluminum; a bronze alloy; an alloy of beryllium and copper; an alloy of nickel and copper; an alloy of iron, chromium and nickel; and the like. Although thesprings 46 shown in the drawings have a straight cylindrical profile (i.e., the coils are of the same diameter), in other implementations the springs may have a conical profile with decreasing coil diameters (going in either direction) such that the individual coils are not forced against one another, or not as much, in compression, thus allowing greater overall compression of thespring 46. Other configurations are possible using the principles disclosed in this document. Thespring 46 may be coupled to the rigid portions using, by non-limiting example: a solder; a conductive adhesive; a weld; and the like. In various implementations, the entirety of each pin, including the rigid portion(s) and the spring, could be integrally formed from a single piece of material so that the spring is integrally attached to the rigid portion(s). In particular implementations, the relaxed, non-compressed length of the spring in a direction parallel withlongest length 60 is one of: less than half, less than a third, less than a fourth, less than a fifth, less than a sixth, less than a seventh, less than an eighth, less than a ninth, less than a tenth, less than an eleventh, less than a twelfth, less than a thirteenth, less than a fourteenth, less than a fifteenth, and so forth, the length oflongest length 60. - The
rigid portion 50, when included, is formed of an electrically conductive metal. The metal for therigid portions - In implementations the spring could be a type of compression spring other than a coil spring such as, by non-limiting example: a flat spring; a machined spring (which may or may not include the rigid portions of the pin); a volute spring; a Belleville spring; and the like.
- The
elastic coupler 36 is configured so that, when thehousing 24 is lowered towards thesubstrate 6, thelower end 52 of the pin stops at apredetermined point 16 and travels no farther downwards. In this way, the spring of each pin is configured to prevent a contact surface of the pin from lowering beyond the predetermined point relative to the substrate when the housing is lowered towards the substrate. As described herein, thelower end 52 may be therigid portion 42 or, in implementations in whichrigid portion 42 is excluded, it may be a lower end of thespring 46. This allows electrical and/or mechanical communication to be formed between each pin and the connection traces by the act of lowering the housing onto the substrate. Accordingly, in various implementations of packages using the pins described herein, the pins may be coupled with the connection traces without the use of solder, conductive adhesive, a press-fit, and so forth. Additionally, as the coupling of the pins with the connection traces is formed by virtue of the elastic portion 44, thehousing 24 could be raised and the pins would lift off the communication traces without needing to sever the pins or melt solder, or the like, for the removal. - When the spring is compressed, which occurs as the housing is lowered towards the substrate and the base 54 contacts the substrate, the pin then biases the lower end or
base 54 of the pin towards the substrate and, at the same time, biases an upper portion of the pin (in other words, the portion of the pin between the spring and the top of the housing) towards the top of the housing. The spring, when compressed, also biases the two rigid portions away from one another, and it could also be said that the spring, when compressed, biases the lowerrigid portion 50 downwards while biasing the upperrigid portion 42 upwards. Each pin, when compressed, is compressed along a direction that is parallel, or substantially parallel, with alongest length 60 of the pin. The act of lowering the housing electrically couples the pin with the die by contacting the lower end of the pin with a connection trace of the substrate, the connection trace of the substrate being electrically coupled with an electrical contact of the die. The housing may be secured to the substrate, or relative to the substrate, such as with a friction fit, a glue, screws, a clamping mechanism, and the like, and securing the housing to or with the substrate maintains compression of the spring. As shown in the drawings, in various implementations the two rigid portions are directly coupled together only with the spring. In implementations the pin consists of two rigid portions coupled together with a spring. Compressing the spring in various implementations includes compressing the spring between the two rigid portions of the pin. -
Pins 38 may have various shapes, for instance they may have cylindrical or rounded shapes when viewed perpendicular to thelongest length 60, or they may have rectangular or square shapes when viewed from that direction. In various implementations eachpin 38 may have a smallest diameter, taken perpendicular to alongest length 60 of the pin, of, or of about, 0.64 mm. In implementations in which thepin 38 has a rectangular shape where it exits the top 26, thepin 38 may have a cross section taken perpendicular to thelongest length 60 having a rectangular shape with a first side ranging between 1.12 mm and 1.18 mm and a second side ranging between 0.77 mm and 0.83 mm. In other implementations the rectangular shape may have a first side of 1.15 mm and a second side of 1.8 mm. In various implementations the packages shown inFIGS. 1, 2 and 9 may each have a rectangular footprint having a first side of, or of about, 66 mm and another side of, or of about, 32.5 mm. In particular implementations the packages may each have a rectangular footprint having a first side ranging between 107 mm to 108 nun and a second side ranging between 44.5 mm and 45.5 mm. In other implementations the packages may each have a rectangular footprint having a first side of 107.5 mm and a second side of 45 mm. - The
packages 2 shown in the figures do not include a baseplate below thesubstrate 6. In other implementations a baseplate may be used, and in such implementations the baseplate may couple directly to thesubstrate 6 such as with an adhesive or using screws, or the like, and/or may be coupled directly to thehousing 24 and pressed againstsubstrate 6 thereby, and so forth. The baseplate may be metallic and may assist in the extraction of heat away from thedie 4.Package 2 may further include one ormore couplers 34 to couple thepackage 2 to a heat spreader, heat pipes, heat sink, and/or to an electrical ground, and the like. - Referring now to
FIGS. 2, 5, 6 and 8 , a semiconductor package (package) 62 includes ahousing 64 having a top 66, the housing forming acavity 68 configured to receive and/or enclose one ormore die 4 therein.Package 62 includes abaseplate 78 and a plurality ofsubstrates 6 are coupled to the baseplate.Baseplate 78 may be formed of a metallic material and may be used to extract heat or assist in extracting heat away from thedie 4. The baseplate could be formed of steel, aluminum or an aluminum alloy, copper or a copper alloy, an alloy containing molybdenum and/or tungsten, and the like. Thesubstrates 6 may be coupled to thebaseplate 78 such as with a solder, an adhesive, screws, a friction fit, or the like.Housing 64 includesopenings 70 andbaseplate 78 includes correspondingopenings 80 for acoupler 72, such asscrew 74, to couple thehousing 64 to thebaseplate 78. Naturally this may be reversed and the two removed from one another. Other coupling mechanisms could be used such as glue, a friction fit, and so forth. -
FIGS. 7-8 show examples ofassemblies Assembly 76 includes thebaseplate 78 andsubstrates 6, along withdie 4 andelectrical couplers 20, ofFIGS. 5-6 . Some of theelectrical couplers 20 are coupled topads 82 of thedie 4, thepads 82 being electrical contacts on a face of thedie 4.Assembly 116 differs fromassembly 76 in thatassembly 116 includespin receiving members 118.Assembly 116 is a conventional assembly that is used with conventional pins. Conventional pins do not include an elastic portion and, furthermore, with packages that use a baseplate, the pins in some cases are not coupled directly to the substrate(s) atop the baseplate for a variety of reasons. By non-limiting example, when abaseplate 78 is used then, as shown inFIG. 7 , pin receivingmembers 118 may be placed atop the baseplate and contacts of the pin receiving members may be electrically coupled to contacts of elements atop thesubstrate 6 usingelectrical couplers 20, which in implementations may be aluminum wires. Later, when the housing is placed atop theassembly 116, and when the package is installed, such as using a press-fit method with a motherboard or printed circuit board (PCB), or the like, the forces of press-fit installation will push down on the conventional pins but will not push down directly on thesubstrate 6 because the pins are positioned over thepin receiving members 118 instead of over the substrate. The conventional pins will thus press down instead on thebaseplate 78. This may reduce the likelihood of damage to thesubstrate 6 during press-fit installation of the package with a motherboard, PCB or the like. - When the
elastic couplers 84 are used, however, as shown inFIGS. 2 and 5-6 , thepin receiving members 118 may not be needed since during press-fit installation of thepackage 62 thepins 86, if they are pressed down, themembers 118 do not impart undue pressure onto thesubstrate 6 because of the reversibly elastically deformable lower portion (elastic portion) (lower portion) 92 which includesspring 94. Thus,package 62 may be formed with thepins 86 landing directly on thesubstrate 6 instead of onpin receiving members 118 of thebaseplate 78. Accordingly, pin receivingmembers 118 may be excluded, and thusassembly 76 may be used instead ofassembly 116. In implementations the package may be reduced in size because of this, with thebaseplate 78 and thehousing 64 having a smaller area and/or footprint, due to the lack of need to usepin receiving members 118. Package implementations in whichpin receiving members 118 are excluded may also have improved operation and/or life by eliminating aluminum wirebonds. - In various implementations however, the
same size housing 64 andbaseplate 78 could be used and one or more of thepins 86 are formed with ahorizontal section 112 so that thepins 86, instead of landing on thebaseplate 78, extend inwards to land on thesubstrate 6. Thus a perimeter defined by a plurality ofelastic couplers 84 outside the package, such as shown with semiconductor package (package) 120 ofFIG. 9 , may be smaller than a perimeter formed by the same plurality ofelastic couplers 84 within the package. Similarly, referring toFIGS. 8-9 , thehousing 122 may be used withassembly 76, but an outer perimeter defined by theelastic couplers 84, as seen inFIG. 9 , may be larger than an outer perimeter formed by a plurality ofsubstrates 6. Additionally some packages, such aspackage 120, may have pins only along a single rectangular perimeter, while others, aspackages package 120 may be partially or fully filled with an encapsulant through an opening in the housing 122 (which inFIG. 9 is rectangular) which is later covered withcover 124. - The
pins 86 include, along with thehorizontal section 112, a firstvertical section 110 and a secondvertical section 114. Furthermore, anupper portion 88 of thepin 86 includes arigid portion 90, and thespring 94 in implementations includes ahelical coil spring 96. Thespring 94 couples therigid portion 90 withrigid portion 98. Alower end 100 of thepin 86 is defined as a lower end of therigid portion 98, ifrigid portion 98 is included, or the lower end ofspring 94 ifrigid portion 98 is excluded, similar topin 38. Therigid portion 98 in implementations includes aflat plate 104 having acontact surface 106 on abase 102 of theflat plate 104. Thepin 86 has alongest length 108 that is substantially parallel, or parallel, with a direction of compression ofspring 94. - In conventional packages wires of aluminum or another metal may be used to electrically couple one or more connection traces of the substrate with one or more pins of the package. Implementations of
semiconductor packages - There exist conventional packages in which a pin is temporarily fixedly coupled to a housing. For example, U.S. Pat. App. Pub. No. 2014/0199861 to Mattiuzzo, published Jul. 17, 2014, describes a pin which may be locked in place by turning the pin after it has been soldered to a substrate and after the housing has been put in place. The pin is thus temporarily fixedly coupled to the housing in that case, but the pin could also be removed by twisting the pin in the opposite direction, and thus the pin is not permanently fixedly coupled to the housing. Additionally, the housing cannot be lifted without twisting the pin to reverse the locking procedure, and the pin is fixedly coupled to the substrate with solder, such that the housing could not be lifted relative to the substrate, without twisting the pin to the open position, without fracturing the solder connection of the pin with the substrate. Thus in that implementation the pin is only temporarily fixedly coupled to the housing.
- In the implementations of
packages packages package - Each spring as disclosed herein is integrated with one of the pins in the longitudinal direction. In implementations of
packages - Although the
flat plate longest length pin flat plate longest length pin flat plate - In implementations of conventional packages in which pins are soldered to connection traces of the substrate, there can be damage to the substrate, the solder joint, and/or other elements of the package when the housing is lowered towards the substrate and/or when the pins are press-fit into pin receivers of a motherboard or PCB.
Pins elastic portions 44, 92. - In implementations of packages disclosed herein there is no soldering process to couple the pins to the substrate, and there is no wirebond connection between the substrate and the pins. The lack of a solder connection between the pins and the substrate may eliminate a second solder reflow process for the assembly of the package, as a first solder reflow may have occurred when coupling the die to the substrate. This can reduce other problems, such as movement or float of the die during the second solder reflow. In implementations the
pins - In places where the description above refers to particular implementations of semiconductor packages with elastic couplers and related methods and implementing components, sub-components, methods and sub-methods, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these implementations, implementing components, sub-components, methods and sub-methods may be applied to other semiconductor packages with elastic couplers and related methods. For example, characteristics, sizes, and the like of elements and sub-elements of one package, such as a
package 2, may be used with apackage
Claims (8)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/626,758 US9431311B1 (en) | 2015-02-19 | 2015-02-19 | Semiconductor package with elastic coupler and related methods |
US15/230,076 US9691732B2 (en) | 2015-02-19 | 2016-08-05 | Semiconductor package with elastic coupler and related methods |
US15/630,112 US10319652B2 (en) | 2015-02-19 | 2017-06-22 | Semiconductor package with elastic coupler and related methods |
US16/396,904 US10607903B2 (en) | 2015-02-19 | 2019-04-29 | Semiconductor package with elastic coupler and related methods |
US16/799,026 US11569140B2 (en) | 2015-02-19 | 2020-02-24 | Semiconductor package with elastic coupler and related methods |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/626,758 US9431311B1 (en) | 2015-02-19 | 2015-02-19 | Semiconductor package with elastic coupler and related methods |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/230,076 Division US9691732B2 (en) | 2015-02-19 | 2016-08-05 | Semiconductor package with elastic coupler and related methods |
Publications (2)
Publication Number | Publication Date |
---|---|
US20160247735A1 true US20160247735A1 (en) | 2016-08-25 |
US9431311B1 US9431311B1 (en) | 2016-08-30 |
Family
ID=56690008
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/626,758 Active US9431311B1 (en) | 2015-02-19 | 2015-02-19 | Semiconductor package with elastic coupler and related methods |
US15/230,076 Active US9691732B2 (en) | 2015-02-19 | 2016-08-05 | Semiconductor package with elastic coupler and related methods |
US15/630,112 Active 2035-07-29 US10319652B2 (en) | 2015-02-19 | 2017-06-22 | Semiconductor package with elastic coupler and related methods |
US16/396,904 Active US10607903B2 (en) | 2015-02-19 | 2019-04-29 | Semiconductor package with elastic coupler and related methods |
US16/799,026 Active 2035-02-21 US11569140B2 (en) | 2015-02-19 | 2020-02-24 | Semiconductor package with elastic coupler and related methods |
Family Applications After (4)
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US15/230,076 Active US9691732B2 (en) | 2015-02-19 | 2016-08-05 | Semiconductor package with elastic coupler and related methods |
US15/630,112 Active 2035-07-29 US10319652B2 (en) | 2015-02-19 | 2017-06-22 | Semiconductor package with elastic coupler and related methods |
US16/396,904 Active US10607903B2 (en) | 2015-02-19 | 2019-04-29 | Semiconductor package with elastic coupler and related methods |
US16/799,026 Active 2035-02-21 US11569140B2 (en) | 2015-02-19 | 2020-02-24 | Semiconductor package with elastic coupler and related methods |
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US (5) | US9431311B1 (en) |
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Also Published As
Publication number | Publication date |
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US10319652B2 (en) | 2019-06-11 |
US20160343683A1 (en) | 2016-11-24 |
US9691732B2 (en) | 2017-06-27 |
US10607903B2 (en) | 2020-03-31 |
US20190252275A1 (en) | 2019-08-15 |
US11569140B2 (en) | 2023-01-31 |
US9431311B1 (en) | 2016-08-30 |
US20200194322A1 (en) | 2020-06-18 |
US20170294362A1 (en) | 2017-10-12 |
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