US20160240548A1 - Memory device and method for fabricating the same - Google Patents
Memory device and method for fabricating the same Download PDFInfo
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- US20160240548A1 US20160240548A1 US14/623,630 US201514623630A US2016240548A1 US 20160240548 A1 US20160240548 A1 US 20160240548A1 US 201514623630 A US201514623630 A US 201514623630A US 2016240548 A1 US2016240548 A1 US 2016240548A1
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- 238000000034 method Methods 0.000 title claims description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 67
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 67
- 239000010703 silicon Substances 0.000 claims abstract description 67
- 239000002184 metal Substances 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 230000001934 delay Effects 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000013459 approach Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000011295 pitch Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 206010010219 Compulsions Diseases 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011143 downstream manufacturing Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H01L27/11568—
-
- H01L27/11519—
-
- H01L27/11521—
-
- H01L27/11556—
-
- H01L27/11565—
-
- H01L27/11582—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
Definitions
- the disclosure in generally relates to a semiconductor device and a method for fabricating the same, and more particularly to a memory device and a method for fabricating the same.
- Non-volatile memory which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell has been widespreadly adopted by bulk solid state memory applications in portable audiovisual entertainment devices, cell phones or digital cameras etc.
- various three dimensional (3D) memory devices such as a 3D flash memory device having a single gate, a double gate or a surrounding gate, has been provided in order to accommodate the rising demand for superior memory.
- a 3D memory device such as a vertical-channel (VC) 3D NAND flash memory device that has a multi-layer stack structure may possess a higher density memory and excellent electrical characteristics, e.g. reliability in data storage and high operating speed.
- VC vertical-channel
- RC resistance-capacitance
- etch trenches passing through a multi-layer stack structure of the VC 3D NAND flash memory device for performing an etching process to remove sacrifice layers and allowing metal gates (word lines) formed on the position where the sacrifice layers originally disposed may be required.
- the etch trenches may occupy space of the multi-layer stack structure and exclude the forming of memory cells. The memory storage density of the VC 3D NAND flash memory device may thus be reduced.
- the residue of the sacrifice layers may remained in the multi-layer stack structure after the etching process for removing the sacrifice layers is carried out, or otherwise the memory layers could be damaged by over etch while the residue is thoroughly removed by a more aggressive etching process. As a result, defect memory cells may occur and the yield of the VC 3D NAND flash memory device may be also reduced.
- One aspect of the present invention is to provide a memory device, wherein the memory device comprises a plurality of silicon-containing layers, a plurality of string select lines (SSLs), a plurality of strings, a plurality of bit line, plural sets of multi-plugs structure and a plurality of metal strapped word lines.
- the silicon-containing layers are parallel to each other and vertically stacked at a substrate.
- the SSLs are disposed on the silicon-containing layers and extend along a first direction.
- the strings are perpendicular to the silicon-containing layers and the SSLs and electrically connected to the SSLs.
- the bit lines are disposed on the SSLs extending along a second direction and electrically connected to the strings.
- the plural sets of multi-plugs structure are arranged along the first direction, so as to make the strings disposed between two adjacent sets of multi-plugs structure.
- Each set of the multi-plugs structure has a plurality of plugs, and each of the plugs is corresponding to and electrically connected with one of the silicon-containing layers.
- the metal strapped word lines extend along the first direction, and each of the metal strapped word lines is electrically connected to the plugs that are electrically connected to the identical silicon-containing layer.
- a method for fabricating a memory device comprising steps as follows: Firstly, a plurality of silicon-containing layers parallel to each other are formed and vertically stacked at a substrate. A plurality of strings are then formed vertically passing through the silicon-containing layers. Next, a plurality of SSLs extending a long a first direction are formed on the silicon-containing layers and electrically connected to the strings.
- plural sets of multi-plugs structure are formed and arranged along the first direction, so as to make the strings disposed between two adjacent sets of multi-plugs structure, wherein each set of the multi-plugs structure has a plurality of plugs, and each of the plugs is corresponding to and electrically connected with one of the silicon-containing layers.
- a plurality of bit lines are formed on the SSLs extending along a second direction and electrically connected to the strings.
- a plurality of metal strapped word lines extending along the first direction are then formed on the plural sets of multi-plugs structure, wherein each of the metal strapped word lines is electrically connected the plugs that are electrically connected to the identical silicon-containing layer.
- a memory device and a method for fabricating the same are provided.
- Plural sets of multi-plugs structure are formed in a multi-layer stack structure of a memory device including a plurality of silicon-containing layers, and the plural sets of multi-plugs structure are arranged along an extending direction of the SSLs that are formed on the multi-layer stack structure and electrically connected to a plurality of strings vertically passing through the multi-layer stack structure, so as to make some of the plurality of the strings disposed between two adjacent sets of the multi-plugs structure.
- Each set of the multi-plugs structure has a plurality of plugs, and each of the plugs is corresponding to and electrically connected with one of the silicon-containing layers.
- the plugs that are electrically connected to the identical silicon-containing layer are electrically connected to a metal strapped word line.
- the gate resistance of the memory device can be significantly reduced, and the problems due to the parasitic RC time delays caused by the gate resistance and capacitance of the memory device can be avoided.
- the memory device adopts a silicon based gate instead of a metal gate, thus the process for fabricating a metal gate is no longer required. As a result, the bandwidth of the SSLs can be increased and the problems of defect memory cells and poor yield due to the metal gate process can be also avoided.
- FIG. 1A is a perspectivel view illustrating a partial structure of a multi-layer stack structure formed on a substrate in accordance with one embodiment of the present invention
- FIG. 1B is a perspectivel view illustrating the results after a plurality of strings are formed on the structure depicted in FIG. 1A ;
- FIG. 10 is a plan view illustrated in accordance with the structure depicted in FIG. 1B ;
- FIG. 1D is a perspectivel view illustrating the results after a plurality of SSLs are formed on the structure depicted in FIG. 1B ;
- FIG. 1E is a plan view illustrated in accordance with the structure depicted in FIG. 1D ;
- FIG. 1F is a naval view illustrating the results after plural sets of multi-plugs structure and a plurality contact vias are formed on the structure depicted in FIG. 1D ;
- FIG. 1G is a plan view illustrated in accordance with the structure depicted in FIG. 1F ;
- FIG. 1H is a plan view illustrating the results after a plurality of source lines and bit lines are formed on the structure depicted in FIG. 1G ;
- FIG. 1I is a plan view illustrating the results after a plurality of metal strapped word lines are formed on the structure depicted in FIG. 1I ;
- FIGS. 2A to 2D are cross-sectional views illustrating a method for fabricating the strings in accordance with one embodiment of the present invention
- FIG. 3 is a naval view illustrating a multi-plugs structure shaped in another type of staircase in accordance with another embodiment of the present invention
- FIG. 4A is a cross-sectional view taken along a line S 1 depicted in FIG. 1H ;
- FIG. 4B is a cross-sectional view taken along a line S 2 depicted in FIG. 1H ;
- FIG. 5 is a cross-sectional view illustrating another connection type of a grounding (GND) layer, a plurality source contact structures and a source lines in accordance with another embodiment of the present invention
- FIG. 6A is a cross-sectional view taken along a line S 3 depicted in FIG. 1I ;
- FIG. 6B is a cross-sectional view taken along a line S 4 depicted in FIG. 1I ;
- FIG. 7 is a plan view illustrating a partial structure of a VC 3D NAND flash memory device in accordance with another embodiment of the present invention.
- the embodiments as illustrated below provide a VC 3D NAND flash memory device 100 and a method for fabricating the same to avoid the problems due to the parasitic RC time delays of the memory device.
- the present invention will now be described more specifically with reference to the following embodiments illustrating the structure and method for fabricating the memory device.
- FIG. 1A is a naval view illustrating a multi-layer stack structure 10 formed on a substrate 101 in accordance with one embodiment of the present invention.
- the multi-layer stack structure 10 comprises a plurality of silicon-containing layers 102 , 112 , 122 , 132 and 142 , and a plurality of insulating layers 103 alternatively vertically stacked along a Z direction and parallel to each other.
- the silicon-containing layers 102 , 112 , 122 , 132 and 142 may be made of poly-silicon; and the insulating layers 103 are preferable made of silicon oxide. It should be appreciated that although the multi-layer stack structure 10 depicted in FIG. 1A merely comprises 5 silicon-containing layers and 4 insulating layers, it is just illustrative but not used to limit the number of the silicon-containing layers and the insulating layers that are applied in other embodiments of the present invention.
- FIG. 1B is a perspectivel view illustrating the results after a plurality of strings 104 are formed on the structure depicted in FIG. 1A .
- FIG. 1C is a plan view illustrated in accordance with the structure depicted in FIG. 1B .
- each of the strings 104 has a memory layer 104 a and a channel layer 104 b .
- the memory layer 104 a can be an NON structure made of a silicon nitride layer, a silicon oxide layer and a silicon nitride layer.
- the channel layer 104 b preferably consists of poly-silicon.
- a plurality of memory cells arranged in rows and columns can be defined at the intersections of the strings 104 and the silicon-containing layers 102 , 112 , 122 , 132 and 142 .
- the memory cells can be arranged as a matrix array.
- the memory cells can be arranged as a honeycomb array.
- the arrangements of the memory cells are not limited. Any suitable arrangements for the design rule of a 3D memory device may be encompassed within the spirit and scope of the present invention.
- FIGS. 2A to 2D are cross-sectional views illustrating a method for fabricating the strings 104 in accordance with one embodiment of the present invention.
- the process for forming the strings 104 comprises steps as follows: Firstly, a plurality of openings 105 passing though the silicon-containing layers 102 , 112 , 122 , 132 and 142 and the insulating layer 103 are formed to expose a portion of the substrate 101 (see FIG. 2A ).
- the memory layer 104 a is deposited on the sidewalls and the bottom of the openings 105 and the channel layer 104 b is then formed on the memory layer 104 a by depositing semiconductor material, such as poly-silicon or germanium (Ge), meanwhile to form the plurality of strings 104 on the sidewalls of the openings 105 (see FIG. 2B ).
- semiconductor material such as poly-silicon or germanium (Ge)
- a hard mask layer 109 is next deposited on the channel layer 104 b (see FIG. 2C ); and an anisotropic etching process is performed to removing the hard mask layer 109 as well as portions of the memory layer 104 a and the channel layer 104 b to expose a portion of the substrate 101 from the openings 105 . Thereafter, a plurality of source 115 are formed on the exposed portions of the substrate 101 , so as to electrically connect the plurality of strings 104 with the substrate 101 serving as a GND layer of the VC 3D NAND flash memory device 100 (see FIG. 2D ).
- a plurality of source contact structures 107 are also formed in the multi-layer stack structure 10 during the process for forming the strings 104 , wherein the source contact structures 107 are arranged along a X direction, so as to make the strings disposed between two adjacent source contact structures 107 (see FIG. 10 ).
- the process for forming the source contact structures 107 comprises forming a plurality of slits 108 extending along the Y direction and vertically passing through the silicon-containing layers 102 , 112 , 122 , 132 and 142 and the insulating layer 103 are formed to expose a portion of the substrate 101 by anisotropic etching process 108 simultaneous to the process for forming the opening 105 .
- a dielectric layer 107 a is formed on the sidewalls of the slits 108 and conductive material, such as poly-silicon, is then fulfilled in the openings 108 , whereby a plurality of source contact structures 107 extending along the Y direction and vertically passing through the silicon-containing layers 102 , 112 , 122 , 132 and 142 and the insulating layer 103 as well as electrically connected to the substrate 101 are formed in the opening 108 .
- FIG. 1D is a naval view illustrating the results after a plurality of SSLs 106 are formed on the structure depicted in FIG. 1B .
- FIG. 1E is a plan view illustrated in accordance with the structure depicted in FIG. 1D .
- the process for patterning the uppermost silicon-containing layer 102 comprises steps of forming a plurality of trenches 111 to divide the silicon-containing layer 102 into several parts serving as the SSLs 106 .
- Each of the SSLs 106 is corresponding to and electrically connected to some of the plurality of strings 104 .
- the strings 104 are arranged as a matrix array, and each of the SSLs 106 is corresponding to and electrically connected to 5-10 rows of the plurality of strings 104 .
- the strings 104 are arranged as a honeycomb array, and each of the SSLs 106 is corresponding to and electrically connected to 4-20 rows of the plurality of strings 104 .
- the strings 104 are arranged as a honeycomb array, and each of the SSLs 106 is corresponding to and electrically connected to 4 rows of the plurality of strings 104 . Since these memory cells formed on the strings 104 can be accessed at the same time by one of the same SSL 106 , thus the operation speed of the memory device 100 can be increased.
- the gates of memory cells formed on the SSLs 106 are made of silicon-containing material rather than metal. Space conserved between the SSLs 106 for forming trenches allowing metal gates formed there though is thus no more necessary. As a result, bandwidth of the SSL's 106 can be increased, the power compulsion of the memory device 100 can be reduced, and the interference between the selected memory cells and unselected cells can be reduced during the read/program operation.
- FIG. 1F is a naval view illustrating the results after plural sets of the multi-plugs structure 110 and contact via 114 are formed on the structure depicted in FIG. 1D .
- FIG. 1G is a plan view illustrated in accordance with the structure depicted in FIG. 1F .
- each set of the multi-plugs structure 110 has a plurality of plugs, such as the plugs 110 a , 110 b , 110 c and 110 d , and each of the plugs 110 a , 110 b , 110 c and 110 d is corresponding to and electrically connected with one of the silicon-containing layers 112 , 122 , 132 or 142 .
- the plug 110 a is corresponding to and electrically connected with the silicon-containing layer 112 ; the plug 110 b is corresponding to and electrically connected with the silicon-containing layer 122 ; the plug 110 c is corresponding to and electrically connected with the silicon-containing layer 132 ; and the plug 110 d is corresponding to and electrically connected with the silicon-containing layer 142 .
- the plugs 110 a , 110 b , 110 c and 110 d involved in the same set of the multi-plugs structure 110 are arranged along the Y direction to form a straight staircase parallel to the Y axle.
- the type of the straight staircase depicted in FIGS. 1F and 1G are just illustrative but not limited.
- the plugs 110 a , 110 b , 110 c and 110 d involved in the same set of multi-plugs structure 110 may be divided into several groups, such as 2 groups, and the plugs included in different groups may be arranged along the Y direction to form two straight staircases parallel to the Y axle (see FIG. 3 ).
- the distance D 1 between two adjacent sets of the multi-plugs structure 110 may substantially range from 50 ⁇ m to 500 ⁇ m, and preferably may be about 100 ⁇ m.
- Two adjacent source contact structures 107 are also separated for a certain distance determined in accordance with the resistance of the portion of the substrate 101 measured between the two adjacent sets of the multi-plugs structure 110 and the desired operating performance of the VC 3D NAND flash memory device 100 .
- each two adjacent source contact structures 107 are separated by a distance D 2 substantially greater than or equal to 20 ⁇ m.
- the predetermined distance either between each two adjacent sets of the multi-plugs structure 110 or between each two adjacent source contact structures 107 depicted in the aforementioned embodiments is substantially the same, which means that one set of multi-plugs structure 110 is formed accompanying with one source contact structures 107 .
- the predetermined distance either between each two adjacent sets of the multi-plugs structure 110 or between each two adjacent source contact structures 107 may vary respectively. In other words, the distance between two adjacent sets of multi-plugs structure 110 may be different from the distance separated between two adjacent source contact structures 107 .
- there are a plurality source contact structures 107 are disposed between two adjacent sets of the multi-plugs structure 110 .
- FIG. 1H is a plan view illustrating the results after a plurality of source lines and bit lines are formed on the structure depicted in FIG. 1G .
- the source lines 118 and the bit lines 116 are parallel to each other and both are perpendicular to the SSLs 106 .
- the source lines 118 and the bit lines 116 may be either formed on the same metal interconnection layer or formed on different metal interconnection layers.
- FIG. 4A is a cross-sectional view taken along a line S 1 depicted in FIG. 1H ;
- FIG. 4B is a cross-sectional view taken along a line S 2 depicted in FIG. 1H .
- the source lines 118 and the bit lines 116 are formed on the same metal interconnection layer M 1 .
- Each of the bit lines 116 is electrically connected to the corresponding strings 104 through at least one metal interconnection layer and at least one via 119 formed between the metal interconnection layer M 1 and the strings 104 .
- FIG. 5 is a cross-sectional view illustrating another connection type of a grounding (GND) layer, a plurality source contact structures and a source lines in accordance with another embodiment of the present invention.
- GND grounding
- FIG. 5 the structure depicted in FIG. 5 is identical to that depicted in FIG. 4B except that FIG. 5 shows an additional GND layer 301 disposed between the substrate 101 and the silicon-containing layer 142 , wherein the strings 104 are connected to the source lines 118 through the GND layer 301 and the source contact structures 107 , and there are two insulating layers 303 respectively disposed between the substrate 101 and the GND layer 301 and disposed between the GND layer 301 and the silicon-containing layer 142 .
- a plurality of metal strapped word lines such as the metal strapped word lines 117 a , 117 b , 117 c and 117 d , are formed on the plurality sets of multi-plugs structure 110 and the bit lines 116 .
- Each of the metal strapped word lines 117 a , 117 b , 117 c or 117 d extends along the X direction and electrically connected to a plurality of plugs 110 a , 110 b , 110 c or 110 d that are electrically connected to the identical silicon-containing layer 112 , 122 , 132 or 142 .
- a plurality of metal wires 113 used to connected to the contact via 114 may be formed simultaneous to the process for forming the metal strapped word lines 117 a , 117 b , 117 c and 117 d.
- FIG. 1I is a plan view illustrating the results after a plurality of metal strapped word lines 117 a , 117 b , 117 c or 117 d and the metal wires 113 are formed on the structure depicted in FIG. 1I .
- the metal strapped word line 117 a is electrically connected with the plurality of the plugs 110 a that are disposed in different sets of the multi-plugs structure 110 but electrically connected to the identical silicon-containing layer 112 ;
- the metal strapped word lines 117 b is electrically connected with the plurality of the plugs 110 b that are disposed in different sets of the multi-plugs structure 110 but electrically connected to the identical silicon-containing layer 122 ;
- the metal strapped word lines 117 c is electrically connected with the plurality of the plugs 110 c that are disposed in different sets of the multi-plugs structure 110 but electrically connected to the identical silicon-containing layer 132 ;
- the metal strapped word lines 117 d is electrically connected with the plurality of the plugs 110 d that are disposed in different sets of the multi-plugs structure 110 but electrically connected to the identical silicon-containing layer 142 .
- the plurality of the plugs 110 a , 110 b , 110 c and 110 d involved in the same set of the multi-plugs structure 110 are arranged in series in accordance with the step high of the straight staircase, and each of which is corresponding to and electrically connected to one of the metal strapped word lines 117 a , 117 b , 117 c and 117 d that are also arranged in series in accordance with the locations thereof.
- the plugs 110 a is corresponding to and electrically connected to the metal strapped word lines 117 a ; the plugs 110 b is corresponding to and electrically connected to the metal strapped word lines 117 b ; the plugs 110 c is corresponding to and electrically connected to the metal strapped word lines 117 c ; and the plugs 110 c is corresponding to and electrically connected to the metal strapped word lines 117 c .
- the arrangements (or locations) of the plugs 110 a , 110 b , 110 c and 110 d involved in the same set of the multi-plugs structure 110 are corresponding to the arrangements (or locations) of the metal strapped word lines 117 a , 117 b , 117 c and 117 d .
- the distances between each two adjacent plugs 110 a , 110 b , 110 c and 110 d may be equal due to the equal pitches between each two adjacent metal strapped word lines 117 a , 117 b , 117 c and 117 d.
- FIG. 6A is a cross-sectional view taken along a line S 3 depicted in FIG. 1I ;
- FIG. 6B is a cross-sectional view taken along a line S 4 depicted in FIG. 1I .
- sine the plurality of metal strapped word lines 117 a , 117 b , 117 c or 117 d and the metal wires 113 extend along the same direction are formed on the same metal interconnection layer M 2 with a staggered arrangement, thus pitches between each two adjacent metal strapped word lines 117 a , 117 b , 117 c and 117 d are not equal.
- the distance P 1 between the two adjacent plugs 110 b , and 110 c involved in the same set of the multi-plugs structure 110 may be greater than the distance P 2 between the two adjacent plugs 110 a , and 110 b as well as greater than the distance P 3 between the two adjacent plugs 110 c , and 110 d , in order to prevent the plugs 110 a , 110 b , 110 c and 110 d form making an undesired contacts with the metal wires 113 , wherein the distance P 2 is equal to the distance P 3 .
- N there are at least N different distances between each two adjacent plugs 110 a , 110 b , 110 c and 110 d , wherein N is equal to the number of the metal wires 113 each of which is electrically connected to one of the SSLs 106 through a contact via 114 .
- the VC 3D NAND flash memory device 100 may be then formed after series downstream processes are carried out. Since the silicon-containing layers 112 , 122 , 132 and 142 serving as the gates of the memory device 100 are electrically connected with the plugs 110 a , 110 b , 110 c and 110 d as well as the metal strapped word lines 117 a , 117 b , 117 c and 117 d , thus the resistance of the silicon-containing layers 112 , 122 , 132 and 142 can be reduced, and the parasitic RC time delays caused by the resistance and capacitance of the gate can be avoided.
- the resistance of the silicon-containing layers 112 , 122 , 132 and 142 can be reduced to an equivalent resistance of a metal gate. Accordingly, by applying the approach of the present invention, the prior drawbacks and problems of sacrifice layer residue and over etch resulted from the metal gate process can be also avoided. In addition, because the etch trenches formed in the multi-layer stack structure used for removing the sacrifice layer is no more necessary, the distance between two adjacent SSLs can be thus decreased, and the bandwidth of the SSLs can be increased to contain more memory cells. As a result, the memory density of the VC 3D NAND flash memory device 100 can be increased.
- FIG. 7 is a plan view illustrating a partial structure of a VC 3D NAND flash memory device 200 in accordance with another embodiment of the present invention.
- the structure of the VC 3D NAND flash memory device 200 is similar to that of the VC 3D NAND flash memory device 100 except that the VC 3D NAND flash memory device 200 comprises more sets of multi-plugs structure 110 and more source contact structures 107 . From a macro perspective, these sets of multi-plugs structure 110 may overlaps with a plurality of SSLs 106 , whereby each of the SSLs 106 is divided into a plurality of areas A. In the present embodiment, each of the SSLs 106 is divided into 10 to 100 areas A.
- each area A has a contact via 114 formed thereon used to connect to a decoder (not shown) through a metal wire 113 .
- a decoder not shown
- some elements, such as the metal strapped word lines 117 a , 117 b , 117 c and 117 d and the source lines 118 are not be shown in the FIG. 5 . Persons with skill in the art could image and understand the intact arrangements of the memory device 200 in accordance with the detailed description and accompanying drawings.
- a memory device and a method for fabricating the same are provided.
- Plural sets of multi-plugs structure are formed in a multi-layer stack structure of a memory device including a plurality of silicon-containing layers, and the plural sets of multi-plugs structure are arranged along an extending direction of the SSLs that are formed on the multi-layer stack structure and electrically connected to a plurality of strings vertically passing through the multi-layer stack structure, so as to make some of the plurality of the strings disposed between two adjacent sets of the multi-plugs structure.
- Each set of the multi-plugs structure has a plurality of plugs, and each of the plugs is corresponding to and electrically connected with one of the silicon-containing layers.
- the plugs that are electrically connected to the identical silicon-containing layer are electrically connected to a metal strapped word line.
- the gate resistance of the memory device can be significantly reduced, and the problems due to the parasitic RC time delays caused by the gate resistance and capacitance of the memory device can be avoided.
- the memory device adopts a silicon based gate instead of a metal gate, thus the process for fabricating a metal gate is no longer required. As a result, the bandwidth of the SSLs can be increased and the problems of defect memory cells and poor yield due to the metal gate process can be also avoided.
- the memory device further comprises a plurality of source contact structures formed in the multi-layer stack structure and arranged along the extending direction of the SSLs, so as to make some of the plurality of the strings disposed between two adjacent source contact structures, wherein each of the source contact structures extends passing through the silicon-containing layers, so as to electrically connected with the substrate (GND layer).
- the source resistance of the memory device can be significantly reduced, and the problems due to the parasitic RC time delays caused by the resistance and capacitance of the source lines can be avoided.
Abstract
Description
- 1. Technical Field
- The disclosure in generally relates to a semiconductor device and a method for fabricating the same, and more particularly to a memory device and a method for fabricating the same.
- 2. Description of the Related Art
- Non-volatile memory (NVM) which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell has been widespreadly adopted by bulk solid state memory applications in portable audiovisual entertainment devices, cell phones or digital cameras etc. Recently, various three dimensional (3D) memory devices, such as a 3D flash memory device having a single gate, a double gate or a surrounding gate, has been provided in order to accommodate the rising demand for superior memory.
- A 3D memory device, such as a vertical-channel (VC) 3D NAND flash memory device that has a multi-layer stack structure may possess a higher density memory and excellent electrical characteristics, e.g. reliability in data storage and high operating speed. As semiconductor features shrink in size and pitch, the parasitic resistance-capacitance (RC) time delays caused by the resistance and capacitance of interconnect conductive lines, such as the word lines or the source lines, may reversely affect the operating speed and reliability of the VC 3D flash memory device. In order to solve these problems, a VC 3D flash memory device with metal gate has been provided.
- However, there are still some problems in applying a VC 3D NAND flash memory device with a metal gate. During the process foe fabricating the VC 3D flash memory device, etch trenches passing through a multi-layer stack structure of the VC 3D NAND flash memory device for performing an etching process to remove sacrifice layers and allowing metal gates (word lines) formed on the position where the sacrifice layers originally disposed may be required. However, the etch trenches may occupy space of the multi-layer stack structure and exclude the forming of memory cells. The memory storage density of the VC 3D NAND flash memory device may thus be reduced. Furthermore, the residue of the sacrifice layers may remained in the multi-layer stack structure after the etching process for removing the sacrifice layers is carried out, or otherwise the memory layers could be damaged by over etch while the residue is thoroughly removed by a more aggressive etching process. As a result, defect memory cells may occur and the yield of the VC 3D NAND flash memory device may be also reduced.
- Therefore, there is a need of providing an improved memory device and a method for fabricating the same to obviate the drawbacks encountered from the prior art.
- One aspect of the present invention is to provide a memory device, wherein the memory device comprises a plurality of silicon-containing layers, a plurality of string select lines (SSLs), a plurality of strings, a plurality of bit line, plural sets of multi-plugs structure and a plurality of metal strapped word lines. The silicon-containing layers are parallel to each other and vertically stacked at a substrate. The SSLs are disposed on the silicon-containing layers and extend along a first direction. The strings are perpendicular to the silicon-containing layers and the SSLs and electrically connected to the SSLs. The bit lines are disposed on the SSLs extending along a second direction and electrically connected to the strings. The plural sets of multi-plugs structure are arranged along the first direction, so as to make the strings disposed between two adjacent sets of multi-plugs structure. Each set of the multi-plugs structure has a plurality of plugs, and each of the plugs is corresponding to and electrically connected with one of the silicon-containing layers. The metal strapped word lines extend along the first direction, and each of the metal strapped word lines is electrically connected to the plugs that are electrically connected to the identical silicon-containing layer.
- According to another aspect of the present invention, a method for fabricating a memory device is provided, wherein the method comprises steps as follows: Firstly, a plurality of silicon-containing layers parallel to each other are formed and vertically stacked at a substrate. A plurality of strings are then formed vertically passing through the silicon-containing layers. Next, a plurality of SSLs extending a long a first direction are formed on the silicon-containing layers and electrically connected to the strings. Subsequently, plural sets of multi-plugs structure are formed and arranged along the first direction, so as to make the strings disposed between two adjacent sets of multi-plugs structure, wherein each set of the multi-plugs structure has a plurality of plugs, and each of the plugs is corresponding to and electrically connected with one of the silicon-containing layers. Thereafter, a plurality of bit lines are formed on the SSLs extending along a second direction and electrically connected to the strings. A plurality of metal strapped word lines extending along the first direction are then formed on the plural sets of multi-plugs structure, wherein each of the metal strapped word lines is electrically connected the plugs that are electrically connected to the identical silicon-containing layer.
- In accordance with the aforementioned embodiments of the present invention, a memory device and a method for fabricating the same are provided. Plural sets of multi-plugs structure are formed in a multi-layer stack structure of a memory device including a plurality of silicon-containing layers, and the plural sets of multi-plugs structure are arranged along an extending direction of the SSLs that are formed on the multi-layer stack structure and electrically connected to a plurality of strings vertically passing through the multi-layer stack structure, so as to make some of the plurality of the strings disposed between two adjacent sets of the multi-plugs structure. Each set of the multi-plugs structure has a plurality of plugs, and each of the plugs is corresponding to and electrically connected with one of the silicon-containing layers. The plugs that are electrically connected to the identical silicon-containing layer are electrically connected to a metal strapped word line. By these approaches, the gate resistance of the memory device can be significantly reduced, and the problems due to the parasitic RC time delays caused by the gate resistance and capacitance of the memory device can be avoided. In addition, since the memory device adopts a silicon based gate instead of a metal gate, thus the process for fabricating a metal gate is no longer required. As a result, the bandwidth of the SSLs can be increased and the problems of defect memory cells and poor yield due to the metal gate process can be also avoided.
- The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
-
FIG. 1A is a perspectival view illustrating a partial structure of a multi-layer stack structure formed on a substrate in accordance with one embodiment of the present invention; -
FIG. 1B is a perspectival view illustrating the results after a plurality of strings are formed on the structure depicted inFIG. 1A ; -
FIG. 10 is a plan view illustrated in accordance with the structure depicted inFIG. 1B ; -
FIG. 1D is a perspectival view illustrating the results after a plurality of SSLs are formed on the structure depicted inFIG. 1B ; -
FIG. 1E is a plan view illustrated in accordance with the structure depicted inFIG. 1D ; -
FIG. 1F is a perspectival view illustrating the results after plural sets of multi-plugs structure and a plurality contact vias are formed on the structure depicted inFIG. 1D ; -
FIG. 1G is a plan view illustrated in accordance with the structure depicted inFIG. 1F ; -
FIG. 1H is a plan view illustrating the results after a plurality of source lines and bit lines are formed on the structure depicted inFIG. 1G ; -
FIG. 1I is a plan view illustrating the results after a plurality of metal strapped word lines are formed on the structure depicted inFIG. 1I ; -
FIGS. 2A to 2D are cross-sectional views illustrating a method for fabricating the strings in accordance with one embodiment of the present invention; -
FIG. 3 is a perspectival view illustrating a multi-plugs structure shaped in another type of staircase in accordance with another embodiment of the present invention; -
FIG. 4A is a cross-sectional view taken along a line S1 depicted inFIG. 1H ; -
FIG. 4B is a cross-sectional view taken along a line S2 depicted inFIG. 1H ; -
FIG. 5 is a cross-sectional view illustrating another connection type of a grounding (GND) layer, a plurality source contact structures and a source lines in accordance with another embodiment of the present invention; -
FIG. 6A is a cross-sectional view taken along a line S3 depicted inFIG. 1I ; -
FIG. 6B is a cross-sectional view taken along a line S4 depicted inFIG. 1I ; -
FIG. 7 is a plan view illustrating a partial structure of a VC 3D NAND flash memory device in accordance with another embodiment of the present invention. - The embodiments as illustrated below provide a VC 3D NAND
flash memory device 100 and a method for fabricating the same to avoid the problems due to the parasitic RC time delays of the memory device. The present invention will now be described more specifically with reference to the following embodiments illustrating the structure and method for fabricating the memory device. - It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for the purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed. Also, it is also important to point out that there may be other features, elements, steps and parameters for implementing the embodiments of the present disclosure which are not specifically illustrated. Thus, the specification and the drawings are to be regard as an illustrative sense rather than a restrictive sense. Various modifications and similar arrangements may be provided by the persons skilled in the art within the spirit and scope of the present invention. In addition, the illustrations may not be necessarily be drawn to scale, and the identical elements of the embodiments are designated with the same reference numerals.
- The method for fabricating a VC 3D NAND
flash memory device 100 comprises steps as follows: Amulti-layer stack structure 10 is firstly provided.FIG. 1A is a perspectival view illustrating amulti-layer stack structure 10 formed on asubstrate 101 in accordance with one embodiment of the present invention. In the present embodiment, themulti-layer stack structure 10 comprises a plurality of silicon-containinglayers layers 103 alternatively vertically stacked along a Z direction and parallel to each other. - In some embodiments of the present invention, the silicon-containing
layers layers 103 are preferable made of silicon oxide. It should be appreciated that although themulti-layer stack structure 10 depicted inFIG. 1A merely comprises 5 silicon-containing layers and 4 insulating layers, it is just illustrative but not used to limit the number of the silicon-containing layers and the insulating layers that are applied in other embodiments of the present invention. - Next, a plurality of
strings 104 vertically passing through the silicon-containinglayers layers 103 are formed.FIG. 1B is a perspectival view illustrating the results after a plurality ofstrings 104 are formed on the structure depicted inFIG. 1A .FIG. 1C is a plan view illustrated in accordance with the structure depicted inFIG. 1B . - In some embodiments of the present invention, each of the
strings 104 has amemory layer 104 a and achannel layer 104 b. Thememory layer 104 a can be an NON structure made of a silicon nitride layer, a silicon oxide layer and a silicon nitride layer. Thechannel layer 104 b preferably consists of poly-silicon. A plurality of memory cells arranged in rows and columns can be defined at the intersections of thestrings 104 and the silicon-containinglayers - For example, in some embodiments of the present invention, the memory cells can be arranged as a matrix array. Yet in some other embodiments, the memory cells can be arranged as a honeycomb array. However, the arrangements of the memory cells are not limited. Any suitable arrangements for the design rule of a 3D memory device may be encompassed within the spirit and scope of the present invention.
-
FIGS. 2A to 2D are cross-sectional views illustrating a method for fabricating thestrings 104 in accordance with one embodiment of the present invention. The process for forming thestrings 104 comprises steps as follows: Firstly, a plurality ofopenings 105 passing though the silicon-containinglayers layer 103 are formed to expose a portion of the substrate 101 (seeFIG. 2A ). Subsequently, thememory layer 104 a is deposited on the sidewalls and the bottom of theopenings 105 and thechannel layer 104 b is then formed on thememory layer 104 a by depositing semiconductor material, such as poly-silicon or germanium (Ge), meanwhile to form the plurality ofstrings 104 on the sidewalls of the openings 105 (seeFIG. 2B ). - A
hard mask layer 109 is next deposited on thechannel layer 104 b (seeFIG. 2C ); and an anisotropic etching process is performed to removing thehard mask layer 109 as well as portions of thememory layer 104 a and thechannel layer 104 b to expose a portion of thesubstrate 101 from theopenings 105. Thereafter, a plurality ofsource 115 are formed on the exposed portions of thesubstrate 101, so as to electrically connect the plurality ofstrings 104 with thesubstrate 101 serving as a GND layer of the VC 3D NAND flash memory device 100 (seeFIG. 2D ). - In addition, a plurality of
source contact structures 107 are also formed in themulti-layer stack structure 10 during the process for forming thestrings 104, wherein thesource contact structures 107 are arranged along a X direction, so as to make the strings disposed between two adjacent source contact structures 107 (seeFIG. 10 ). - In some embodiments of the present invention, the process for forming the
source contact structures 107 comprises forming a plurality ofslits 108 extending along the Y direction and vertically passing through the silicon-containinglayers layer 103 are formed to expose a portion of thesubstrate 101 byanisotropic etching process 108 simultaneous to the process for forming theopening 105. Subsequently, adielectric layer 107 a is formed on the sidewalls of theslits 108 and conductive material, such as poly-silicon, is then fulfilled in theopenings 108, whereby a plurality ofsource contact structures 107 extending along the Y direction and vertically passing through the silicon-containinglayers layer 103 as well as electrically connected to thesubstrate 101 are formed in theopening 108. - Next, the uppermost silicon-containing
layer 102 is patterned to form a plurality ofSSLs 106 extending along the X direction.FIG. 1D is a perspectival view illustrating the results after a plurality ofSSLs 106 are formed on the structure depicted inFIG. 1B .FIG. 1E is a plan view illustrated in accordance with the structure depicted inFIG. 1D . In some embodiments of the present invention, the process for patterning the uppermost silicon-containinglayer 102 comprises steps of forming a plurality oftrenches 111 to divide the silicon-containinglayer 102 into several parts serving as theSSLs 106. - Each of the
SSLs 106 is corresponding to and electrically connected to some of the plurality ofstrings 104. For example, in some embodiments of the present invention, thestrings 104 are arranged as a matrix array, and each of theSSLs 106 is corresponding to and electrically connected to 5-10 rows of the plurality ofstrings 104. Alternatively, in some other embodiments, thestrings 104 are arranged as a honeycomb array, and each of theSSLs 106 is corresponding to and electrically connected to 4-20 rows of the plurality ofstrings 104. - For purposes of making a clearer description, in the present embodiment, the
strings 104 are arranged as a honeycomb array, and each of theSSLs 106 is corresponding to and electrically connected to 4 rows of the plurality ofstrings 104. Since these memory cells formed on thestrings 104 can be accessed at the same time by one of thesame SSL 106, thus the operation speed of thememory device 100 can be increased. In addition the, because the gates of memory cells formed on theSSLs 106 are made of silicon-containing material rather than metal. Space conserved between theSSLs 106 for forming trenches allowing metal gates formed there though is thus no more necessary. As a result, bandwidth of the SSL's 106 can be increased, the power compulsion of thememory device 100 can be reduced, and the interference between the selected memory cells and unselected cells can be reduced during the read/program operation. - Thereafter, plural sets of the
multi-plugs structure 110 arranged along the X direction are formed in themulti-layer stack structure 10, so as to make thestrings 104 disposed between two adjacent sets of themulti-plugs structure 110. In addition, a contact via 114 may be formed on each of theSSLs 106 simultaneous to the process for forming the plural sets of themulti-plugs structure 110.FIG. 1F is a perspectival view illustrating the results after plural sets of themulti-plugs structure 110 and contact via 114 are formed on the structure depicted inFIG. 1D .FIG. 1G is a plan view illustrated in accordance with the structure depicted inFIG. 1F . - In the present embodiment, each set of the
multi-plugs structure 110 has a plurality of plugs, such as theplugs plugs layers plug 110 a is corresponding to and electrically connected with the silicon-containinglayer 112; theplug 110 b is corresponding to and electrically connected with the silicon-containinglayer 122; theplug 110 c is corresponding to and electrically connected with the silicon-containinglayer 132; and theplug 110 d is corresponding to and electrically connected with the silicon-containinglayer 142. Theplugs multi-plugs structure 110 are arranged along the Y direction to form a straight staircase parallel to the Y axle. However, the type of the straight staircase depicted inFIGS. 1F and 1G are just illustrative but not limited. In some other embodiments, theplugs multi-plugs structure 110 may be divided into several groups, such as 2 groups, and the plugs included in different groups may be arranged along the Y direction to form two straight staircases parallel to the Y axle (seeFIG. 3 ). - It should be appreciated that two adjacent sets of the
multi-plugs structure 110 are separated for a certain distance, and the distance is determined in accordance with the resistance of the portion of the silicon-containinglayers multi-plugs structure 110 and the desired operating performance of the VC 3D NANDflash memory device 100. In some embodiments of the present invention, the distance D1 between two adjacent sets of themulti-plugs structure 110 may substantially range from 50 μm to 500 μm, and preferably may be about 100 μm. - Two adjacent
source contact structures 107 are also separated for a certain distance determined in accordance with the resistance of the portion of thesubstrate 101 measured between the two adjacent sets of themulti-plugs structure 110 and the desired operating performance of the VC 3D NANDflash memory device 100. In some embodiments of the present invention each two adjacentsource contact structures 107 are separated by a distance D2 substantially greater than or equal to 20 μm. - Although the predetermined distance either between each two adjacent sets of the
multi-plugs structure 110 or between each two adjacentsource contact structures 107 depicted in the aforementioned embodiments is substantially the same, which means that one set ofmulti-plugs structure 110 is formed accompanying with onesource contact structures 107. But it is worthy to known that the arrangements of the plural sets of themulti-plugs structure 110 and thesource contact structures 107 are just illustrative, for the purpose of making a concise description. The predetermined distance either between each two adjacent sets of themulti-plugs structure 110 or between each two adjacentsource contact structures 107 may vary respectively. In other words, the distance between two adjacent sets ofmulti-plugs structure 110 may be different from the distance separated between two adjacentsource contact structures 107. In one embodiment, there are a pluralitysource contact structures 107 are disposed between two adjacent sets of themulti-plugs structure 110. - Subsequent, a plurality of
source lines 118 are formed on thesource contact structures 107 extending along the Y direction, and electrically connected to thesource contact structures 107 respectively. A plurality ofbit lines 116 are formed on theSSLs 106 extending along the Y direction, wherein each of the bit lines 116 is electrically connected to the one of thestrings 104 that are connected to thesame SSL 106.FIG. 1H is a plan view illustrating the results after a plurality of source lines and bit lines are formed on the structure depicted inFIG. 1G . In the present embodiment, the source lines 118 and thebit lines 116 are parallel to each other and both are perpendicular to theSSLs 106. - In some embodiments of the present invention, the source lines 118 and the
bit lines 116 may be either formed on the same metal interconnection layer or formed on different metal interconnection layers.FIG. 4A is a cross-sectional view taken along a line S1 depicted inFIG. 1H ;FIG. 4B is a cross-sectional view taken along a line S2 depicted inFIG. 1H . In the present embodiment, the source lines 118 and thebit lines 116 are formed on the same metal interconnection layer M1. Each of the bit lines 116 is electrically connected to thecorresponding strings 104 through at least one metal interconnection layer and at least one via 119 formed between the metal interconnection layer M1 and thestrings 104. - In addition, although the
substrate 101 illustrated in the aforementioned embodiments may serve as a GND layer, and thestrings 104 are connected to the source lines 118 through thesubstrate 101 and thesource contact structures 107, but the source connection of the VC 3D NANDflash memory device 100 are not limited. For example,FIG. 5 is a cross-sectional view illustrating another connection type of a grounding (GND) layer, a plurality source contact structures and a source lines in accordance with another embodiment of the present invention. - In the present embodiment, the structure depicted in
FIG. 5 is identical to that depicted inFIG. 4B except thatFIG. 5 shows anadditional GND layer 301 disposed between thesubstrate 101 and the silicon-containinglayer 142, wherein thestrings 104 are connected to the source lines 118 through theGND layer 301 and thesource contact structures 107, and there are two insulatinglayers 303 respectively disposed between thesubstrate 101 and theGND layer 301 and disposed between theGND layer 301 and the silicon-containinglayer 142. - Thereafter, a plurality of metal strapped word lines, such as the metal strapped
word lines multi-plugs structure 110 and the bit lines 116. Each of the metal strappedword lines plugs layer metal wires 113 used to connected to the contact via 114 may be formed simultaneous to the process for forming the metal strappedword lines -
FIG. 1I is a plan view illustrating the results after a plurality of metal strappedword lines metal wires 113 are formed on the structure depicted inFIG. 1I . In the present embodiment, the metal strappedword line 117 a is electrically connected with the plurality of theplugs 110 a that are disposed in different sets of themulti-plugs structure 110 but electrically connected to the identical silicon-containinglayer 112; the metal strappedword lines 117 b is electrically connected with the plurality of theplugs 110 b that are disposed in different sets of themulti-plugs structure 110 but electrically connected to the identical silicon-containinglayer 122; the metal strappedword lines 117 c is electrically connected with the plurality of theplugs 110 c that are disposed in different sets of themulti-plugs structure 110 but electrically connected to the identical silicon-containinglayer 132; and the metal strappedword lines 117 d is electrically connected with the plurality of theplugs 110 d that are disposed in different sets of themulti-plugs structure 110 but electrically connected to the identical silicon-containinglayer 142. - The plurality of the
plugs multi-plugs structure 110 are arranged in series in accordance with the step high of the straight staircase, and each of which is corresponding to and electrically connected to one of the metal strappedword lines plugs 110 a is corresponding to and electrically connected to the metal strappedword lines 117 a; theplugs 110 b is corresponding to and electrically connected to the metal strappedword lines 117 b; theplugs 110 c is corresponding to and electrically connected to the metal strappedword lines 117 c; and theplugs 110 c is corresponding to and electrically connected to the metal strappedword lines 117 c. Accordingly, it can be appreciated that the arrangements (or locations) of theplugs multi-plugs structure 110 are corresponding to the arrangements (or locations) of the metal strappedword lines adjacent plugs word lines - However, in some other embodiments the distances between each two
adjacent plugs FIG. 6A is a cross-sectional view taken along a line S3 depicted inFIG. 1I ;FIG. 6B is a cross-sectional view taken along a line S4 depicted inFIG. 1I . In the present embodiment, sine the plurality of metal strappedword lines metal wires 113 extend along the same direction are formed on the same metal interconnection layer M2 with a staggered arrangement, thus pitches between each two adjacent metal strappedword lines - Accordingly, in the present embodiment, the distance P1 between the two
adjacent plugs multi-plugs structure 110 may be greater than the distance P2 between the twoadjacent plugs adjacent plugs plugs metal wires 113, wherein the distance P2 is equal to the distance P3. - In some embodiments of the present invention, there are at least N different distances between each two
adjacent plugs metal wires 113 each of which is electrically connected to one of theSSLs 106 through a contact via 114. - The VC 3D NAND
flash memory device 100 may be then formed after series downstream processes are carried out. Since the silicon-containinglayers memory device 100 are electrically connected with theplugs word lines layers layers flash memory device 100 can be increased. -
FIG. 7 is a plan view illustrating a partial structure of a VC 3D NAND flash memory device 200 in accordance with another embodiment of the present invention. The structure of the VC 3D NAND flash memory device 200 is similar to that of the VC 3D NANDflash memory device 100 except that the VC 3D NAND flash memory device 200 comprises more sets ofmulti-plugs structure 110 and moresource contact structures 107. From a macro perspective, these sets ofmulti-plugs structure 110 may overlaps with a plurality ofSSLs 106, whereby each of theSSLs 106 is divided into a plurality of areas A. In the present embodiment, each of theSSLs 106 is divided into 10 to 100 areas A. In addition, each area A has a contact via 114 formed thereon used to connect to a decoder (not shown) through ametal wire 113. For the purpose of making a clear description, some elements, such as the metal strappedword lines FIG. 5 . Persons with skill in the art could image and understand the intact arrangements of the memory device 200 in accordance with the detailed description and accompanying drawings. - In accordance with the aforementioned embodiments of the present invention, a memory device and a method for fabricating the same are provided. Plural sets of multi-plugs structure are formed in a multi-layer stack structure of a memory device including a plurality of silicon-containing layers, and the plural sets of multi-plugs structure are arranged along an extending direction of the SSLs that are formed on the multi-layer stack structure and electrically connected to a plurality of strings vertically passing through the multi-layer stack structure, so as to make some of the plurality of the strings disposed between two adjacent sets of the multi-plugs structure. Each set of the multi-plugs structure has a plurality of plugs, and each of the plugs is corresponding to and electrically connected with one of the silicon-containing layers. The plugs that are electrically connected to the identical silicon-containing layer are electrically connected to a metal strapped word line. By these approaches, the gate resistance of the memory device can be significantly reduced, and the problems due to the parasitic RC time delays caused by the gate resistance and capacitance of the memory device can be avoided. In addition, since the memory device adopts a silicon based gate instead of a metal gate, thus the process for fabricating a metal gate is no longer required. As a result, the bandwidth of the SSLs can be increased and the problems of defect memory cells and poor yield due to the metal gate process can be also avoided.
- In some embodiments of the present invention, the memory device further comprises a plurality of source contact structures formed in the multi-layer stack structure and arranged along the extending direction of the SSLs, so as to make some of the plurality of the strings disposed between two adjacent source contact structures, wherein each of the source contact structures extends passing through the silicon-containing layers, so as to electrically connected with the substrate (GND layer). By these approaches, the source resistance of the memory device can be significantly reduced, and the problems due to the parasitic RC time delays caused by the resistance and capacitance of the source lines can be avoided.
- While the disclosure has been described by way of example and in terms of the exemplary embodiment(s), it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
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JP2022535517A (en) * | 2019-08-30 | 2022-08-09 | 長江存儲科技有限責任公司 | Three-dimensional memory device with source contacts connected by adhesion layers and method for forming the same |
JP7330301B2 (en) | 2019-08-30 | 2023-08-21 | 長江存儲科技有限責任公司 | Three-dimensional memory device with source contacts connected by adhesion layers and method for forming same |
US11758723B2 (en) | 2019-08-30 | 2023-09-12 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device with source contacts connected by an adhesion layer and methods for forming the same |
WO2022163992A1 (en) * | 2021-01-28 | 2022-08-04 | 한양대학교 산학협력단 | Method for manufacturing step areas of plurality of word lines in 3d flash memory |
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