JP2010056443A - Nonvolatile semiconductor memory and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the degradation of element characteristics by disposing a terminal of a direction (x) of a source line contact on a dummy active region and by avoiding alignment displacement to the direction (x) of the source line contact. <P>SOLUTION: A nonvolatile semiconductor memory includes: a plurality of first active regions (AA) that are disposed along with the direction (x) in a memory cell array 100 and provided with a smaller dimension than a processing limit by exposure; a memory cell unit, provided in each of the plurality of the active regions AA having a memory cell (MC) and selection transistor (STS) to which a current path is connected in series along with a direction (y); and a straight line contact (LI) that is connected to an end of the memory cell unit and extended to the direction (x). In the memory, a region (SA) on which the straight line contact (LI) is disposed is a semiconductor region to which the plurality of the first active regions (AA) are connected by a second active region, and a bottom surface of the straight line contact (LI) is flat. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory and a manufacturing method thereof, and more particularly to a structure of a flash memory and a manufacturing method thereof.

A nonvolatile semiconductor memory, for example, a flash memory, is mounted on various electronic devices as a storage device.
Since the flash memory is required to have an increased storage capacity, miniaturization of the element size is being promoted. In recent years, for example, a sidewall processing technique has been proposed in order to realize a dimension smaller than the processing limit dimension of lithography (exposure) (see, for example, Patent Document 1).

  The storage capacity is also increased by devising the layout and structure of the wiring of the flash memory. As an example of this, there is a contact shape for connecting a memory cell or a memory cell unit including a plurality of memory cells to a source line. In the flash memory, when considering its operation, the source lines connected to the memory cells (memory cell units) are collectively controlled by a plurality of memory cells arranged side by side in the extending direction of the source lines. So you can share. Therefore, in the flash memory, a line-shaped contact that can be shared by a plurality of memory cells is used. By adopting such a line-shaped (referred to as LI structure) contact, the size of the contact can be reduced.

  When the active region is formed in the memory cell array using the above sidewall processing technique, the memory cell array has the active region and the element isolation region (element isolation insulating film) alternately arranged in the extending direction of the LI structure contact. It becomes the structure made. In this case, the contact bottom portion of the LI structure is in contact with the active region and the element isolation insulating film.

  When forming a trench on the line for embedding the contact in the interlayer insulating film on the active region and on the element isolation insulating film to form the LI structure contact, the upper surface of the active region and the upper surface of the element isolation insulating film are interlayer insulating The film is exposed to etching conditions. At this time, the element isolation insulating film often cannot ensure a sufficiently large etching selection ratio as compared with the active region with respect to the etching condition of the interlayer insulating film, and etching occurs in the element isolation insulating film. The upper end of the isolation insulating film falls closer to the semiconductor substrate than the upper end of the active region.

For this reason, the surface of the semiconductor substrate in the contact region has an uneven structure, and the contact bottom portion of the LI structure is in contact with not only the upper surface of the active region but also the side surface of the active region.
As a result, the withstand voltage of the element isolation insulating film is lowered, and element characteristics are deteriorated such as an increase in leakage current.
JP 2006-156657 A

  The present invention proposes a technique for suppressing deterioration of element characteristics.

  A non-volatile semiconductor memory according to an example of the present invention includes a memory cell array provided in a semiconductor substrate, and a plurality of second semiconductor elements arranged in the memory cell array along the first direction and having a size smaller than a processing limit by exposure. A memory cell unit comprising: one active region; a memory cell provided in each of the plurality of active regions; a memory cell having a current path connected in series along a second direction intersecting the first direction; and a selection transistor; A linear contact connected to one end of the cell unit and extending in the first direction, and the region in which the linear contact is provided is defined by a plurality of second active regions. It is one semiconductor region to which the region is connected, and the bottom surface of the linear contact is flat.

  A method of manufacturing a nonvolatile semiconductor memory according to an example of the present invention includes a step of forming a mask layer above the semiconductor substrate, and arranged in a first direction on the mask layer and orthogonal to the first direction. A step of forming a plurality of line-shaped core materials extending in the second direction, and after making the line width of the plurality of core materials smaller than a processing limit dimension by exposure, on each side surface of these core materials A step of forming a sidewall mask, and a step of forming a first resist mask extending in the first direction and covering the upper portion of the contact region after removing the core material on the mask layer and the plurality of sidewall masks And a step of patterning the mask layer using the sidewall mask and the first resist mask, and being arranged in the first direction in the semiconductor substrate using the patterned mask layer as a mask. And a plurality of active regions having a smaller line width than the processing limit dimension by exposure, and forming a contact region extending in the first direction to be shared by the plurality of active regions.

  According to the present invention, deterioration of element characteristics can be suppressed.

  Hereinafter, embodiments for carrying out examples of the present invention will be described in detail with reference to the drawings.

1. Overview
The nonvolatile semiconductor memory according to the embodiment of the present invention relates to a flash memory, for example. In the flash memory according to the embodiment of the present invention, the plurality of active regions arranged side by side in the first direction in the memory cell array are formed using a sidewall processing technique. Therefore, the dimension of the active region in the first direction is smaller than the processing limit dimension (minimum processing dimension) by exposure.

  Each of the plurality of active regions is provided with a memory cell unit, and a source line contact is connected to one end (source side) of the memory cell unit. This source line contact is, for example, a line-shaped (LI structure) contact extending in the first direction. In the region where the source line contact is provided (source line contact region), no element isolation insulating film is provided, and the source line contact region extends in the first direction.

  Thus, in the present embodiment, the source line contact region is one semiconductor region shared by a plurality of active regions arranged in the first direction, and the bottom of the source line contact provided in this region is flat. It is characterized by becoming.

  In the flash memory according to the embodiment of the present invention, in the manufacturing method of the active region using the sidewall mask, the upper portion of the source line contact region is covered with the resist mask, and the semiconductor substrate in the region is not etched by the sidewall mask pattern. Like that. As a result, the source line contact region becomes one semiconductor substrate region that is not separated by the element isolation region, and is shared by a plurality of active regions arranged along the first direction. Since the source line contact is formed on the semiconductor substrate region where the element isolation insulating film is not provided, the source line contact forming region can ensure flatness even if it is exposed to the etching conditions for the interlayer insulating film. Since the source line contact of the LI structure to be formed can be formed on a contact region having a flat surface, the bottom surface of the contact becomes flat.

  As described above, according to the embodiment of the present invention, it is possible to suppress the deterioration of the element characteristics of the flash memory.

2. Embodiment
The first to third embodiments of the present invention will be described with reference to FIGS.

(1) First embodiment
(A) Structure
The overall configuration of the nonvolatile semiconductor memory according to the embodiment of the present invention will be described with reference to FIG. In the present embodiment, a flash memory will be described as an example of a nonvolatile semiconductor memory.

  FIG. 1 is a schematic diagram showing a configuration of a flash memory. As shown in FIG. 1, the flash memory includes a memory cell array 100 and peripheral circuits that control the operation of the memory cell array 100, such as a word line / select gate line driver 120, a sense amplifier circuit 110, and a control circuit 130. Yes.

  FIG. 2 is a plan view showing an example of the structure of the memory cell array 100.

  As shown in FIG. 2, the memory cell array 100 extends in the y direction (first direction) and has a plurality of active areas (first active areas) AA arranged along the x direction (second direction). It has. An element isolation region STI is provided between two active areas AA adjacent in the x direction, and the element isolation region STI electrically isolates the active areas AA adjacent in the x direction. The active area AA is formed by using, for example, a sidewall processing technique capable of forming a dimension smaller than a processing limit dimension by exposure. Therefore, the dimension (line width) in the x direction of the active area AA is smaller than the minimum processing dimension F (feature size) which is a processing limit dimension by exposure.

  In the memory cell array 100, dummy active areas DAA are provided adjacent to one end and the other end in the x direction of the plurality of active areas AA. The dimension in the x direction of the dummy active area AA is equal to or larger than the dimension in the x direction of the active area AA, and is about 3F, for example.

A plurality of word lines WL and select gate lines SGS, SGD extending in the x direction are provided on the active area AA. A plurality of bit lines (not shown) extending in the y direction are provided above the active area AA.
In the active area AA, a memory cell unit (not shown) including a plurality of memory cells and current selection transistors connected in series is provided. The memory cell and the select transistor are arranged in the active area AA extending in the y direction along the y direction (first direction). Memory cells are provided at the intersections between the word lines WL and the active areas AA. The selection transistors are provided at the intersections of the select gate lines SGD, SGS and the active area AA, respectively.

  Further, a dummy line DCG is provided at the end in the y direction in the memory cell array 100 adjacent to the select gate lines SGD and SGS and the word line WL arranged side by side in the y direction.

  When the flash memory is, for example, a NAND flash memory, the memory cell array 100 includes a plurality (in this example, n) of blocks BLOCK1 to BLOCKn. Blocks BLOCK1 to BLOCKn are arranged side by side in the y direction. One block BLOCK1 to BLOCKn is composed of a plurality of memory cell units arranged in the x direction. In the NAND flash memory, the blocks BLOCK1 to BLOCKn mean the minimum unit of erasure, that is, the minimum number of memory cells that can be erased at one time.

  FIG. 3 shows an equivalent circuit of two blocks BLOCKi and BLOCK (i + 1) adjacent to each other in the memory cell array 100.

  As shown in FIG. 3, a memory cell unit (hereinafter referred to as a NAND cell unit) of a NAND flash memory has a plurality of stack gate structure MIS (Metal-Insulator-Semiconductor) transistors as memory cells MC. The drain is shared and connected in series. A word line WL extending in the x direction is connected to the gate of the memory cell MC.

In addition, select transistors STS and STD connect memory cells MC and source / drains to one end (source side) and the other end (drain side) of a plurality of memory cells MC (hereinafter referred to as NAND strings) connected in series. Shared and connected in series.
A drain-side select gate line SGDL extending in the x direction is connected to the gate of a select transistor (hereinafter referred to as a drain-side select transistor) STD connected to the drain side of the NAND string. A bit line BL extending in the y direction is connected to the drain of the drain side select transistor STD. The bit line BL is shared by two blocks BLOCKi and BLOCK (i + 1) adjacent in the y direction.

  A source-side select gate line SGSL extending in the x direction is connected to the gate of a select transistor (hereinafter referred to as source-side select transistor) STS connected to the source side of the NAND string. A source line SL is connected to the source of the source side select transistor STS. The source line SL is shared by two blocks BLOCKi and BLOCK (i + 1) adjacent in the y direction, and is shared by a plurality of NAND cell units arranged along the x direction.

  A bit line contact (not shown) is used to electrically connect the bit line BL and the NAND cell unit, and the bit line contact is provided in a predetermined area in the active area AA shown in FIG. . Further, in order to electrically connect the source line SL and the NAND cell unit, a source line contact is used, and the source line contact is provided in a predetermined area in the active area AA shown in FIG. Hereinafter, the structure of the portion corresponding to the regions IV and VIII surrounded by the broken lines in FIG. 3 will be described in detail with reference to FIGS.

  A plane and a cross-sectional structure of a portion corresponding to the region IV shown in FIG. 3 will be described with reference to FIGS. FIG. 4 shows a planar structure corresponding to the region IV of FIG. FIG. 5 shows a cross-sectional structure taken along line VV in FIG. 6 shows a cross-sectional structure taken along line VI-VI in FIG. 4, and FIG. 7 shows a cross-sectional structure taken along line VII-VII in FIG. The locations of the memory cell array shown in FIGS. 4 to 7 show an example of the configuration on the drain side of the NAND cell unit.

  As shown in FIGS. 4 to 7, the surface of the semiconductor substrate 1 in the memory cell array is composed of an active area AA and an element isolation area STI. The active area AA is formed by using a sidewall processing technique, and the dimension (line width) in the x direction is smaller than the processing limit dimension (minimum processing dimension) by exposure.

  In this active area AA, a memory cell MC and a drain side select transistor STD are arranged. An element isolation insulating film 9 is buried in the element isolation region STI.

  The memory cell MC is a MIS transistor having a stack gate structure as described above. That is, the memory cell MC has a structure in which the control gate electrode 5A is stacked on the floating gate electrode 3A.

  The floating gate electrode 3A is provided on a gate insulating film (tunnel insulating film) 2A on the surface of the semiconductor substrate 1 (active region). The floating gate electrode 3A functions as a charge storage layer that holds data (electrons). For example, a polysilicon film is used for the floating gate electrode 3A.

The control gate electrode 5A is provided on the floating gate electrode 3A via the inter-gate insulating film 4A. The control gate electrode 5A functions as a word line WL and is shared by a plurality of memory cells MC arranged in the x direction. The control gate electrode 5A covers the upper surface and side surfaces of the floating gate electrode 3A. As a result, the coupling ratio of the memory cell MC is improved. For example, a silicide film containing any one of nickel (Ni), cobalt (Co), titanium (Ti), and the like is used for the control gate electrode 5A. However, the control gate electrode 5A may have a single layer structure of a polysilicon film or a polycide structure in which a silicide film is stacked on the polysilicon film.
For example, an ONO (Oxide-Nitride-Oxide) film or a high dielectric insulating film made of an oxide such as hafnium (Hf) or aluminum (Al) is used for the inter-gate insulating film 4A.

  In the embodiment of the present invention, a memory cell using the floating gate electrode 3A as a charge storage layer will be described as an example, but the present invention is not limited to this. For example, it is a matter of course that the memory cell may have a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure using an insulating film such as a silicon nitride film as a charge storage layer.

  In the semiconductor substrate 1, a diffusion layer 6A (hereinafter referred to as a source / drain diffusion layer) functioning as a source / drain region of the memory cell MC is provided. A plurality of memory cells MC constituting one NAND string (NAND cell unit) share these source / drain diffusion layers 6A, so that current paths are connected in series.

  The drain side select transistor STD provided on the drain side of the NAND string is formed simultaneously with the memory cell MC. Therefore, the select transistor STD also has a stack gate structure like the memory cell MC. However, in the select transistor STD, the inter-gate insulating film 4B has an opening, and the lower gate electrode 3B and the upper gate electrode 5A are directly connected via the opening. The lower gate electrode 3B on the gate insulating film 2B is made of the same material as the floating gate electrode 3A, and the upper gate electrode 5A is made of the same material as the control gate electrode 5B. The gate electrodes 3B and 5B of the drain side select transistor STD are shared by a plurality of drain side select transistors STD arranged side by side in the x direction, and function as the drain side select gate line SGDL.

  The drain side select transistor STD shares one of the source / drain diffusion layers 6A and 6D with the adjacent memory cell MC. A bit line BL extending in the y direction is connected to the source / drain diffusion layer 6D on the other side (drain side) of the drain side select transistor STD.

  The bit line BL and the source / drain diffusion layer 6D pass through the bit line contact BC provided on the source / drain diffusion layer 6D, the metal wiring layer M0 and the via contact V1 provided in the interlayer insulating film 11. And connected. Thus, the bit line contact BC is arranged on the drain side of one NAND cell unit in the active area AA. The area of the active area AA in which the bit line contact is disposed is hereinafter referred to as a bit line contact area. The bit line BL is provided in a groove formed in the interlayer insulating film 12.

In the NAND flash memory, data transfer to one NAND cell unit is executed in bit line units. Therefore, the bit line contact region in the active area AA is isolated in the x direction by the element isolation insulating film 9 as in the NAND cell unit (memory cell MC). That is, the bit line contact BC is provided in each of the bit line contact areas (active areas AA) as independent circular (ellipse) or prismatic contact plugs. However, the bit line contact BC is shared by two NAND cell units adjacent in the y direction, and one bit line contact BC is used for the two NAND cell units.
Further, when the active region is formed using the sidewall processing technique as in the present embodiment, the interval in the x direction is small. Therefore, in order to avoid a short circuit between the bit line contacts BC adjacent in the x direction, the bit line contact BC has an active region as a bit line contact region by a layout in which the locations of the contacts BC are alternately shifted in the y direction. Arranged in AA.

  A plane and a cross-sectional structure of a portion corresponding to the region VIII shown in FIG. 3 will be described with reference to FIGS. FIG. 8 shows a planar structure corresponding to the region VIII of FIG. FIG. 9 shows a cross-sectional structure taken along line IX-IX in FIG. FIG. 10 shows a cross-sectional structure taken along line XX of FIG. The locations of the memory cell array shown in FIGS. 8 to 10 show the configuration of the source side of the NAND cell unit. The same members as those shown in FIGS. 4 to 7 are denoted by the same reference numerals, and description thereof will be made as necessary.

  Similarly to the drain side selection transistor STD, the source side selection transistor STS provided on the source side of the NAND string is formed at the same time as the memory cell MC. Therefore, the gate electrodes 3B and 5B of the selection transistor STS are formed between the intergate insulating films 4B. The lower gate electrode 3B and the upper electrode 5A are directly connected to each other through the opening. The gate electrodes 3B and 5B of the source side select transistor STS are shared by a plurality of source side select transistors STS arranged in the x direction and function as the source side select gate line SGSL.

  The source side select transistor STS shares one of the source / drain diffusion layers 6A, 6S with the memory cell MC. Also, a source line contact LI is provided on the other (source side) source / drain diffusion layer 6S of the source side select transistor STS. The source line contact LI is embedded in the trench Z of the interlayer insulating film 10. One end of the memory cell unit is connected to the source line SL extending in the x direction via the contact LI. The source line contact LI has a line-like structure extending in the x direction, which is called an LI structure. Hereinafter, a region in the source / drain diffusion layer 6S where the source line contact is disposed is also referred to as a source line contact region SA.

  The source line contact region SA (source / drain diffusion layer 6S of the source side select transistor STS) in the active region AA is formed by the active region (second active region) that connects the plurality of active regions AA adjacent in the x direction. The source / drain diffusion layer 6S and the source line contact LI having the LI structure are shared by a plurality of active regions AA adjacent in the x direction. Yes. The second active region is a semiconductor region located between the element isolation regions STI adjacent in the y direction in the source line contact region SA.

Thus, since the source line contact region SA becomes one connected region that is not separated by the element isolation insulating film 9, the source line contact LI is formed on the source / drain diffusion layer 6C having a flat surface. Therefore, the bottom surface of the source line contact LI is flat.
The source / drain diffusion layer 6S and the source line contact SC having the LI structure are shared by two adjacent blocks BLOCKi and BLOCK (i + 1).

  Thus, unlike the bit line contact region and the bit line contact BC, the source line contact region SA and the source line contact LI are shared by a plurality of active regions AA (NAND cell units) arranged along the x direction. This is because the source line SL is collectively controlled for one block BLOCKi.

  FIG. 11 shows a planar structure of the end of the memory cell array in the y direction. As shown in FIG. 11, the end portion of the source line contact LI in the x direction is provided in the dummy active area AA. In the dummy active area DAA, the dimension in the x direction is larger than the dimension in the x direction of the active area AA, but the structure in the y direction of the dummy active area DAA is almost the same as the structure in the y direction of the active area AA. It is. That is, in the dummy active area DAA, elements having the same structure as the memory cell MC are formed, but these elements do not function as dummy elements and as storage elements.

  A nonvolatile semiconductor memory according to a first embodiment of the present invention is a flash memory in which a memory cell unit is provided in an active region having a dimension smaller than a minimum processing dimension F by a sidewall processing technique. The line-shaped (LI structure) source line contact LI extending in the x direction is connected to the memory cell unit.

  In the flash memory according to the first embodiment of the present invention, the region SA where the line-shaped source line contact LI is arranged is formed by a plurality of active regions (second active regions) provided in the region SA. It is one semiconductor region to which a plurality of active regions (first active regions) AA provided side by side in the x direction are connected, and the bottom of the source line contact LI of the LI structure has a flat structure. Features.

  Thus, the source line contact region SA of this embodiment is not isolated by the element isolation region (element isolation insulating film). That is, the source line contact region SA is one connected semiconductor region (diffusion layer), and the element isolation insulating film 9 is not provided in the source line contact region SA.

  Therefore, in this embodiment, when the interlayer insulating film 10 is etched during the source line contact LI formation step, the element isolation insulating film is etched even if the surface of the source line contact region SA is exposed under the etching conditions. It won't get thinner. Further, the etching does not cause the upper end of the element isolation insulating film 9 to recede toward the semiconductor substrate from the upper end of the active area AA, and the side surface of the active area AA is not exposed.

  Therefore, in the present embodiment, the surface of the source line contact region LI is flat, and the source line contact LI having the LI structure extending in the x direction can be provided on the source line contact region SA having a flat surface. . That is, the bottom surface of the source line contact LI is flat, and the bottom portion of the source line contact LI having the LI structure does not contact the side surface of the active area AA.

  Further, since the element isolation film 9 is not provided in the source line contact region SA, the source line contact LI having the LI structure extending in the x direction and the element isolation insulating film 9 do not cross each other.

  As described above, in the flash memory according to the present embodiment, the breakdown voltage of the element isolation insulating film does not decrease and no leak current occurs.

  Furthermore, the end portion in the x direction of the source line contact LI is provided in the dummy active area AA, so that misalignment of the source line contact LI with respect to the x direction can be avoided. This is because the dimension of the dummy active area DAA in the x direction is larger than the dimension of the active area AA in the x direction.

  Therefore, according to the nonvolatile semiconductor memory according to the first embodiment of the present invention, it is possible to suppress deterioration of element characteristics.

(B) Manufacturing method
A manufacturing process of the nonvolatile semiconductor memory (flash memory) according to the first embodiment of the present invention will be described with reference to FIGS.

  First, a process of manufacturing the flash memory according to the present embodiment will be described with reference to FIGS. FIG. 12 schematically shows a planar structure of the entire memory cell array. 13 schematically shows a cross-sectional structure taken along line XIII-XIII in FIG. 12, and FIG. 14 schematically shows a cross-sectional structure taken along line XIV-XIV in FIG.

  As shown in FIGS. 12 to 14, the insulating film 2 is formed on the surface of the semiconductor substrate 1 on which the well region (not shown) is formed by using, for example, a thermal oxidation method. Then, a polysilicon film 3 is formed on the insulating film 2 by using, for example, a CVD (Chemical Vapor Deposition) method. The formed insulating film 2 becomes a tunnel insulating film of the memory cell and a gate insulating film of the selection transistor. Further, the polysilicon film 3 becomes a floating gate electrode of the memory cell. When the memory cell has a MONOS structure, an insulating film such as a silicon nitride film is formed instead of the polysilicon film 3.

Subsequently, a first mask layer 40 (for example, a silicon nitride film) is deposited on the polysilicon film 3 by using, for example, a CVD method. A line-shaped core material 41 extending in the y direction (second direction) is formed on the mask layer 40 by using, for example, a CVD method, a photolithography technique, a RIE (Reactive Ion Etching) method, or the like. . A plurality of core members 41 are formed on the mask layer 40, and these core members 41 are provided side by side along the x direction with an interval of a processing limit dimension (minimum processing dimension) F, for example. The material used for the core material 41 is, for example, a material that is different from the mask layer and can sufficiently ensure the etching selectivity between the core material and the mask layer.
Then, the core material 41 is subjected to a slimming process using etching. By this slimming process, the dimension (line width) W1 of the core material 41 in the x direction is determined from the processing limit dimension (minimum processing dimension) F (broken line in FIG. 13) by the photolithography (exposure) technique. Is also set to a small dimension (line width) W1.

  One process of the manufacturing process of the flash memory according to this embodiment will be described with reference to FIGS. FIG. 15 schematically shows a planar structure of the entire memory cell array. 15 schematically shows a cross-sectional structure taken along line XVI-XVI in FIG. 16, and FIG. 17 schematically shows a cross-sectional structure taken along line XVII-XVII in FIG.

As shown in FIGS. 15 to 17, a mask material is formed on the first mask layer 40 and the core material 41. Then, the mask material is left in a self-aligned manner only on the side surface of the core material by, for example, anisotropic etching such as RIE. As a result, a loop-shaped side wall mask 43 surrounding the core material 41 is formed. The dimension (line width) W2 in the x direction of the side wall mask 43 is smaller than the minimum processing dimension F.
The material (mask material) used for the sidewall mask 43 is a material different from the first mask layer 40 and the core material 41, and has a sufficient etching selectivity with respect to the first mask layer 40 and the core material 41. Materials that can be secured are used. As an example of these combinations, when a silicon nitride film is used for the first mask layer 40, for example, a polysilicon film is used for the core material 41, and for example, a silicon oxide film is used for the sidewall mask 43. Used.

  Here, when the dimension (interval) of the space portion where the core material 41 and the side wall mask 43 are not provided is W3, these dimensions W1, W2, and W3 preferably have a relationship of W1 = W2 = W3. In this case, the relationship with the processing limit dimension (minimum processing dimension) F is W1 = W2 = W3 = (1/2) F.

  One process of the manufacturing process of the flash memory according to this embodiment will be described with reference to FIGS. FIG. 18 schematically shows a planar structure of the entire memory cell array. FIG. 19 schematically shows a cross-sectional structure taken along line XIX-XIX in FIG. 18, and FIG. 20 schematically shows a cross-sectional structure taken along line XX-XX in FIG. FIG. 21 schematically shows a cross-sectional structure taken along line XXI-XXI in FIG.

  As shown in FIGS. 18 to 21, the core material 41 is selectively removed, and only the sidewall mask 43 remains. Then, for example, the end portion (loop portion) in the y direction of the sidewall mask 43 is removed by etching, so that a linear sidewall mask 43 extending in the y direction is formed. In this manner, removing the loop portion of the loop-shaped side wall mask and forming the independent line-shaped side wall mask 43 is hereinafter referred to as a loop cut.

As a result, a plurality of line-shaped side wall masks 43 are arranged on the first mask layer 40 side by side in the x direction. The semiconductor substrate 1 below the sidewall mask 43 becomes an active region having a dimension (line width) W2 smaller than the minimum processing dimension F by a process described later.
Further, for example, the dummy active area DAA having a size larger than the size of the active region in the x direction is provided at one end and the other end in the x direction in the memory cell array 100. Therefore, as shown in FIG. The core material 41 provided at one end and the other end in the x direction may be left without being removed.
Thus, by using the core material 41 and the side wall masks 43 formed on both side surfaces thereof as one mask 45, the dummy active area DAA can be formed in the semiconductor substrate 1 below the mask 45.

  One process of the manufacturing process of the flash memory according to this embodiment will be described with reference to FIGS. FIG. 22 schematically shows a planar structure of the entire memory cell array. FIG. 23 is a plan view in which a part XXIII in the memory cell array is extracted. 24 shows a cross-sectional structure taken along line XXIV-XXIV in FIG. 23, and FIG. 25 shows a cross-sectional structure taken along line XXV-XXV in FIG. FIG. 26 shows a cross-sectional structure taken along line XXVI-XXVI in FIG.

  As shown in FIGS. 22 to 26, for example, a plurality of line-shaped resist masks 47 extending in the x direction intersect with the sidewall masks 43 extending in the y direction in the memory cell array 100. The first mask layer 40 and the sidewall mask 43 are formed. This resist mass 47 covers, for example, between the two source line side select gate line formation scheduled regions SGSL in the memory cell array 100 as shown in FIG. 23, more specifically, above the source line contact region SA. Formed respectively. At this time, a resist mask is not formed between the bit line side select gate line formation regions, more specifically, above the bit line contact region.

  That is, in one block forming region where a plurality of active regions are formed, a linear resist mask 47 extending in the x direction (first direction) above one end (source line contact region SA) of the block forming region. Is formed. On the other hand, no resist mask is formed above the other end (bit line contact region) of one block formation region.

An end portion in the x direction of the resist mask 47 is located on the mask 45, for example. The dimension (line width) in the y direction of the resist mask 47 is, for example, not less than the minimum processing dimension F. However, the resist mask 47 may be subjected to a slimming process so as to have a dimension (line width) smaller than the minimum processing dimension F.
In the memory cell array 100, the portion where the resist mask 47 is not formed has the same structure as that shown in FIGS.

  One process of the manufacturing process of the flash memory according to this embodiment will be described with reference to FIGS. FIG. 27 is a diagram schematically showing a planar structure showing a part of the memory cell array, and shows a region corresponding to FIG. 28 shows a cross-sectional structure taken along line XXVIII-XXVIII in FIG. 27, and FIG. 29 shows a cross-sectional structure taken along line XXIX-XXIX in FIG. 30 shows a sectional structure taken along line XXX-XXX in FIG. 27, and FIG. 31 shows a sectional structure taken along line XXXI-XXXI in FIG. FIG. 33 is a sectional process diagram corresponding to FIG.

  Based on the sidewall mask 43 and the resist mask 47 shown in FIGS. 22 to 26, the first mask layer 40 is etched using, for example, the RIE method. After the etching, the sidewall mask 43 and the resist mask 47 are removed. Accordingly, the mask pattern based on the sidewall mask 43 and the resist mask 47 is transferred to the first mask layers 40A and 40B.

  As shown in FIGS. 27 to 32, in the patterned first mask layers 40A and 40B, a portion 40A extending in the y direction is a portion to which the pattern of the sidewall mask is transferred. The dimension is substantially the same as the dimension W2.

  In the patterned first mask layers 40A and 40B, the portion 40B extending in the x direction is a portion to which the pattern of the resist mask is transferred. The first mask layer 40B covers the source line contact region SA. The dimension in the y direction of the first mask layer 40B is, for example, a dimension equal to or larger than the minimum processing dimension F.

  FIG. 32 shows a cross section in the vicinity of the dummy active area DAA along the x direction. In this region, the pattern composed of the core material and the side wall masks on both side surfaces thereof is transferred to the first mask layer 40C, and below this mask 40C is a dummy active region. The dimension of the mask layer 40C in the x direction is the sum of the dimension 2 × W2 of the two sidewall masks and the dimension W1 of the core material.

  The loop cut performed in the process described with reference to FIGS. 18 to 21 is not performed on the sidewall mask in the process, and the pattern of the loop-shaped sidewall mask is transferred to the first mask layer 40. Thereafter, in this step (FIGS. 27 to 32), the first mask layers 40A and 4B may be subjected to loop cut.

  One process of the manufacturing process of the flash memory according to this embodiment will be described with reference to FIGS. FIG. 33 schematically shows a planar structure of a part of the memory cell array and corresponds to FIG. 34 shows a cross-sectional structure taken along line XXXIV-XXXIV in FIG. 33, and FIG. 35 shows a cross-sectional structure taken along line XXXV-XXXV in FIG. FIG. 36 is a sectional process diagram corresponding to FIG.

  As shown in FIGS. 33 to 36, the polysilicon film 3 and the semiconductor substrate 1 are etched using the patterned first mask layers 40A and 40B as a mask, and a trench T is formed in the semiconductor substrate 1.

  When the polysilicon film 3 and the semiconductor substrate 1 are etched using the sidewall processing technique, the trench T has a structure in which shallow grooves and deep grooves are alternately arranged in the semiconductor substrate 1. Many. This is because the shape of the upper portion of the sidewall mask 43 is asymmetrical, the processing variation of the core material in the photolithography process / slimming process described with reference to FIGS. Occurs due to dimensional variations.

  Then, the element isolation insulating film 9 is embedded in the formed trench T. Thereafter, for example, the upper surface of the element isolation insulating film 9 is etched, and the upper end of the element isolation insulating film 9 is retracted to the semiconductor substrate 1 side from the upper end of the polysilicon film 3.

  As a result, an active region AA sandwiched between two element isolation regions STI (element isolation insulating film 9) arranged in the x direction is formed in the semiconductor substrate 1. Since the active area AA is formed using the mask layer 40A having the line width W2 smaller than the minimum processing dimension F as described in the process shown in FIG. 29, the active area AA has a dimension smaller than the minimum processing dimension F. ing.

Here, since the surface of the source line contact region SA is covered with the mask layer 40B during the trench formation process of the present embodiment, no trench is formed in the source line contact region SA.
Therefore, the source line contact region SA at one end of the memory cell unit formation region (active region AA) is not separated by the element isolation insulating film 9, but becomes one semiconductor region extending in the x direction, and in the x direction. It is commonly connected to one end of a plurality of adjacent active areas AA. The bit line contact region as the other end of the active region AA is isolated by the element isolation insulating film 9.

  At the same time, at the end in the x direction in the memory cell array, a dummy active area DAA is formed in the semiconductor substrate 1 using the mask layer 40C as a mask, as shown in FIG. As described above, in this embodiment, the active area AA and the dummy active area DAA having different dimensions (line widths) can be simultaneously formed, and the manufacturing process can be simplified.

  One process of the manufacturing process of the flash memory according to this embodiment will be described with reference to FIGS. FIG. 37 schematically shows a planar structure of a part of the memory cell array and corresponds to FIG. 38 shows a cross-sectional structure taken along line XXXVIII-XXXVIII in FIG. 37, and FIG. 39 shows a cross-sectional structure taken along line XLIX-XLIX in FIG. FIG. 40 shows a cross-sectional structure taken along line XL-XL in FIG.

  After the first mask layers 40A and 40B shown in FIGS. 33 to 36 are removed, an inter-gate insulating film material and a polysilicon film (control gate electrode material) are formed on the polysilicon film 3, for example, by CVD. It is formed sequentially using the method.

  Then, for example, the second mask layer 50 is formed on the polysilicon films 5A and 5B by a process substantially similar to the process shown in FIGS. 12 to 21, and a core material (not shown) is formed on the second mask layer 50. And the side wall mask 53 is formed. Then, for example, gate processing of the memory cell MC is performed using a sidewall processing technique using the sidewall mask 53 as a mask. As a result, a stack gate structure composed of the floating gate electrode 3A and the control gate electrode 5A is formed below the sidewall mask 53.

  In addition, since the dimension in the y direction of the gate electrode of the select transistor STS is larger than the dimension in the y direction of the gate electrode of the memory cell MC, for example, by an exposure technique using a resist mask 57 as shown in FIG. Gate electrodes 3B and 5B may be formed. However, the present invention is not limited to this, and the gate processing of the selection transistor may be performed using a sidewall processing technique. When the sidewall processing technique is used, for example, in substantially the same manner as the formation process of the dummy active area DAA, the core material in the selection transistor formation area is not removed but left on the second mask layer 50, and the core material and its side surface are left. Gate processing of the select transistor is performed using the side wall formed in (1) as one mask.

  After the gate processing, the source / drain diffusion layers 6A and 6S of the memory cell and the selection transistor are formed in the semiconductor substrate 1 (active area AA) using the formed gate electrodes 5A and 5B as a mask. As described above, since the source line contact region SA extends in the x direction, the source / drain diffusion layer 6S of the source side select transistor STS is composed of a plurality of source side select transistors STS adjacent in the x direction. Shared. This source / drain diffusion layer 6S is also shared by two select transistors STS adjacent in the y direction.

  After the masks 50, 53, and 57 used for gate processing are removed, as shown in FIGS. 4 to 11, formation of the interlayer insulating film 10 and silicidation of the control gate electrode (word line) are well-known techniques. It is executed using

  A line-shaped groove Z extending in the x direction is formed in the interlayer insulating film 10 on the source line contact region SA. A plug material such as tungsten (W) or molybdenum (Mo) is buried in the groove Z, and a line-shaped (LI structure) source line contact LI is formed on the source / drain diffusion layer 6S. In the present embodiment, the element isolation insulating film 9 is not formed in the source line contact region SA, which is a single semiconductor region (source / drain diffusion layer 6S).

  Therefore, when the trench Z is formed in the interlayer insulating film 10, even if the surface of the source line contact region SA is exposed to the etching conditions of the interlayer insulating film 10, the source / drain diffusion layer 6S as the source line contact region SA is formed. Flatness is ensured. Therefore, the bottom surface of the source line contact LI formed on the source / drain diffusion layer 6S is flat.

  The bit line contact BC is formed in the interlayer insulating film 10 in each of the active areas AA (bit line contact areas) separated by the element isolation insulating film 9 simultaneously with the source line contact LI in the source line contact forming process. The connection is made via the contact hole formed in However, since the bit line contact BC has a different shape from the source line contact LI, the bit line contact BC may be formed in a separate process from the source line contact LI.

  Then, a first metal wiring layer M0 is formed on the interlayer insulating film 10. The metal wiring layer M0 connected to the source line contact LI functions as the source line SL. The metal wiring layer M0 connected to the bit line contact BC functions as an intermediate layer for the bit line formed in a later process. An interlayer insulating film 11 is formed on the metal wiring layer M0 and the interlayer insulating film 10.

  Thereafter, the interlayer insulating film 12 and the bit line BL are formed. In the bit line BL formation process, for example, a sidewall processing technique is used as in the formation process of the active region and the word line (control gate electrode). However, when the sidewall processing technique is used for the bit line BL formation process, unlike the active region formation process and the word line formation process, the trench extending in the y direction in the interlayer insulating film 12 using the sidewall mask as a mask. Is formed. Then, the bit line BL is formed by using a damascene technique in which a metal material is embedded in the formed groove. Note that the bit line BL may be formed by using a photolithography technique.

  Further, the via contact for connecting the bit line BL and the metal wiring layer M0 may be formed in the interlayer insulating film 11 before the interlayer insulating film 12 is deposited, or at the same time as the bit line BL is formed. Alternatively, a contact hole separately formed in the interlayer insulating film 11 may be embedded using damascene technology.

  As described above, the flash memory that is the nonvolatile semiconductor memory according to the present embodiment is manufactured.

  In the method for manufacturing the nonvolatile semiconductor memory (flash memory) according to the first embodiment of the present invention, the source region contact area SA is formed before the step of forming the active area AA using the sidewall mask 43 by the sidewall processing technique. Then, a linear resist mask 47 extending in the x direction is formed. Then, the semiconductor substrate 1 is etched using a pattern based on the sidewall mask 43 and the resist mask 47, and a plurality of active regions having dimensions smaller than the processing limit dimension by exposure are formed.

  At this time, in the portion patterned by the resist mask 47 extending in the x direction, that is, in the source line contact region SA, etching using the sidewall mask as a mask is not performed. Therefore, the trench and the element isolation insulating film 9 are not formed in the source line contact region SA, and the source line contact region SA includes a plurality of active regions (memory cell unit formation regions) AA arranged side by side in the x direction. This is one semiconductor region (diffusion layer region) that extends in the x direction and is shared by the two.

  In the present embodiment, the source line contact region SA is exposed to etching conditions for the interlayer insulating film 10 when the trench Z for embedding the source line contact having the LI structure is formed in the interlayer insulating film 10 on the source line contact region SA. However, since the element isolation insulating film is not provided in the region SA, the flatness of the surface of the source line contact region SA is ensured. As a result, the bottom surface of the source line contact LI having the LI structure becomes flat.

  As described above, in the present embodiment, in the source line contact region SA, the element isolation insulating film is etched during contact formation to reduce the film thickness, and the upper end of the element isolation insulating film is closer to the semiconductor substrate than the upper end of the active region. There is no retreat. In the present embodiment, the bottom surface of the source line contact LI having the LI structure does not contact the side surface in the x direction of the active area AA.

  Therefore, the flash memory manufactured by the above-described manufacturing method does not cause a decrease in the breakdown voltage of the element isolation insulating film or an increase in leakage current.

  Therefore, according to the method for manufacturing the nonvolatile semiconductor memory (flash memory) according to the first embodiment of the present invention, it is possible to prevent deterioration of element characteristics.

(2) Second embodiment
A nonvolatile semiconductor memory according to the second embodiment of the present invention will be described with reference to FIGS. Note that the same members as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

The difference between the present embodiment and the first embodiment is the shape of the source line contact. In the first embodiment, the line-shaped source line contact LI extending in the x direction is used.
On the other hand, in the present embodiment, the source line contacts SC are contact plugs arranged in the x direction independently of each other. For example, the source line contact SC of the present embodiment is arranged in the source line contact region SA every other active region (NAND cell unit) arranged in the x direction.

  The manufacturing method of the nonvolatile semiconductor memory (flash memory) according to the present embodiment is substantially the same as the manufacturing method described in the first embodiment. However, in the present embodiment, a line-shaped groove is not formed in the interlayer insulating film 10 on the source line contact region SA, but a contact hole is formed at a predetermined position in the source line contact region SA. Formed in each. Then, a source line contact SC is buried in this contact hole. These source line contacts SC are formed simultaneously with the bit line contact BC, for example.

Also in the present embodiment, as in the first embodiment, the source line contact region SA in which the source line contact SC is provided is one semiconductor region (source / drain diffusion layer 6S) extending in the x direction. They are connected by active areas (second active areas) arranged side by side in the x direction.
In the present embodiment, a plurality of independent source line contacts SC are provided in the source contact region SA.

  When the line-like source line contact LI is used as in the first embodiment, the bit line contact BC and the source line contact LI have different shapes, and therefore the bottom area is different. As a result, the etching rate for the interlayer insulating film 10 differs between the bit line contact side and the source line contact side, and the etching end points of the bit line contact BC and the source line contact LI with respect to the semiconductor substrate 1 are the same. It is difficult to do.

  On the other hand, if the shape of the source line contact SC is the same as the shape of the bit line contact BC as in this embodiment, the bit line contact BC and the source line contact SC are processed in the same process and the same end point. Can be processed.

In addition, when an independent contact plug is connected to each of the active regions in the active region formed using the sidewall processing technique and separated by the element isolation insulating film, the misalignment between the contact plug and the active region (contact region) When this occurs, the contact area is reduced, and the parasitic resistance of the contact portion is increased.
However, according to the present embodiment, the source line contact region SA is one semiconductor region connected by a plurality of active regions (second active regions) arranged along the x direction. Misalignment with the contact area SA does not occur. Therefore, deterioration of element characteristics due to parasitic resistance does not occur.

  Therefore, according to the second embodiment of the present invention, it is possible to suppress the deterioration of the characteristics of the nonvolatile semiconductor memory (flash memory). Furthermore, according to the nonvolatile semiconductor memory according to the second embodiment of the present invention, the manufacturing process of the nonvolatile semiconductor memory can be reduced.

(3) Third embodiment
A third embodiment of the present invention will be described with reference to FIGS. In addition, about the same member as 1st and 2nd embodiment, the same code | symbol is attached | subjected and detailed invention is abbreviate | omitted.

(A) Structure
The structure of the nonvolatile semiconductor memory (flash memory) according to the third embodiment of the present invention will be described with reference to FIGS. FIG. 44 shows the overall configuration of the memory cell array, and FIG. 45 shows a cross-sectional structure taken along line XLV-XLV in FIG. In the present embodiment, the structure of the memory cell MC and the selection transistors STS and STD and the shape of the source line contacts LI and SC are the same as those in the first or second embodiment, and thus description thereof is omitted here. .

  As in the flash memory described in the first and second embodiments, in the mask pattern in which the loop cut is performed, the end portion in the y direction of the active region is tapered or chipped, thereby generating dust. As a result, there is a problem that dust defects occur in the flash memory. Further, there is a problem that the manufacturing yield is reduced due to the dust defect.

  In order to prevent these problems, the flash memory of this embodiment is provided with extending portions 70A and 70B extending in the y direction at the end portion in the y direction of the active area AA. The extending portions 70A and 70B have a structure in which, for example, a conductive layer 3Z is formed on the semiconductor substrate 1, and the conductive layer 3Z is sandwiched between two insulating films 2Z and 4Z. Conductive layer 3Z is made of the same material as floating gate electrode 3A. The insulating film 2Z on the semiconductor substrate 1 is made of the same material as the gate insulating film 2A, and the insulating film 4Z on the conductive layer 3Z is made of the same material as the inter-gate insulating film 4A.

  As described above, by providing the extending portions 70A and 70B, the end portion in the y direction of the active region does not become an independent pattern, so that the end portion of the active region can be prevented from being tapered or chipped. Therefore, it is possible to prevent a dust defect from the end portion of the active area AA, and it is possible to suppress a decrease in manufacturing yield due to the dust defect.

  In the embodiment of the present invention, the process for forming the extending portions 70A and 70B and the process for forming the source line contact region extending in the x direction can be simultaneously performed by the manufacturing method described later.

  Note that a plurality of active areas AA adjacent in the x direction are electrically connected via the extending portions 70A and 70B. However, when the flash memory is in operation, the extending portions 70A and 70B are electrically separated from the blocks BLOCK1 to BLOCKn in which the memory cells are provided by turning the dummy line DCG off or in a floating state. The problem does not occur.

Therefore, according to the non-volatile semiconductor memory according to the third embodiment of the present invention, it is possible to suppress the deterioration of the element characteristics and the decrease in the manufacturing yield. Furthermore, according to the nonvolatile semiconductor memory according to the present embodiment, the manufacturing process can be simplified. (B) Manufacturing method
A method for manufacturing a nonvolatile semiconductor memory (flash memory) according to the third embodiment of the present invention will be described below. Note that detailed description of steps similar to those in the manufacturing method described in the first embodiment is omitted.

  A sidewall mask 43 is formed on the first mask layer 40 using a process similar to the process shown in FIGS. Then, a first resist mask 47A is formed on the first mask layer 40 and the plurality of sidewall masks 43 so as to cover the source line contact region SA.

  At the same time, in this embodiment, in addition to the resist mask 47 shown in FIG. 22 (shown as the resist mask 47A in FIG. 46), as shown in FIG. A line-shaped second resist mask 47B extending in the x direction is formed so as to cover it. At this time, the cross section along the x direction of the terminal portions in the y direction of the plurality of side wall masks 43 is the same as the cross sectional view shown in FIG.

  The resist mask 47B is patterned into a line extending in the x direction, and the line resist mask 47B extending in the x direction is a terminal portion in the y direction of the sidewall mask 43 extending in the y direction. Are formed on the first mask layer 40 and the side wall mask 43.

  An end portion in the x direction of the resist mask 47B is located on the mask 45, for example. Further, a side surface in one direction (outside of the memory cell array) in the y direction of the resist mask 47 </ b> B is, for example, substantially coincident with the end portion of the mask 45 in the y direction or positioned outside the end portion of the mask layer 45. The reason why the resist mask 47B is formed in this way is that it is possible to effectively prevent chipping at the end portion in the y direction of the active region. The dimension (line width) in the y direction of the resist mask 47B is, for example, not less than the minimum processing dimension F. However, the resist mask 47B may be subjected to a slimming process so as to have a dimension (line width) smaller than the minimum processing dimension F.

Thereafter, patterning and formation of an active region for the first mask layer 40 are performed using the same processes as those shown in FIGS.
In addition to the pattern of the sidewall mask 43 and the first resist mask 47A, the pattern of the second resist mask 47B is transferred to the first mask layer 40, and extends in the x direction at the end in the y direction in the memory cell array 100. The first mask layer remains.

  Based on the pattern of the first mask, at the same time as the formation of the active area AA and the source line contact area SA, the extension extending in the x direction at the end of the plurality of active areas provided in the memory cell array 100 in the y direction. A conductive layer 3Z to be a portion is formed.

  Thereafter, inter-gate insulating films 4A and 4B are formed by the same process as described with reference to FIGS. 37 to 40, and the insulating film 4Z made of the same material as the gate insulating film 4A is formed on the conductive layer 3Z. It is formed. As a result, extending portions 70A and 70B composed of the two insulating films 2Z and 4Z and the conductive layer 3Z are formed. Then, after depositing the control gate electrode material, gate electrodes 3A and 5A of the memory cell MC are formed by gate processing. Subsequently, a source / drain diffusion layer 6A is formed. However, in the region where the extending portions 70A and 70B are provided, the conductive material (control gate electrode material) on the extending portion 3Z is removed.

Thereafter, contacts LI, SC, BC, source line SL, and bit line BL are formed using the same processes as those shown in FIGS.
The flash memory according to this embodiment is manufactured through the above steps.

  In the present embodiment, extending portions 70A and 70B shared by a plurality of active areas AA arranged side by side in the x direction are provided at the end of the active area in the y direction. As a result, the end portion in the y direction of the active region does not form an independent pattern, so that the end portion of the active region can be prevented from being tapered or chipped, and the generation of dust can be prevented.

  Further, in the present embodiment, since the extension portion forming process can be performed simultaneously with the patterning and processing of the source line contact region, it is possible to prevent an increase in the manufacturing process.

  Therefore, according to the method for manufacturing a nonvolatile semiconductor memory (flash memory) according to the third embodiment of the present invention, it is possible to provide a nonvolatile semiconductor memory capable of preventing deterioration of element characteristics and simplify the manufacturing process. be able to.

3. Other
According to the embodiment of the present invention, it is possible to prevent deterioration of element characteristics.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the gist thereof. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

The figure which shows the whole structure of the non-volatile semiconductor memory which concerns on embodiment of this invention. The top view which shows the structure of a memory cell array typically. The equivalent circuit diagram which shows the internal structure of a memory cell array. FIG. 4 is a plan view showing a structure corresponding to a region VI in FIG. 3. Sectional drawing which shows the structure which follows the VV line | wire of FIG. Sectional drawing which shows the structure which follows the VI-VI line of FIG. Sectional drawing which shows the structure which follows the VII-VII line of FIG. FIG. 4 is a plan view showing a structure corresponding to a region VIII in FIG. 3. Sectional drawing which shows the structure which follows the IX-IX line of FIG. Sectional drawing which shows the structure which follows the XX line of FIG. The top view which shows the structure of a memory cell array edge part. The top view which shows typically 1 process of the manufacturing process of 1st Embodiment. Sectional drawing which follows the XIII-XIII line | wire of FIG. Sectional drawing which follows the XIV-XIV line | wire of FIG. The figure which shows typically the planar structure of 1 process of the manufacturing process of 1st Embodiment. Sectional drawing which follows the XVI-XVI line | wire of FIG. Sectional drawing which follows the XVII-XVII line | wire of FIG. The figure which shows typically the planar structure of 1 process of the manufacturing process of 1st Embodiment. Sectional drawing which follows the XIX-XIX line | wire of FIG. Sectional drawing which follows the XX-XX line of FIG. Sectional drawing which follows the XXI-XXI line | wire of FIG. The figure which shows typically the planar structure of 1 process of the manufacturing process of 1st Embodiment. The top view which extracted area | region XXIII of FIG. FIG. 24 is a sectional view taken along line XXIV-XXIV in FIG. 23. FIG. 24 is a sectional view taken along line XXV-XXV in FIG. 23. FIG. 23 is a sectional view taken along line XXVI-XXVI in FIG. 22. The figure which shows typically the planar structure of 1 process of the manufacturing method of 1st Embodiment. Sectional drawing which follows the XXVIII-XXVIII line | wire of FIG. FIG. 28 is a sectional view taken along line XXIX-XXIX in FIG. 27. Sectional drawing which follows the XXX-XXX line of FIG. FIG. 28 is a sectional view taken along line XXXI-XXXI in FIG. 27. Sectional drawing for demonstrating 1 process of the manufacturing method of 1st Embodiment. The top view for demonstrating one process of the manufacturing method of 1st Embodiment. Sectional drawing which follows the XXXIV-XXXIV line | wire of FIG. Sectional drawing which follows the XXXV-XXXV line | wire of FIG. Sectional drawing for demonstrating 1 process of the manufacturing method of 1st Embodiment. The top view for demonstrating one process of the manufacturing method of 1st Embodiment. Sectional drawing which follows the XXXVIII-XXXVIII line of FIG. Sectional drawing which follows the XXXIX-XXXIX line | wire of FIG. Sectional drawing which follows the XL-XL line | wire of FIG. The top view which shows the structure of the non-volatile semiconductor memory of 2nd Embodiment. FIG. 42 is a sectional view taken along line XLII-XLII in FIG. 41. FIG. 42 is a sectional view taken along line XLIII-XLIII in FIG. 41. The top view which shows the structure of the non-volatile semiconductor memory of 3rd Embodiment. Sectional drawing which follows the XLV-XLV line | wire of FIG. The top view for demonstrating one process of the manufacturing process of the non-volatile semiconductor memory of 3rd Embodiment.

Explanation of symbols

  1: semiconductor substrate, 2A: tunnel insulating film, 2B: gate insulating film, 3A: floating gate electrode, 4A: intergate insulating film, 5A: control gate electrode, 6A, 6D, 6S: source / drain diffusion layer, 3B, 5B: Gate electrode, 9: Element isolation insulating film, 10, 11, 12: Interlayer insulating film, LI, SC: Source line contact, SL: Source line, BC: Bit line contact, BL: Bit line, M0: Metal wiring Layer, V1: via contact, 40, 40A, 40B: first mask layer, 41: core material, 43, 53: sidewall mask, 47, 47A, 47B, 57: resist mask, 50: second mask layer, 70A, 70B: Extension portion, MC: Memory cell, STS, STD: Selection transistor, AA: Active region, STI: Element isolation region, SA: Source line contour Door area.

Claims (5)

A memory cell array provided in a semiconductor substrate;
A plurality of first active regions provided in the memory cell array along the first direction and having a size smaller than a processing limit by exposure;
A memory cell unit including a memory cell and a selection transistor provided in each of the plurality of active regions and having a current path connected in series along a second direction intersecting the first direction;
A linear contact connected to one end of the memory cell unit and extending in the first direction;
The region where the linear contact is provided is one semiconductor region in which the plurality of first active regions are connected by a plurality of second active regions,
The bottom surface of the linear contact is flat;
A non-volatile semiconductor memory.   2. The nonvolatile semiconductor memory according to claim 1, wherein an extension portion connected to the plurality of first active regions is provided at a terminal portion in the second direction of the plurality of first active regions. . A dummy active region provided at an end of the memory cell array in the first direction;
3. The nonvolatile semiconductor memory according to claim 1, wherein an end portion of the linear contact in the first direction is on the dummy active region. 4. Forming a mask layer above the semiconductor substrate;
Forming a plurality of line-shaped core members arranged in a first direction on the mask layer and extending in a second direction orthogonal to the first direction;
Forming a sidewall mask on the side surface of each of the core materials after making the line width of the plurality of core materials smaller than the processing limit dimension by exposure; and
Forming a first resist mask extending in the first direction covering the upper part of the contact region after removing the core material on the mask layer and the plurality of sidewall masks;
Patterning the mask layer using the sidewall mask and the first resist mask;
Using the patterned mask layer as a mask, a plurality of active regions arranged in the first direction in the semiconductor substrate and having a line width smaller than a processing limit dimension by exposure are shared by the plurality of active regions. Forming a contact region extending in the first direction,
A method of manufacturing a nonvolatile semiconductor memory, comprising: Forming a second resist mask covering the end of the sidewall mask in the second direction on the mask layer and the plurality of sidewall masks;
Patterning the mask layer simultaneously with patterning the sidewall mask and the first resist mask using the second resist mask;
Using the patterned mask layer as a mask, simultaneously forming the active region and the contact region, and simultaneously forming an extended portion connected to a terminal portion in the second direction of the plurality of active regions;
The method for manufacturing a nonvolatile semiconductor memory according to claim 4, further comprising:

Images