US20160179073A1 - Real Time Trigger Using A Finite State Machine Having A Counting State - Google Patents

Real Time Trigger Using A Finite State Machine Having A Counting State Download PDF

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US20160179073A1
US20160179073A1 US14/578,198 US201414578198A US2016179073A1 US 20160179073 A1 US20160179073 A1 US 20160179073A1 US 201414578198 A US201414578198 A US 201414578198A US 2016179073 A1 US2016179073 A1 US 2016179073A1
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fsm
state
signal
symbol
symbols
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Andrew Robert Lehane
Antony J. A. Kirkham
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Keysight Technologies Inc
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Keysight Technologies Inc
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Assigned to KEYSIGHT TECHNOLOGIES, INC. reassignment KEYSIGHT TECHNOLOGIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIRKHAM, ANTONY J A, LEHANE, ANDREW ROBERT
Assigned to KEYSIGHT TECHNOLOGIES, INC. reassignment KEYSIGHT TECHNOLOGIES, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE CORRESPONDENCE AND RECEIVING PARTY ADDRESSES PREVIOUSLY RECORDED ON REEL 034561 FRAME 0833. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Assignors: KIRKHAM, ANTONY J A, LEHANE, ANDREW ROBERT
Priority to CN201510959333.1A priority patent/CN105717851B/zh
Publication of US20160179073A1 publication Critical patent/US20160179073A1/en
Priority to US16/248,642 priority patent/US10908184B2/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
    • G01R13/0218—Circuits therefor
    • G01R13/0254—Circuits therefor for triggering, synchronisation
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/045—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/13—Plc programming
    • G05B2219/13009—State machine instructions
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/23—Pc programming
    • G05B2219/23289—State logic control, finite state, tasks, machine, fsm
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/10—Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier
    • Y02P80/15—On-site combined power, heat or cool generation or distribution, e.g. combined heat and power [CHP] supply

Definitions

  • Measurement instruments that measure, record, process a signal, and display the results of the processing are known to the art.
  • a digital oscilloscope measures the amplitude of a signal as a function of time and displays a portion of the observed signal as a graph of signal amplitude as a function of time.
  • Modern digital oscilloscopes can measure a signal at a rate of close to 100 Gigasamples/second in each of a plurality of measurement channels. To generate data at this rate, the signal is typically digitized using a bank of sample and hold circuits that sample the signal in successive time slots. Each sample and hold circuit feeds a high speed analog-to-digital converter (ADC) that stores its output in a high speed memory bank that is assigned to that ADC.
  • ADC analog-to-digital converter
  • trigger is utilized to define the beginning of a region of interest in the signal.
  • the instrument records the signal from the trigger to some point in time that depends on the storage capacity of the memory banks.
  • Simple triggers such as detecting a rising edge in the signal can be implemented in hardware in real time.
  • a trigger system that can consume samples as fast as the bank of ADCs can generate the samples will be referred to as a real time trigger system.
  • more complex triggers must rely on storing a data sequence and then examining the sequence using hardware that is too slow to operate in real time. In such schemes, a real time trigger is used to define some preliminary trigger event.
  • the instrument then records the data from that trigger point to some predetermined number of samples. The recorded data is then examined by a more complex trigger system to determine if the more complex trigger is present. Such secondary trigger systems are referred to as post acquisition triggers (PATs). If the complex trigger is found, the instrument displays the data starting with that trigger. If the complex trigger pattern is not found, the process is repeated. During the time the PAT is operating on the stored data, the instrument is not acquiring any new data, and hence, the instrument is “blind” for that period of time. The blind time is typically a large fraction of the total operating time, and hence, a signal of interest can be lost.
  • PATs post acquisition triggers
  • a scheme for using finite state machines (FSMs) to implement a trigger system for complex trigger criteria is disclosed.
  • the digitized signal values are first converted to a sequence of symbols that have much fewer states than the digitized signal values.
  • a 12 bit ADC-generated value can be reduced to three symbols, L, M, and H by comparing the signal values to three ranges of values.
  • a trigger is defined as a sequence in the symbol sequence that satisfies a predetermined regular expression.
  • the FSM-implemented trigger system operates on the resultant sequence of symbols. Many triggers of interest can be expressed as patterns on these symbols.
  • the present invention includes an apparatus that searches for a pattern in a signal.
  • the apparatus includes a symbol generator and an FSM.
  • the symbol generator receives an ordered sequence of signal values and converts the ordered sequence of signal values into an ordered sequence of symbols, each symbol having a plurality of states.
  • the FSM receives the ordered sequence of symbols and generates a match signal if the ordered sequence of symbols includes a target sequence specified by a regular expression that includes a counting limitation on one of the symbol states.
  • the FSM includes a counting state that includes a counter that counts instances of the one of the symbol states.
  • the FSM is characterized by an input word and an FSM clock period.
  • the FSM processes one input word during each FSM clock period, and the input words includes a plurality of the symbols.
  • the counting limitation includes a requirement that a precise number of instances of one of the symbol states be present in the target sequence. In yet another aspect of the invention, the counting limitation includes a requirement that more than a specified number of instances of one of the symbol states be present in the target sequence. In a still further aspect of the invention, the counting limitation includes a requirement that more than a first specified number of the instances of one of the symbol states and less than a second specified number of the instances of the one of the symbols be present in the target sequence.
  • the FSM has a memory that stores a state table that specifies a next state for the FSM based on a present state for the FSM, and the input word currently is processed by the FSM.
  • the state table specifies first and second next states for the FSM when the FSM is in the counting state.
  • the FSM chooses one of the first and second next states based on whether the counting limitation has been satisfied.
  • the counting limitation is not satisfied if the counter has a value less than a first value or greater than a second value, and the one of the first and second states that the FSM chooses also depends on whether the counter is less than the first value or greater than the second value.
  • the apparatus also includes a signal digitizer and a signal memory, the signal generator receiving a signal and generating the ordered sequence of signal values therefrom.
  • the ordered sequence of signal values is stored in the signal memory.
  • the signal digitizer generates a first number of signal values during each FSM clock period, each of the first number of signal values being converted to a corresponding symbol during one FSM clock period.
  • the FSM processes the first number of symbols as a single input word during one FSM clock period.
  • the apparatus includes a display controller and a display, the display controller displaying a portion of the signal values on the display in response to the FSM generating the match signal.
  • the FSM is a Mealy FSM.
  • FIG. 1 illustrates a digital oscilloscope system that utilizes an FSM-based trigger system to implement a real time trigger.
  • FIG. 2 illustrates an FSM that searches for regular expression [ ⁇ L]*L+M*H ⁇ 3,4 ⁇ M*L.
  • FIG. 3A illustrates the state diagram for a counter extended FSM for detecting the glitch sequence [ ⁇ L]*L+M*H ⁇ m ⁇ M*L.
  • FIG. 3B illustrates the state diagram for a counter extended FSM for detecting the glitch sequence [ ⁇ L]*L+M*H ⁇ m, ⁇ M*L.
  • FIG. 3C illustrates a counter extended FSM for the glitch sequence [ ⁇ L]*L+M*H ⁇ m,n ⁇ M*L.
  • FIG. 4 illustrates a base FSM for a two symbol input word that searches for the sequence shown in FIG. 3A .
  • FIG. 5 illustrates the portion of the hardware that implements an FSM according to the present invention.
  • FIG. 6 illustrates a base FSM for a two symbol input word FSM that counts an odd number of Hs.
  • FIG. 1 illustrates a digital oscilloscope system that utilizes an FSM-based trigger system to implement a real time trigger (RTT).
  • the input to digital oscilloscope 10 is digitized by a bank of ADCs 12 .
  • each ADC includes a sample and hold circuit that has a very narrow sampling window. The window is much shorter than the time needed to digitize the captured sample value.
  • a bank of ADCs is utilized in which successive ADCs in the bank capture signal values that are displaced in time from one another so as to provide a continuous series of samples separated by the width of the sampling window in time.
  • the output from each ADC is stored in a corresponding memory bank in memory 14 .
  • the details of the banking of the ADCs and the banks in the memory have been omitted from the drawing to simplify the drawing and following discussion.
  • the ADC output is monitored by a symbol generator 15 that generates a symbol from each ADC measurement.
  • the symbols are then inputted to trigger generator 16 . If trigger generator 16 finds a match to the trigger sequence, display controller 19 displays the corresponding ADC measurements on display 20 starting from a point defined by the trigger sequence.
  • each input signal value is converted to a symbol set having only three states, L, M, and H.
  • a signal value that is less than a first threshold value is assigned the symbol L; a signal value that is between the first threshold and less than or equal to a second threshold is assigned the symbol M, and signal values that are greater than the second threshold are assigned the symbol H.
  • the trigger patterns that can be defined in the present invention are limited to patterns that can be defined by regular expressions.
  • a regular expression is defined to be a sequence of characters that defines a search pattern. Given a regular expression, an FSM that executes the search so defined exists, and there are procedures for automatically generating that FSM. It should also be noted that there is more than one FSM that is capable of performing the search for any given regular expression.
  • An FSM is a machine that has a plurality of states connected by “directed edges”. At each processing cycle, the FSM moves from its current state to a next state when a new input word is received by the FSM. Hence, each edge has one or more input values associated with that edge. When the FSM receives an input word having a value equal to the value corresponding to an edge, and the FSM is in the state associated with the input side of the edge, the FSM changes to the state associated with the output side of the edge. The FSM then proceeds to process the next input word. Certain transitions give rise to the FSM reporting a match that includes information associated with the transition. The transition may be the entry into a particular state or the entry into that state by a specified edge. For the purposes of the present discussion, the processing cycle is complete when the FSM has moved to its new state and made any required reports.
  • a regular expression is defined to be a sequence of characters that defines a search pattern.
  • Each character in the expression is either a regular character with its literal meaning or one of a predetermined number of metacharacters that have a special meaning.
  • ” denotes an alternative.
  • b” is satisfied by a or b.
  • the metacharacters “?”, “*”, and “+” quantify the preceding element. Metacharacter “?” is satisfied if the preceding element occurs zero or one time, “*” is satisfied if the preceding element occurs zero or more times, and “+” is satisfied if the preceding element occurs one or more times. Many patterns of interest require the repetition of some string.
  • the expression that is to be repeated is surrounded (grouped) by ( ) if there is more than one character, or more than one character range in the expression.
  • Metacharacters “[” and “]” are used to create character classes, such as [LMH], “ ⁇ ” is used to represent negation, i.e., [ ⁇ L], everything but ‘L’.
  • ⁇ m ⁇ is used after the expression.
  • ⁇ m, ⁇ is used after the expression.
  • a range between n and m the expression is followed by ⁇ m,n ⁇ .
  • a regular expression for a rising edge is “L+M*H”, i.e., one or more Ls followed by zero or more Ms followed by an H.
  • a regular expression for a falling edge is “H+M*L”.
  • a regular expression for either a rising or falling edge is (H+M*L)
  • Additional features of interest in defining trigger sequences are state transitions, glitches, and runt pulses.
  • a state transition occurs when the waveform, having been established in one of the logic states, switches to the other state and becomes established there.
  • a glitch occurs when the waveform, having been established in one logic state, switches to the other state, but not long enough to be considered established.
  • a runt pulse occurs when the waveform, having been established in one logic state, moves into the indeterminate region but then returns to the first logic state without ever having crossed the other logic state threshold.
  • a glitch trigger must only trigger when the width of the pulse is less than a certain time.
  • an edge followed by a second edge should only trigger when the time between the edges is a greater than a predetermined time.
  • the amount of time passed between events of interest is equivalent to the number of samples. For example, at 1 Gigasample/second, a sample is generated every nanosecond, and hence, the passage of time is equivalent to counting the number of samples.
  • a glitch trigger can be defined by the regular expression [ ⁇ L]*L+M*H ⁇ 3,4 ⁇ M*L. That is, zero or more symbols that are not L, i.e., M or H, followed by one or more L followed by zero or more M, followed by between three and four Hs followed by zero or more Ms and an L.
  • FIG. 2 illustrates an FSM that searches for this regular expression.
  • the final reporting state is indicated by the double circle around the state.
  • the counting feature is implemented by inserting additional states into the FSM, namely states S 3 -S 5 . This is a viable approach for small values of the counter.
  • this FSM will trigger on a glitch having a width between 3 ns and 4 ns.
  • this approach is not efficient when the count is significantly larger. For example, a glitch that is defined as being in the high state for a microsecond would require a thousand states.
  • a second problem relates to the need to match the processing rate of the trigger generator to the rate at which the input signal is being sampled and digitized.
  • a system in which samples are digitized at a rate of 6.4 Gigasamples/second.
  • An FSM implemented in a programmable gate array is limited to running at a clock rate of 400 MHz.
  • the FSM must operate on an input word that is 16 samples wide to keep up with the ADC bank.
  • Counting symbols presents significant challenges when the word size processed by the FSM is large.
  • a wide word FSM must be able to recognize data changes at any alignment in the incoming data. For simplicity, consider a four word system where four symbols arrive on each FSM clock edge. Consider the regular expression discussed above for a glitch that is required to count H symbols.
  • the FSM must be able to detect the sequence of Hs independent of the alignment of the symbols in the four-symbol input word. That is, the input word that commences a string of Hs could be ‘LMMH’ followed by four words of ‘HHHH’ followed ‘HMML’, i.e., 18 ‘H’ symbols. However, the same sequence could arrive on a different word boundary such as ‘LMHH’ then four lots of ‘HHHH’ then ‘MMML’. This is also 18 ‘H’ symbols but on a different alignment. Hence, any mechanism for counting a symbol must deal with all of the possible alignments of the symbol sequence within the multi-symbol input words.
  • a third problem that must be overcome with multiple symbol input words is the need to count samples, not FSM clock cycles. If the word size is one and the FSM consumes one symbol per clock cycle, then counting clock cycles of the FSM is equivalent to counting samples. When the number of symbols per FSM clock cycle is greater than one, counting FSM clock cycles is equivalent to counting multiple samples.
  • a fourth problem that must be overcome is the need for the FSM to consume a multi-symbol word every FSM clock cycle. Hence, the hardware cannot take two or more clock cycles to make a transition. The FSM must be able to calculate the next state in a single FSM clock cycle and on each and every subsequent FSM clock cycle.
  • the counting hardware must support the different styles of counters. There are three fundamentally different styles of counting in regular expressions.
  • the first problem can be solved by using an extended FSM that includes a counting function associated with one or more states.
  • Such states will be referred to as counting states in the present discussion.
  • Each counting state has a counter associated with that state. The counter is reset to a particular value when the FSM enters that counting state. The count is incremented or decremented each time a particular input word is input to the FSM when the FSM is in that counting state.
  • the choice of the next state executed by the FSM upon receiving a particular input word when the FSM is in the counting state depends on the count in the counter at the time the input word is received.
  • the predetermined condition will be referred to as the count satisfied condition.
  • a state table for the FSM in FIG. 3A is shown in Table 1 which shows the next state as a function of the current state, input symbol, and whether or not the count satisfied condition has been met. For reasons that will be explained in more detail below, a next state as a function of the counter value is provided even for states that do not reference the counter so that all states have the same format.
  • the next state values for the cases in which the count satisfied condition has not been met are shown in the columns marked “ ⁇ ”.
  • the next state values for the cases in which the count satisfied condition has been met are shown in the columns marked “ ⁇ ”.
  • the identity of the counter does not need to be shown. However, in many cases of interest, there will be multiple counters. Hence, the identity of the counter corresponding to each state is stored in the state table or an associated table.
  • FIG. 3B illustrates the state diagram for a counter extended FSM for detecting the glitch sequence [ ⁇ L]*L+M*H ⁇ m, ⁇ M*L.
  • the count satisfied condition is that at least m Hs have been received. If the count condition has not been satisfied and an H is received, S 3 continues to loop. Once the count satisfied condition has been met, S 3 will still loop on receiving an H. Since the pattern requires “at least” m Hs, there can be more; hence, there are two looping transitions shown in the figure.
  • the third type of counting style presents additional challenges.
  • the count condition is satisfied when the counter value is greater than or equal to m and less than or equal to n.
  • FIG. 3C illustrates a counter extended FSM for the glitch sequence, [ ⁇ L]*L+M*H ⁇ m,n ⁇ M*L. If the count is less than m, and an H is received, the count condition is not satisfied and the edge loops back to S 3 , as shown by the dotted loop on S 3 . If the count is greater than n, the edge marked H′ is taken. If the count is between m and n, the count satisfied condition is met, and an additional H is merely added to the count as indicated by the solid loop back to S 3 .
  • the additional column in the state tables is avoided by noting that there are only two “next states” in the table for an H, even though there are three possible cases for S 3 when an H is received.
  • the first next state is 0, and the second next state is S 3 , i.e., a loop back to S 3 .
  • two flags are defined. The first indicates whether the count condition is satisfied, the second indicates whether the fail condition corresponds to the count being too low or too high.
  • the second flag will be denoted by f and will be defined to be true if the count is less than m. When the count reaches m, f is set to false.
  • a state table is constructed corresponding to one of the fail conditions, in this case, the flag being true.
  • the next state in this fail case is S 3 .
  • the other possible next state, S 0 is stored in the H row of the condition satisfied column, even though this is not the correct next state for that location in the state table.
  • the FSM is programmed to reverse the entries in the condition not satisfied and condition satisfied columns if the flag is true.
  • the correct next state, S 3 will be used.
  • the count exceeds n, the flag is reset, and hence, the value in the count satisfied column is used for H, even though the count is not actually satisfied. It should be noted that the state table based on this flag is shown below.
  • the state tables for any of the three counting styles can be constructed by having at lease two columns for the counting state.
  • the choice of column is determined by a first flag that indicates whether the count satisfied condition has been met.
  • a second flag that indicates the manner in which the count satisfied condition has not been met is needed.
  • This flag can be used in conjunction with a third column to pick the next state by selecting which of the count condition not satisfied next states is the correct one.
  • the third column can be eliminated by using the second flag to reverse the entries in the two column table depending on the manner in which the count condition is not satisfied.
  • the above-described embodiments allow the counting function to be implemented without significantly increasing the number of states in the FSM.
  • the computational engine needs to have one counter for each counting function in the regular expression that is operative at any given time.
  • the state table must be expanded to include an entry for each count enhanced state to provide the next state for the two different count possibilities. One provides the next state if the count is satisfied, and one provides the next state if the count has not been satisfied.
  • the above-described embodiments are single trigger FSMs in that once the reporting state is achieved, the trigger stops functioning until it is reset. Embodiments in which the trigger operates in a continuous manner will be discussed in more detail below.
  • One method for constructing a state table for a multi-symbol FSM that includes counting states and searches for a sequence that satisfies some predetermined regular expression starts from an FSM that processes one symbol per FSM clock cycle and searches for the sequence in question.
  • an intermediate one symbol FSM is constructed by expanding the counting states in the one symbol FSM.
  • This expanded FSM will be referred to as a base FSM for an FSM that processes w symbols at each cycle.
  • the base FSM is a construct that allows one to construct the state table for the multi-symbol FSM.
  • the base FSM for a single symbol input word must first be expanded.
  • the expansion introduces additional counted states for each counted state in the single symbol input word FSM.
  • the number of counted states corresponding to a given counted state in the single symbol FSM is equal to the number of symbols in the input word.
  • Each counted state corresponds to a different alignment of the counted symbols within the input word when the counted state is entered.
  • State S 3 is expanded into two states, S 3 A and S 3 B.
  • the state counting H input symbols could be entered in response to an input word XH, or HH, where X is either L or M.
  • State 3 A counts H strings that enter via input words of the form XH. This counter will be referred to as the odd count state.
  • State S 3 B counts H strings that enter via an input word of HH. This state will be referred to as the even count state.
  • the next input word could be HX, HH, or XX′, where X′ can be either L or M.
  • the counter will either have just reached the desired count on the last HH input word or it is still in need of processing a further HH to complete the count.
  • the fail transition is taken, since the X was received before the desired count was obtained.
  • the state table will have an exit transition for the next H.
  • the H completes the missing symbol from the first pair.
  • the odd counter will have an output edge on count satisfied for any word of the form HX.
  • State S 3 B is entered in response to an input word of HH. This counter is likewise reset to the value corresponding to m.
  • While the base FSM has two counted states, these states can be implemented using a single counter, since only one of the states will be operative at any given time. If two different counters are used, then the counter for state 3 B must be reset to zero on entry from the edge connecting S 3 A to S 3 B. This guarantees that S 3 B will not start counting any additional Hs instead of taking the failed edge on another H. If a single counter is used, then the counter that was used for S 3 A will already have counted down to zero, and hence, no reset is needed.
  • the path starting at the state and traversed by the mini-path represented by that input word is determined with reference to the base FSM. For example, if the current state is S 0 and the input word LM is received, the next state will be S 2 , as the FSM first transitions to S 1 on the first symbol and then to S 2 on the second symbol. If the FSM is currently at S 2 and XH is received, the FSM will transition to S 3 A and decrement the counter. If on the other hand, HH was received, the FSM would transition to S 3 B and then decrement the counter.
  • Table 3 is the state table for the regular expression shown in Table 1 for a word size of two symbols per FSM clock cycle.
  • the above described embodiments refer to a counter whose contents are examined to determine if a count condition has been satisfied. If a single count register is utilized, the register can be incremented until it matches a value stored in another register, e.g., m/w-1. Alternatively, the register can be reset to the desired value and decremented on each clock cycle. This second alternative is preferred because testing the contents of the register for zero can be done more economically.
  • a single counter can also be utilized.
  • the counter is first loaded with the value corresponding to m, and the flag that indicates that the count condition has been achieved is set to false. After the counter counts down to zero, the counter is reset to the value corresponding to n, and the flag is set to true. When the counter again counts down to zero, the flag is reset to false.
  • a two register counter could be utilized in which the first register is loaded with a value related to m and the second is loaded with a value related to n. Two flags are used to keep track of whether the count condition is satisfied, and if not, which non-satisfied state is present, i.e., count below the m value or above the n value.
  • the present invention is preferably implemented in custom computer hardware to provide the desired speed.
  • FIG. 5 illustrates the portion of the hardware that implements an FSM according to the present invention.
  • the state table for FSM processor 30 is stored in a memory 35 which is loaded by trigger generator 16 shown in FIG. 1 .
  • the type of trigger is specified by the user input to trigger generator 16 .
  • the symbols of the current word are loaded into a current input word generator 32 which together with the current state of the FSM which is stored in register 33 to determine an address in memory 35 at which the next state values for the count satisfied and count not satisfied entries are located together with any information associated with the next state such as reset values for the counter and flags that determine which of the two entries is to be used.
  • the choice of column is made by controller 38 which generates a selection signal that is input to multiplexer 36 which receives the two possible values.
  • Controller 38 controls counter 37 . Controller 38 receives signals defining the count mode and the values to be loaded into counter 37 when the counter is reset. Controller 38 loads a starting value into counter 37 when required either by the start of the trigger or reset instructions associated with the next state output from multiplexer 36 . Counter 37 is decremented on each clock cycle and controller 38 tests the contents of counter 37 to determine if the count stored therein is now zero. Controller 38 also includes the flags discussed above. The first flag determines if the count condition specified by the mode and values of m and n has been satisfied. Controller 38 also sets the second flag needed to process a ⁇ m,n ⁇ count condition.
  • a trigger generator may include a number of counters.
  • a single hardware counter is sufficient, since only one counting state is operating at any time.
  • a state table with more than one active counter could be utilized for a particular trigger sequence.
  • counter 37 would be replaced by a plurality of counters and the current state would specify which counter is to be used for that state transition.
  • each state in the state table is assigned two next state entries for each possible input word. If the state does not depend on the count in counter 37 , both entries are identical.
  • controller 38 can be programmed to take the first of the two entries unless the current state is a counting state. Strategies to remove this redundant information via compression techniques can also be employed.
  • the ADCs 12 operate in banks to achieve the necessary throughput for a high speed instrument.
  • the symbol generator 15 also includes a bank of symbol generators that create a corresponding group of symbols that become the input symbols to the multi-symbol FSM of the present invention.
  • an instrument having a bank of 16 ADCs generates 16 consecutive time samples each FSM clock cycle. These 16 time samples are then converted to 16 consecutive symbols that are loaded into the input word trigger generator 16 .
  • the FSM clockperiod is set to be less than or equal to the clock in the ADCs in embodiments in which the FSM provides a real time trigger.
  • the number of symbols in an input word must at least match the number of symbols generated by the bank of ADCs in the instrument.
  • the amount of memory needed to store the state table increases exponentially with the number of symbols in the multi-symbol input word to the FSM.
  • FSM designs that reduce the memory requirements are preferred.
  • the state table for this FSM has three rows and ten columns in embodiments in which each state stores a two entry next symbol value.
  • the corresponding FSM with a 16 symbol input word requires 3 16 rows and 30 columns corresponding to the 15 states.
  • the maximum number of different rows that can be created from the 30 columns is less than 30 2 or 900, since the four columns are identical for the non-counted states.
  • the state tables must have a large number of cases in which the row for one input word is the same as the row for another input word with the exception of the input word in the first column.
  • This redundancy can be used to reduce the size of the memory needed by storing a reduced table that has only the unique rows with the input word replaced by a key value.
  • a correspondence table that stores the correspondence between the input words and the key values is then used to access the reduced table.
  • the correspondence table has one column that is indexed by the input word.
  • This form of table compression is particularly well suited to the type of state table generated by multi-symbol FSMs. However, other forms of table compression could also be utilized to further reduce the size of the state table.
  • the above-described embodiments of the present invention utilize Moore FSMs in which the FSM stops when a match is found.
  • the output values are determined solely by the current state of the FSM. That is, the FSM reports a match when it enters a state no matter how it got to that state.
  • the output depends on the current state and the current inputs.
  • a Mealy machine reports on a particular edge being taken.
  • a state may report a match if entered by one edge, but not if entered by another edge.
  • Mealy machines can also be used for implementing the present invention. For triggers in which the trigger is to operate continually without resetting, a Mealy FSM is preferred.
  • a non-stopping trigger can have transitioned through a matching state on a w-symbol path, while reporting on the edge that passes through the matching state.
  • the Mealy machine is more compact.
  • a Mealy machine can be made to match and return to the start state all in one transition. For example, in a Moore machine which repeats S 5 is both a match state and the next pass through the start state, which is not ideal.
  • the edges carry the information about incrementing counters and whether a match has occurred instead of associating this information with entering a particular state.
  • the Mealy FSM embodiments are also generated from a base FSM.
  • Each state of the multi-symbol FSM corresponds to a w-symbol path within the base FSM. An intermediate stop on that path may trigger a count operation or match report.
  • the two edges that terminate on the same state in the base FSM can correspond to different counting and reporting behaviors even though the two paths end on the same state.
  • a multi-symbol FSM counting state counts in units of the word size. That is m and n must be divisible by the word size w, and the counters are incremented or decremented by w. If an m or n value that is not a multiple of w is desired, the state table can be augmented to include the appropriate number of additional states that consume the needed symbols.
  • the state table can be constructed from a base FSM by inserting one or more additional states that are entered on the receipt of another symbol of the type being counted. Refer now to FIG. 6 , which illustrates a base FSM for a two symbol input word FSM that counts an odd number of Hs. The base FSM is obtained by adding the state S 6 after state S 3 B.
  • the additional states could be added before S 3 A and/or after S 3 A.
  • the extra states are added before S 3 A.
  • the states may have to be added both before S 3 A and after S 3 B depending upon the required values of m and n.
  • the FSM of the present invention is preferably implemented in special purpose hardware to provide the speed needed to implement a real-time trigger for a high speed oscilloscope or similar instrument.
  • embodiments could be implemented on general purpose data processing systems if the speed of the incoming data stream was sufficiently low.

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