US20160071743A1 - Integrated circuit package fabrication with die attach paddle having middle channels - Google Patents

Integrated circuit package fabrication with die attach paddle having middle channels Download PDF

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Publication number
US20160071743A1
US20160071743A1 US14/941,865 US201514941865A US2016071743A1 US 20160071743 A1 US20160071743 A1 US 20160071743A1 US 201514941865 A US201514941865 A US 201514941865A US 2016071743 A1 US2016071743 A1 US 2016071743A1
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Prior art keywords
die
die attach
attach paddle
integrated circuit
channels
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US14/941,865
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US9620388B2 (en
Inventor
You Chye HOW
Maria Christina Bernardo Violante
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Texas Instruments Inc
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Texas Instruments Inc
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Priority claimed from US13/974,323 external-priority patent/US9202778B2/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to US14/941,865 priority Critical patent/US9620388B2/en
Publication of US20160071743A1 publication Critical patent/US20160071743A1/en
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Publication of US9620388B2 publication Critical patent/US9620388B2/en
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    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
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    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects

Definitions

  • multiple dies are attached to the die attach paddle.
  • a power die is mounted on the die attach paddle with conductive epoxy and a controller die is mounted on the die attach paddle with nonconductive epoxy.
  • Each die is connected by bondwires to one or more leads.
  • Such a configuration is sometimes provided in a quad-flat no-leads package (“QFN”) in which the bottom of the die attach paddle is exposed and surface portions of the leads are exposed at the bottom and side walls of the package.
  • QFN quad-flat no-leads package
  • a controller die 32 having a top surface 34 and a bottom surface 36 is attached to the top surface 16 of the die attach paddle 14 by a nonconductive die attach film 38 .
  • controller dies such as die 32
  • the wafer Prior to singulation of the controller die wafer, the wafer is attached at its lower surface to a sheet of nonconductive die attach film (not shown).
  • the sheet of die attach film is attached to the top surface of a sheet of dicing tape (not shown), which is, in turn, attached at its periphery to a wafer frame.
  • a singulating saw cuts entirely through the wafer and entirely through the die attach film sheet and half way through the sheet of dicing tape.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Die Bonding (AREA)

Abstract

A method of making an integrated circuit package. A leadframe having a die attach paddle surrounded by lead portions is formed. Middle channels underlying in said die attach paddle portion in a region thereof adapted to receive a first die are formed

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a Divisional of and claims priority to U.S. patent application Ser. No. 13/974,323, filed Aug. 23, 2013, the disclosure of which is hereby incorporated by reference herein in its entirety.
    • BACKGROUND
  • Integrated circuit packages are produced in a variety of different configurations for different purposes. A typical integrated circuit package includes a leadframe having a die attach paddle (pad) and a plurality of surrounding leads. A die is typically mounted on the die attach paddle either by a conductive or nonconductive adhesive layer. One or more contacts on a top surface of the die are typically attached to one or more of the leadframe leads by bondwires.
  • The leadframe, die and bondwires are generally encapsulated in mold compound which protects the various components of the die package from moisture, etc. Portions of the die attach paddle may be exposed to enable heat dissipation from the package. Portions of the leads are also exposed to enable electrical connection of the package to other electronic components.
  • In some integrated circuit packages multiple dies are attached to the die attach paddle. In one known package configuration a power die is mounted on the die attach paddle with conductive epoxy and a controller die is mounted on the die attach paddle with nonconductive epoxy. Each die is connected by bondwires to one or more leads. Such a configuration is sometimes provided in a quad-flat no-leads package (“QFN”) in which the bottom of the die attach paddle is exposed and surface portions of the leads are exposed at the bottom and side walls of the package.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic cross sectional elevation view of an integrated circuit package illustrating a defect discovered by applicants.
  • FIG. 2 is a schematic top plan view of a portion of the integrated circuit package of FIG. 1.
  • FIG. 3 is a schematic cross sectional elevation view of an integrated circuit package illustrating another defect discovered by applicants.
  • FIG. 4 is a top plan view of a portion of the integrated circuit package of FIG. 3.
  • FIG. 5 is a schematic cross sectional elevation view of an integrated circuit package having a plurality of half etched channels positioned below a controller die.
  • FIG. 6 is a top plan view of a lead frame which is half etched as illustrated in FIG. 5, prior to mounting of dies thereon.
  • FIG. 7 is a flow chart illustrating a method of making an integrated circuit package.
    •  DETAILED DESCRIPTION
  • This specification, in general, discloses an integrated circuit package 10 having a die attach paddle 14 as illustrated in FIGS. 5 and 6. A power die 22 and a controller die 32 are mounted on the die attach paddle 14. The die attach paddle 14 has at least one recessed portion, e.g., 72, which is at least partially underlays the controller die 32.
  • FIG. 1 illustrates a problem in an integrated circuit package 10 such as a quad flat no leads integrated circuit package (QFN). The IC package 10 includes a lead frame 12 having a die attach paddle 14 with a top surface 16, a bottom surface 18 and a plurality of leads 20. The leads 20 are separated from the die attach paddle 14 by voids 19.
  • A power die 22 having a top surface 24 and a bottom surface 26 is mounted on the top surface 16 of the die attach paddle by a layer of conductive adhesive 28 such as conductive die attach film or conductive epoxy. A bond wire 30 connects a contact surface on the power die to one of the leads 20.
  • A controller die 32 having a top surface 34 and a bottom surface 36 is attached to the top surface 16 of the die attach paddle 14 by a nonconductive die attach film 38. As is known in the art controller dies, such as die 32, are singulated from a controller die wafer. Prior to singulation of the controller die wafer, the wafer is attached at its lower surface to a sheet of nonconductive die attach film (not shown). The sheet of die attach film is attached to the top surface of a sheet of dicing tape (not shown), which is, in turn, attached at its periphery to a wafer frame. During singulation of the wafer, a singulating saw cuts entirely through the wafer and entirely through the die attach film sheet and half way through the sheet of dicing tape. A pick-and-place head engages a top surface of each die, one at a time, and places each die on an associated die attach paddle. A singulated portion of die attach film sheet is retained on the bottom surface of each die as it is lifted from the dicing tape sheet. The singulated portion of the nonconductive die attach film sheet, referred to herein as the nonconductive die attach film layer 38, is thus positioned between the controller die 34 and the top surface 16 of the die attach paddle 14 to which the die 34 is transferred. The nonconductive die attach film layer 38 thus holds the associated die 34 on the die attach paddle 14 in electrical isolation from the die attach paddle 14.
  • A bond wire 31 may connect a contact on the controller die 32 to a leadframe lead 20. The leadframe 12, power die 22, controller die 32 and bondwires 30, 31 may all be encapsulated in mold compound 40. In a typical QFN package, the die attach paddle bottom surface 18 is exposed through the mold compound 40. Bottom and end surfaces of the leads 20 are also exposed through the mold compound 40.
  • Applicant has discovered that during the controller die singulation process, silicon splinters, such as splinter 52, may become embedded in the die attach film layer 38 near the periphery of the controller die 32. Such splinters 52 may create an electrical path between the controller die and the die attach paddle 14. Because the die attach paddle 14 is electrically connected to the power die 22, this leakage path provided by the silicon splinter 52 may cause a short circuit to the power die 22, resulting in failure of the integrated circuit package 10. FIG. 2 is a top plan view of the controller die 32 illustrating a typical position of a silicon splinter 52 about the periphery of the controller die 32.
  • FIG. 3 illustrates another source of defects in integrated circuit packages that has been discovered by applicant. The structure of the illustrated integrated circuit package is the same as that illustrated in FIG. 1. However, in the integrated circuit package of FIG. 3, a defect is caused by a hole 56 produced in the center of the die attach film layer 38 by an ejector needle (not shown) that pushed through the layer 38 during die ejection from a die bonding machine (not shown). This hole 56 which is typically on the order of 0.05 mm to 0.2 mm in diameter places the bottom surface 36 of the controller die sufficiently close to the top surface 16 of the die attach paddle 14 to create an electrical path to the die attach paddle 14 and thence to the power die 22. FIG. 4 is a top plan view of the power die 22 mounted on the die paddle 14 showing the hole 56 in hidden lines. Thus, the result of such a hole in the film layer 38 is often a short circuit and resulting failure of the integrated circuit package 10.
  • An integrated circuit package 110, which obviates package failures caused by silicon splinters 52 or ejector pin holes 56, is illustrated in FIG. 5. The structure of this IC package 10 may be substantially the same as that described above with respect to FIGS. 1-4. A difference is that at least one recessed portion, e.g., 72 or 74 is provided beneath the controller die 34 and die attach film 38. In the embodiment illustrated in FIGS. 5 and 6, three parallel channels 62, 64 and 66 intersect at right angles with three other parallel channels 72, 74 and 76. (The position of the periphery of a controller die 34 when it is mounted on the die attach paddle 14 is indicated in dashed lines in FIG. 6.) The channels 62, etc., may be formed by half etching the die attach paddle 14. The half etching process is known in the art and will thus not be further described herein. The channels 62, etc., are provided in an arrangement such that the peripheral portion 33 of the controller die 32 is suspended within the half etch channels, specifically channels 62, 66, 72 and 76. Since any silicon splinters 52 are located in the die attach film 38 at the periphery 33 of the controller die, any such splinter 52 is suspended well above the closest electrical contact surface of the die attach paddle 14, and thus it is incapable of producing a current path to the die attach paddle 14. Accordingly, this potential cause of IC package failure is eliminated.
  • As further shown by FIG. 5, the intersecting channels 74, 64 create an open space between the center of the controller die 34 where any die attach film void 56 produced by an ejector pin would be located. Thus, there is no electrical path provided between the bottom surface 36 of the controller die 34 and the die attach paddle 14. Thus, this potential failure causing defect is also obviated by the die paddle half etching configuration shown in FIG. 6.
  • Various alternative channel configurations could be provided. For example, one of the two channels 64, 74 could be eliminated if the other channel were made sufficiently large. In situations where an ejector pin void 56 is rarely encountered, the etching of channels 64 and 74 could be eliminated. Similarly, in situations where silicon splinters 52 are rarely encountered, the peripheral recesses 66, 62, 72, 76 could be eliminated. However, since the etching process is a relatively simple and inexpensive process, it may in most cases make sense to simply provide the etched channels indicated in FIGS. 5 and 6 in any situation where either of the above discussed defects is a possibility.
  • It will be understood by those skilled in the art that the above-described die attach paddle construction has a number of advantages. No change in package form, fit and function occurs as a result of the half etched channels. The silicon thickness of the controller die 34 and power die 22 and the mold compound thickness are unchanged. All the materials used to make the package remain unchanged. Also, there is no change of in the process flow that is used to make this package 110 as compared to the process flow for making the package 10.
  • There is no additional cost associated with making the package 110 illustrated in FIG. 5 as compared to the cost of package 10 illustrated in FIGS. 1 and 3. The only additional features of the package 110 are the half etch channels on the die attach paddle 14. These channels 62, etc., are typically etched by a lead frame supplier at the same cost as that for forming the lead frame shown in FIG. 1, since the leadframe etching processes for the package 10 of FIG. 1 and the package 110 are both a one mask process. Again, this configuration solves the problems of electrical leakage failure between the controller die and the die attach paddle due to silicon splinters in the die attach film and/or due to a central hole in the die attach film produced by a die ejector pin.
  • FIG. 7 is a flow chart illustrating a method of making an integrated circuit die package. The method includes forming a lead frame having a die attach paddle portion surrounded by a plurality of lead portions as shown at 202. The method also includes forming at least one recessed portion in the die paddle portion in a region thereof adapted to receive a first die, as shown at block 204.
  • Certain methods and structures for eliminating short circuits in an integrated circuit die package have been expressly disclosed in detail herein. Alternative embodiments of such expressly described structures and methods will become obvious to those skilled in the art after reading this disclosure. It is intended that the appended claims be construed broadly so as to cover such alternative embodiments, except as limited by the prior art.

Claims (10)

What is claimed is:
1-20. (canceled)
21. A method of making an integrated circuit die package comprising:
forming a leadframe having a die attach paddle portion surrounded by a plurality of lead portions; and
forming at least two middle channels underlying in said die attach paddle portion in a region thereof adapted to receive a first die.
22. The method of claim 21 further comprising mounting said first die on said die attach paddle portion of said leadframe in at least partial overlying relationship with said at least two middle channels.
23. The method of claim 22 wherein said mounting said first die comprises mounting a controller die with a layer of nonconductive die attach material.
24. The method of claim 21 wherein said forming at least two middle channels comprises forming a plurality of channels in said die attach paddle portion that define a plurality of island portions in said die attach paddle portion.
25. The method of claim 24 further comprising attaching a controller die to said plurality of island portions with a layer of nonconductive material.
26. The method of claim 25 further comprising attaching a power die to said die attach paddle portion with a layer of conductive material.
27. The method of claim 24 further comprising filling said plurality of channel portions with mold compound.
28. The method of claim 24 wherein said forming a plurality of channels comprises etching half etch channels on the die attach paddle.
29. The method of claim 28 wherein said etching uses a one mask process.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170098597A1 (en) * 2014-10-22 2017-04-06 Nxp Usa, Inc. Die attachment for packaged semiconductor device
US9978613B1 (en) 2017-03-07 2018-05-22 Texas Instruments Incorporated Method for making lead frames for integrated circuit packages
CN110783303A (en) * 2018-07-31 2020-02-11 德州仪器公司 Lead frame for die
US20200135632A1 (en) * 2018-10-24 2020-04-30 Texas Instruments Incorporated Die isolation on a substrate
US11114387B2 (en) 2017-02-15 2021-09-07 Industrial Technology Research Institute Electronic packaging structure

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9892999B2 (en) * 2016-06-07 2018-02-13 Globalfoundries Inc. Producing wafer level packaging using leadframe strip and related device

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US4595945A (en) * 1983-10-21 1986-06-17 At&T Bell Laboratories Plastic package with lead frame crossunder
US8481368B2 (en) * 2008-03-31 2013-07-09 Alpha & Omega Semiconductor, Inc. Semiconductor package of a flipped MOSFET and its manufacturing method
TWI420630B (en) * 2010-09-14 2013-12-21 Advanced Semiconductor Eng Semiconductor package structure and semiconductor package process
KR101354894B1 (en) * 2011-10-27 2014-01-23 삼성전기주식회사 Semiconductor package and method for manufacturing the same and semiconductor package module having the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170098597A1 (en) * 2014-10-22 2017-04-06 Nxp Usa, Inc. Die attachment for packaged semiconductor device
US10217698B2 (en) * 2014-10-22 2019-02-26 Nxp Usa, Inc. Die attachment for packaged semiconductor device
US11114387B2 (en) 2017-02-15 2021-09-07 Industrial Technology Research Institute Electronic packaging structure
US9978613B1 (en) 2017-03-07 2018-05-22 Texas Instruments Incorporated Method for making lead frames for integrated circuit packages
US10079162B1 (en) 2017-03-07 2018-09-18 Texas Instruments Incorporated Method for making lead frames for integrated circuit packages
CN110783303A (en) * 2018-07-31 2020-02-11 德州仪器公司 Lead frame for die
US20200135632A1 (en) * 2018-10-24 2020-04-30 Texas Instruments Incorporated Die isolation on a substrate

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