US20150340297A1 - Power semiconductor module - Google Patents
Power semiconductor module Download PDFInfo
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- US20150340297A1 US20150340297A1 US14/695,276 US201514695276A US2015340297A1 US 20150340297 A1 US20150340297 A1 US 20150340297A1 US 201514695276 A US201514695276 A US 201514695276A US 2015340297 A1 US2015340297 A1 US 2015340297A1
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- power semiconductor
- semiconductor module
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
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- H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
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Definitions
- the present invention relates to a power semiconductor module.
- Some flat semiconductor devices seek to achieve downsizing and reduced impedance of the wiring by connecting the electrodes to external circuits by pressure welding. Such flat semiconductor devices are described in Patent Document 1, for example.
- FIG. 8 shows an example of a flat semiconductor device in a cross-sectional view.
- a power semiconductor module 101 is equipped with a metal electrode plate 102 .
- Semiconductor chips 103 are electrically and physically connected on the electrode plate 102 .
- the semiconductor chips 103 are power MOSFETs, and are provided in a plurality of units on the electrode plate 102 .
- a drain electrode formed on the reverse surface of each of the semiconductor chips 103 is joined to the electrode plate 102 by a joining material not shown in the diagram, such as solder.
- a multilayer substrate 104 is joined on the electrode plate 102 .
- the multilayer substrate 104 is constituted by: an insulating plate 141 , a metal plate 142 , and a circuit plate 143 .
- the metal plate 142 is provided on one surface of the insulating plate 141 and joined to the multilayer substrate by a joining material not shown in the diagram, such as solder.
- the circuit plate 143 is provided on the other surface of the insulating plate 141 and forms prescribed circuits.
- a metal block 110 is electrically and physically connected to the circuit plate 143 of the multilayer substrate 104 .
- the top surface of the metal block 110 protrudes out of a cover 111 , and also serves as an electrode of the power semiconductor module 101 .
- the semiconductor chips 103 and the multilayer substrate 104 are sealed by a sealing material 108 , such as a thermosetting resin.
- a source electrode formed on the front surface of the semiconductor chip 103 is connected to the circuit plate 143 by bonding wiring 107 .
- a gate electrode formed on the front surface of the semiconductor chip 103 is connected to the circuit plate 143 by the bonding wiring 107 .
- the power semiconductor module 101 shown in FIG. 8 is not independently insulated from the outside, and therefore requires a device on which the power semiconductor module 101 is installed to provide an insulating function to the power semiconductor module 101 .
- the power semiconductor module 101 is a non-insulated power semiconductor module.
- Flat type welding structure packages are designed to establish a contact between an electrode layer on the top surface of a semiconductor element provided on a substrate and a contact terminal.
- a thermal stress mitigating member is inserted between the contact terminal and the semiconductor element (Patent Document 2).
- the power semiconductor module described in Patent Document 2 is able to dissipate heat generated by the semiconductor element from not only the substrate but also the contact terminal, and is therefore considered to be more advanced than the power semiconductor module of Patent Document 1.
- Patent Document 1 Japanese Patent Application Laid-Open Publication H1-122146
- Patent Document 2 Japanese Patent Application Laid-Open Publication 2013-149762
- the present invention aims to effectively solve the problems described above.
- the objective of the present invention is to provide a power semiconductor module capable of effectively dissipating heat from the top and bottom electrodes, while preventing excessive load from being applied to the semiconductor chip when the power semiconductor module is used.
- the present disclosure provides a power semiconductor module, including: a frame made of an insulator and having a bottom opening and a top opening; a first electrode plate made of a metal and fixed in the bottom opening in the frame; a semiconductor element having a front surface electrode and a reverse surface electrode, the reverse surface electrode being electrically and physically connected to a principal surface of the first electrode plate; a multilayer substrate comprising a circuit plate, an insulating plate, and a metal plate stacked together, the metal plate being fixed to the principal surface of the first electrode plate; a wiring member that electrically connects the front surface electrode of the semiconductor element to the circuit plate of the multilayer substrate; a second electrode plate made of a metal and fixed in the top opening in the frame; and a metal block that has a first surface having a protrusion and a second surface opposite thereto and that tapers from the first surface to the second surface, the protrusion being electrically
- the power semiconductor module in one aspect of the present invention, since the metal block is tapered, heat can be dissipated from the front surfaces of the semiconductor chips via the metal block. Additionally, the power semiconductor module is capable of preventing a linear load from being applied to the semiconductor chips, thereby achieving a reliable power semiconductor module.
- FIG. 1 is a cross-sectional view of a power semiconductor module of Embodiment 1 of the present invention.
- FIG. 2 is a cross-sectional view showing paths in which heat is dissipated in the power semiconductor module of FIG. 1 .
- FIG. 3 is a cross-sectional view showing directions of load application in the power semiconductor module of FIG. 1 .
- FIG. 4 is a cross-sectional view of a power semiconductor module of Embodiment 2 of the present invention.
- FIG. 5 is a cross-sectional view of a power semiconductor module of Embodiment 3 of the present invention.
- FIGS. 6A to 6C are perspective views for describing a power semiconductor module of Embodiment 4 of the present invention.
- FIG. 7 is a front view of a power semiconductor module of Embodiment 5 of the present invention.
- FIG. 8 is a cross-sectional view of a conventional power semiconductor module.
- Embodiments of the power semiconductor module of the present invention will be described below in detail with reference to diagrams. Note that the expression, “electrically and physically connected,” used in the description of this application is not limited to cases where the applicable objects are directly connected to each other, but also includes cases where the applicable objects are connected via conductive materials such as solder or metal sintering materials.
- a power semiconductor module 1 of Embodiment 1 of the present invention shown as a cross-sectional view in FIG. 1 , has a substantially cylindrical outer shape (see FIG. 6A ).
- the power semiconductor module 1 is equipped with: a frame 9 ; a first electrode plate 2 ; semiconductor chips 3 that serve as semiconductor elements; a multilayer substrate 4 ; wiring members 7 ; a second electrode plate 10 ; and a metal block 11 .
- the first electrode plate 2 is an electrode that is pressure welded to an external conductive plate to pass current when the power semiconductor module 1 of the present embodiment is used.
- the first electrode plate 2 has a projected portion 2 a at the center of the outer surface so as to be aligned with an external conductive plate.
- the projected portion 2 a with a height of approximately 1 mm can secure sufficient contact.
- the semiconductor chips 3 are fixed on a principal surface of the first electrode plate 2 .
- the semiconductor chip 3 has a front electrode and a reverse electrode.
- the semiconductor chip 3 is a diode chip. Note, however, that this does not exclude the possibility of employing a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET for the semiconductor chip 3 .
- a semiconductor element made of silicon carbide (SiC) or silicon is employed for the semiconductor chip 3 .
- a semiconductor element made of silicon carbide is especially preferable, since such a semiconductor element has a wide band gap and high heat resistance, which allows for high-temperature operation.
- FIG. 1 shows six semiconductor chips 3 in total, or three semiconductor chips 3 respectively on the left and right sides of the page, with the multilayer substrate 4 therebetween.
- a plurality of semiconductor chips 3 are provided around the multilayer substrate 4 .
- the reverse surface electrode (anode electrode, for example) of the semiconductor chip 3 is electrically and physically connected to the first electrode plate 2 by a conductive joining material not shown in the diagram, such as solder or a metal sintering material.
- the multilayer substrate 4 is configured by stacking together a circuit plate 43 , an insulating plate 41 , and a metal plate 42 .
- the insulating plate 41 is an insulating plate made of an insulating ceramic, such as aluminum nitride or aluminum oxide, for example, and the metal plate 42 and the circuit plate 43 are made of copper, for example.
- a DCB (Direct Copper Bond) substrate or the like formed by directly joining the insulating plate 41 , the metal plate 42 , and the circuit plate 43 can be used as the multilayer substrate 4 .
- the multilayer substrate 4 can be configured by joining the circuit plate 43 and the metal plate 42 to the insulating plate 41 using a joining material not shown in the diagram.
- the metal plate 42 of the multilayer substrate 4 is in contact with a principal surface of the first electrode plate 2 , and is fixed to the first electrode plate 2 with a joining material not shown in the diagram.
- the wiring members 7 face ends of the multilayer substrate 4 , as well as the semiconductor chips 3 .
- the wiring member 7 electrically connects a front surface electrode (a cathode electrode, for example) of the semiconductor chip 3 and the circuit plate 43 of the multilayer substrate 4 .
- the wiring member 7 is equipped with a printed board 5 and conductive posts 6 .
- the printed board 5 has, on at least one surface of an insulating plate thereof, a metal film for wiring made of a conductive metal such as copper or aluminum. It is preferable that copper be used for the metal film to achieve low inductance. If the semiconductor chip 3 is a switching element and has a plurality of front surface electrodes on the front surface of the semiconductor chip 3 , the printed board 5 has at least two types of metal films for wiring to accommodate these electrodes.
- the insulating plate of the printed board 5 may be a rigid substrate made of a glass epoxy material, a flexible substrate made of a polyimide material, or a ceramic substrate.
- the metal film of the printed board 5 can be formed on one surface of the insulating plate, or on both surfaces.
- One end of the conductive post 6 is electrically and physically connected to the metal film of the printed board 5 by a conductive joining material such as solder (not shown in the diagram).
- the other end of the conductive post 6 is electrically and physically connected to the front surface electrode of the semiconductor chip 3 or the circuit plate 43 by a conductive joining material such as solder (not shown in the diagram).
- the conductive post 6 is made of a metal material with good conductivity, such as copper. Additionally, metal plating can be applied to the surface, if needed.
- the outer shape of the conductive post 6 can be a cylinder, a cuboid, or the like. Note that the bottom surface of the conductive post 6 must be smaller than the front surface electrode of the semiconductor chip 3 .
- the diameter of the conductive post 6 is approximately 0.5 mm, for example.
- any number of conductive posts 6 can be installed on each of the semiconductor chips 3 , and it is also possible to join a plurality of conductive posts 6 to one electrode.
- the power semiconductor module 1 of the present embodiment is configured with the wiring members 7 equipped with the printed boards 5 and the conductive posts 6 in lieu of the bonding wiring 107 used in the conventional power semiconductor module 101 shown in FIG. 8 .
- the wiring members 7 allow the cross section of the wiring to be thicker than the bonding wiring 107 . Additionally, the length of wiring can be shortened. For these reasons, with the power semiconductor module 1 of the present embodiment, it is possible to lower inductance than with the conventional power semiconductor module 101 . For the same reasons, it is possible to realize a larger current flow in the semiconductor chips and an increase in current density. Further, the wiring members 7 are superior to the bonding wiring with respect to heat dissipation from the semiconductor chips 3 .
- the wiring members 7 are physically connected to the semiconductor chips 3 using a joining material, the wiring members 7 are adhered more securely to the semiconductor chips 3 than the bonding wiring and are therefore more resistant to thermal stress. This makes it possible to enhance the reliability of the power semiconductor module 1 .
- the wiring members 7 can reduce the height or the amount of the sealing material 8 filled inside the enclosure than the bonding wiring 107 can. This makes it possible to lower the cost of the power semiconductor module 1 , and enhance the reliability thereof.
- the power semiconductor module 1 uses the wiring members 7 , each of which is formed by joining the printed board 5 and the conductive posts 6 into an integral whole, thereby allowing easy assembly and simplifying the steps of manufacturing the power semiconductor module 1 .
- the wiring members 7 are sealed by a sealing material 8 made of a thermosetting resin. It is preferable that the amount of the sealing material 8 injected into the enclosure be an amount that covers up to approximately 1 to 3 mm, most preferably 2 mm, above the top ends of the printed boards 5 and the conductive posts 6 to ensure that the printed boards 5 and the conductive posts 6 are insulated.
- a sealing material made of a thermosetting resin has a higher thermal resistance and pressure resistance than a sealing material made of gel, and is therefore preferable for the sealing material 8 .
- an epoxy resin can be used for the sealing material 8 .
- a sealing material made of a resin to which a filler with high heat conductivity is added be used, in order to increase heat dissipation.
- Aluminum, boron nitride, or the like may be employed as a filler, for example.
- a recessed portion 2 b is provided at the center of the surface of the first electrode plate 2 .
- the multilayer substrate 4 is disposed in the recessed portion 2 b to align the heights of the semiconductor chips 3 and the circuit plate 43 . This is done so that conductive posts with the same length can be used for the conductive posts 6 of the wiring members 7 , and so that the printed boards 5 can be disposed substantially parallel to the first electrode plate 2 and the multilayer substrate 4 .
- the frame 9 is a hollow cylinder, and has a bottom opening 9 a to which the first electrode plate 2 is joined by an adhesive agent not shown in the diagram. Additionally, the second electrode plate 10 is joined to a top opening 9 b of the frame 9 with an adhesive agent not shown in the diagram.
- a recessed and projected portion 9 c is provided on the outer surface of the frame 9 of the present embodiment to secure a sufficient creepage distance in the event a high voltage is applied between the first electrode plate 2 and the second electrode plate 10 .
- the enclosure of the power semiconductor module 1 is constituted by the frame 9 , the first electrode plate 2 , and the second electrode plate 10 , and houses the semiconductor chips 3 , the multilayer substrate 4 , the wiring members 7 , and the metal block 11 .
- the second electrode plate 10 is an electrode that is pressure welded to an external conductive plate to pass current when the power semiconductor module 1 of the present embodiment is used, in a manner similar to the first electrode plate 2 .
- the second electrode plate 10 has a projected portion 10 a at the center of the outer surface, so as to be aligned with an external conductive plate.
- the projected portion 10 a with a height of approximately 1 mm can ensure sufficient contact.
- the metal block 11 is provided to allow current to flow from the multilayer substrate 4 to the second electrode plate 10 inside the enclosure.
- the metal block 11 is made of a metal material with good heat conductivity and electrical conductivity, such as copper.
- a projected portion 1 lb is provided on a first surface 11 a of the metal block 11 .
- the projected portion 1 lb is connected electrically and physically to the circuit plate 43 of the multilayer substrate 4 by a conductive joining material not shown in the diagram, such as solder.
- a second surface 11 c of the metal block 11 is electrically and physically connected to the second electrode plate 10 by a joining material such as solder, screws, or the like.
- the first surface 1 la of the metal block 11 is adhered to the sealing material 8 , which covers the printed boards 5 and the conductive posts 6 .
- the metal block 11 and the semiconductor chips 3 are in close proximity to each other, with the sealing material 8 and the wiring members 7 therebetween.
- the second surface 11 c of the metal block 11 and the multilayer substrate 4 are roughly equal in size. It follows then that the metal block 11 tapers from the first surface 11 a to the second surface 11 c . More specifically, the metal block 11 of the present embodiment shown in FIG. 1 is a conical frustum provided with the projected portion 1 lb on the bottom surface.
- the first surface 1 la of the metal block 11 is positioned immediately above the semiconductor chips 3 , and is in close proximity with the semiconductor chips 3 with the sealing material 8 and the wiring member 7 therebetween. For this reason, heat generated by the semiconductor chips 3 is transferred to the metal block 11 via the sealing material 8 and the wiring members 7 . As heat is transferred from the semiconductor chips 3 to the second electrode plate 10 via the metal block 11 , heat can be dissipated to the outside. Using arrows, FIG. 2 shows paths in which heat is dissipated from the semiconductor chips 3 in the present embodiment. As shown in FIG. 2 , heat is dissipated from not only the first electrode plate 2 , to which the semiconductor chips 3 are joined, but also from the second electrode plate 10 via the metal block 11 , as described above. As a result, it is possible to achieve better heat dissipation than in the past.
- the distance between the metal block 11 and the semiconductor chips 3 be as small as possible, so that heat can be efficiently dissipated to the outside via the metal block 11 .
- the amount of the sealing material 8 inside the enclosure is kept to a minimum amount required to sufficiently insulate the conductive posts 6 and the printed boards 5 , so that the metal block 11 and the semiconductor chips 3 can be placed as close to each other as possible.
- the height of the wiring members 7 of the present embodiment can be lower than the conventional bonding wiring; this makes it possible to place the metal block 11 and the semiconductor chips 3 even closer to each other.
- the size of the second surface 11 c of the metal block 11 is roughly equal to the size of the surface of the circuit plate 43 of the multilayer substrate 4 , for example.
- FIG. 3 shows the directions of load applied when the power semiconductor module 1 is pressure welded to external conductive plates.
- load is primarily supported by an area surrounded by the dashed line between the second surface 11 c and the projected portion 1 lb of the first surface 1 la, as shown in FIG. 3 .
- it is made less likely that load will apply to the semiconductor chips 3 which are placed farther away from the area surrounded by the dashed line. According to the present embodiment, therefore, it is possible to prevent excessive load from being applied to the semiconductor chips 3 .
- the metal block 11 is shaped in a conical frustum, so as to allow the semiconductor chips 3 to dissipate heat while making it less likely that load will apply to the semiconductor chips 3 .
- the shape of the metal block 11 is not limited to a conical frustum in the power semiconductor module of the present invention.
- the metal block 11 is tapered from the first electrode plate to the second electrode plate 10 , so as to allow the semiconductor chips 3 to dissipate heat while making it less likely that load will apply to the semiconductor chips 3 .
- the metal block 11 can be a quadrangular pyramid to fit the outer shape of the enclosure.
- FIG. 4 is a cross-sectional view of a power semiconductor module 20 of Embodiment 2 of the present invention. Components that are identical to the components of the power semiconductor module 1 of Embodiment 1 shown in FIG. 1 are given identical reference characters in FIG. 4 , and duplicate descriptions will be omitted below.
- a metal block 21 of the power semiconductor module 20 in FIG. 4 is a combination of a conical frustum 21 a at the center and conical frustums 21 b on the peripheral sides, and is connected to a second electrode plate 10 at a plurality of points. All other structures are identical to the structures of the power semiconductor module 1 shown in FIG. 1 . Since the metal block 21 is in contact with the second electrode plate 10 at a plurality of points, heat dissipation from semiconductor chips 3 is better with the metal block 21 than with the metal block 11 shown in FIG. 1 . Additionally, the metal block 21 has trough portions 21 c between the conical frustum 21 a at the center and the conical frustums 21 b on the peripheral sides.
- the metal block 21 in FIG. 4 also allows heat dissipation from the semiconductor chips 3 while making it less likely that load will apply to the semiconductor chips 3 .
- FIG. 5 shows a cross-sectional view of a power semiconductor module 30 of Embodiment 3 of the present invention.
- Components that are identical to the components of the power semiconductor module 1 of Embodiment 1 shown in FIG. 1 are given identical reference characters in FIG. 5 , and duplicate descriptions will be omitted below.
- a metal block 31 of the power semiconductor module 30 in FIG. 5 is a combination of a cylinder 31 a and conical frustums 31 b . All other structures are identical to the structures of the power semiconductor module 1 shown in FIG. 1 .
- the metal block 31 in FIG. 5 also allows heat dissipation from semiconductor chips 3 while making it less likely that load will apply to the semiconductor chips 3 .
- Embodiment 4 of the power semiconductor module of the present invention will be described using FIGS. 6A to 6C .
- a plurality of power semiconductor modules 1 , 20 , or 30 of Embodiments 1 to 3 are prepared, and a cooling plate 61 on which such power semiconductor modules can be mounted is prepared ( FIG. 6A ).
- the power semiconductor modules 1 (or 20 or 30 ) (three units in FIGS. 6B to 6C ) are mounted on the cooling plate 61 .
- an external electrode 62 to which second electrode plates 10 of the mounted power semiconductor modules 1 (or 20 or 30 ) are electrically and physically connected, is prepared ( FIG. 6B ).
- a power semiconductor module 40 ( FIG. 6C ) is formed. Since the power semiconductor module 40 is formed by connecting three units of the power semiconductor modules 1 (or 20 or 30 ) in parallel, the rated current can be increased more than with one unit of the power semiconductor module 1 (or 20 or 30 ).
- Embodiment 5 of the power semiconductor module of the present invention will be described using FIG. 7 .
- a power semiconductor module 50 is formed by stacking and pressure welding a plurality (three in the illustrated example) of power semiconductor modules 1 , 20 , or 30 of Embodiments 1 to 3.
- the power semiconductor modules are connected in series to form one power semiconductor module 50 . Since the power semiconductor module 50 shown in FIG. 7 is formed by connecting three units of power semiconductor modules 1 (or 20 or 30 ) in parallel, the rated current can be increased more than with one unit of the power semiconductor module 1 (or 20 or 30 ).
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Abstract
Description
- 1. Technical Field
- The present invention relates to a power semiconductor module.
- 2. Background Art
- Some flat semiconductor devices seek to achieve downsizing and reduced impedance of the wiring by connecting the electrodes to external circuits by pressure welding. Such flat semiconductor devices are described in
Patent Document 1, for example. -
FIG. 8 shows an example of a flat semiconductor device in a cross-sectional view. A power semiconductor module 101 is equipped with ametal electrode plate 102.Semiconductor chips 103 are electrically and physically connected on theelectrode plate 102. In the illustrated example, thesemiconductor chips 103 are power MOSFETs, and are provided in a plurality of units on theelectrode plate 102. A drain electrode formed on the reverse surface of each of thesemiconductor chips 103 is joined to theelectrode plate 102 by a joining material not shown in the diagram, such as solder. - In addition to the
semiconductor chips 103, amultilayer substrate 104 is joined on theelectrode plate 102. Themultilayer substrate 104 is constituted by: aninsulating plate 141, ametal plate 142, and acircuit plate 143. Themetal plate 142 is provided on one surface of theinsulating plate 141 and joined to the multilayer substrate by a joining material not shown in the diagram, such as solder. Thecircuit plate 143 is provided on the other surface of theinsulating plate 141 and forms prescribed circuits. - Additionally, the bottom surface of a
metal block 110 is electrically and physically connected to thecircuit plate 143 of themultilayer substrate 104. The top surface of themetal block 110 protrudes out of acover 111, and also serves as an electrode of the power semiconductor module 101. Thesemiconductor chips 103 and themultilayer substrate 104 are sealed by a sealingmaterial 108, such as a thermosetting resin. - In order to electrically connect the
semiconductor chip 103 and themultilayer substrate 104, a source electrode formed on the front surface of thesemiconductor chip 103 is connected to thecircuit plate 143 by bondingwiring 107. Additionally, a gate electrode formed on the front surface of thesemiconductor chip 103 is connected to thecircuit plate 143 by thebonding wiring 107. - The power semiconductor module 101 shown in
FIG. 8 is not independently insulated from the outside, and therefore requires a device on which the power semiconductor module 101 is installed to provide an insulating function to the power semiconductor module 101. In other words, the power semiconductor module 101 is a non-insulated power semiconductor module. - When current is passed through the conventional power semiconductor module 101, heat generated from the
semiconductor chips 103 is predominantly dissipated through theelectrode plate 102. The reason for this is that heat dissipation from the front surfaces of thesemiconductor chips 103 on the side opposite to theelectrode plate 102 contributes very little to the overall heat dissipation, due to the large thermal resistance of the sealingmaterial 108 and thebonding wiring 107. This has limited the extent to which heat is dissipated from thesemiconductor chips 103. - Flat type welding structure packages are designed to establish a contact between an electrode layer on the top surface of a semiconductor element provided on a substrate and a contact terminal. In one such flat type welding structure package, a thermal stress mitigating member is inserted between the contact terminal and the semiconductor element (Patent Document 2). The power semiconductor module described in
Patent Document 2 is able to dissipate heat generated by the semiconductor element from not only the substrate but also the contact terminal, and is therefore considered to be more advanced than the power semiconductor module ofPatent Document 1. - However, with respect to the power semiconductor module described in
Patent Document 2, linear load from the contact terminal is exerted on the semiconductor element when the power semiconductor module is undergoes pressure welding, thus posing the risk that excessive load may be applied to the semiconductor element. - Patent Document 1: Japanese Patent Application Laid-Open Publication H1-122146
- Patent Document 2: Japanese Patent Application Laid-Open Publication 2013-149762
- The present invention aims to effectively solve the problems described above. The objective of the present invention is to provide a power semiconductor module capable of effectively dissipating heat from the top and bottom electrodes, while preventing excessive load from being applied to the semiconductor chip when the power semiconductor module is used.
- Additional or separate features and advantages of the invention will be set forth in the descriptions that follow and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
- To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in one aspect, the present disclosure provides a power semiconductor module, including: a frame made of an insulator and having a bottom opening and a top opening; a first electrode plate made of a metal and fixed in the bottom opening in the frame; a semiconductor element having a front surface electrode and a reverse surface electrode, the reverse surface electrode being electrically and physically connected to a principal surface of the first electrode plate; a multilayer substrate comprising a circuit plate, an insulating plate, and a metal plate stacked together, the metal plate being fixed to the principal surface of the first electrode plate; a wiring member that electrically connects the front surface electrode of the semiconductor element to the circuit plate of the multilayer substrate; a second electrode plate made of a metal and fixed in the top opening in the frame; and a metal block that has a first surface having a protrusion and a second surface opposite thereto and that tapers from the first surface to the second surface, the protrusion being electrically and physically connected to the circuit plate of the multilayer substrate, and the second surface of the metal block being electrically and physically connected to the second electrode plate.
- According to the power semiconductor module in one aspect of the present invention, since the metal block is tapered, heat can be dissipated from the front surfaces of the semiconductor chips via the metal block. Additionally, the power semiconductor module is capable of preventing a linear load from being applied to the semiconductor chips, thereby achieving a reliable power semiconductor module.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the invention as claimed.
-
FIG. 1 is a cross-sectional view of a power semiconductor module ofEmbodiment 1 of the present invention. -
FIG. 2 is a cross-sectional view showing paths in which heat is dissipated in the power semiconductor module ofFIG. 1 . -
FIG. 3 is a cross-sectional view showing directions of load application in the power semiconductor module ofFIG. 1 . -
FIG. 4 is a cross-sectional view of a power semiconductor module ofEmbodiment 2 of the present invention. -
FIG. 5 is a cross-sectional view of a power semiconductor module ofEmbodiment 3 of the present invention. -
FIGS. 6A to 6C are perspective views for describing a power semiconductor module ofEmbodiment 4 of the present invention. -
FIG. 7 is a front view of a power semiconductor module ofEmbodiment 5 of the present invention. -
FIG. 8 is a cross-sectional view of a conventional power semiconductor module. - Embodiments of the power semiconductor module of the present invention will be described below in detail with reference to diagrams. Note that the expression, “electrically and physically connected,” used in the description of this application is not limited to cases where the applicable objects are directly connected to each other, but also includes cases where the applicable objects are connected via conductive materials such as solder or metal sintering materials.
- A
power semiconductor module 1 ofEmbodiment 1 of the present invention, shown as a cross-sectional view inFIG. 1 , has a substantially cylindrical outer shape (seeFIG. 6A ). Thepower semiconductor module 1 is equipped with: aframe 9; afirst electrode plate 2;semiconductor chips 3 that serve as semiconductor elements; amultilayer substrate 4;wiring members 7; asecond electrode plate 10; and ametal block 11. Thefirst electrode plate 2 is an electrode that is pressure welded to an external conductive plate to pass current when thepower semiconductor module 1 of the present embodiment is used. Thefirst electrode plate 2 has a projectedportion 2 a at the center of the outer surface so as to be aligned with an external conductive plate. The projectedportion 2 a with a height of approximately 1 mm can secure sufficient contact. - The
semiconductor chips 3 are fixed on a principal surface of thefirst electrode plate 2. Thesemiconductor chip 3 has a front electrode and a reverse electrode. In the present embodiment, thesemiconductor chip 3 is a diode chip. Note, however, that this does not exclude the possibility of employing a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET for thesemiconductor chip 3. A semiconductor element made of silicon carbide (SiC) or silicon is employed for thesemiconductor chip 3. A semiconductor element made of silicon carbide is especially preferable, since such a semiconductor element has a wide band gap and high heat resistance, which allows for high-temperature operation. -
FIG. 1 shows sixsemiconductor chips 3 in total, or threesemiconductor chips 3 respectively on the left and right sides of the page, with themultilayer substrate 4 therebetween. In addition to those shown in the diagram, a plurality ofsemiconductor chips 3 are provided around themultilayer substrate 4. The reverse surface electrode (anode electrode, for example) of thesemiconductor chip 3 is electrically and physically connected to thefirst electrode plate 2 by a conductive joining material not shown in the diagram, such as solder or a metal sintering material. - As shown in
FIG. 1 , themultilayer substrate 4 is configured by stacking together acircuit plate 43, an insulatingplate 41, and ametal plate 42. The insulatingplate 41 is an insulating plate made of an insulating ceramic, such as aluminum nitride or aluminum oxide, for example, and themetal plate 42 and thecircuit plate 43 are made of copper, for example. A DCB (Direct Copper Bond) substrate or the like formed by directly joining the insulatingplate 41, themetal plate 42, and thecircuit plate 43 can be used as themultilayer substrate 4. In addition, themultilayer substrate 4 can be configured by joining thecircuit plate 43 and themetal plate 42 to the insulatingplate 41 using a joining material not shown in the diagram. Themetal plate 42 of themultilayer substrate 4 is in contact with a principal surface of thefirst electrode plate 2, and is fixed to thefirst electrode plate 2 with a joining material not shown in the diagram. - The
wiring members 7 face ends of themultilayer substrate 4, as well as thesemiconductor chips 3. Thewiring member 7 electrically connects a front surface electrode (a cathode electrode, for example) of thesemiconductor chip 3 and thecircuit plate 43 of themultilayer substrate 4. - The
wiring member 7 is equipped with a printedboard 5 andconductive posts 6. The printedboard 5 has, on at least one surface of an insulating plate thereof, a metal film for wiring made of a conductive metal such as copper or aluminum. It is preferable that copper be used for the metal film to achieve low inductance. If thesemiconductor chip 3 is a switching element and has a plurality of front surface electrodes on the front surface of thesemiconductor chip 3, the printedboard 5 has at least two types of metal films for wiring to accommodate these electrodes. - The insulating plate of the printed
board 5 may be a rigid substrate made of a glass epoxy material, a flexible substrate made of a polyimide material, or a ceramic substrate. The metal film of the printedboard 5 can be formed on one surface of the insulating plate, or on both surfaces. - One end of the
conductive post 6 is electrically and physically connected to the metal film of the printedboard 5 by a conductive joining material such as solder (not shown in the diagram). The other end of theconductive post 6 is electrically and physically connected to the front surface electrode of thesemiconductor chip 3 or thecircuit plate 43 by a conductive joining material such as solder (not shown in the diagram). - The
conductive post 6 is made of a metal material with good conductivity, such as copper. Additionally, metal plating can be applied to the surface, if needed. The outer shape of theconductive post 6 can be a cylinder, a cuboid, or the like. Note that the bottom surface of theconductive post 6 must be smaller than the front surface electrode of thesemiconductor chip 3. The diameter of theconductive post 6 is approximately 0.5 mm, for example. - Further, any number of
conductive posts 6 can be installed on each of thesemiconductor chips 3, and it is also possible to join a plurality ofconductive posts 6 to one electrode. - In other words, the
power semiconductor module 1 of the present embodiment is configured with thewiring members 7 equipped with the printedboards 5 and theconductive posts 6 in lieu of thebonding wiring 107 used in the conventional power semiconductor module 101 shown inFIG. 8 . - The
wiring members 7 allow the cross section of the wiring to be thicker than thebonding wiring 107. Additionally, the length of wiring can be shortened. For these reasons, with thepower semiconductor module 1 of the present embodiment, it is possible to lower inductance than with the conventional power semiconductor module 101. For the same reasons, it is possible to realize a larger current flow in the semiconductor chips and an increase in current density. Further, thewiring members 7 are superior to the bonding wiring with respect to heat dissipation from thesemiconductor chips 3. - Additionally, since the
wiring members 7 are physically connected to thesemiconductor chips 3 using a joining material, thewiring members 7 are adhered more securely to thesemiconductor chips 3 than the bonding wiring and are therefore more resistant to thermal stress. This makes it possible to enhance the reliability of thepower semiconductor module 1. - Further, the
wiring members 7 can reduce the height or the amount of the sealingmaterial 8 filled inside the enclosure than thebonding wiring 107 can. This makes it possible to lower the cost of thepower semiconductor module 1, and enhance the reliability thereof. - The
power semiconductor module 1 uses thewiring members 7, each of which is formed by joining the printedboard 5 and theconductive posts 6 into an integral whole, thereby allowing easy assembly and simplifying the steps of manufacturing thepower semiconductor module 1. - The
wiring members 7 are sealed by a sealingmaterial 8 made of a thermosetting resin. It is preferable that the amount of the sealingmaterial 8 injected into the enclosure be an amount that covers up to approximately 1 to 3 mm, most preferably 2 mm, above the top ends of the printedboards 5 and theconductive posts 6 to ensure that the printedboards 5 and theconductive posts 6 are insulated. - A sealing material made of a thermosetting resin has a higher thermal resistance and pressure resistance than a sealing material made of gel, and is therefore preferable for the sealing
material 8. Specifically, an epoxy resin can be used for the sealingmaterial 8. Additionally, it is preferable that a sealing material made of a resin to which a filler with high heat conductivity is added be used, in order to increase heat dissipation. Aluminum, boron nitride, or the like may be employed as a filler, for example. - In the
power semiconductor module 1 of the present embodiment, a recessedportion 2 b is provided at the center of the surface of thefirst electrode plate 2. Themultilayer substrate 4 is disposed in the recessedportion 2 b to align the heights of thesemiconductor chips 3 and thecircuit plate 43. This is done so that conductive posts with the same length can be used for theconductive posts 6 of thewiring members 7, and so that the printedboards 5 can be disposed substantially parallel to thefirst electrode plate 2 and themultilayer substrate 4. - The
frame 9 is a hollow cylinder, and has abottom opening 9 a to which thefirst electrode plate 2 is joined by an adhesive agent not shown in the diagram. Additionally, thesecond electrode plate 10 is joined to atop opening 9 b of theframe 9 with an adhesive agent not shown in the diagram. A recessed and projectedportion 9 c is provided on the outer surface of theframe 9 of the present embodiment to secure a sufficient creepage distance in the event a high voltage is applied between thefirst electrode plate 2 and thesecond electrode plate 10. - The enclosure of the
power semiconductor module 1 is constituted by theframe 9, thefirst electrode plate 2, and thesecond electrode plate 10, and houses thesemiconductor chips 3, themultilayer substrate 4, thewiring members 7, and themetal block 11. - The
second electrode plate 10 is an electrode that is pressure welded to an external conductive plate to pass current when thepower semiconductor module 1 of the present embodiment is used, in a manner similar to thefirst electrode plate 2. Thesecond electrode plate 10 has a projectedportion 10 a at the center of the outer surface, so as to be aligned with an external conductive plate. The projectedportion 10 a with a height of approximately 1 mm can ensure sufficient contact. - The
metal block 11 is provided to allow current to flow from themultilayer substrate 4 to thesecond electrode plate 10 inside the enclosure. Themetal block 11 is made of a metal material with good heat conductivity and electrical conductivity, such as copper. Additionally, a projectedportion 1 lb is provided on afirst surface 11 a of themetal block 11. The projectedportion 1 lb is connected electrically and physically to thecircuit plate 43 of themultilayer substrate 4 by a conductive joining material not shown in the diagram, such as solder. Further, asecond surface 11 c of themetal block 11 is electrically and physically connected to thesecond electrode plate 10 by a joining material such as solder, screws, or the like. - The
first surface 1 la of themetal block 11 is adhered to the sealingmaterial 8, which covers the printedboards 5 and theconductive posts 6. Themetal block 11 and thesemiconductor chips 3 are in close proximity to each other, with the sealingmaterial 8 and thewiring members 7 therebetween. In addition, thesecond surface 11 c of themetal block 11 and themultilayer substrate 4 are roughly equal in size. It follows then that themetal block 11 tapers from thefirst surface 11 a to thesecond surface 11 c. More specifically, themetal block 11 of the present embodiment shown inFIG. 1 is a conical frustum provided with the projectedportion 1 lb on the bottom surface. - The
first surface 1 la of themetal block 11 is positioned immediately above thesemiconductor chips 3, and is in close proximity with thesemiconductor chips 3 with the sealingmaterial 8 and thewiring member 7 therebetween. For this reason, heat generated by thesemiconductor chips 3 is transferred to themetal block 11 via the sealingmaterial 8 and thewiring members 7. As heat is transferred from thesemiconductor chips 3 to thesecond electrode plate 10 via themetal block 11, heat can be dissipated to the outside. Using arrows,FIG. 2 shows paths in which heat is dissipated from thesemiconductor chips 3 in the present embodiment. As shown inFIG. 2 , heat is dissipated from not only thefirst electrode plate 2, to which thesemiconductor chips 3 are joined, but also from thesecond electrode plate 10 via themetal block 11, as described above. As a result, it is possible to achieve better heat dissipation than in the past. - It is preferable that the distance between the
metal block 11 and thesemiconductor chips 3 be as small as possible, so that heat can be efficiently dissipated to the outside via themetal block 11. In thepower semiconductor module 1 of the present embodiment, the amount of the sealingmaterial 8 inside the enclosure is kept to a minimum amount required to sufficiently insulate theconductive posts 6 and the printedboards 5, so that themetal block 11 and thesemiconductor chips 3 can be placed as close to each other as possible. Furthermore, the height of thewiring members 7 of the present embodiment can be lower than the conventional bonding wiring; this makes it possible to place themetal block 11 and thesemiconductor chips 3 even closer to each other. - The size of the
second surface 11 c of themetal block 11 is roughly equal to the size of the surface of thecircuit plate 43 of themultilayer substrate 4, for example. Using arrows,FIG. 3 shows the directions of load applied when thepower semiconductor module 1 is pressure welded to external conductive plates. With respect to themetal block 11, load is primarily supported by an area surrounded by the dashed line between thesecond surface 11 c and the projectedportion 1 lb of thefirst surface 1 la, as shown inFIG. 3 . In other words, it is made less likely that load will apply to thesemiconductor chips 3, which are placed farther away from the area surrounded by the dashed line. According to the present embodiment, therefore, it is possible to prevent excessive load from being applied to thesemiconductor chips 3. - The
metal block 11 is shaped in a conical frustum, so as to allow thesemiconductor chips 3 to dissipate heat while making it less likely that load will apply to thesemiconductor chips 3. Note, however, that the shape of themetal block 11 is not limited to a conical frustum in the power semiconductor module of the present invention. Various modifications are possible, provided that themetal block 11 is tapered from the first electrode plate to thesecond electrode plate 10, so as to allow thesemiconductor chips 3 to dissipate heat while making it less likely that load will apply to thesemiconductor chips 3. For example, if the enclosure of the power semiconductor module is a cuboid, themetal block 11 can be a quadrangular pyramid to fit the outer shape of the enclosure. -
FIG. 4 is a cross-sectional view of apower semiconductor module 20 ofEmbodiment 2 of the present invention. Components that are identical to the components of thepower semiconductor module 1 ofEmbodiment 1 shown inFIG. 1 are given identical reference characters inFIG. 4 , and duplicate descriptions will be omitted below. - A
metal block 21 of thepower semiconductor module 20 inFIG. 4 is a combination of aconical frustum 21 a at the center andconical frustums 21 b on the peripheral sides, and is connected to asecond electrode plate 10 at a plurality of points. All other structures are identical to the structures of thepower semiconductor module 1 shown inFIG. 1 . Since themetal block 21 is in contact with thesecond electrode plate 10 at a plurality of points, heat dissipation fromsemiconductor chips 3 is better with themetal block 21 than with themetal block 11 shown inFIG. 1 . Additionally, themetal block 21 hastrough portions 21 c between theconical frustum 21 a at the center and theconical frustums 21 b on the peripheral sides. The low rigidity of these portions makes it less likely that load will apply to thesemiconductor chips 3. As a result, themetal block 21 inFIG. 4 also allows heat dissipation from thesemiconductor chips 3 while making it less likely that load will apply to thesemiconductor chips 3. -
FIG. 5 shows a cross-sectional view of apower semiconductor module 30 ofEmbodiment 3 of the present invention. Components that are identical to the components of thepower semiconductor module 1 ofEmbodiment 1 shown inFIG. 1 are given identical reference characters inFIG. 5 , and duplicate descriptions will be omitted below. - A
metal block 31 of thepower semiconductor module 30 inFIG. 5 is a combination of acylinder 31 a andconical frustums 31 b. All other structures are identical to the structures of thepower semiconductor module 1 shown inFIG. 1 . Themetal block 31 inFIG. 5 also allows heat dissipation fromsemiconductor chips 3 while making it less likely that load will apply to thesemiconductor chips 3. -
Embodiment 4 of the power semiconductor module of the present invention will be described usingFIGS. 6A to 6C . First, a plurality ofpower semiconductor modules Embodiments 1 to 3 are prepared, and acooling plate 61 on which such power semiconductor modules can be mounted is prepared (FIG. 6A ). Next, the power semiconductor modules 1 (or 20 or 30) (three units inFIGS. 6B to 6C ) are mounted on thecooling plate 61. Additionally, anexternal electrode 62, to whichsecond electrode plates 10 of the mounted power semiconductor modules 1 (or 20 or 30) are electrically and physically connected, is prepared (FIG. 6B ). Then, by installing theexternal electrode 62 on the power semiconductor modules 1 (or 20 or 30) by pressure welding, a power semiconductor module 40 (FIG. 6C ) is formed. Since thepower semiconductor module 40 is formed by connecting three units of the power semiconductor modules 1 (or 20 or 30) in parallel, the rated current can be increased more than with one unit of the power semiconductor module 1 (or 20 or 30). -
Embodiment 5 of the power semiconductor module of the present invention will be described usingFIG. 7 . Apower semiconductor module 50 is formed by stacking and pressure welding a plurality (three in the illustrated example) ofpower semiconductor modules Embodiments 1 to 3. The power semiconductor modules are connected in series to form onepower semiconductor module 50. Since thepower semiconductor module 50 shown inFIG. 7 is formed by connecting three units of power semiconductor modules 1 (or 20 or 30) in parallel, the rated current can be increased more than with one unit of the power semiconductor module 1 (or 20 or 30). - The power semiconductor module according to various aspects of the present invention has been described in detail above using diagrams and embodiments, but the present invention is not limited to the above embodiments and diagrams, and can be implemented by appropriately modifying the above embodiments without departing from the spirit thereof.
- It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover modifications and variations that come within the scope of the appended claims and their equivalents. In particular, it is explicitly contemplated that any part or whole of any two or more of the embodiments and their modifications described above can be combined and regarded within the scope of the present invention.
Claims (11)
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JP2014104366A JP6248803B2 (en) | 2014-05-20 | 2014-05-20 | Power semiconductor module |
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US9209099B1 US9209099B1 (en) | 2015-12-08 |
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Cited By (3)
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US20170170150A1 (en) * | 2015-12-14 | 2017-06-15 | Kabushiki Kaisha Toshiba | Semiconductor module and semiconductor device |
DE102018133089A1 (en) * | 2018-12-20 | 2020-06-25 | Danfoss Silicon Power Gmbh | Semiconductor module with a semiconductor and a housing partially housing the semiconductor |
CN117766470A (en) * | 2024-02-20 | 2024-03-26 | 北京怀柔实验室 | Packaging structure and packaging method of semiconductor device |
Families Citing this family (1)
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JP6330436B2 (en) * | 2014-04-01 | 2018-05-30 | 富士電機株式会社 | Power semiconductor module |
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JP3003452B2 (en) | 1993-04-08 | 2000-01-31 | 富士電機株式会社 | Conductive contact structure of two conductors |
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JP3228043B2 (en) | 1994-03-24 | 2001-11-12 | 富士電機株式会社 | Parallel connection structure of flat semiconductor switches |
JPH10294421A (en) | 1997-04-17 | 1998-11-04 | Hitachi Ltd | Multichip module and its manufacture |
JP3352918B2 (en) * | 1997-09-17 | 2002-12-03 | 株式会社東芝 | Electronic components |
JP3726767B2 (en) * | 2002-03-28 | 2005-12-14 | 株式会社日立製作所 | Semiconductor module |
JP3960230B2 (en) | 2003-01-24 | 2007-08-15 | 富士電機ホールディングス株式会社 | Semiconductor module, method for manufacturing the same, and switching power supply device |
JP2004296764A (en) * | 2003-03-27 | 2004-10-21 | Toshiba Corp | Stack for flat semiconductor element and power converter using it |
JP4294405B2 (en) * | 2003-07-31 | 2009-07-15 | 株式会社ルネサステクノロジ | Semiconductor device |
JP4637784B2 (en) | 2006-04-14 | 2011-02-23 | 三菱電機株式会社 | Power semiconductor device |
JP2009105389A (en) * | 2007-10-02 | 2009-05-14 | Rohm Co Ltd | Power module |
JP5083226B2 (en) | 2009-01-14 | 2012-11-28 | 富士電機株式会社 | Semiconductor device and manufacturing method thereof |
JP4947169B2 (en) * | 2010-03-10 | 2012-06-06 | オムロン株式会社 | Semiconductor device and microphone |
KR20130055867A (en) * | 2011-11-21 | 2013-05-29 | 한국전자통신연구원 | Piezoelectric micro power generator and fabrication method thereof |
JP2012074730A (en) | 2011-12-07 | 2012-04-12 | Mitsubishi Electric Corp | Power semiconductor module |
JP5899952B2 (en) | 2012-01-19 | 2016-04-06 | 株式会社明電舎 | Semiconductor module |
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JP6330436B2 (en) * | 2014-04-01 | 2018-05-30 | 富士電機株式会社 | Power semiconductor module |
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US20170170150A1 (en) * | 2015-12-14 | 2017-06-15 | Kabushiki Kaisha Toshiba | Semiconductor module and semiconductor device |
DE102018133089A1 (en) * | 2018-12-20 | 2020-06-25 | Danfoss Silicon Power Gmbh | Semiconductor module with a semiconductor and a housing partially housing the semiconductor |
CN117766470A (en) * | 2024-02-20 | 2024-03-26 | 北京怀柔实验室 | Packaging structure and packaging method of semiconductor device |
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US9209099B1 (en) | 2015-12-08 |
JP2015220398A (en) | 2015-12-07 |
JP6248803B2 (en) | 2017-12-20 |
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