US20150155226A1 - Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing - Google Patents
Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing Download PDFInfo
- Publication number
- US20150155226A1 US20150155226A1 US14/612,247 US201514612247A US2015155226A1 US 20150155226 A1 US20150155226 A1 US 20150155226A1 US 201514612247 A US201514612247 A US 201514612247A US 2015155226 A1 US2015155226 A1 US 2015155226A1
- Authority
- US
- United States
- Prior art keywords
- attachment area
- lead
- coupler
- lead finger
- finger
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 54
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 42
- 238000004377 microelectronic Methods 0.000 title claims abstract description 22
- 238000009736 wetting Methods 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims description 44
- 230000000873 masking effect Effects 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 238000013508 migration Methods 0.000 claims description 9
- 230000005012 migration Effects 0.000 claims description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 239000004332 silver Substances 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000008393 encapsulating agent Substances 0.000 claims description 5
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims description 2
- 230000000717 retained effect Effects 0.000 claims description 2
- 238000007650 screen-printing Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 10
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- 239000010949 copper Substances 0.000 description 7
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- 239000010410 layer Substances 0.000 description 4
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- 230000005670 electromagnetic radiation Effects 0.000 description 3
- 238000004381 surface treatment Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
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- 235000012431 wafers Nutrition 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910016411 CuxO Inorganic materials 0.000 description 1
- 229920001875 Ebonite Polymers 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
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- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
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Definitions
- the present technology is directed to microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing.
- Flip chip is a method for directly interconnecting semiconductor dies and a substrate with solder balls (or solder bumps). During assembly, solder balls are first deposited onto a semiconductor die. A solder mask is formed on the substrate (e.g., a printed circuit board) to define a plurality of connection sites. The semiconductor die with the solder balls is then flipped over to align the solder balls with corresponding connection sites on the substrate. The solder balls are then reflowed to complete the interconnection.
- solder balls are first deposited onto a semiconductor die.
- a solder mask is formed on the substrate (e.g., a printed circuit board) to define a plurality of connection sites.
- the semiconductor die with the solder balls is then flipped over to align the solder balls with corresponding connection sites on the substrate.
- the solder balls are then reflowed to complete the interconnection.
- solder balls tend to uncontrollably collapse during reflow when the substrate is a lead frame having a plurality of lead fingers.
- the collapsed solder balls may cause various structural, functional, and/or other types of damages to the resulting microelectronic package.
- adjacent solder balls may come in contact with one another to short circuit the semiconductor die and/or the substrate.
- solder mask on the lead frame as on a printed circuit board.
- forming a solder mask on the small lead fingers is difficult, time consuming, and costly. Accordingly, there is a need for improved flip chip techniques that can at least reduce or eliminate the risk of uncontrollable collapse of solder balls during reflow.
- FIGS. 1A-1F are partially schematic, cross-sectional views of a semiconductor die and/or a portion of a lead frame undergoing a process to form a microelectronic package in accordance with embodiments of the technology.
- FIGS. 2A-2E are partially schematic, cross-sectional or plan views of a portion of a lead frame undergoing a process in accordance with additional embodiments of the technology.
- FIGS. 3A-3C are partially schematic and cross-sectional views of a portion of a lead frame undergoing a process in accordance with further embodiments of the technology.
- FIGS. 4A and 4B are partially schematic, cross-sectional views of a portion of a lead frame undergoing a process in accordance with yet additional embodiments of the technology.
- FIGS. 5A and 5B are cross-sectional images of chip-on-lead packages taken during experiments in accordance with several embodiments of the technology.
- microelectronic packages include microelectronic circuits or components, thin-film recording heads, data storage elements, microfluidic devices, and other components manufactured on microelectronic substrates.
- Microelectronic substrates can include semiconductor pieces (e.g., doped silicon wafers or gallium arsenide wafers), non-conductive pieces (e.g., various ceramic substrates), or conductive pieces (e.g., metal or metal alloy). Many of the details regarding certain embodiments are also described below with reference to semiconductor dies.
- semiconductor die is used throughout to include a variety of articles of manufacture, including, for example, individual integrated circuit dies, imager dies, sensor dies, and/or dies having other semiconductor features.
- FIGS. 1A-1F are partially schematic, cross-sectional views of a semiconductor die and/or a portion of a lead frame undergoing a process to form a microelectronic package in accordance with embodiments of the technology.
- an initial stage of the process can include attaching a plurality of electrical couplers 104 to ball/bump sites 102 of a semiconductor die 100 , as indicated by the arrows 103 .
- the electrical couplers 104 prior to attachment and/or plating are shown in phantom lines for clarity. In the illustrated embodiment, two electrical couplers 104 are shown for illustration purposes. In other embodiments, one, three, or any other suitable numbers of electrical couplers may be used.
- the semiconductor die 100 can include any suitable type of integrated circuit device.
- the semiconductor die 100 can include a plurality of metal-oxide-semiconductor field-effect transistors (“MOSFETs”), junction gate field-effect transistors (“JFETs”), insulated gate bipolar transistors, capacitors, and/or other suitable electrical components.
- MOSFETs metal-oxide-semiconductor field-effect transistors
- JFETs junction gate field-effect transistors
- insulated gate bipolar transistors insulated gate bipolar transistors
- capacitors and/or other suitable electrical components.
- the semiconductor die 100 can include other suitable types of electrical and/or mechanical components.
- the electrical couplers 104 can include solder balls attached to the ball/bump sites 102 using tack welding, partial reflow, and/or other suitable techniques. In other embodiments, the electrical couplers 104 can include solder bumps plated onto and/or otherwise formed on the ball/bump sites 102 .
- the term “solder” generally refers to a fusible metal alloy with a melting point in the range of about 90° C. to 450° C. Examples of a solder include alloys of at least some of copper (Cu), tin (Sn), lead (Pb), silver (Ag), zinc (Zn), and/or other suitable metals.
- the electrical couplers 104 can also include other suitable electrically conductive couplers.
- FIGS. 1B-1D illustrate stages of forming an attachment area 112 and a non-attachment area 113 on a lead frame 105 in accordance with embodiments of the technology.
- the lead frame 105 can include a plurality of lead fingers 106 .
- a first lead finger 106 a is shown juxtaposed with a second lead finger 106 b for illustration purposes.
- the lead frame 105 can also include a die paddle (not shown), a dam bar (not shown), other number of lead fingers, and/or other suitable components.
- the lead fingers 106 can include a first surface 107 a opposite a second surface 107 b.
- the first surface 107 a may be configured to interface with the semiconductor die 100 ( FIG. 1A )
- the second surface 107 b may be configured to interface with an external device (e.g., a printed circuit board, not shown).
- the process includes a deposition stage in which a masking material 108 is formed on the first surface 107 a of the lead fingers 106 .
- the masking material 108 can include a photoresist deposited on the lead fingers 106 via a spin-on operation and/or other suitable techniques.
- the photoresist can include a tape of a dry film photoresist that may be laminated onto and/or otherwise attached to the lead fingers 106 .
- the term “photoresist” generally refers to a material that can be chemically modified when exposed to electromagnetic radiation.
- the term encompasses both positive photoresist (i.e., soluble when activated by the electromagnetic radiation) and negative photoresist (i.e., insoluble when activated by the electromagnetic radiation).
- the masking material 108 can also include hard rubber and/or other suitable types of “hard” masking materials.
- FIG. 1C illustrates a material removal stage of the process, in which a portion of the masking material 108 is removed to form a plurality of openings 110 .
- the material removal stage can include patterning a photoresist based on a desired configuration using photolithography and/or other suitable techniques.
- the openings 110 in the masking material 108 may also be formed using laser ablation, wet etching, dry etching, and/or other suitable techniques.
- forming the attachment area 112 includes depositing a wetting material 111 into the openings 110 of the masking material 108 .
- the wetting material 111 can include silver (Ag), a nickel (Ni)/gold (Au) alloy, and/or other suitable metal or metal alloys that exhibit first wetting characteristics with regard to the electrical couplers 104 ( FIG. 1A ) during reflow. As used herein, wetting characteristics are represented by a wetting contact angle.
- the wetting contact angle between the wetting material 111 and the electrical couplers 104 during reflow can be less than about 90°, indicating generally wettable characteristics. In other embodiments, the wetting contact angle can be less than about 60°, about 45°, about 30°, and/or other suitable values.
- the process can include removing the masking material 108 (shown in phantom lines for clarity) and any excess wetting material 111 .
- the exposed portions of the first surface 107 a can be treated to form the non-attachment area 113 that has second wetting characteristics.
- the exposed portions of the first surface 107 a may be oxidized by contacting an oxidizing chemical solution (e.g., sulfuric acid, nitric acid, hydrochloric acid, and/or a combination thereof), heating the lead fingers 106 in air, by contacting with oxygen plasma, and/or by using other suitable techniques.
- the exposed portions of the first surface 107 a may be treated using other suitable surface treatment techniques.
- the non-attachment area 113 can be generally non-wettable to the electrical couplers 104 ( FIG. 1A ) during reflow.
- a contact angle between the non-attachment area 113 and the electrical couplers 104 during reflow can be greater than about 90°, indicating generally non-wettable characteristics.
- the non-wetting contact angle can be greater than about 120°, about 135°, and/or other suitable values.
- FIG. 1E illustrates another stage of the process in which the semiconductor die 100 is attached to the lead frame 105 with the electrical couplers 104 generally aligned and in contact with the attachment area 112 of the lead fingers 106 .
- the lead frame 105 with the attached semiconductor die 100 can then be reflowed, for example, in a reflow chamber (not shown), and heat (as represented by the arrows 116 ) and/or other suitable forms of energy can be applied.
- the electrical couplers 104 can be at least partially melted in order to join the lead frame 105 and the semiconductor die 100 together when subsequently cooled.
- the lead fingers 106 with the attachment area 112 and the non-attachment area 113 can enable a controllable collapse of the electrical couplers 104 during the reflow operation without using a solder mask. As a result, the risk of various structural and/or electrical damages to the resulting microelectronic package may be reduced and/or avoided.
- the attachment area 112 is generally wettable while the non-attachment area 113 is generally non-wettable to the electrical couplers 104 .
- the wettability differential between the attachment area 112 and the non-attachment area 113 can at least limit or substantially eliminate migration or spreading of the reflowed electrical couplers 104 . It is believed that the reflowed electrical couplers 104 may not readily bond to the non-attachment area 113 due to a lack of surface contact. As a result, the reflowed electrical couplers 104 tend to be confined in the attachment area 112 .
- a wettability differential between the attachment area 112 and the non-attachment area 113 may be adjusted based on a target degree of migration of the reflowed electrical couplers 104 .
- a target degree of migration of the reflowed electrical couplers 104 it is believed that the larger the wettability differential, the smaller the degree of migration, and vice versa.
- a large wettability differential e.g., a contact angle difference of greater than about 20°, about 30°, or about 40°
- a small wettability differential e.g., a contact angle difference of less than about 15°, about 10°, or about 5°
- a small wettability differential e.g., a contact angle difference of less than about 15°, about 10°, or about 5°
- an underfill material 117 may be deposited between the semiconductor die 100 and the lead fingers 106 .
- the underfill material 117 may at least partially encapsulate the electrical couplers 104 .
- the underfill material 117 may be omitted.
- the semiconductor die 100 and the lead frame 105 can also be encapsulated by an encapsulant 120 (e.g., an epoxy or other types of molding compounds).
- the semiconductor die 100 is substantially encapsulated in the encapsulant 120 .
- the lead fingers 106 are partially encapsulated in the encapsulant 120 with the second surfaces 107 b exposed for interconnecting to external devices (not shown).
- the lead frame 105 may include lead fingers 106 that extend beyond the encapsulant 120 .
- the semiconductor die 100 and the lead frame 105 may be encapsulated in other suitable configurations.
- forming the attachment area 112 and the non-attachment area 113 may include other processing operations.
- FIGS. 2A-2E illustrate another process that does not include depositing a wetting material.
- an initial stage of the process can include depositing the masking material 108 on the first surface 107 a of the lead fingers 106 .
- another stage of the process can include patterning the masking material 108 to define a covered portion 109 a and an exposed portion 109 b of the first surface 107 a of the lead fingers 106 .
- the covered portion 109 a generally corresponds to the attachment area 112
- the exposed portion 109 b generally corresponds to the non-attachment area 113 .
- the covered portion 109 a is illustratively shown to have a generally circular shape. In other embodiments, the covered portion 109 a may have a rectangular, an oval, a trapezoidal, and/or other suitable shapes.
- the exposed portion 109 b may then be treated to achieve the target wettability characteristics while the covered portion 109 a is protected from the treatment by the remaining masking material 108 .
- the exposed portion 109 b may be treated in a generally similar manner, as described above with reference to FIG. 1D .
- the exposed portion 109 b may be treated using other suitable techniques such that the exposed portion 109 b is generally non-wettable to the electrical couplers 104 ( FIG. 1A ) during reflow.
- the exposed area 109 b of the lead fingers 106 may be treated based on a target wettability differential between the attachment area 112 and the non-attachment area 113 .
- the lead frame 105 can include copper (Cu) lead fingers 106 .
- the wettability of the reflowed electric coupler 104 ( FIG. 1A ) to the copper lead fingers 106 may be readily determined.
- a target wettability for the non-attachment area 113 may be derived based on the wettability of the reflowed electric coupler 104 ( FIG. 1A ) to the copper lead fingers 106 and the target wettability differential.
- suitable techniques and/or operation parameters may be selected (e.g., oxygen plasma treatment, heating, etc.) to achieve the target wettability for the non-attachment area 113 .
- another stage of the process can include removing the remaining masking material 108 ( FIGS. 2B and 2C ) to expose the attachment area 112 .
- the lead frame 105 can undergo other suitable processing stages to form the microelectronic package, as described in more detail with reference to FIGS. 1E and 1F .
- FIGS. 3A-3C illustrate another process of forming the attachment area 112 and the non-attachment area 113 using screen printing.
- an initial stage of the process can include placing a stencil 132 proximate the lead fingers 106 .
- the stencil 132 can include apertures 134 generally corresponding to the attachment area 112 .
- the wetting material 111 (represented by the arrows 111 in FIG. 3A ) may be sprayed, printed, and/or otherwise formed on the first surface 107 a of the lead fingers 106 through the apertures 134 of the stencil 132 .
- the process can then include removing the stencil 132 ( FIG. 3B ) from the first surface 107 a of the lead fingers 106 .
- the exposed portion of the first surface 107 a may then optionally undergo surface treatment, as described above with reference to FIG. 1D .
- the lead frame 105 can undergo other suitable processing stages to form the microelectronic package, as described in more detail with reference to FIGS. 1E and 1F .
- FIGS. 4A and 4B illustrate another process for forming the attachment area 112 and the non-attachment area 113 using a preform.
- the process can include attaching a preform 150 to the first surface 107 a of the lead fingers 106 .
- the preform 150 includes a laminated structure with an interface layer 152 and an adhesive layer 156 .
- the interface layer 152 can include a first portion 154 that is wettable to the reflowed electrical couplers 104 ( FIG. 1A ) and a second portion 158 that is generally non-wettable to the reflowed electrical couplers 104 .
- the first portion 154 can include silver (Ag)
- the second portion 158 can include copper oxide (Cu x O).
- the first portion 154 and the second portion 158 generally correspond to the attachment area 112 and the non-attachment area 113 .
- the lead frame 105 with the attached preform 150 may then be optionally cured and/or undergo other suitable processing before being attached to the semiconductor die 100 , as described in more detail with reference to FIGS. 1E and 1F .
- the preform 150 is shown in FIGS. 4A and 4B as having the adhesive layer 156 pre-attached, in other embodiments, the preform 150 may include the interface layer 152 carried by an optional backing layer (not shown) without the adhesive layer 156 . Instead, an adhesive (not shown) may be applied to at least one of the preform 150 and the lead frame 105 before attachment thereof.
- FIGS. 5A and 5B are cross-sectional images of chip-on-lead packages taken during such experiments.
- a semiconductor die 200 with attached solder balls 204 was placed in contact with a lead frame 205 with copper lead fingers 206 that have generally the same regional wettability.
- the semiconductor die 200 and the lead frame 205 were subsequently reflowed.
- the solder balls 206 uncontrollably collapsed during reflow and came in contact with each other.
- a semiconductor die 300 with an attached solder ball 304 was placed in contact with a lead frame 305 with a lead finger 306 processed according to several embodiments of the process described above with reference to FIGS. 1A-1E .
- the lead finger 306 included a contact pad 312 containing silver (Ag) on a portion of the top surface of the lead finger 306 .
- the semiconductor die 300 and the lead frame 305 were subsequently reflowed.
- the solder ball 304 substantially retained its shape and did not significantly migrate away from the contact pad 312 .
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Abstract
Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non- attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.
Description
- The present technology is directed to microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing.
- Flip chip is a method for directly interconnecting semiconductor dies and a substrate with solder balls (or solder bumps). During assembly, solder balls are first deposited onto a semiconductor die. A solder mask is formed on the substrate (e.g., a printed circuit board) to define a plurality of connection sites. The semiconductor die with the solder balls is then flipped over to align the solder balls with corresponding connection sites on the substrate. The solder balls are then reflowed to complete the interconnection.
- One drawback of the foregoing flip chip technique is that the solder balls tend to uncontrollably collapse during reflow when the substrate is a lead frame having a plurality of lead fingers. The collapsed solder balls may cause various structural, functional, and/or other types of damages to the resulting microelectronic package. For example, adjacent solder balls may come in contact with one another to short circuit the semiconductor die and/or the substrate.
- One conventional solution is to form a solder mask on the lead frame as on a printed circuit board. However, forming a solder mask on the small lead fingers is difficult, time consuming, and costly. Accordingly, there is a need for improved flip chip techniques that can at least reduce or eliminate the risk of uncontrollable collapse of solder balls during reflow.
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FIGS. 1A-1F are partially schematic, cross-sectional views of a semiconductor die and/or a portion of a lead frame undergoing a process to form a microelectronic package in accordance with embodiments of the technology. -
FIGS. 2A-2E are partially schematic, cross-sectional or plan views of a portion of a lead frame undergoing a process in accordance with additional embodiments of the technology. -
FIGS. 3A-3C are partially schematic and cross-sectional views of a portion of a lead frame undergoing a process in accordance with further embodiments of the technology. -
FIGS. 4A and 4B are partially schematic, cross-sectional views of a portion of a lead frame undergoing a process in accordance with yet additional embodiments of the technology. -
FIGS. 5A and 5B are cross-sectional images of chip-on-lead packages taken during experiments in accordance with several embodiments of the technology. - Several embodiments of the present technology are described below with reference to processes of assembling microelectronic packages with lead frames and/or other suitable substrates. Typical microelectronic packages include microelectronic circuits or components, thin-film recording heads, data storage elements, microfluidic devices, and other components manufactured on microelectronic substrates. Microelectronic substrates can include semiconductor pieces (e.g., doped silicon wafers or gallium arsenide wafers), non-conductive pieces (e.g., various ceramic substrates), or conductive pieces (e.g., metal or metal alloy). Many of the details regarding certain embodiments are also described below with reference to semiconductor dies. The term “semiconductor die” is used throughout to include a variety of articles of manufacture, including, for example, individual integrated circuit dies, imager dies, sensor dies, and/or dies having other semiconductor features.
- Many specific details that relate to certain embodiments are set forth in the following text to provide a thorough understanding of these embodiments. Several other embodiments can have configurations, components, and/or processes that are different from those described below. A person skilled in the relevant art, therefore, will appreciate that additional embodiments may be practiced without several of the details of the embodiments shown in
FIGS. 1A-5B . -
FIGS. 1A-1F are partially schematic, cross-sectional views of a semiconductor die and/or a portion of a lead frame undergoing a process to form a microelectronic package in accordance with embodiments of the technology. As shown inFIG. 1A , an initial stage of the process can include attaching a plurality ofelectrical couplers 104 to ball/bump sites 102 of asemiconductor die 100, as indicated by thearrows 103. Theelectrical couplers 104 prior to attachment and/or plating are shown in phantom lines for clarity. In the illustrated embodiment, twoelectrical couplers 104 are shown for illustration purposes. In other embodiments, one, three, or any other suitable numbers of electrical couplers may be used. - The
semiconductor die 100 can include any suitable type of integrated circuit device. For example, in certain embodiments, the semiconductor die 100 can include a plurality of metal-oxide-semiconductor field-effect transistors (“MOSFETs”), junction gate field-effect transistors (“JFETs”), insulated gate bipolar transistors, capacitors, and/or other suitable electrical components. In other examples, thesemiconductor die 100 can include other suitable types of electrical and/or mechanical components. - In certain embodiments, the
electrical couplers 104 can include solder balls attached to the ball/bump sites 102 using tack welding, partial reflow, and/or other suitable techniques. In other embodiments, theelectrical couplers 104 can include solder bumps plated onto and/or otherwise formed on the ball/bump sites 102. As used herein, the term “solder” generally refers to a fusible metal alloy with a melting point in the range of about 90° C. to 450° C. Examples of a solder include alloys of at least some of copper (Cu), tin (Sn), lead (Pb), silver (Ag), zinc (Zn), and/or other suitable metals. In other embodiments, theelectrical couplers 104 can also include other suitable electrically conductive couplers. -
FIGS. 1B-1D illustrate stages of forming anattachment area 112 and anon-attachment area 113 on alead frame 105 in accordance with embodiments of the technology. As shown inFIGS. 1B-1D , thelead frame 105 can include a plurality of lead fingers 106. In the illustrated embodiment, afirst lead finger 106 a is shown juxtaposed with asecond lead finger 106 b for illustration purposes. In other embodiments, thelead frame 105 can also include a die paddle (not shown), a dam bar (not shown), other number of lead fingers, and/or other suitable components. The lead fingers 106 can include afirst surface 107 a opposite asecond surface 107 b. As described in more detail later, thefirst surface 107 a may be configured to interface with the semiconductor die 100 (FIG. 1A ), and thesecond surface 107 b may be configured to interface with an external device (e.g., a printed circuit board, not shown). - As shown in
FIG. 1B , the process includes a deposition stage in which amasking material 108 is formed on thefirst surface 107 a of the lead fingers 106. In one embodiment, themasking material 108 can include a photoresist deposited on the lead fingers 106 via a spin-on operation and/or other suitable techniques. In other embodiments, the photoresist can include a tape of a dry film photoresist that may be laminated onto and/or otherwise attached to the lead fingers 106. As used herein, the term “photoresist” generally refers to a material that can be chemically modified when exposed to electromagnetic radiation. The term encompasses both positive photoresist (i.e., soluble when activated by the electromagnetic radiation) and negative photoresist (i.e., insoluble when activated by the electromagnetic radiation). In other embodiments, themasking material 108 can also include hard rubber and/or other suitable types of “hard” masking materials. -
FIG. 1C illustrates a material removal stage of the process, in which a portion of the maskingmaterial 108 is removed to form a plurality ofopenings 110. In one embodiment, the material removal stage can include patterning a photoresist based on a desired configuration using photolithography and/or other suitable techniques. In other embodiments, theopenings 110 in the maskingmaterial 108 may also be formed using laser ablation, wet etching, dry etching, and/or other suitable techniques. - As shown in
FIG. 1D , another stage of the process includes forming theattachment area 112 and thenon-attachment area 113 on thefirst surface 107 a of the lead fingers 106. In the illustrated embodiment, forming the attachment area 112 (or solder wetting pads) includes depositing a wettingmaterial 111 into theopenings 110 of the maskingmaterial 108. The wettingmaterial 111 can include silver (Ag), a nickel (Ni)/gold (Au) alloy, and/or other suitable metal or metal alloys that exhibit first wetting characteristics with regard to the electrical couplers 104 (FIG. 1A ) during reflow. As used herein, wetting characteristics are represented by a wetting contact angle. For example, in certain embodiments, the wetting contact angle between the wettingmaterial 111 and theelectrical couplers 104 during reflow can be less than about 90°, indicating generally wettable characteristics. In other embodiments, the wetting contact angle can be less than about 60°, about 45°, about 30°, and/or other suitable values. - After forming the
attachment area 112, the process can include removing the masking material 108 (shown in phantom lines for clarity) and anyexcess wetting material 111. Subsequently, the exposed portions of thefirst surface 107 a can be treated to form thenon-attachment area 113 that has second wetting characteristics. In one embodiment, the exposed portions of thefirst surface 107 a may be oxidized by contacting an oxidizing chemical solution (e.g., sulfuric acid, nitric acid, hydrochloric acid, and/or a combination thereof), heating the lead fingers 106 in air, by contacting with oxygen plasma, and/or by using other suitable techniques. In other embodiments, the exposed portions of thefirst surface 107 a may be treated using other suitable surface treatment techniques. - After surface treatment, the
non-attachment area 113 can be generally non-wettable to the electrical couplers 104 (FIG. 1A ) during reflow. For example, in one embodiment, a contact angle between thenon-attachment area 113 and theelectrical couplers 104 during reflow can be greater than about 90°, indicating generally non-wettable characteristics. In other examples, the non-wetting contact angle can be greater than about 120°, about 135°, and/or other suitable values. -
FIG. 1E illustrates another stage of the process in which the semiconductor die 100 is attached to thelead frame 105 with theelectrical couplers 104 generally aligned and in contact with theattachment area 112 of the lead fingers 106. Thelead frame 105 with the attached semiconductor die 100 can then be reflowed, for example, in a reflow chamber (not shown), and heat (as represented by the arrows 116) and/or other suitable forms of energy can be applied. As a result, theelectrical couplers 104 can be at least partially melted in order to join thelead frame 105 and the semiconductor die 100 together when subsequently cooled. - It has been observed that the lead fingers 106 with the
attachment area 112 and thenon-attachment area 113 can enable a controllable collapse of theelectrical couplers 104 during the reflow operation without using a solder mask. As a result, the risk of various structural and/or electrical damages to the resulting microelectronic package may be reduced and/or avoided. As discussed above, theattachment area 112 is generally wettable while thenon-attachment area 113 is generally non-wettable to theelectrical couplers 104. Without being bound by theory, it is believed that the wettability differential between theattachment area 112 and thenon-attachment area 113 can at least limit or substantially eliminate migration or spreading of the reflowedelectrical couplers 104. It is believed that the reflowedelectrical couplers 104 may not readily bond to thenon-attachment area 113 due to a lack of surface contact. As a result, the reflowedelectrical couplers 104 tend to be confined in theattachment area 112. - In certain embodiments, a wettability differential between the
attachment area 112 and thenon-attachment area 113 may be adjusted based on a target degree of migration of the reflowedelectrical couplers 104. In general, it is believed that the larger the wettability differential, the smaller the degree of migration, and vice versa. Thus, if a small degree of migration is desired, a large wettability differential (e.g., a contact angle difference of greater than about 20°, about 30°, or about 40°) may be used. If a large degree of migration may be tolerated, a small wettability differential (e.g., a contact angle difference of less than about 15°, about 10°, or about 5°) may be used. - Subsequent to reflow, the process can also include various additional processing stages. For example, as shown in
FIG. 1F , anunderfill material 117 may be deposited between the semiconductor die 100 and the lead fingers 106. Theunderfill material 117 may at least partially encapsulate theelectrical couplers 104. In other embodiments, theunderfill material 117 may be omitted. - The semiconductor die 100 and the
lead frame 105 can also be encapsulated by an encapsulant 120 (e.g., an epoxy or other types of molding compounds). In the illustrated embodiment, the semiconductor die 100 is substantially encapsulated in theencapsulant 120. The lead fingers 106 are partially encapsulated in theencapsulant 120 with thesecond surfaces 107 b exposed for interconnecting to external devices (not shown). In other embodiments, thelead frame 105 may include lead fingers 106 that extend beyond theencapsulant 120. In further embodiments, the semiconductor die 100 and thelead frame 105 may be encapsulated in other suitable configurations. - Even though the foregoing process includes forming the
attachment area 112 and thenon-attachment area 113 by depositing the wettingmaterial 111 and surface treating the lead fingers 106, in other embodiments, forming theattachment area 112 and thenon-attachment area 113 may include other processing operations. For example,FIGS. 2A-2E illustrate another process that does not include depositing a wetting material. - As shown in
FIG. 2A , an initial stage of the process can include depositing the maskingmaterial 108 on thefirst surface 107 a of the lead fingers 106. As shown inFIGS. 2B and 2C , another stage of the process can include patterning the maskingmaterial 108 to define a coveredportion 109 a and an exposedportion 109 b of thefirst surface 107 a of the lead fingers 106. The coveredportion 109 a generally corresponds to theattachment area 112, and the exposedportion 109 b generally corresponds to thenon-attachment area 113. In the illustrated embodiment, the coveredportion 109 a is illustratively shown to have a generally circular shape. In other embodiments, the coveredportion 109 a may have a rectangular, an oval, a trapezoidal, and/or other suitable shapes. - The exposed
portion 109 b may then be treated to achieve the target wettability characteristics while the coveredportion 109 a is protected from the treatment by the remainingmasking material 108. In certain embodiments, the exposedportion 109 b may be treated in a generally similar manner, as described above with reference toFIG. 1D . In other embodiments, the exposedportion 109 b may be treated using other suitable techniques such that the exposedportion 109 b is generally non-wettable to the electrical couplers 104 (FIG. 1A ) during reflow. - Similar to the process described above with reference to
FIGS. 1A-1F , the exposedarea 109 b of the lead fingers 106 may be treated based on a target wettability differential between theattachment area 112 and thenon-attachment area 113. For example, in one embodiment, thelead frame 105 can include copper (Cu) lead fingers 106. As a result, the wettability of the reflowed electric coupler 104 (FIG. 1A ) to the copper lead fingers 106 may be readily determined. Thus, a target wettability for thenon-attachment area 113 may be derived based on the wettability of the reflowed electric coupler 104 (FIG. 1A ) to the copper lead fingers 106 and the target wettability differential. Based on the target wettability for thenon-attachment area 113, suitable techniques and/or operation parameters may be selected (e.g., oxygen plasma treatment, heating, etc.) to achieve the target wettability for thenon-attachment area 113. - As shown in
FIGS. 2D and 2E , another stage of the process can include removing the remaining masking material 108 (FIGS. 2B and 2C ) to expose theattachment area 112. Subsequently, thelead frame 105 can undergo other suitable processing stages to form the microelectronic package, as described in more detail with reference toFIGS. 1E and 1F . -
FIGS. 3A-3C illustrate another process of forming theattachment area 112 and thenon-attachment area 113 using screen printing. As shown inFIG. 3A , an initial stage of the process can include placing astencil 132 proximate the lead fingers 106. Thestencil 132 can includeapertures 134 generally corresponding to theattachment area 112. Subsequently, as shown inFIG. 3B , the wetting material 111 (represented by thearrows 111 inFIG. 3A ) may be sprayed, printed, and/or otherwise formed on thefirst surface 107 a of the lead fingers 106 through theapertures 134 of thestencil 132. - As shown in
FIG. 3C , the process can then include removing the stencil 132 (FIG. 3B ) from thefirst surface 107 a of the lead fingers 106. The exposed portion of thefirst surface 107 a may then optionally undergo surface treatment, as described above with reference toFIG. 1D . Subsequently, thelead frame 105 can undergo other suitable processing stages to form the microelectronic package, as described in more detail with reference toFIGS. 1E and 1F . -
FIGS. 4A and 4B illustrate another process for forming theattachment area 112 and thenon-attachment area 113 using a preform. As shown inFIG. 4A , the process can include attaching apreform 150 to thefirst surface 107 a of the lead fingers 106. In the illustrated embodiment, thepreform 150 includes a laminated structure with aninterface layer 152 and anadhesive layer 156. Theinterface layer 152 can include afirst portion 154 that is wettable to the reflowed electrical couplers 104 (FIG. 1A ) and asecond portion 158 that is generally non-wettable to the reflowedelectrical couplers 104. For example, thefirst portion 154 can include silver (Ag), and thesecond portion 158 can include copper oxide (CuxO). As a result, thefirst portion 154 and thesecond portion 158 generally correspond to theattachment area 112 and thenon-attachment area 113. - As shown in
FIG. 4B , thelead frame 105 with the attachedpreform 150 may then be optionally cured and/or undergo other suitable processing before being attached to the semiconductor die 100, as described in more detail with reference toFIGS. 1E and 1F . Even though thepreform 150 is shown inFIGS. 4A and 4B as having theadhesive layer 156 pre-attached, in other embodiments, thepreform 150 may include theinterface layer 152 carried by an optional backing layer (not shown) without theadhesive layer 156. Instead, an adhesive (not shown) may be applied to at least one of thepreform 150 and thelead frame 105 before attachment thereof. - Experiments of assembling chip-on-lead packages were conducted.
FIGS. 5A and 5B are cross-sectional images of chip-on-lead packages taken during such experiments. In a first experiment, asemiconductor die 200 with attachedsolder balls 204 was placed in contact with alead frame 205 withcopper lead fingers 206 that have generally the same regional wettability. The semiconductor die 200 and thelead frame 205 were subsequently reflowed. As clearly shown inFIG. 5A , thesolder balls 206 uncontrollably collapsed during reflow and came in contact with each other. - In a second experiment, a
semiconductor die 300 with an attachedsolder ball 304 was placed in contact with alead frame 305 with alead finger 306 processed according to several embodiments of the process described above with reference toFIGS. 1A-1E . Thelead finger 306 included acontact pad 312 containing silver (Ag) on a portion of the top surface of thelead finger 306. The semiconductor die 300 and thelead frame 305 were subsequently reflowed. As clearly shown inFIG. 5B , thesolder ball 304 substantially retained its shape and did not significantly migrate away from thecontact pad 312. - From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the technology. Many of the elements of one embodiment may be combined with other embodiments in addition to or in lieu of the elements of the other embodiments. Accordingly, the technology is not limited except as by the appended claims.
Claims (28)
1-23. (canceled)
24. A method for fabricating a semiconductor assembly, comprising:
defining an attachment area and a non-attachment area on a lead finger of a lead frame, wherein said defining creates wettability differential between the attachment area and the non-attachment area;
contacting an electrical coupler of a semiconductor die with the attachment area of the lead finger;
reflowing the electrical coupler while the electrical coupler is in contact with the attachment area of the lead finger; and
controlling an amount of migration in the electrical coupler from the attachment area toward the non-attachment area.
25. The method of claim 24 , wherein the defining an attachment area and a non-attachment area comprises screen printing.
26. The method of claim 24 , further comprising attaching the electrical coupler to a bump site of the semiconductor die using plating.
27. The method of claim 24 , wherein defining the attachment area and the non-attachment area comprises attaching a preform onto the lead finger with an adhesive, the preform having a first portion generally corresponding to the attachment area and a second portion generally corresponding to the non-attachment area.
28. The method of claim 24 , further comprising:
attaching the coupler to a bump site of the semiconductor die prior to contacting the coupler with the attachment area of the lead finger; and
at least partially encapsulating the semiconductor die, the coupler, and the lead finger with an encapsulant.
29. The method of claim 24 wherein defining the attachment area and the non-attachment area comprises:
depositing a masking material on a surface of the lead finger;
patterning the masking material to form an opening corresponding to the attachment area, the opening exposing a first portion of the surface of the lead finger, wherein a second portion of the surface is covered by the masking material;
depositing a wetting material on the first portion of the surface of the lead finger through the opening in the masking material;
removing the masking material from the surface of the lead finger; and
treating the second portion of the surface of the lead finger such that the second portion is less wettable to the solder coupler during reflow than the first portion.
30. The method of claim 24 wherein defining the attachment area and the non-attachment area comprises:
depositing a photoresist on a surface of the lead finger;
patterning the photoresist to form an opening corresponding to the attachment area, the opening exposing a first portion of the surface of the lead finger, wherein a second portion of the surface is covered by the photoresist;
depositing a material comprising silver (Ag) on the first portion of the surface of the lead finger through the opening in the photoresist;
removing the photoresist from the second portion of the surface of the lead finger; and p1 oxidizing the second portion of the surface of the lead finger.
31. The method of claim 24 wherein defining the attachment area and the non-attachment area comprises at least one of:
depositing a wetting material on a first portion of the lead finger such that the first portion is more wettable to the solder during reflow than the second portion; or
treating a second portion of the lead finger such that the second portion is less wettable to the solder during reflow than the first portion.
32. The method of claim 24 wherein defining the attachment area and the non-attachment area comprises:
depositing a masking material on a surface of the lead finger;
removing a portion of the masking material, a remaining portion of the masking material covering a first portion of the surface of the lead finger, wherein a second portion of the surface of the lead finger is exposed through the masking material;
treating the second portion of the surface of the lead finger such that the second portion is less wettable to the solder coupler during reflow than the first portion; and
thereafter, removing the remaining portion of the masking material from the lead finger.
33. The method of claim 24 wherein:
the attachment area has a first wettability to the coupler during reflow;
the non-attachment area has a second wettability to the coupler during reflow; and
controlling the amount of migration of the coupler comprises treating at least one of the attachment area or the non-attachment area such that the second wettability is less than the first wettability by a target amount.
34. The method of claim 33 , wherein
controlling the amount of migration of the coupler comprises at least one of (a) depositing silver (Ag) onto a first portion of the lead finger or (b) oxidizing a second portion of the lead finger.
35. The method of claim 24 , wherein defining the non-attachment area includes allowing the non-attachment area to oxidize.
36. A flip-chip semiconductor device, comprising:
a semiconductor die with a bump site;
a lead frame with a lead frame finger having an attachment area and a non-attachment area, the attachment area and non-attachment area having a wettability differential; and
a solder coupler contacting the bump site and the attachment area of the lead frame finger, wherein the migration of the solder coupler has been controlled such that the solder coupler has not substantially migrated onto the non-attachment area.
37. The flip-chip semiconductor device of claim 36 , wherein the attachment area of the lead frame finger comprises deposited silver (Ag).
38. The flip-chip semiconductor device of claim 36 , wherein the solder coupler has substantially retained its pre-reflow shape.
39. The flip-chip semiconductor device of claim 36 , wherein the non-attachment area of the lead frame finger is oxidized.
40. The flip-chip semiconductor device of claim 36 , wherein the solder coupler is plated to the semiconductor die bump site.
41. The flip-chip semiconductor device of claim 36 , wherein the semiconductor die is disposed over the lead frame in a flip-chip configuration to align the solder coupler between the semiconductor die and the corresponding attachment area on the lead frame.
42. The flip-chip semiconductor device of claim 36 , wherein the non-attachment area comprises oxidized metal.
43. A microelectronic package, comprising:
a lead frame including lead fingers, each lead finger including a first surface and a second surface;
a contact pad including a wetting material disposed on a portion of the first surface, wherein the contact pad and an area on the first surface adjacent to the contact pad have a wettability differential;
a semiconductor die including bump sites; and
electrical couplers attached to the bump sites of the semiconductor die and the contact pads of the lead fingers, wherein the electrical couplers are confined to the contact pads;
wherein the second surface of the lead finger is configured to interface with an external device.
44. The microelectronic package of claim 43 , wherein the wetting material includes a material wettable to the electrical couplers.
45. The microelectronic package of claim 44 , wherein the wetting material includes a metal or a metal alloy.
46. The microelectronic package of claim 43 , wherein the electrical couplers include a solder material.
47. The microelectronic package of claim 46 , wherein the solder material includes a metal alloy.
48. The microelectronic package of claim 43 , wherein the electrical couplers are spaced apart.
49. The microelectronic package of claim 43 , wherein the semiconductor die is disposed over the lead frame in a flip-chip configuration to align the electrical couplers between the bump sites of the semiconductor die and the corresponding contact pads on the lead fingers.
50. The microelectronic package of claim 43 , wherein the area on the first surface adjacent to the contact pad comprises oxidized metal.
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US14/612,247 US20150155226A1 (en) | 2010-12-16 | 2015-02-02 | Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing |
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US12/970,784 US8361899B2 (en) | 2010-12-16 | 2010-12-16 | Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing |
US13/706,062 US8906797B2 (en) | 2010-12-16 | 2012-12-05 | Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing |
US14/481,602 US9070671B2 (en) | 2010-12-16 | 2014-09-09 | Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing |
US14/612,247 US20150155226A1 (en) | 2010-12-16 | 2015-02-02 | Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing |
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US14/481,602 Continuation US9070671B2 (en) | 2010-12-16 | 2014-09-09 | Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing |
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US13/706,062 Active US8906797B2 (en) | 2010-12-16 | 2012-12-05 | Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing |
US14/481,602 Active US9070671B2 (en) | 2010-12-16 | 2014-09-09 | Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing |
US14/612,247 Abandoned US20150155226A1 (en) | 2010-12-16 | 2015-02-02 | Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing |
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US13/706,062 Active US8906797B2 (en) | 2010-12-16 | 2012-12-05 | Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing |
US14/481,602 Active US9070671B2 (en) | 2010-12-16 | 2014-09-09 | Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing |
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Also Published As
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US8361899B2 (en) | 2013-01-29 |
US20140004662A1 (en) | 2014-01-02 |
US8906797B2 (en) | 2014-12-09 |
TW201241943A (en) | 2012-10-16 |
US20120153447A1 (en) | 2012-06-21 |
CN102522341A (en) | 2012-06-27 |
US20140377912A1 (en) | 2014-12-25 |
TWI474416B (en) | 2015-02-21 |
US9070671B2 (en) | 2015-06-30 |
CN202352660U (en) | 2012-07-25 |
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