US20150136458A1 - Printed circuit board and method of manufacturing the same - Google Patents
Printed circuit board and method of manufacturing the same Download PDFInfo
- Publication number
- US20150136458A1 US20150136458A1 US14/182,206 US201414182206A US2015136458A1 US 20150136458 A1 US20150136458 A1 US 20150136458A1 US 201414182206 A US201414182206 A US 201414182206A US 2015136458 A1 US2015136458 A1 US 2015136458A1
- Authority
- US
- United States
- Prior art keywords
- metal layer
- circuit board
- printed circuit
- crystal orientations
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
- C23C14/18—Metallic material, boron or silicon on other inorganic substrates
- C23C14/185—Metallic material, boron or silicon on other inorganic substrates by cathodic sputtering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/58—After-treatment
- C23C14/5826—Treatment with charged particles
- C23C14/5833—Ion beam bombardment
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
- C23F4/04—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00 by physical dissolution
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0391—Using different types of conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/09—Treatments involving charged particles
- H05K2203/092—Particle beam, e.g. using an electron beam or an ion beam
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
- H05K3/16—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation by cathodic sputtering
Definitions
- the present invention relates to a printed circuit board and a method of manufacturing the same.
- the additive method is to form the circuit pattern on an insulating layer by a plating scheme. Recently, a semi additive method of more efficiently performing a plating scheme has been used The semi additive method performs surface treatment on the insulating layer to increase roughness and forms a seed layer, which is a base layer for electroplating, by chemical plating. The circuit pattern is completed by forming the seed layer and then performing the electroplating till a thickness of the circuit pattern reaches a predetermined level.
- the existing semi additive method requires a surface roughness treatment process and a thickness of 10,000 ⁇ or more to entirely, uniformly form the seed layer on the substrate.
- a lead time of a flash etching process to form the circuit pattern and then remove the seed layer may be long and it is difficult to form a fine pitch.
- the circuit pattern having the fine pitch may be implemented by forming the thin, uniform seed layer.
- the sputtering process scheme may be formed a thin film at a thin thickness.
- the film undergoes the process, and thus most of the film is grown to have a crystal orientation of (111).
- the thin film has a deflective characteristic in terms of mechanical properties, due to anisotropy of a material.
- Patent Document 1 discloses a manufacturing method of forming the seed layer using the sputtering process, in the method for manufacturing a printed circuit board, but the so formed seed layer has a limitation in terms of the anisotropy of the material physical property. Further, the seed layer may have very strong mechanical physical property in a thickness direction, but have a relatively weak physical property in a lateral direction.
- Patent Document 1 Korean Patent Laid-Open Publication No. 2009-0105162
- the present invention has been made in an effort to provide a printed circuit board including a metal layer having different crystal orientations to minimize factors of hindering electrical characteristics such as electric conductivity and improve isotropy of mechanical properties.
- the present invention has been made in an effort to provide a method of manufacturing a printed circuit board using a metal layer.
- a printed circuit board including: an insulating layer; and a metal layer formed on the insulating layer, wherein in the metal layer, a ratio occupied by crystal orientations of (110) and (112) may be 20 to 80%.
- the crystal orientations of (110) and (112) may be formed in an island type.
- the crystal orientations of (110) and (112) may have a twin structure.
- a material of the metal layer may include copper (Cu).
- a method of manufacturing a printed circuit board including: preparing an insulating layer; forming a metal layer on the insulating layer; and etching the metal layer by dry etching, wherein in the metal layer, a ratio occupied by crystal orientations of (110) and (112) is 20 to 80%.
- the forming of the metal layer may be performed by a deposition method.
- the deposition method may be sputtering.
- the etching of the metal layer by dry etching may be performed by ion beam etching
- An ion source of the ion beam etching may be gallium (Ga).
- the crystal orientations of (110) and (112) may be formed in an island type.
- the crystal orientations of (110) and (112) may have a twin structure.
- a material of the metal layer may include copper (Cu).
- FIG. 1 is a plan view of a metal layer of a printed circuit board according to a preferred embodiment of the present invention
- FIG. 2 is a cross-sectional view of the printed circuit board according to the preferred embodiment of the present invention.
- FIG. 3 is a photograph of the metal layer of the printed circuit board according to the preferred embodiment of the present invention which is analyzed by electron back-scattered diffraction (EBSD); and
- FIGS. 4 to 6 are cross-sectional views illustrating a manufacturing process flow for describing a method of manufacturing a printed circuit board according to a preferred embodiment of the present invention.
- FIG. 1 is a plan view of a metal layer of a printed circuit board according to a preferred embodiment of the present invention.
- the printed circuit board includes an insulating layer 100 and a metal layer 200 formed on the insulating layer 100 , in which in the metal layer 200 , a ratio of an area occupied by crystal orientations 20 of (110) and (112) may be 20 to 80%.
- a ratio of an area occupied by crystal orientations 20 of (110) and (112) may be 20 to 80%.
- the metal layer 200 may have (111) as a main crystal orientation.
- a ratio thereof may be limited or may be locally present.
- the printed circuit board including the formed metal layer 200 may have a limitation in anisotropy of material properties. That is, an elastic modulus value depending on the crystal orientation of the metal layer 200 is very strong physical properties in a thickness direction, but may have relatively very small in a lateral direction.
- the metal layer 200 includes the crystal orientations 20 of (110) and (112), such that the elastic modulus of the metal layer 200 may have excellent physical properties in a thickness direction and a lateral direction.
- the elastic modulus of the metal layer 200 may be relatively weak in the lateral direction and when the ratio of the area exceeds 80%, many grain boundaries are distributed within the metal layer 200 and thus electrons may not flow smoothly and a scattering phenomenon occurs and thus electrical resistance may also be increased.
- FIG. 2 is a cross-sectional view of the printed circuit board according to the preferred embodiment of the present invention.
- the crystal orientations 20 of (110) and (112) may be formed in an island type.
- the crystal orientations 20 of (110) and (112) are present in the island type, such that the isotropy of mechanical properties may be improved. That is, the crystal orientations 20 of (110) and (112) have a grain shape and soft grains of (110) and (112) are positioned between the strong grains of the existing crystal orientation 10 of (111), such that the mechanical deformation occurring during the process may be accepted well.
- FIG. 3 is a photograph of the metal layer 200 of the printed circuit board according to the preferred embodiment of the present invention which is analyzed by electron back-scattered diffraction (EBSD).
- EBSD electron back-scattered diffraction
- the electron back-scattered diffraction technique is equipment which is used to analyze the orientations of each of the grains by using a kikuchi pattern of back-scattered electrons.
- the crystal material has different orientations for each grain, and therefore a diffraction form of the back-scattered electrons is changed when an electron beam generated from an electron microscope is irradiated to a sample. Therefore, a structure analysis using the electron back-scattered diffraction may be analyzed by analyzing the crystal orientation.
- the kikuchi pattern means a band type obtained when an electron beam is incident on a single crystal or a diffraction pattern which is formed as a pair of parallel lines of contrast.
- the crystal orientations 20 of (110) and (112) of the metal layer 200 of the printed circuit board according to the preferred embodiment of the present invention have a twin structure by using the electron back-scattered diffraction.
- the electrons do not flow smoothly due to a lattice mismatch and the scattering occurs, such that the electrical resistance may be increased.
- the electrical connection of the metal layer 200 one of the big factors hindering the progress may be considered as the grain boundary.
- the grain boundaries are not in disorder and are arranged having a constant rule. Therefore, the grain having the crystal orientations 20 of (110) and (112) may minimize the hindrance of the flow of electrons.
- An example of the material of the metal layer 200 of the printed circuit board according to the preferred embodiment of the present invention may include copper (Cu) which is most appropriate when considering an economic aspect and an electric conductivity aspect.
- the thickness of the metal layer 200 may range from 30 to 300 nm.
- the thickness of the metal layer 200 is less than 30 nm, the crystal orientation is little changed by ion beam etching, and the etching is more rapidly performed than forming a slip surface by ion implantation energy such that the metal layer 200 formed by the sputtering may also disappear.
- the thickness of the metal layer 200 exeeds 300 nm, since the crystal orientation which does not cause a phase change of an inner layer is more dominated than a crystal orientation of a surface layer, it may difficult to control a direction of a crystal surface for the film.
- FIGS. 4 to 6 are cross-sectional views illustrating a manufacturing process flow for describing a method of manufacturing a printed circuit board according to a preferred embodiment of the present invention.
- the method of manufacturing a printed circuit board includes: preparing the insulating layer 100 ; forming the metal layer 200 on the insulating layer 100 ; and etching the metal layer 200 by dry etching, in which in the metal layer 200 , the ratio of the area occupied by the crystal orientations 20 of (110) and (112) may be 20 to 80%.
- the insulating layer 100 may include silicon dioxide (SiO 2 ), but is not particularly limited thereto. Further, the insulating layer 100 made of an epoxy resin composition may be used.
- the forming of the metal layer 200 may be performed by a deposition method. Further, the deposition method may be sputtering.
- the sputtering is a technology of escaping metal molecules by colliding inert elements such as argon (Ar) with a target and then attaching a film on a surface.
- inert elements such as argon (Ar)
- Ar argon
- the inert gas is ionized into anion within the plasma by a high output DC amperemeter.
- the anion of the inert gas is accelerated to a cathode by the DC ampere meter and thus collides with the surface of the target.
- an atom jumps out from the surface to the outside by exchanging momentum by perfectly elastic collision.
- the metal plate made of the metal material to be plated as the target When the sputtering is performed by using the metal plate made of the metal material to be plated as the target, the metal atom jumping out from the metal plate adheres to the insulating layer 100 , such that the metal layer 200 may be formed uniformly.
- An example of the material of the metal plate forming the metal layer 200 may include copper (Cu) which is most appropriate when considering the economic aspect and the electric conductivity aspect.
- the elastic modulus of the metal layer 200 may be relatively weak in the lateral direction and when the ratio of the area exceeds 80%, many grain boundaries are distributed within the metal layer 200 and thus electrons may not flow smoothly and a scattering phenomenon occurs and thus electrical resistance may also be increased.
- the thickness of the metal layer 200 may range from 30 to 300 nm.
- the thickness of the metal layer 200 is less than 30 nm, the crystal orientation is little changed by ion beam etching, and the etching is more rapidly performed than forming a slip surface by ion implantation energy such that the metal layer 200 formed by the sputtering may also disappear.
- the thickness of the metal layer 200 exeeds 300 nm, since the crystal orientation which does not cause a phase change of an inner layer is more dominated than a crystal orientation of a surface layer, it may difficult to control a direction of a crystal surface for the film.
- the etching of the metal layer 200 by dry etching may be performed by the ion beam etching.
- an ion source of the ion beam etching may be gallium (Ga).
- the ion beam is a cluster of molecules or atoms having charges as a mass of ion flow and when an electric field or a magnetic field is applied to the ion, the flow of ion may be accelerated.
- the accelerated ion in a high energy state is irradiated to the surface of the metal layer 200 , thereby etching a part of the metal layer 200 .
- the printed circuit board according to the preferred embodiment of the present invention uses a phenomenon in which the crystal orientation is changed while being etched when the gallium (Ga) ion is irradiated to the metal layer 200 .
- the driving force changing the crystal orientation may be heat energy or mechanical collision energy.
- the metal layer 200 may have (111) as a main crystal orientation.
- a part of the crystal orientations of (220), (112), or the like may be included, a ratio thereof may be limited or may be locally present.
- the printed circuit board including the formed metal layer 200 may have a limitation in anisotropy of material properties. That is, a modulus value depending on the crystal orientation of the metal layer 200 is very strong physical properties in a thickness direction, but may have a relatively very small value.
- the gallium (Ga) ion fills an empty space from which a part of the metal layer 200 is separated when the gallium (Ga) ion is irradiated to the metal layer 200 .
- the crystal orientation 10 of (111) is changed to the crystal orientations 20 of (110) and (112) while the empty space from which the metal layer 200 of the crystal orientation 10 of (111) is separated is filled with the gallium (Ga) ion.
- the metal layer 200 has different crystal orientations and the elastic modulus of the metal layer 200 may have the excellent physical properties in the thickness direction and the lateral direction.
- the ratio of the crystal orientations 20 of (110) and (112) included in the metal layer 200 may be controlled by the exposure time, acceleration voltage, or current amount of the ion beam.
- one adhesive layer may also be formed between the insulating layer 100 and the metal layer 200 .
- the adhesive layer may be made of, for example, titanium (Ti), chromium (Cr), nickel (Ni), iron (Fe), zirconium (Zr), tantalum (Ta), aluminum (Al), tungsten (W), platinum (Pt), or a mixture thereof, but is not particularly limited thereto.
- the crystal orientations 20 of (110) and (112) may be formed in the island type.
- the crystal orientations 20 of (110) and (112) are present in the island type, such that the isotropy of mechanical properties may be improved. That is, the crystal orientations 20 of (110) and (112) have a grain shape and soft grains of (110) and (112) are positioned between the strong grains of the existing crystal orientation 10 of (111), such that the mechanical deformation occurring during the process may be accepted well.
- the grain boundaries are not in disorder and are arranged having a constant rule. Therefore, the grain having the crystal orientations 20 of (110) and (112) may minimize the hindrance of the flow of electrons.
- the printed circuit board according to the preferred embodiments of the present invention, it is possible to minimize the factors of hindering electrical characteristics, such as electric conductivity, by using the printed circuit board including the metal layer 200 in which the ratio of the area occupied by the crystal orientations 20 of (110) and (112) is 20 to 80%.
- the printed circuit board according to the preferred embodiments of the present invention, it is possible to provide the printed circuit board including the metal layer 200 having different crystal orientations to improve the isotropy of the mechanical physical property.
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
- This application claims the benefit of Korean Patent Application No. 10-2013-0140862, filed on Nov. 19, 2013, entitled “Printed Circuit Board and Method of Manufacturing the Same,” which is hereby incorporated by reference in its entirety into this application.
- 1. Technical Field
- The present invention relates to a printed circuit board and a method of manufacturing the same.
- 2. Description of the Related Art
- Recently, as a substrate serving as an interposer between the substrate and electronic devices becomes light, thin, short, and small rapidly, a high-density and fine pattern has been required. Various attempts to simplify the existing process together with improvement in technologies have been progressed.
- There is an additive method of forming a circuit pattern of a printed circuit board. The additive method is to form the circuit pattern on an insulating layer by a plating scheme. Recently, a semi additive method of more efficiently performing a plating scheme has been used The semi additive method performs surface treatment on the insulating layer to increase roughness and forms a seed layer, which is a base layer for electroplating, by chemical plating. The circuit pattern is completed by forming the seed layer and then performing the electroplating till a thickness of the circuit pattern reaches a predetermined level.
- The existing semi additive method requires a surface roughness treatment process and a thickness of 10,000 Å or more to entirely, uniformly form the seed layer on the substrate. When the thickness of the seed layer is larger, there is a problem in that a lead time of a flash etching process to form the circuit pattern and then remove the seed layer may be long and it is difficult to form a fine pitch.
- Therefore, when a sputtering process is applied during a process of forming a metal layer of the printed circuit board, the number of processes is reduced, such that the lead time of the process may be short and costs may be saved correspondingly. Further, the circuit pattern having the fine pitch may be implemented by forming the thin, uniform seed layer.
- For this reason, as the substrate is miniaturized and highly integrated, a demand for the sputtering process scheme is more increased than the existing plating scheme. The sputtering process scheme may be formed a thin film at a thin thickness. In this case, the film undergoes the process, and thus most of the film is grown to have a crystal orientation of (111). When the crystal orientation is grown only the specific direction, the thin film has a deflective characteristic in terms of mechanical properties, due to anisotropy of a material.
- Meanwhile, Patent Document 1 discloses a manufacturing method of forming the seed layer using the sputtering process, in the method for manufacturing a printed circuit board, but the so formed seed layer has a limitation in terms of the anisotropy of the material physical property. Further, the seed layer may have very strong mechanical physical property in a thickness direction, but have a relatively weak physical property in a lateral direction.
- Patent Document 1: Korean Patent Laid-Open Publication No. 2009-0105162
- The present invention has been made in an effort to provide a printed circuit board including a metal layer having different crystal orientations to minimize factors of hindering electrical characteristics such as electric conductivity and improve isotropy of mechanical properties.
- Further, the present invention has been made in an effort to provide a method of manufacturing a printed circuit board using a metal layer.
- According to a preferred embodiment of the present invention, there is provided a printed circuit board, including: an insulating layer; and a metal layer formed on the insulating layer, wherein in the metal layer, a ratio occupied by crystal orientations of (110) and (112) may be 20 to 80%.
- The crystal orientations of (110) and (112) may be formed in an island type.
- The crystal orientations of (110) and (112) may have a twin structure.
- A material of the metal layer may include copper (Cu).
- According to another preferred embodiment of the present invention, there is provided a method of manufacturing a printed circuit board, including: preparing an insulating layer; forming a metal layer on the insulating layer; and etching the metal layer by dry etching, wherein in the metal layer, a ratio occupied by crystal orientations of (110) and (112) is 20 to 80%.
- The forming of the metal layer may be performed by a deposition method.
- The deposition method may be sputtering.
- The etching of the metal layer by dry etching may be performed by ion beam etching
- An ion source of the ion beam etching may be gallium (Ga).
- The crystal orientations of (110) and (112) may be formed in an island type.
- The crystal orientations of (110) and (112) may have a twin structure.
- A material of the metal layer may include copper (Cu).
- The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a plan view of a metal layer of a printed circuit board according to a preferred embodiment of the present invention; -
FIG. 2 is a cross-sectional view of the printed circuit board according to the preferred embodiment of the present invention; -
FIG. 3 is a photograph of the metal layer of the printed circuit board according to the preferred embodiment of the present invention which is analyzed by electron back-scattered diffraction (EBSD); and -
FIGS. 4 to 6 are cross-sectional views illustrating a manufacturing process flow for describing a method of manufacturing a printed circuit board according to a preferred embodiment of the present invention. - The objects, features and advantages of the present invention will be more clearly understood from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant descriptions thereof are omitted. Further, in the following description, the terms “one side,” “the other side” and the like are used to differentiate a certain component from other components, but the configuration of such components should not be construed to be limited by the terms. Further, in the description of the present invention, when it is determined that the detailed description of the related art would obscure the gist of the present invention, the description thereof will be omitted.
- Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.
- Printed Circuit Board
-
FIG. 1 is a plan view of a metal layer of a printed circuit board according to a preferred embodiment of the present invention. - Referring to
FIG. 1 , the printed circuit board according to the preferred embodiment of the present invention includes aninsulating layer 100 and ametal layer 200 formed on theinsulating layer 100, in which in themetal layer 200, a ratio of an area occupied bycrystal orientations 20 of (110) and (112) may be 20 to 80%. Generally, when a sputtering process is performed to form themetal layer 200, themetal layer 200 may have (111) as a main crystal orientation. In addition, when a part of the crystal orientations of (220), (112), or the like may be included, a ratio thereof may be limited or may be locally present. - However, the printed circuit board including the formed
metal layer 200 may have a limitation in anisotropy of material properties. That is, an elastic modulus value depending on the crystal orientation of themetal layer 200 is very strong physical properties in a thickness direction, but may have relatively very small in a lateral direction. - Therefore, in the printed circuit board according to the preferred embodiment of the present invention, the
metal layer 200 includes thecrystal orientations 20 of (110) and (112), such that the elastic modulus of themetal layer 200 may have excellent physical properties in a thickness direction and a lateral direction. - When in the
metal layer 200, the ratio of the area occupied by thecrystal orientations 20 of (110) and (112) is less than 20%, the elastic modulus of themetal layer 200 may be relatively weak in the lateral direction and when the ratio of the area exceeds 80%, many grain boundaries are distributed within themetal layer 200 and thus electrons may not flow smoothly and a scattering phenomenon occurs and thus electrical resistance may also be increased. -
FIG. 2 is a cross-sectional view of the printed circuit board according to the preferred embodiment of the present invention. - Referring to
FIG. 2 , thecrystal orientations 20 of (110) and (112) may be formed in an island type. Thecrystal orientations 20 of (110) and (112) are present in the island type, such that the isotropy of mechanical properties may be improved. That is, thecrystal orientations 20 of (110) and (112) have a grain shape and soft grains of (110) and (112) are positioned between the strong grains of the existingcrystal orientation 10 of (111), such that the mechanical deformation occurring during the process may be accepted well. -
FIG. 3 is a photograph of themetal layer 200 of the printed circuit board according to the preferred embodiment of the present invention which is analyzed by electron back-scattered diffraction (EBSD). Referring toFIG. 3 , the electron back-scattered diffraction technique is equipment which is used to analyze the orientations of each of the grains by using a kikuchi pattern of back-scattered electrons. The crystal material has different orientations for each grain, and therefore a diffraction form of the back-scattered electrons is changed when an electron beam generated from an electron microscope is irradiated to a sample. Therefore, a structure analysis using the electron back-scattered diffraction may be analyzed by analyzing the crystal orientation. Herein, the kikuchi pattern means a band type obtained when an electron beam is incident on a single crystal or a diffraction pattern which is formed as a pair of parallel lines of contrast. - Therefore, it may be appreciated that the
crystal orientations 20 of (110) and (112) of themetal layer 200 of the printed circuit board according to the preferred embodiment of the present invention have a twin structure by using the electron back-scattered diffraction. - In the grain boundary which is a section in which the crystal orientation is changed, the electrons do not flow smoothly due to a lattice mismatch and the scattering occurs, such that the electrical resistance may be increased. In the electrical connection of the
metal layer 200, one of the big factors hindering the progress may be considered as the grain boundary. When electrons pass through the grain boundary of which the atom arrangement is in disorder, the scattering occurs, such that the electrons may not flow smoothly, thereby increasing the electrical resistance. - However, since the
crystal orientations 20 of (110) and (112) have the twin structure, the grain boundaries are not in disorder and are arranged having a constant rule. Therefore, the grain having thecrystal orientations 20 of (110) and (112) may minimize the hindrance of the flow of electrons. - An example of the material of the
metal layer 200 of the printed circuit board according to the preferred embodiment of the present invention may include copper (Cu) which is most appropriate when considering an economic aspect and an electric conductivity aspect. - Further, although not particularly limited, the thickness of the
metal layer 200 may range from 30 to 300 nm. When the thickness of themetal layer 200 is less than 30 nm, the crystal orientation is little changed by ion beam etching, and the etching is more rapidly performed than forming a slip surface by ion implantation energy such that themetal layer 200 formed by the sputtering may also disappear. When the thickness of themetal layer 200 exeeds 300 nm, since the crystal orientation which does not cause a phase change of an inner layer is more dominated than a crystal orientation of a surface layer, it may difficult to control a direction of a crystal surface for the film. - Method of Manufacturing Printed Circuit Board
-
FIGS. 4 to 6 are cross-sectional views illustrating a manufacturing process flow for describing a method of manufacturing a printed circuit board according to a preferred embodiment of the present invention. - The method of manufacturing a printed circuit board according to a preferred embodiment of the present invention includes: preparing the insulating
layer 100; forming themetal layer 200 on the insulatinglayer 100; and etching themetal layer 200 by dry etching, in which in themetal layer 200, the ratio of the area occupied by thecrystal orientations 20 of (110) and (112) may be 20 to 80%. - Referring to
FIG. 4 , the insulatinglayer 100 may include silicon dioxide (SiO2), but is not particularly limited thereto. Further, the insulatinglayer 100 made of an epoxy resin composition may be used. - Referring to
FIG. 5 , the forming of themetal layer 200 may be performed by a deposition method. Further, the deposition method may be sputtering. - The sputtering is a technology of escaping metal molecules by colliding inert elements such as argon (Ar) with a target and then attaching a film on a surface. When DC power is applied to the target while inert gas as sputtering gas flows within a chamber in a vacuum state, plasma occurs between the substrate to be deposited and the target. The inert gas is ionized into anion within the plasma by a high output DC amperemeter. The anion of the inert gas is accelerated to a cathode by the DC ampere meter and thus collides with the surface of the target. In the so colliding target material, an atom jumps out from the surface to the outside by exchanging momentum by perfectly elastic collision. When ions collide with each other with kinetic energy larger than inter-atom bond energy, an interstitial atom of the material is pushed to another position by the collision of ions. In this case, the surface escaping of the atom occurs, which is referred to as the sputtering.
- When the sputtering is performed by using the metal plate made of the metal material to be plated as the target, the metal atom jumping out from the metal plate adheres to the insulating
layer 100, such that themetal layer 200 may be formed uniformly. An example of the material of the metal plate forming themetal layer 200 may include copper (Cu) which is most appropriate when considering the economic aspect and the electric conductivity aspect. - When in the
metal layer 200, the ratio of the area occupied by thecrystal orientations 20 of (110) and (112) is less than 20%, the elastic modulus of themetal layer 200 may be relatively weak in the lateral direction and when the ratio of the area exceeds 80%, many grain boundaries are distributed within themetal layer 200 and thus electrons may not flow smoothly and a scattering phenomenon occurs and thus electrical resistance may also be increased. - Further, although not particularly limited, the thickness of the
metal layer 200 may range from 30 to 300 nm. When the thickness of themetal layer 200 is less than 30 nm, the crystal orientation is little changed by ion beam etching, and the etching is more rapidly performed than forming a slip surface by ion implantation energy such that themetal layer 200 formed by the sputtering may also disappear. - When the thickness of the
metal layer 200 exeeds 300 nm, since the crystal orientation which does not cause a phase change of an inner layer is more dominated than a crystal orientation of a surface layer, it may difficult to control a direction of a crystal surface for the film. - Referring to
FIG. 6 , the etching of themetal layer 200 by dry etching may be performed by the ion beam etching. Further, an ion source of the ion beam etching may be gallium (Ga). - The ion beam is a cluster of molecules or atoms having charges as a mass of ion flow and when an electric field or a magnetic field is applied to the ion, the flow of ion may be accelerated. The accelerated ion in a high energy state is irradiated to the surface of the
metal layer 200, thereby etching a part of themetal layer 200. - The printed circuit board according to the preferred embodiment of the present invention uses a phenomenon in which the crystal orientation is changed while being etched when the gallium (Ga) ion is irradiated to the
metal layer 200. In this case, the driving force changing the crystal orientation may be heat energy or mechanical collision energy. - Generally, when the sputtering process is performed to form the
metal layer 200, themetal layer 200 may have (111) as a main crystal orientation. In addition, when a part of the crystal orientations of (220), (112), or the like may be included, a ratio thereof may be limited or may be locally present. - However, the printed circuit board including the formed
metal layer 200 may have a limitation in anisotropy of material properties. That is, a modulus value depending on the crystal orientation of themetal layer 200 is very strong physical properties in a thickness direction, but may have a relatively very small value. - Therefore, in the printed circuit board according to the preferred embodiment of the present invention, the gallium (Ga) ion fills an empty space from which a part of the
metal layer 200 is separated when the gallium (Ga) ion is irradiated to themetal layer 200. In this case, thecrystal orientation 10 of (111) is changed to thecrystal orientations 20 of (110) and (112) while the empty space from which themetal layer 200 of thecrystal orientation 10 of (111) is separated is filled with the gallium (Ga) ion. - By doing so, the
metal layer 200 has different crystal orientations and the elastic modulus of themetal layer 200 may have the excellent physical properties in the thickness direction and the lateral direction. - In the process of forming the
crystal orientations 20 of (110) and (112) on themetal layer 200 by the ion beam etching, the ratio of thecrystal orientations 20 of (110) and (112) included in themetal layer 200 may be controlled by the exposure time, acceleration voltage, or current amount of the ion beam. - To improve the adhesion between the insulating
layer 100 and themetal layer 200, one adhesive layer may also be formed between the insulatinglayer 100 and themetal layer 200. The adhesive layer may be made of, for example, titanium (Ti), chromium (Cr), nickel (Ni), iron (Fe), zirconium (Zr), tantalum (Ta), aluminum (Al), tungsten (W), platinum (Pt), or a mixture thereof, but is not particularly limited thereto. - The crystal orientations 20 of (110) and (112) may be formed in the island type. The crystal orientations 20 of (110) and (112) are present in the island type, such that the isotropy of mechanical properties may be improved. That is, the
crystal orientations 20 of (110) and (112) have a grain shape and soft grains of (110) and (112) are positioned between the strong grains of the existingcrystal orientation 10 of (111), such that the mechanical deformation occurring during the process may be accepted well. - Further, since the
crystal orientations 20 of (110) and (112) have the twin structure, the grain boundaries are not in disorder and are arranged having a constant rule. Therefore, the grain having thecrystal orientations 20 of (110) and (112) may minimize the hindrance of the flow of electrons. - According to the printed circuit board according to the preferred embodiments of the present invention, it is possible to minimize the factors of hindering electrical characteristics, such as electric conductivity, by using the printed circuit board including the
metal layer 200 in which the ratio of the area occupied by thecrystal orientations 20 of (110) and (112) is 20 to 80%. - Further, according to the printed circuit board according to the preferred embodiments of the present invention, it is possible to provide the printed circuit board including the
metal layer 200 having different crystal orientations to improve the isotropy of the mechanical physical property. - Although the embodiments of the present invention have been disclosed for illustrative purposes, it will be appreciated that the present invention is not limited thereto, and those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention.
- Accordingly, any and all modifications, variations or equivalent arrangements should be considered to be within the scope of the invention, and the detailed scope of the invention will be disclosed by the accompanying claims.
Claims (12)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020130140862A KR101983157B1 (en) | 2013-11-19 | 2013-11-19 | Printed circuit board and method of manufacturing the same |
KR10-2013-0140862 | 2013-11-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20150136458A1 true US20150136458A1 (en) | 2015-05-21 |
US9095063B2 US9095063B2 (en) | 2015-07-28 |
Family
ID=53172143
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/182,206 Active US9095063B2 (en) | 2013-11-19 | 2014-02-17 | Printed circuit board and method of manufacturing the same |
Country Status (2)
Country | Link |
---|---|
US (1) | US9095063B2 (en) |
KR (1) | KR101983157B1 (en) |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5456978A (en) * | 1993-08-03 | 1995-10-10 | Hmt Technology Corporation | Thin-film recording medium with thin metal sublayer |
US20020100909A1 (en) * | 2001-01-26 | 2002-08-01 | Shinya Yamaguchi | Thin film transistor |
US20020102823A1 (en) * | 2001-02-01 | 2002-08-01 | Shinya Yamaguchi | Thin film semiconductor device and method for producing thereof |
US6875324B2 (en) * | 1998-06-17 | 2005-04-05 | Tanaka Kikinzoku Kogyo K.K. | Sputtering target material |
US20090111247A1 (en) * | 2007-10-29 | 2009-04-30 | Semiconductor Energy Laboratory Co., Ltd. | Formation method of single crystal semiconductor layer, formation method of crystalline semiconductor layer, formation method of polycrystalline layer, and method for manufacturing semiconductor device |
US20100026952A1 (en) * | 2008-07-30 | 2010-02-04 | Kabushiki Kaisha Toshiba | Display device and method for manufacturing same |
US7821018B2 (en) * | 2006-02-16 | 2010-10-26 | Showa Denko K.K. | GaN-based semiconductor light-emitting device and method for the fabrication thereof |
US20110017020A1 (en) * | 2008-01-10 | 2011-01-27 | Shibaura Institute Of Technology | Method of recycling useful metal |
US20110027968A1 (en) * | 2007-08-24 | 2011-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US20130127295A1 (en) * | 2011-11-21 | 2013-05-23 | Electronics And Telecommunications Research Institute | Piezoelectric micro power generator and fabrication method thereof |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4430509B2 (en) * | 2004-10-20 | 2010-03-10 | 住友金属鉱山伸銅株式会社 | Rolled copper foil |
KR100936079B1 (en) | 2008-04-01 | 2010-01-12 | 삼성전기주식회사 | Method for manufacturing PCB |
KR101018161B1 (en) * | 2009-09-07 | 2011-02-28 | 삼성전기주식회사 | Wiring board and method for manufacturing the same |
JP2013053362A (en) * | 2011-09-06 | 2013-03-21 | Mitsubishi Materials Corp | Copper foil for forming circuit superior in etching property, and copper-clad laminate plate using the same and printed wiring board |
-
2013
- 2013-11-19 KR KR1020130140862A patent/KR101983157B1/en active IP Right Grant
-
2014
- 2014-02-17 US US14/182,206 patent/US9095063B2/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5456978A (en) * | 1993-08-03 | 1995-10-10 | Hmt Technology Corporation | Thin-film recording medium with thin metal sublayer |
US6875324B2 (en) * | 1998-06-17 | 2005-04-05 | Tanaka Kikinzoku Kogyo K.K. | Sputtering target material |
US20020100909A1 (en) * | 2001-01-26 | 2002-08-01 | Shinya Yamaguchi | Thin film transistor |
US20020102823A1 (en) * | 2001-02-01 | 2002-08-01 | Shinya Yamaguchi | Thin film semiconductor device and method for producing thereof |
US7821018B2 (en) * | 2006-02-16 | 2010-10-26 | Showa Denko K.K. | GaN-based semiconductor light-emitting device and method for the fabrication thereof |
US20110027968A1 (en) * | 2007-08-24 | 2011-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US20090111247A1 (en) * | 2007-10-29 | 2009-04-30 | Semiconductor Energy Laboratory Co., Ltd. | Formation method of single crystal semiconductor layer, formation method of crystalline semiconductor layer, formation method of polycrystalline layer, and method for manufacturing semiconductor device |
US20110017020A1 (en) * | 2008-01-10 | 2011-01-27 | Shibaura Institute Of Technology | Method of recycling useful metal |
US20100026952A1 (en) * | 2008-07-30 | 2010-02-04 | Kabushiki Kaisha Toshiba | Display device and method for manufacturing same |
US20130127295A1 (en) * | 2011-11-21 | 2013-05-23 | Electronics And Telecommunications Research Institute | Piezoelectric micro power generator and fabrication method thereof |
Also Published As
Publication number | Publication date |
---|---|
US9095063B2 (en) | 2015-07-28 |
KR20150057466A (en) | 2015-05-28 |
KR101983157B1 (en) | 2019-05-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4454246B2 (en) | Spring structure, method for manufacturing spring structure, integrated processing tool, and method for manufacturing spring structure on wafer | |
CN111463185B (en) | Nano double crystal structure | |
JP4738541B2 (en) | Circuit board manufacturing method | |
US20130122326A1 (en) | Electrodeposited Nano-Twins Copper Layer and Method of Fabricating the Same | |
WO2012111567A1 (en) | Cu-Zr-BASED COPPER ALLOY PLATE AND PROCESS FOR MANUFACTURING SAME | |
JP4930527B2 (en) | Copper alloy material and method for producing copper alloy material | |
CN114929911A (en) | Cu-Ni-Si-based copper alloy sheet material, method for producing same, and electrical component | |
US9095063B2 (en) | Printed circuit board and method of manufacturing the same | |
CN116666025A (en) | Nanoparticle magnetic film and electronic component | |
US20150130064A1 (en) | Methods of manufacturing semiconductor devices and a semiconductor structure | |
KR20060051651A (en) | Copper alloy for semiconductor interconnections, fabrication method thereof, semiconductor device having copper alloy interconnections fabricated by the method, and sputtering target for fabricating copper alloy interconnections for semiconductors | |
US20060219546A1 (en) | Concentration-graded alloy sputtering target | |
KR20190111140A (en) | Method for Forming Magnetic Film and Method for Manufacturing Magnetic Storage Element | |
US20180073104A1 (en) | Methods and apparatus for rejuvenation of amorphous alloys and micro-alloying | |
TWI803984B (en) | Nano-twinned structure on metallic thin film surface and method for forming the same | |
JPH07335575A (en) | Manufacture of thin film | |
Jo et al. | Thermal stress driven Sn whisker growth: in air and in vacuum | |
US10784045B2 (en) | Laminated magnetic materials for on-chip magnetic inductors/transformers | |
Sarkar | Synthesis and in situ Characterization of Nanostructured and Amorphous Metallic Films | |
JP2022088909A (en) | Slide contact member, conductive high hardness protective film and method for manufacturing slide contact member | |
CN115404451A (en) | Magnetic field adjusting device, thin film deposition equipment capable of generating uniform magnetic field and deposition method thereof | |
Lyu et al. | Microstructure analysis of sputtered copper thin film in packaging substrate | |
Xu | Nanotwin formation by electrodeposition and its influence on the physical properties and reliability of copper interconnects | |
JP5535131B2 (en) | Probe pin for semiconductor inspection apparatus and manufacturing method thereof | |
Yamamoto et al. | The Electroless Deposition of Fe-Ni Alloy Thin Films for Power Semiconductor Package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SAMSUNG ELECTRO-MECHANICS CO., LTD., KOREA, REPUBL Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YANG, EUN JU;KIM, GYU SEOK;HAM, SUK JIN;AND OTHERS;SIGNING DATES FROM 20140119 TO 20140120;REEL/FRAME:032232/0867 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |