US20140217475A1 - Manufacturing method of solid-state image pickup device and solid-state image pickup device - Google Patents
Manufacturing method of solid-state image pickup device and solid-state image pickup device Download PDFInfo
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- US20140217475A1 US20140217475A1 US13/896,568 US201313896568A US2014217475A1 US 20140217475 A1 US20140217475 A1 US 20140217475A1 US 201313896568 A US201313896568 A US 201313896568A US 2014217475 A1 US2014217475 A1 US 2014217475A1
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Definitions
- An embodiment described herein relates generally to a manufacturing method of a solid-state image pickup device and the solid-state image pickup device.
- the dark current is reduced by storing positive holes through ion implantation into the part of the light-receiving surface of the photodiode, and rejoining electrons excited regardless of incident light and positive holes.
- FIG. 1 is an explanatory diagram showing a top surface view of a CMOS sensor according to an embodiment
- FIG. 2 is an explanatory diagram showing a section view of a part of a pixel unit according to the embodiment
- FIG. 3 is an explanatory diagram showing an enlarged view near a transfer gate electrode shown in FIG. 2 ;
- FIGS. 4A to 4 c and FIGS. 5A to 5 c are explanatory diagrams showing a manufacturing method of the CMOS sensor according to the embodiment
- FIGS. 6A to 6 c are explanatory diagrams showing a top surface view of a manufacturing method of the CMOS sensor according to the embodiment
- FIGS. 7A to 7C are explanatory diagrams showing a manufacturing method of the CMOS sensor according to the embodiment.
- FIGS. 8A to 8C are explanatory diagrams showing a modification form as seen from a top surface view of an insulating film according to the embodiment.
- FIG. 9 is an explanatory diagram showing a part of a solid-state image pickup device which has been manufactured in accordance with the manufacturing method according to a modification of the embodiment.
- a manufacturing method of a solid-state image pickup device In the manufacturing method of a solid-state image pickup device, a transfer gate electrode, which transfer charges that are photoelectrically converted by a photoelectric conversion device to a floating diffusion area, is formed in a predetermined position on the upper surface of a first conductive semiconductor area through a gate insulating film. A second conductive charge storage area for storing the charges photoelectrically converted by the photoelectric conversion area is formed in an area adjacent to the transfer gate electrode in the first conductive semiconductor area. A sidewall is formed on the side surface of the transfer gate electrode.
- An insulating film is formed to extend from the circumference surface of the sidewall on the side of the charge storage area to a position partially covering the upper part of the charge storage area.
- a first conductive charge storage layer is formed on the upper surface of the charge storage area, by implanting first conductive impurities from above to the charge storage area which is partially covered with the insulating film.
- CMOS Complementary Metal Oxide Semiconductor
- wiring layer is formed on both sides of a photoelectric conversion device, onto which incident light enters and which performs photoelectric conversion on incident light.
- the solid-state image pickup device is not limited to the surface irradiation CMOS image sensor, and may include an arbitrary image sensor, such as so-called a back-surface irradiation CMOS image sensor, and a CCD (Charge Coupled Device) image sensor.
- an arbitrary image sensor such as so-called a back-surface irradiation CMOS image sensor, and a CCD (Charge Coupled Device) image sensor.
- CCD Charge Coupled Device
- FIG. 1 is an explanatory diagram showing a top surface view of the surface irradiation CMOS image sensor (hereinafter referred to as a CMOS sensor 1 ) according to the embodiment.
- the CMOS sensor 1 includes a pixel unit 2 and a peripheral circuit unit 3 .
- the pixel unit 2 includes a plurality of photoelectric conversion devices formed in matrix.
- the photoelectric conversion devices convert incident light into a certain amount of electric charges (in this case, electrons) in accordance with the amount of received light (intensity of received light), and store them in a charge storage area.
- a configuration of the photoelectric conversion devices will specifically be described with reference to FIG. 2 and FIG. 3 .
- the peripheral circuit unit 3 includes an analog circuit or a logic circuit. Specifically, the peripheral circuit unit 3 includes a timing generator 31 , a vertical selection circuit 32 , a sampling circuit 33 , a horizontal selection circuit 34 , a gain control circuit 35 , an A/D (analog/digital) conversion circuit 36 , and an input/output circuit 37 .
- the timing generator 31 is a processing unit which outputs a pulse signal as an operational timing criterion, for the pixel unit 2 , the vertical selection circuit 32 , the sampling circuit 33 , the horizontal selection circuit 34 , the gain control circuit 35 , the A/D conversion circuit 36 , and the input/output circuit 37 .
- the vertical selection circuit 32 is a processing unit which sequentially selects the photoelectric conversion devices in the unit of rows.
- the photoelectric conversion devices read electric charges from a plurality of photoelectric conversion devices arranged in matrix.
- the vertical selection circuit 32 causes the photoelectric conversion devices to output the electric charges stored in the photoelectric conversion devices selected in the unit of rows to the sampling circuit 33 , as pixel signals representing the brightness of each of pixels.
- the sampling circuit 33 is a processing unit which removes noise from the pixel signals input from each of the photoelectric conversion devices selected in the unit of rows by the vertical selection circuit 32 using CDS (Correlated Double Sampling) and temporarily stores them.
- CDS Correlated Double Sampling
- the horizontal selection circuit 34 is a processing unit which sequentially selects and reads each row of the pixel signals stored by the sampling circuit 33 and outputs the read signals to the gain control circuit 35 .
- the gain control circuit 35 is a processing unit which adjusts the gain of the pixel signal input from the horizontal selection circuit 34 and outputs the gain to the A/D conversion circuit 36 .
- the A/D conversion circuit 36 is a processing unit which converts the analog pixel signal input from the gain control circuit 35 into a digital pixel signal and outputs the signal to the input/output circuit 37 .
- the input/output circuit 37 is a processing unit which outputs the digital signal input from the A/D conversion circuit 36 to a predetermined DSP (Digital Signal Processor (not illustrated)).
- DSP Digital Signal Processor
- the image pickup is performed by the plurality of photoelectric conversion devices (arranged in the pixel unit 2 ) performing photoelectric conversion on incident light into a certain amount of electric charges in accordance with the amount of received light and storing them, and by the peripheral circuit unit 3 reading the electric charges stored in the photoelectric conversion devices as pixel signals.
- CMOS sensor 1 when there occurs an interface state due to crystal defect therein or when the contaminant is adhered to a side surface side (hereinafter referred to as “light receiving surface”) of the photoelectric conversion devices onto which incident light enters, electrons may be excited and stored into the photoelectric conversion devices onto which incident light has not entered yet.
- CMOS sensor 1 In the CMOS sensor 1 according to this embodiment, a positive hole storage layer in which positive holes are stored is included in the light receiving surface for the photoelectric conversion devices, to suppress a dark current by rejoining the electrons excited regardless of entrance of incident light with the positive holes of the positive hole storage area.
- the positive hole storage area in the photoelectric conversion devices preferably has a deep depth, and the concentration of the positive holes is preferably high. Note, however, if the positive hole storage area has a deep depth, and the concentration of the positive holes is high, it is difficult to read the electrons from the charge storage area. As a result, electrons which have not been read appear in the form of afterimages in the picked-up image.
- the CMOS sensor 1 includes the pixel unit 2 which is configured to suppress both white defects and afterimages in the picked up image.
- the configuration of the pixel unit 2 of this embodiment will now be described with reference to FIG. 2 .
- FIG. 2 is an explanatory diagram showing a section view of a part of the pixel unit 2 of this embodiment.
- constituent elements included in one pixel of the pixel unit 2 those constituent elements near the photoelectric conversion device 9 and the transfer gate electrode 6 are selectively illustrated, while a reset transistor, an amplifier transistor, and an address selection transistor are not illustrated.
- each pixel part of the pixel unit 2 has a first conductive semiconductor area 5 , a photoelectric conversion device 9 , a floating diffusion area 10 , a gate insulating film 61 , a transfer gate electrode 6 , a sidewall 62 , and an insulating 11 , on a semiconductor substrate 4 .
- each pixel part of the pixel unit 2 includes an antireflection film 12 , an interlayer insulating film 13 , multilayer wiring 14 , a contact plug 15 , a color filter 16 , and a micro lens 17 .
- the first conductive (hereinafter referred to as “P-type”) semiconductor area 5 (hereinafter referred to as “P-well 5 ”) is provided on the semiconductor substrate 4 .
- the transfer gate electrode 6 (hereinafter referred to as “TG 6 ”) is provided in a predetermined position on the upper surface of the P-well 5 through the gate insulating film 61 .
- the sidewall 62 is provided on the side surface of the TG 6 .
- the photoelectric conversion device 9 is provided in an area adjacent to one side surface of the top view TG 6 in the P-well 5 , as illustrated in the frame with dashed lines, and includes a second conductive (hereinafter referred to as “N-type”) charge storage area 8 and a P-type semiconductor layer (hereinafter referred to as “positive hole storage layer 7 ”) which stores positive holes.
- the photoelectric conversion device 9 (hereinafter referred to as “PD 9 ”) is a photodiode which is formed with a PN junction of the charge storage area 8 and the positive hole storage layer 7 .
- the device 9 performs photoelectric conversion on incident light from the micro lens 17 into a certain amount of electrons in accordance with the amount of light, and stores them into the charge storage area 8 .
- the positive hole storage layer 7 includes a first P-type layer 71 , a second P-type layer 72 , and a third P-type layer 73 , which have different depths in depth directions from the upper surface to the semiconductor substrate 4 and different concentrations of P-type impurities therebetween.
- the first P-type layer 71 is provided in the nearest position to the TG 6 in the positive hole storage layer 7 , has the shallowest depth in the positive hole storage layer 7 , and has the lowest concentration of the P-type impurities.
- the second P-type layer 72 is provided in the second nearest position to the TG 6 , after the first P-type layer 71 in the positive hole storage layer 7 , has the second deepest depth in the positive hole storage layer 7 , and has the second highest concentration of the P-type impurities.
- the third P-type layer 73 is provided in the farthest position from the TG 6 in the positive hole storage layer 7 , has the deepest depth in the positive hole storage layer 7 , and has the highest concentration of the P-type impurities.
- the P-type impurities are introduced at an energy level higher than the above introduction to the first P-type layer 71 which is partially covered with the sidewall 62 and the insulating film 11 .
- the second P-type layer 72 and the third P-type layer 73 are simultaneously formed to have the depths illustrated in FIG. 2 . This manufacturing method will more specifically be described with reference to FIGS. 4A to 7C .
- the TG 6 functions as the gate for transferring electrons from the charge storage area 8 to the floating fusion area 10 , when a predetermined gate voltage is applied.
- the floating diffusion area 10 (hereinafter referred to as “FD 10 ”) temporarily stores electrons transferred from the charge storage area 8 .
- the insulating film 11 is provided to cover the upper surface of the TG 6 on the side of the PD 9 , the peripheral surface of the sidewall 62 on the side of the PD 9 , and a part of the upper surface of the PD 9 on the side of the TG 6 . As described above, the insulating film 11 is provided to simultaneously form the second P-type layer 72 and the third P-type layer 73 which have different concentrations of the P-type impurities and different depths.
- the insulating film 11 does not necessarily cover a part of the upper surface of the TG 6 and the peripheral surface of the sidewall 62 , and may extend at least to a position covering the upper part of the charge storage area 8 from the circumference surface of the sidewall 62 on the side of the top view charge storage area 8 .
- the antireflection film 12 is a thin film provided to cover the light receiving surface of the PD 9 , the sidewall 62 , and the upper surface of the TG 6 , with a low photorefractive index and high light transmittance for suppressing reflection of incident light from the micro lens 17 to the PD 9 .
- the interlayer insulating film 13 is provided on the upper surface of the antireflection film 12 , and has the multilayer wiring 14 and the contact plug 15 which are embedded thereinside.
- the multilayer wiring 14 is wiring for transmitting a control signal for controlling operations of the pixel unit 2 to an active device of each pixel.
- the contact plug 15 is a plug for applying a predetermined gate voltage to the TG 6 .
- the color filter 16 is provided on the upper surface of the interlayer insulating film 13 , and transmits either incident light of either one color from the three primary colors of read, green, and blue.
- the micro lens 17 is provided on the upper surface of the color filter 16 , and is a plane-convex lens for condensing incident light to the PD 9 .
- the pixel unit 2 performs photoelectric conversion on the incident light into electrons using the PD 9 , and stores the electrons as signal charges in the charge storage area 8 . After this, the pixel unit 2 transfers the signal charges from the charge storage area 8 of the PD 9 to the FD 10 , when a gate voltage is applied to the TG 6 .
- the signal charges transferred to the FD 10 are amplified by a non-illustrative amplifier transistor. Further, when a non-illustrative address selection transistor is selected, the signal charges are transferred to the peripheral circuit unit 3 as pixel signals, and are used as brightness information for one pixel when the picked-up image is generated.
- FIG. 3 is an explanatory diagram showing an enlarged view near the TG 6 illustrated in FIG. 2 , according to this embodiment.
- the PD 9 of the pixel unit 2 includes the positive hole storage layer 7 in the upper surface part of the charge storage area 8 .
- the PD 9 can rejoin the excited electrons with the positive holes of the positive hole storage layer 7 , when the electrons are excited regardless of entrance of incident light by contaminant on the light receiving surface or the interface state due to crystal defect.
- the electrons excited regardless of the entrance of incident light are suppressed from being transferred to the FD 10 in the form of a dark current. This results in suppressing the white defects in the picked up image due to the dark current.
- the periphery of the positive hole storage layer 7 on the side of the TG 6 forms the insulating film 11 after forming the first P-type layer 71 .
- the second P-type layer 72 and the third P-type layer 73 are formed.
- the nearer to the TG 6 the shallower the depth becomes, and the lower the concentration of the P-type impurities becomes.
- the positive hole storage layer 7 has the same depth as that of the third P-type layer 73 and has the same concentration of the P-type impurities, in its entirety except the part right below the sidewall 62 .
- the potential barrier increase between the channel formed right below the TG 6 and the charge storage area 8 , when a gate voltage is applied to the TG 6 .
- the insulating film 11 is formed before forming the second P-type layer 72 and the third P-type layer 73 , thereby attaining the shallow depth of the positive hole storage layer 7 and the low concentration of the P-type impurities, as nearer to the TG 6 .
- the potential barrier can be low between the channel formed right below the TG 6 and the charge storage area 8 , when the gate voltage is applied to the TG 6 .
- the pixel unit 2 can transfer the electrons to the FD 10 through the upper layer unit of the charge storage area 8 through which the electrons are easily moved, from the charge storage area 8 toward the channel right below the TG 6 .
- the pixel unit 2 it is possible to avoid the phenomenon that the electrons without being transferred to the FD 10 remain in the charge storage area 8 . Therefore, it is also possible to suppress that the electrons remaining in the charge storage area 8 are transferred to the FD 10 afterwards and appear as afterimages in the picked up image.
- FIGS. 4A to 7C are explanatory diagrams showing the manufacturing method of the CMOS sensor 1 according to this embodiment. The descriptions will be made to a step of forming the part illustrated in FIG. 2 , in the pixel unit 2 included in the CMOS sensor 1 .
- the P-type P-well 5 is formed on the upper surface of the semiconductor substrate 4 , for example, a silicon wafer.
- P-type impurities for example, B (boron)
- the P-well 5 may be formed by forming a hole in the formation position for the P-well 5 of the semiconductor substrate 4 , and by performing an epitaxial growth process for a P-type silicon layer in the hole.
- the TG 6 is formed through the gate insulating film 6 in a predetermined position on the upper surface of the P-well 5 .
- a thin silicon oxide film with a thickness of approximately 5 nm is formed on the upper surface of the P-well 5
- a polysilicon layer with a thickness of approximately 150 nm is formed on the upper surface of the silicon oxide film.
- any unnecessary parts of the polysilicon layer and the silicon oxide film are removed therefrom, to form the gate insulating film 61 and the TG 6 .
- the charge storage area 8 and the first P-type layer 71 are formed in a position for forming the PD 9 in the P-well 5 .
- a resist M 1 is formed on a part excluding a predetermined area adjacent to one side surface of the TG 6 in the top view and on the upper surface of the TG 6 , of the upper surface of the P-well 5 .
- N-type impurities for example, P (phosphorus)
- P-type impurities are implanted into the P-well, as the resist M 1 .
- an annealing process is performed.
- the charge storage area 8 and the first P-type layer 71 are formed.
- the sidewall 62 is formed on the side surface of the TG 6 .
- a silicon oxide film and a silicon nitride film are sequentially formed on the entire surface of the structure.
- etching back is performed in accordance with RIE (Reactive Ion Etching), thereby forming the sidewall 62 .
- the FD 10 is formed in an area opposed to the charge storage area 8 across the TG 6 of the P-well 5 in the top view.
- This FF 10 is formed in accordance with the same method as for the charge storage area 8 .
- the part excluding the position for forming the FD 10 is covered with the resist.
- the resist is separated therefrom, and an annealing process is performed, thereby forming the FD 10 .
- the first P-type layer 71 and the FD 10 are formed in positions opposed to each other across the TG 6 in the top view.
- the insulating film 11 is formed on the entire surface of the structure illustrated in FIG. 5A .
- a silicon oxide film or a silicon nitride, with a thickness of approximately 10 nm, film is formed.
- a resist M 2 is formed on the insulating film 11 in a part, including the boundary between the TG 6 and the charge storage area 8 in the top view and covering both of a part of the TG 6 on the side of the charge storage area 8 and the upper part of the charge storage area 8 on the side of the TG 6 .
- any unnecessary parts of the insulating film 11 are removed through an etching process, using the resist M 2 as a mask, thereby forming the structure illustrated in FIG. 5C and FIG. 6C . This results in forming the insulating film 11 which has been patterned. In this patterning, one end of the film 11 extends at least from the circumference surface of the sidewall on the side of the charge storage area 8 to a position partially covering the upper part of the charge storage area 8 , in the top view.
- a distance “d”, from the circumference surface of the sidewall 62 on the side of the charge storage area 8 to a position partially covering the upper part of the charge storage area 8 is approximately from 10 nm to 40 nm. Because the second P-type layer 72 (see FIGS. 7A to 7C ) will be formed afterwards, the insulating film 11 is formed to cover from the circumference surface of the sidewall 62 on the side of the charge storage area 8 to the upper part of the charge storage area 8 , instead of covering the entire surface of the charge storage area 8 .
- the insulating film 11 is not formed on the entire surface of the charge storage area 8 , to form the second P-type layer 72 afterwards.
- the second P-type layer 72 it is possible to attain the suppression characteristic of suppressing white defects and afterimages, by the second P-type layer 72 to be formed afterwards.
- the insulating film 11 is formed in a manner that the other end thereof extends from the circumference surface of the sidewall 62 on the charge storage area 8 to at least a part of the upper surface of the TG 6 , in the top view.
- the insulating film 11 of FIG. 5C exists on the upper surface of the first P-type layer 71 .
- the insulating film 11 extends up to the upper surface of the TG 6 to have a large area of the insulating film 11 , thereby easily performing patterning of the insulating film 11 .
- the positive hole storage layer 7 is formed by forming the second P-type layer 72 and the third P-type layer 73 .
- a resist M 3 is formed to cover a part excluding the upper part of the charge storage area 8 , on the upper surface of the structure illustrated in FIG. 5C .
- the P-type impurities are implanted from above, while using the resist M 3 as a mask. After this, the annealing process is performed, thereby forming the positive hole storage layer 7 to form the PD 9 .
- the ion implantation is performed at a higher energy level than that for forming the first P-type layer 71 .
- the amount of implantation of P-type impurities and the energy level of the second P-type layer 72 can be limited by the insulating film 11 .
- the second P-type layer 72 is shallower than the third P-type layer 73 and deeper than the first P-type layer 71 , has a lower concentration of the P-type impurities than that of the third P-type layer 73 , and has a higher concentration of the P-type impurities than the first P-type layer 71 .
- the relative relationship of the depth or impurity concentration between the first P-type layer 71 and the second P-type layer 72 can be adjusted in accordance with the energy level applied to the impurity ions to be implanted.
- the relative relationship of the depth or impurity concentration between the third P-type layer 73 and the second P-type layer 72 can be adjusted by changing the thickness of the insulating film 11 .
- the positive hole storage layer 7 is formed to be shallower as nearer to the TG 6 , and to have a lower concentration of the P-type impurities. Accordingly, in the pixel unit 2 , the white defects and afterimages can be suppressed in the picked up image.
- the antireflection film 12 is formed on the entire surface including the PD 9 , the TG 6 and the FD 10 .
- a silicon nitride film with a thickness of approximately 10 nm is formed as an antireflection film.
- the antireflection film 12 has been formed on the entire surface of the structure including the insulating film 11 .
- the insulating film 11 may be removed before forming the antireflection film 12 . If the insulating film 11 is removed before forming the antireflection film 12 , the flatness of the constituent elements (the interlayer insulating film 13 formed in the upper layer) can be improved afterwards.
- the interlayer insulating film 13 , the contact plug 15 , and the multilayer wiring 14 are formed on the antireflection film 12 , using a known damascene technique or a dual damascene technique.
- the color filter 16 and the micro lens 17 are sequentially laminated to form the pixel unit 2 in a position overlapping with the top view PD 9 on the upper surface of the interlayer insulating film 13 , to manufacture the CMOS sensor 1 .
- the transfer gate electrode is formed in a predetermined position on the upper surface of the first conductive semiconductor area through the gate insulating film.
- the transfer gate electrode transfers the charges which have been photoelectrically converted by the photoelectric conversion device to the floating diffusion area.
- a second conductive charge storage area is formed in an area adjacent to the top view transfer gate electrode in the first conductive semiconductor area, to form sidewalls on the side surfaces of the transfer gate electrode. Note that the second conductive charge storage area is formed to store those charges which have been photoelectrically converted by the photoelectric conversion device.
- an insulating film is formed to extend from the circumference surface of the sidewall on the side of the top view charge storage area up to a position partially covering the upper part of the charge storage area.
- the first conductive impurities are implanted from above into the charge storage area whose upper part is partially covered with the insulating film, to form the first conductive charge storage layer on the upper surface of the charge storage area.
- the manufacturing method of the solid-state image pickup device it is possible to manufacture a solid-state image pickup device in which the white defects and afterimages can be suppressed in the picked up image.
- FIGS. 8A to 8C are explanatory diagrams showing a modification of the form of the insulating film in the top view.
- FIGS. 8A to 8C the same constituent elements as those of the FIGS. 6A to 6C are identified by the same reference symbols as those of FIGS. 6A to 6C .
- an insulating film 11 a may be formed in place of the insulating film 11 , includes at least the boundary between the sidewall 62 and the first P-type layer 71 in the top view, and surrounds the upper surface of the TG 6 in a C-shape in the top view.
- an insulating film 11 b may be formed in place of the insulating film 11 , includes at least the boundary between the sidewall 62 and the first P-type layer 71 in the top view, and covers half of the first P-type layer 71 on the upper surface of the sidewall 62 and the TG 6 .
- an insulating film 11 c may be formed in place of the insulating film 11 , includes at least the boundary between the sidewall 62 and the first P-type layer 71 in the top view, and covers the entire surface of the sidewall 62 , the TG 6 , and the FD 10 .
- the second P-type layer 72 may be formed right below an area surrounded by the frame with dashed-dotted line in FIGS. 8A to 8C .
- the third P-type layer 73 may be formed right below the first P-type layer 71 which is not covered with the insulating films 11 a , 11 b , and 11 c.
- FIG. 9 is an explanatory diagram showing a part of the solid-state image pickup device which is manufactured using a manufacturing method according to a modification of the embodiment.
- the part of the solid-state image pickup device illustrated in FIG. 9 corresponds to the part illustrated in FIG. 3 .
- the constituent elements having the same functions as those of the constituent elements of FIG. 3 are identified by the same reference symbols illustrated in FIG. 3 .
- the insulating film 11 d is formed before forming the sidewall 62 .
- the charge storage area 8 , the first P-type layer 71 , the FD 10 , and the insulating film 11 d are sequentially formed.
- the sidewall 62 is formed, the second P-type layer 72 and the third P-type layer 73 are sequentially formed. Then, the device is manufactured in accordance with the same manufacturing steps illustrated in and after FIG. 7B .
- the positive hole storage layer 7 may be formed on the upper surface part of the charge storage area 8 .
- This positive hole storage layer 7 is shallower, and has a lower concentration of the P-type impurities, as nearer to the TG 6 .
- the second P-type layer 72 is formed deep as illustrated with the dashed-dotted line in FIG. 9 .
- those electrons stored in the charge storage area 8 are transferred from the charge storage area 8 to the FD 10 through the lower layer part of the charge storage area 8 whose potential barrier is relatively high, as illustrated with a dotted arrow.
- the charges can be transferred from the charge storage area 8 to the FD 10 through the upper layer part of the charge storage area 8 whose potential barrier is relatively low, as illustrated with a solid arrow. Therefore, according to the solid-state image pickup device illustrated in FIG. 9 , it is possible to avoid the occurrence of afterimages due to the electrons remaining in the charge storage area 8 without being transferred to the FD 10 .
- the descriptions have been made to the surface irradiation CMOS as an example of the solid-state image pickup device.
- the manufacturing method of the solid-state image pickup device according to this embodiment is applicable to a back-surface irradiation CMOS image sensor.
Abstract
Description
- This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2013-019632, filed on Feb. 4, 2013; the entire contents of which are incorporated herein by reference.
- An embodiment described herein relates generally to a manufacturing method of a solid-state image pickup device and the solid-state image pickup device.
- Conventionally, in solid-state image pickup devices, electrons which are excited regardless of incident light may sometimes be a dark current and read out, due to crystal defect or metal contamination on the light receiving surface of a photodiode. This dark current causes white defects appearing in a picked-up image.
- Thus, according to an applicable method, in a step of manufacturing the solid-state image pickup device, the dark current is reduced by storing positive holes through ion implantation into the part of the light-receiving surface of the photodiode, and rejoining electrons excited regardless of incident light and positive holes.
- However, when there is an increased amount of positive holes stored in the light receiving surface part of the photodiode, it is difficult to read the photoelectrically-converted electrons from the photodiode. This results in a problem that some electrons without being read and remaining in the photodiode cause so-called afterimages.
-
FIG. 1 is an explanatory diagram showing a top surface view of a CMOS sensor according to an embodiment; -
FIG. 2 is an explanatory diagram showing a section view of a part of a pixel unit according to the embodiment; -
FIG. 3 is an explanatory diagram showing an enlarged view near a transfer gate electrode shown inFIG. 2 ; -
FIGS. 4A to 4 c andFIGS. 5A to 5 c are explanatory diagrams showing a manufacturing method of the CMOS sensor according to the embodiment; -
FIGS. 6A to 6 c are explanatory diagrams showing a top surface view of a manufacturing method of the CMOS sensor according to the embodiment; -
FIGS. 7A to 7C are explanatory diagrams showing a manufacturing method of the CMOS sensor according to the embodiment; -
FIGS. 8A to 8C are explanatory diagrams showing a modification form as seen from a top surface view of an insulating film according to the embodiment; and -
FIG. 9 is an explanatory diagram showing a part of a solid-state image pickup device which has been manufactured in accordance with the manufacturing method according to a modification of the embodiment. - According to one embodiment of the present invention, there is provided a manufacturing method of a solid-state image pickup device. In the manufacturing method of a solid-state image pickup device, a transfer gate electrode, which transfer charges that are photoelectrically converted by a photoelectric conversion device to a floating diffusion area, is formed in a predetermined position on the upper surface of a first conductive semiconductor area through a gate insulating film. A second conductive charge storage area for storing the charges photoelectrically converted by the photoelectric conversion area is formed in an area adjacent to the transfer gate electrode in the first conductive semiconductor area. A sidewall is formed on the side surface of the transfer gate electrode. An insulating film is formed to extend from the circumference surface of the sidewall on the side of the charge storage area to a position partially covering the upper part of the charge storage area. A first conductive charge storage layer is formed on the upper surface of the charge storage area, by implanting first conductive impurities from above to the charge storage area which is partially covered with the insulating film.
- An exemplary embodiment of a manufacturing method of a solid-state image pickup device and the solid-state image pickup device will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiment.
- In this embodiment, descriptions will be made to so-called a surface irradiation CMOS (Complementary Metal Oxide Semiconductor) image sensor as an example of a solid-state image pickup device. In the CMOS image sensor, wiring layer is formed on both sides of a photoelectric conversion device, onto which incident light enters and which performs photoelectric conversion on incident light.
- The solid-state image pickup device according to this embodiment is not limited to the surface irradiation CMOS image sensor, and may include an arbitrary image sensor, such as so-called a back-surface irradiation CMOS image sensor, and a CCD (Charge Coupled Device) image sensor.
-
FIG. 1 is an explanatory diagram showing a top surface view of the surface irradiation CMOS image sensor (hereinafter referred to as a CMOS sensor 1) according to the embodiment. As illustrated inFIG. 1 , the CMOS sensor 1 includes apixel unit 2 and aperipheral circuit unit 3. - The
pixel unit 2 includes a plurality of photoelectric conversion devices formed in matrix. The photoelectric conversion devices convert incident light into a certain amount of electric charges (in this case, electrons) in accordance with the amount of received light (intensity of received light), and store them in a charge storage area. A configuration of the photoelectric conversion devices will specifically be described with reference toFIG. 2 andFIG. 3 . - The
peripheral circuit unit 3 includes an analog circuit or a logic circuit. Specifically, theperipheral circuit unit 3 includes atiming generator 31, avertical selection circuit 32, asampling circuit 33, ahorizontal selection circuit 34, again control circuit 35, an A/D (analog/digital)conversion circuit 36, and an input/output circuit 37. - The
timing generator 31 is a processing unit which outputs a pulse signal as an operational timing criterion, for thepixel unit 2, thevertical selection circuit 32, thesampling circuit 33, thehorizontal selection circuit 34, thegain control circuit 35, the A/D conversion circuit 36, and the input/output circuit 37. - The
vertical selection circuit 32 is a processing unit which sequentially selects the photoelectric conversion devices in the unit of rows. The photoelectric conversion devices read electric charges from a plurality of photoelectric conversion devices arranged in matrix. Thevertical selection circuit 32 causes the photoelectric conversion devices to output the electric charges stored in the photoelectric conversion devices selected in the unit of rows to thesampling circuit 33, as pixel signals representing the brightness of each of pixels. - The
sampling circuit 33 is a processing unit which removes noise from the pixel signals input from each of the photoelectric conversion devices selected in the unit of rows by thevertical selection circuit 32 using CDS (Correlated Double Sampling) and temporarily stores them. - The
horizontal selection circuit 34 is a processing unit which sequentially selects and reads each row of the pixel signals stored by thesampling circuit 33 and outputs the read signals to thegain control circuit 35. Thegain control circuit 35 is a processing unit which adjusts the gain of the pixel signal input from thehorizontal selection circuit 34 and outputs the gain to the A/D conversion circuit 36. - The A/
D conversion circuit 36 is a processing unit which converts the analog pixel signal input from thegain control circuit 35 into a digital pixel signal and outputs the signal to the input/output circuit 37. The input/output circuit 37 is a processing unit which outputs the digital signal input from the A/D conversion circuit 36 to a predetermined DSP (Digital Signal Processor (not illustrated)). - In this manner, in the CMOS sensor 1, the image pickup is performed by the plurality of photoelectric conversion devices (arranged in the pixel unit 2) performing photoelectric conversion on incident light into a certain amount of electric charges in accordance with the amount of received light and storing them, and by the
peripheral circuit unit 3 reading the electric charges stored in the photoelectric conversion devices as pixel signals. - In the CMOS sensor 1, when there occurs an interface state due to crystal defect therein or when the contaminant is adhered to a side surface side (hereinafter referred to as “light receiving surface”) of the photoelectric conversion devices onto which incident light enters, electrons may be excited and stored into the photoelectric conversion devices onto which incident light has not entered yet.
- These electrons become a dark current and flows from the
pixel unit 2 to theperipheral circuit unit 3, and may appear in the form of white defects in the picked-up image, while the pixel signals are read by theperipheral circuit unit 3. Thus, in the CMOS sensor 1 according to this embodiment, a positive hole storage layer in which positive holes are stored is included in the light receiving surface for the photoelectric conversion devices, to suppress a dark current by rejoining the electrons excited regardless of entrance of incident light with the positive holes of the positive hole storage area. - To improve the suppression characteristic of suppressing the dark current, the positive hole storage area in the photoelectric conversion devices preferably has a deep depth, and the concentration of the positive holes is preferably high. Note, however, if the positive hole storage area has a deep depth, and the concentration of the positive holes is high, it is difficult to read the electrons from the charge storage area. As a result, electrons which have not been read appear in the form of afterimages in the picked-up image.
- The CMOS sensor 1 includes the
pixel unit 2 which is configured to suppress both white defects and afterimages in the picked up image. The configuration of thepixel unit 2 of this embodiment will now be described with reference toFIG. 2 . -
FIG. 2 is an explanatory diagram showing a section view of a part of thepixel unit 2 of this embodiment. InFIG. 2 , of constituent elements included in one pixel of thepixel unit 2, those constituent elements near thephotoelectric conversion device 9 and thetransfer gate electrode 6 are selectively illustrated, while a reset transistor, an amplifier transistor, and an address selection transistor are not illustrated. - As illustrated in
FIG. 2 , each pixel part of thepixel unit 2 has a firstconductive semiconductor area 5, aphotoelectric conversion device 9, afloating diffusion area 10, a gateinsulating film 61, atransfer gate electrode 6, asidewall 62, and an insulating 11, on asemiconductor substrate 4. Further, each pixel part of thepixel unit 2 includes anantireflection film 12, an interlayerinsulating film 13,multilayer wiring 14, acontact plug 15, acolor filter 16, and amicro lens 17. - The first conductive (hereinafter referred to as “P-type”) semiconductor area 5 (hereinafter referred to as “P-well 5”) is provided on the
semiconductor substrate 4. The transfer gate electrode 6 (hereinafter referred to as “TG 6”) is provided in a predetermined position on the upper surface of the P-well 5 through thegate insulating film 61. Thesidewall 62 is provided on the side surface of theTG 6. - The
photoelectric conversion device 9 is provided in an area adjacent to one side surface of thetop view TG 6 in the P-well 5, as illustrated in the frame with dashed lines, and includes a second conductive (hereinafter referred to as “N-type”)charge storage area 8 and a P-type semiconductor layer (hereinafter referred to as “positivehole storage layer 7”) which stores positive holes. The photoelectric conversion device 9 (hereinafter referred to as “PD 9”) is a photodiode which is formed with a PN junction of thecharge storage area 8 and the positivehole storage layer 7. Thedevice 9 performs photoelectric conversion on incident light from themicro lens 17 into a certain amount of electrons in accordance with the amount of light, and stores them into thecharge storage area 8. - The positive
hole storage layer 7 includes a first P-type layer 71, a second P-type layer 72, and a third P-type layer 73, which have different depths in depth directions from the upper surface to thesemiconductor substrate 4 and different concentrations of P-type impurities therebetween. The first P-type layer 71 is provided in the nearest position to theTG 6 in the positivehole storage layer 7, has the shallowest depth in the positivehole storage layer 7, and has the lowest concentration of the P-type impurities. - The second P-
type layer 72 is provided in the second nearest position to theTG 6, after the first P-type layer 71 in the positivehole storage layer 7, has the second deepest depth in the positivehole storage layer 7, and has the second highest concentration of the P-type impurities. The third P-type layer 73 is provided in the farthest position from theTG 6 in the positivehole storage layer 7, has the deepest depth in the positivehole storage layer 7, and has the highest concentration of the P-type impurities. - This results from particular introduction of the P-type impurities. Specifically, after the first P-
type layer 71 is formed by introducing the P-type impurities to the upper surface of thecharge storage area 8 before the positionhole storage layer 7 is formed, the P-type impurities are introduced at an energy level higher than the above introduction to the first P-type layer 71 which is partially covered with thesidewall 62 and the insulatingfilm 11. Then, the second P-type layer 72 and the third P-type layer 73 are simultaneously formed to have the depths illustrated inFIG. 2 . This manufacturing method will more specifically be described with reference toFIGS. 4A to 7C . - The
TG 6 functions as the gate for transferring electrons from thecharge storage area 8 to the floatingfusion area 10, when a predetermined gate voltage is applied. The floating diffusion area 10 (hereinafter referred to as “FD 10”) temporarily stores electrons transferred from thecharge storage area 8. - The insulating
film 11 is provided to cover the upper surface of theTG 6 on the side of thePD 9, the peripheral surface of thesidewall 62 on the side of thePD 9, and a part of the upper surface of thePD 9 on the side of theTG 6. As described above, the insulatingfilm 11 is provided to simultaneously form the second P-type layer 72 and the third P-type layer 73 which have different concentrations of the P-type impurities and different depths. - The insulating
film 11 does not necessarily cover a part of the upper surface of theTG 6 and the peripheral surface of thesidewall 62, and may extend at least to a position covering the upper part of thecharge storage area 8 from the circumference surface of thesidewall 62 on the side of the top viewcharge storage area 8. - The
antireflection film 12 is a thin film provided to cover the light receiving surface of thePD 9, thesidewall 62, and the upper surface of theTG 6, with a low photorefractive index and high light transmittance for suppressing reflection of incident light from themicro lens 17 to thePD 9. Theinterlayer insulating film 13 is provided on the upper surface of theantireflection film 12, and has themultilayer wiring 14 and thecontact plug 15 which are embedded thereinside. - The
multilayer wiring 14 is wiring for transmitting a control signal for controlling operations of thepixel unit 2 to an active device of each pixel. Thecontact plug 15 is a plug for applying a predetermined gate voltage to theTG 6. Thecolor filter 16 is provided on the upper surface of theinterlayer insulating film 13, and transmits either incident light of either one color from the three primary colors of read, green, and blue. Themicro lens 17 is provided on the upper surface of thecolor filter 16, and is a plane-convex lens for condensing incident light to thePD 9. - The
pixel unit 2 performs photoelectric conversion on the incident light into electrons using thePD 9, and stores the electrons as signal charges in thecharge storage area 8. After this, thepixel unit 2 transfers the signal charges from thecharge storage area 8 of thePD 9 to theFD 10, when a gate voltage is applied to theTG 6. The signal charges transferred to theFD 10 are amplified by a non-illustrative amplifier transistor. Further, when a non-illustrative address selection transistor is selected, the signal charges are transferred to theperipheral circuit unit 3 as pixel signals, and are used as brightness information for one pixel when the picked-up image is generated. - After the first P-
type layer 71 is formed in thePD 9, thepixel unit 2 forms the insulatingfilm 11 illustrated inFIG. 2 , before forming the second P-type layer 72 and the third P-type layer 73, resulting in a configuration for suppressing both the white defects and afterimages in the picked-up image. The configuration for suppressing the white defects and the afterimages will now be described with reference toFIG. 3 .FIG. 3 is an explanatory diagram showing an enlarged view near theTG 6 illustrated inFIG. 2 , according to this embodiment. - As illustrated in
FIG. 3 , thePD 9 of thepixel unit 2 includes the positivehole storage layer 7 in the upper surface part of thecharge storage area 8. With this configuration, thePD 9 can rejoin the excited electrons with the positive holes of the positivehole storage layer 7, when the electrons are excited regardless of entrance of incident light by contaminant on the light receiving surface or the interface state due to crystal defect. - With the
pixel unit 2, the electrons excited regardless of the entrance of incident light are suppressed from being transferred to theFD 10 in the form of a dark current. This results in suppressing the white defects in the picked up image due to the dark current. - The periphery of the positive
hole storage layer 7 on the side of theTG 6 forms the insulatingfilm 11 after forming the first P-type layer 71. After this, the second P-type layer 72 and the third P-type layer 73 are formed. As a result, the nearer to theTG 6, the shallower the depth becomes, and the lower the concentration of the P-type impurities becomes. - Before forming the second P-
type layer 72 and the third P-type layer 73, if the insulatingfilm 11 had not been formed, as illustrated with the dashed-dotted line inFIG. 3 , the positivehole storage layer 7 has the same depth as that of the third P-type layer 73 and has the same concentration of the P-type impurities, in its entirety except the part right below thesidewall 62. As a result, the potential barrier increase between the channel formed right below theTG 6 and thecharge storage area 8, when a gate voltage is applied to theTG 6. - When the gate voltage is applied to the
TG 6, as illustrated with a dotted arrow inFIG. 3 , electrons are transferred to theFD 10 through the lower layer unit of thecharge storage area 8 through which the electrons are not easily moved, from thecharge storage area 8 toward the channel right below theTG 6. Therefore, there occurs a phenomenon that some electrons without being transferred to theFD 10 remain in thecharge storage area 8, and the electrons remaining in thecharge storage area 8 are transferred to theFD 10 afterwards and appear as afterimages in the picked up image. - In the
pixel unit 2, after forming the first P-type layer 71, the insulatingfilm 11 is formed before forming the second P-type layer 72 and the third P-type layer 73, thereby attaining the shallow depth of the positivehole storage layer 7 and the low concentration of the P-type impurities, as nearer to theTG 6. In thepixel unit 2, the potential barrier can be low between the channel formed right below theTG 6 and thecharge storage area 8, when the gate voltage is applied to theTG 6. - As illustrated with a solid arrow in
FIG. 3 , when the gate voltage is applied to theTG 6, thepixel unit 2 can transfer the electrons to theFD 10 through the upper layer unit of thecharge storage area 8 through which the electrons are easily moved, from thecharge storage area 8 toward the channel right below theTG 6. - According to the
pixel unit 2, it is possible to avoid the phenomenon that the electrons without being transferred to theFD 10 remain in thecharge storage area 8. Therefore, it is also possible to suppress that the electrons remaining in thecharge storage area 8 are transferred to theFD 10 afterwards and appear as afterimages in the picked up image. - Descriptions will now be made to a manufacturing method of the CMOS sensor 1 according to this embodiment, with reference to
FIGS. 4A to 7C .FIGS. 4A to 7C are explanatory diagrams showing the manufacturing method of the CMOS sensor 1 according to this embodiment. The descriptions will be made to a step of forming the part illustrated inFIG. 2 , in thepixel unit 2 included in the CMOS sensor 1. - In the manufacturing method of the CMOS sensor 1 according to this embodiment, as illustrated in
FIG. 4A , the P-type P-well 5 is formed on the upper surface of thesemiconductor substrate 4, for example, a silicon wafer. To form the P-well 5, P-type impurities (for example, B (boron)) are implanted into a position for forming the P-well 5 of thesemiconductor substrate 4, thereafter performing an annealing process thereon. The P-well 5 may be formed by forming a hole in the formation position for the P-well 5 of thesemiconductor substrate 4, and by performing an epitaxial growth process for a P-type silicon layer in the hole. - Subsequently, the
TG 6 is formed through thegate insulating film 6 in a predetermined position on the upper surface of the P-well 5. Specifically, a thin silicon oxide film with a thickness of approximately 5 nm is formed on the upper surface of the P-well 5, and a polysilicon layer with a thickness of approximately 150 nm is formed on the upper surface of the silicon oxide film. Then, using a photolithography/etching process, any unnecessary parts of the polysilicon layer and the silicon oxide film are removed therefrom, to form thegate insulating film 61 and theTG 6. - As illustrated in
FIG. 4B , thecharge storage area 8 and the first P-type layer 71 are formed in a position for forming thePD 9 in the P-well 5. Specifically, a resist M1 is formed on a part excluding a predetermined area adjacent to one side surface of theTG 6 in the top view and on the upper surface of theTG 6, of the upper surface of the P-well 5. N-type impurities (for example, P (phosphorus)) are implanted into the P-well, as the resist M1. Then, after P-type impurities are implanted into the P-well 5, using the resist M1 as a mask, an annealing process is performed. As a result, thecharge storage area 8 and the first P-type layer 71 are formed. - Subsequently, after separating the resist M1 therefrom, as illustrated in
FIG. 4C , thesidewall 62 is formed on the side surface of theTG 6. For example, after separating the resist M1 from the structure illustrated inFIG. 4B , a silicon oxide film and a silicon nitride film are sequentially formed on the entire surface of the structure. Then, etching back is performed in accordance with RIE (Reactive Ion Etching), thereby forming thesidewall 62. - Subsequently, as illustrated in
FIG. 5A , theFD 10 is formed in an area opposed to thecharge storage area 8 across theTG 6 of the P-well 5 in the top view. ThisFF 10 is formed in accordance with the same method as for thecharge storage area 8. - For example, of the upper surface of the structure illustrated in
FIG. 4C , the part excluding the position for forming theFD 10 is covered with the resist. After the N-type impurities are implanted using the resist as a mask, the resist is separated therefrom, and an annealing process is performed, thereby forming theFD 10. As a result, as illustrated inFIG. 6A , the first P-type layer 71 and theFD 10 are formed in positions opposed to each other across theTG 6 in the top view. - Subsequently, as illustrated in
FIG. 5B , the insulatingfilm 11 is formed on the entire surface of the structure illustrated inFIG. 5A . As the insulatingfilm 11, a silicon oxide film or a silicon nitride, with a thickness of approximately 10 nm, film is formed. - After this, as illustrated in
FIG. 5B andFIG. 6B , a resist M2 is formed on the insulatingfilm 11 in a part, including the boundary between theTG 6 and thecharge storage area 8 in the top view and covering both of a part of theTG 6 on the side of thecharge storage area 8 and the upper part of thecharge storage area 8 on the side of theTG 6. - Any unnecessary parts of the insulating
film 11 are removed through an etching process, using the resist M2 as a mask, thereby forming the structure illustrated inFIG. 5C andFIG. 6C . This results in forming the insulatingfilm 11 which has been patterned. In this patterning, one end of thefilm 11 extends at least from the circumference surface of the sidewall on the side of thecharge storage area 8 to a position partially covering the upper part of thecharge storage area 8, in the top view. - In this case, a distance “d”, from the circumference surface of the
sidewall 62 on the side of thecharge storage area 8 to a position partially covering the upper part of thecharge storage area 8, is approximately from 10 nm to 40 nm. Because the second P-type layer 72 (seeFIGS. 7A to 7C ) will be formed afterwards, the insulatingfilm 11 is formed to cover from the circumference surface of thesidewall 62 on the side of thecharge storage area 8 to the upper part of thecharge storage area 8, instead of covering the entire surface of thecharge storage area 8. - That is, the insulating
film 11 is not formed on the entire surface of thecharge storage area 8, to form the second P-type layer 72 afterwards. As a result, it is possible to attain the suppression characteristic of suppressing white defects and afterimages, by the second P-type layer 72 to be formed afterwards. - At this time, the insulating
film 11 is formed in a manner that the other end thereof extends from the circumference surface of thesidewall 62 on thecharge storage area 8 to at least a part of the upper surface of theTG 6, in the top view. - To suppress the white defects and afterimages, the insulating
film 11 ofFIG. 5C exists on the upper surface of the first P-type layer 71. The insulatingfilm 11 extends up to the upper surface of theTG 6 to have a large area of the insulatingfilm 11, thereby easily performing patterning of the insulatingfilm 11. - Subsequently, as illustrated in
FIG. 7A , the positivehole storage layer 7 is formed by forming the second P-type layer 72 and the third P-type layer 73. Specifically, a resist M3 is formed to cover a part excluding the upper part of thecharge storage area 8, on the upper surface of the structure illustrated inFIG. 5C . The P-type impurities are implanted from above, while using the resist M3 as a mask. After this, the annealing process is performed, thereby forming the positivehole storage layer 7 to form thePD 9. - In this case, the ion implantation is performed at a higher energy level than that for forming the first P-
type layer 71. This results in forming the third P-type layer 73 deeper than the first P-type layer 71 and with a higher concentration of the P-type impurities than that. The amount of implantation of P-type impurities and the energy level of the second P-type layer 72 can be limited by the insulatingfilm 11. As a result, the second P-type layer 72 is shallower than the third P-type layer 73 and deeper than the first P-type layer 71, has a lower concentration of the P-type impurities than that of the third P-type layer 73, and has a higher concentration of the P-type impurities than the first P-type layer 71. - The relative relationship of the depth or impurity concentration between the first P-
type layer 71 and the second P-type layer 72 can be adjusted in accordance with the energy level applied to the impurity ions to be implanted. The relative relationship of the depth or impurity concentration between the third P-type layer 73 and the second P-type layer 72 can be adjusted by changing the thickness of the insulatingfilm 11. - As described, the positive
hole storage layer 7 is formed to be shallower as nearer to theTG 6, and to have a lower concentration of the P-type impurities. Accordingly, in thepixel unit 2, the white defects and afterimages can be suppressed in the picked up image. - Subsequently, after separating the resist M3, as illustrated in
FIG. 7B , theantireflection film 12 is formed on the entire surface including the PD9, theTG 6 and theFD 10. In this case, as an antireflection film, a silicon nitride film with a thickness of approximately 10 nm is formed. - In this case, the
antireflection film 12 has been formed on the entire surface of the structure including the insulatingfilm 11. However, the insulatingfilm 11 may be removed before forming theantireflection film 12. If the insulatingfilm 11 is removed before forming theantireflection film 12, the flatness of the constituent elements (theinterlayer insulating film 13 formed in the upper layer) can be improved afterwards. - As illustrated in
FIG. 7C , theinterlayer insulating film 13, thecontact plug 15, and the multilayer wiring 14 (seeFIG. 2 ) are formed on theantireflection film 12, using a known damascene technique or a dual damascene technique. After this, as illustrated inFIG. 2 , thecolor filter 16 and themicro lens 17 are sequentially laminated to form thepixel unit 2 in a position overlapping with thetop view PD 9 on the upper surface of theinterlayer insulating film 13, to manufacture the CMOS sensor 1. - As described above, in the manufacturing method of the solid-state image pickup device according to the embodiment, the transfer gate electrode is formed in a predetermined position on the upper surface of the first conductive semiconductor area through the gate insulating film. The transfer gate electrode transfers the charges which have been photoelectrically converted by the photoelectric conversion device to the floating diffusion area.
- A second conductive charge storage area is formed in an area adjacent to the top view transfer gate electrode in the first conductive semiconductor area, to form sidewalls on the side surfaces of the transfer gate electrode. Note that the second conductive charge storage area is formed to store those charges which have been photoelectrically converted by the photoelectric conversion device.
- Further, an insulating film is formed to extend from the circumference surface of the sidewall on the side of the top view charge storage area up to a position partially covering the upper part of the charge storage area. In addition, the first conductive impurities are implanted from above into the charge storage area whose upper part is partially covered with the insulating film, to form the first conductive charge storage layer on the upper surface of the charge storage area.
- According to the manufacturing method of the solid-state image pickup device according to the embodiment, it is possible to manufacture a solid-state image pickup device in which the white defects and afterimages can be suppressed in the picked up image.
- The form of the insulating
film 11 illustrated inFIG. 6C is made only by way of example, and various changes may be made thereto.FIGS. 8A to 8C are explanatory diagrams showing a modification of the form of the insulating film in the top view. InFIGS. 8A to 8C , the same constituent elements as those of theFIGS. 6A to 6C are identified by the same reference symbols as those ofFIGS. 6A to 6C . - For example, as illustrated in
FIG. 8A , an insulatingfilm 11 a may be formed in place of the insulatingfilm 11, includes at least the boundary between thesidewall 62 and the first P-type layer 71 in the top view, and surrounds the upper surface of theTG 6 in a C-shape in the top view. - As illustrated in
FIG. 8B , an insulatingfilm 11 b may be formed in place of the insulatingfilm 11, includes at least the boundary between thesidewall 62 and the first P-type layer 71 in the top view, and covers half of the first P-type layer 71 on the upper surface of thesidewall 62 and theTG 6. - As illustrated in
FIG. 8C , an insulatingfilm 11 c may be formed in place of the insulatingfilm 11, includes at least the boundary between thesidewall 62 and the first P-type layer 71 in the top view, and covers the entire surface of thesidewall 62, theTG 6, and theFD 10. - When the insulating
films FIGS. 8A to 8C are formed, the second P-type layer 72 may be formed right below an area surrounded by the frame with dashed-dotted line inFIGS. 8A to 8C . The third P-type layer 73 may be formed right below the first P-type layer 71 which is not covered with the insulatingfilms - When the insulating
films FIGS. 8A to 8C are formed, it is possible to manufacture a solid-state image pickup device, in which white defects and afterimages can be suppressed in the picked up image. - In the above-described embodiment, after the
sidewall 62 is formed, the insulatingfilm 11 is formed. However, the film may be formed before forming thesidewall 62.FIG. 9 is an explanatory diagram showing a part of the solid-state image pickup device which is manufactured using a manufacturing method according to a modification of the embodiment. - The part of the solid-state image pickup device illustrated in
FIG. 9 corresponds to the part illustrated inFIG. 3 . Thus, inFIG. 9 , the constituent elements having the same functions as those of the constituent elements ofFIG. 3 are identified by the same reference symbols illustrated inFIG. 3 . - In the manufactured solid-state image pickup device illustrated in
FIG. 9 , the insulatingfilm 11 d is formed before forming thesidewall 62. For example, after forming the structure illustrated inFIG. 4A , thecharge storage area 8, the first P-type layer 71, theFD 10, and the insulatingfilm 11 d are sequentially formed. After thesidewall 62 is formed, the second P-type layer 72 and the third P-type layer 73 are sequentially formed. Then, the device is manufactured in accordance with the same manufacturing steps illustrated in and afterFIG. 7B . - When the solid-state image pickup device is manufactured in accordance with the manufacturing method, as illustrated in
FIG. 9 , the positivehole storage layer 7 may be formed on the upper surface part of thecharge storage area 8. This positivehole storage layer 7 is shallower, and has a lower concentration of the P-type impurities, as nearer to theTG 6. - In the solid-state image pickup device manufactured without forming the insulating
film 11 d illustrated inFIG. 9 , the second P-type layer 72 is formed deep as illustrated with the dashed-dotted line inFIG. 9 . Thus, those electrons stored in thecharge storage area 8 are transferred from thecharge storage area 8 to theFD 10 through the lower layer part of thecharge storage area 8 whose potential barrier is relatively high, as illustrated with a dotted arrow. - In contrast, in the solid-state image pickup device illustrated in
FIG. 9 , the charges can be transferred from thecharge storage area 8 to theFD 10 through the upper layer part of thecharge storage area 8 whose potential barrier is relatively low, as illustrated with a solid arrow. Therefore, according to the solid-state image pickup device illustrated inFIG. 9 , it is possible to avoid the occurrence of afterimages due to the electrons remaining in thecharge storage area 8 without being transferred to theFD 10. - In the above-described embodiment, the descriptions have been made to the surface irradiation CMOS as an example of the solid-state image pickup device. However, the manufacturing method of the solid-state image pickup device according to this embodiment is applicable to a back-surface irradiation CMOS image sensor.
- While a certain embodiment has been described, the embodiment has been presented by way of example only, and not intended to limit the scope of the inventions. Indeed, the novel embodiment described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiment described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Claims (15)
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US20200105821A1 (en) * | 2015-03-31 | 2020-04-02 | Trustees Of Dartmouth College | Image Sensor and Image Sensor Pixel Having JFET Source Follower |
CN111448664A (en) * | 2017-12-09 | 2020-07-24 | 国立大学法人静冈大学 | Charge modulation element and solid-state image pickup device |
US11069739B2 (en) * | 2017-02-21 | 2021-07-20 | Sony Semiconductor Solutions Corporation | Imaging device and electronic apparatus |
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CN104517976B (en) * | 2013-09-30 | 2018-03-30 | 中芯国际集成电路制造(北京)有限公司 | Dot structure of cmos image sensor and forming method thereof |
WO2018110258A1 (en) * | 2016-12-15 | 2018-06-21 | パナソニック・タワージャズセミコンダクター株式会社 | Solid-state image pickup element |
JP2019057649A (en) * | 2017-09-21 | 2019-04-11 | 株式会社リコー | Imaging element, imaging apparatus, and image input device |
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JPH11126893A (en) * | 1997-10-23 | 1999-05-11 | Nikon Corp | Solid-state image-pickup element and manufacture thereof |
JPH11274454A (en) * | 1998-03-19 | 1999-10-08 | Canon Inc | Solid image pick-up device and its forming method |
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- 2013-02-04 JP JP2013019632A patent/JP2014150230A/en not_active Abandoned
- 2013-05-17 US US13/896,568 patent/US8803204B1/en active Active
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Cited By (4)
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US20200105821A1 (en) * | 2015-03-31 | 2020-04-02 | Trustees Of Dartmouth College | Image Sensor and Image Sensor Pixel Having JFET Source Follower |
US11764249B2 (en) * | 2015-03-31 | 2023-09-19 | Trustees Of Dartmouth College | Image sensor and image sensor pixel having JFET source follower |
US11069739B2 (en) * | 2017-02-21 | 2021-07-20 | Sony Semiconductor Solutions Corporation | Imaging device and electronic apparatus |
CN111448664A (en) * | 2017-12-09 | 2020-07-24 | 国立大学法人静冈大学 | Charge modulation element and solid-state image pickup device |
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CN103972251A (en) | 2014-08-06 |
KR101476035B1 (en) | 2014-12-23 |
US20140333807A1 (en) | 2014-11-13 |
US8803204B1 (en) | 2014-08-12 |
KR20140099809A (en) | 2014-08-13 |
JP2014150230A (en) | 2014-08-21 |
US9237283B2 (en) | 2016-01-12 |
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