US20140151848A1 - Mimcap structure in a semiconductor device package - Google Patents

Mimcap structure in a semiconductor device package Download PDF

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US20140151848A1
US20140151848A1 US14/092,762 US201314092762A US2014151848A1 US 20140151848 A1 US20140151848 A1 US 20140151848A1 US 201314092762 A US201314092762 A US 201314092762A US 2014151848 A1 US2014151848 A1 US 2014151848A1
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layer
conductive layer
metallization
stack
layers
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US14/092,762
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Mikael Detalle
Eric Beyne
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Interuniversitair Microelektronica Centrum vzw IMEC
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Interuniversitair Microelektronica Centrum vzw IMEC
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Publication of US20140151848A1 publication Critical patent/US20140151848A1/en
Priority to US15/014,343 priority Critical patent/US20160155699A1/en
Priority to US15/411,891 priority patent/US10256183B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016—Thin-film circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Definitions

  • the disclosed technology relates generally to semiconductor processing, and more particularly to integration of a metal-insulator-metal capacitor in the back-end-of-line (BEOL) processing of a semiconductor package.
  • BEOL back-end-of-line
  • CMOS technology Device downscaling in present day CMOS technology is leading to faster switching speeds of the transistors integrated with a higher density on the semiconductor wafer.
  • large current spikes may occur due to a large number of ‘simultaneous’ switching events in the circuit within a short period of time, which can cause considerable current-resistance drop and noise over the power supply network. Voltage fluctuation and power supply noise may impact signal integrity, speed and reliability of the devices.
  • MIMCAP Metal-Insulator-Metal capacitor
  • the MIMCAP can compensate voltage fluctuations by delivering charges to the power-supply network. However, its capacitance needs to be large enough to be actually efficient.
  • a MIMCAP is formed between first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers, formed by damascene processes.
  • the stack can support one or more semiconductor devices, which are connected through the metallization layers to an external power source.
  • the MIMCAP comprises a bottom plate in the first metallization layer, a first conductive layer on and in electrical contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, a second conductive layer on and in contact with the dielectric layer, and a top plate in the second metallization layer, on and in electrical contact with the second metal plate.
  • the contacting of the bottom and top plates of the MIMCAP from the first and second metallization layer is thereby established without vias between the plates and the metallization layers.
  • the first conductive layer of the MIMCAP may extend beyond the surface of the dielectric and the second layer for forming other structures.
  • a semiconductor device package comprises one or more semiconductor devices electrically coupled to a metallization stack comprising a plurality of interconnected metallization layers.
  • the semiconductor device package additionally includes a metal-insulator-metal capacitor formed between a lower layer (M 1 ) of the metallization layers and an upper layer (M 2 ) of the metallization layers, where the lower and upper layers are adjacent metallization layers within the stack.
  • the capacitor includes at least a portion of a bottom plate which forms a part of the lower metallization layer (M 1 ).
  • the capacitor additionally includes at least a portion of a first conductive layer on and in contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, and a second conductive layer on and in contact with the dielectric layer.
  • the capacitor further includes a top plate which forms a part of the upper metallization layer, the top plate being on and in contact with the second conductive layer.
  • the first and second conductive layer and the dielectric layer in between the layers have the same size in the plane of the layers.
  • the first conductive layer extends beyond the surface of the dielectric layer and the second dielectric layer.
  • the first conductive layer may be patterned in the area outside the area covered by the MIMCAP.
  • the first conductive layer may be patterned to form one or more patterned portions, which serve as contact portions for electrical circuit elements in the lower or upper metallization layer and/or which serve themselves as the electrical circuit elements.
  • a patterned portion of the first conductive layer forms a resistor in the upper metallization layer, and wherein a stack of a dielectric layer portion and a top conductive layer portion is present on top of the resistor, the dielectric layer and top conductive layer portion being of the same material and thickness of the dielectric layer and second conductive layer of the capacitor.
  • the second conductive layer is surrounded in the plane of the layer by a ring structure of the same material and thickness of the second conductive layer.
  • the first and second metallization layer may be the power supply layer and the ground layer respectively of an interposer substrate carrying one or more integrated circuit devices.
  • the bottom and/or top plate may be provided with perforations through the complete thickness of the plates, the perforations being filled with a dielectric material.
  • the invention is equally related to a method for producing a semiconductor package according to the invention, comprising the processes of:
  • the patterning step may be performed to the effect of forming a stack of the first conductive layer, the dielectric layer and the second conductive layer, the layers being of the same size in the plane of the layers.
  • the patterning step is performed to the effect of forming a stack of the dielectric layer and the second conductive layer on top of the first conductive layer, the first conductive layer remaining intact after the patterning step.
  • the first conductive layer is further patterned in a second patterning step.
  • the first conductive layer and the second conductive layer portion of the stack may be patterned simultaneously.
  • the second conductive layer portion of the stack may be patterned to form a ring structure around a central portion of the second conductive layer.
  • FIGS. 1 a to 1 g illustrate a method of fabricating a MIMCAP structure according to one embodiment.
  • FIGS. 2 a to 2 e illustrate a method of fabricating a MIMCAP structure according to another embodiment.
  • FIGS. 3 a to 3 c illustrate a method of fabricating a MIMCAP according to another embodiment.
  • FIGS. 4 a and 4 b illustrate a device structure according to one embodiment.
  • FIGS. 5 a and 5 b illustrate a resistor device that can be fabricated together with a MIMCAP according to one embodiment.
  • a metallization layer refers to a layer or a stack of layers including a dielectric material and a pattern of electrically conductive material embedded in the layer or the stack of layers including the dielectric material. Subsequent metallization layers in the stack are isolated from each other except through vertical connections between the electrically conductive material.
  • a patterning process refers to a fabrication process in which portions of a layer are removed by etching away the portions while the remainder of the layer is protected by an etch mask, leaving a pattern formed by the remaining parts of the layer.
  • the patterning may take place by known photolithography techniques involving a resist layer, or by hard mask techniques, equally known in the art.
  • FIGS. 1 a - 1 g illustrate a method of fabricating a MIMCAP according to one embodiment.
  • the MIMCAP is formed between two copper metallization layers produced on a substrate.
  • the substrate may for example be an active or passive interposer substrate onto which various integrated circuit chips are to be assembled.
  • FIG. 1 a shows a base substrate 1 , provided with an isolation layer 2 over the substrate.
  • the base substrate 1 comprises silicon and the isolation layer 2 comprises a layer formed of, for example, silicon oxide, silicon nitride, silicon carbide or a combination (e.g. a stack) of two or three of these materials.
  • the substrate may comprise a glass substrate (i.e. instead of the combined Si+isolation layer).
  • a first metallization layer M 1 is provided, which can be formed, for example, by a damascene process as known in the art.
  • a first layer 3 of inter-metal dielectric (IMD) is deposited, and patterned by a patterning step as defined above, to form openings and/or trenches, which can then be lined with a barrier layer for preventing Cu-diffusion into the IMD combined with a copper seed deposited by a suitable deposition technique (such as physical or chemical vapour deposition—PVD or CVD), as known in the art.
  • a suitable deposition technique such as physical or chemical vapour deposition—PVD or CVD
  • the first metallization layer M 1 thus obtained comprises at least one plate 4 which is to form the bottom plate of the MIMCAP. This may be a rectangular plate for example.
  • the bottom plate 4 is preferably provided with perforations (not shown) filled with dielectric, which serve to maintain flatness of the bottom plate during CMP.
  • the perforations are obtained as non-etched IMD portions during the IMD patterning step, onto which the copper is deposited, the copper filling the spaces between the IMD portions.
  • three additional copper structures 5 are shown, which can include, for example, conductors running along a pre-defined pattern in the first metallization layer M 1 . Then a stack of three layers ( 6 , 7 , 8 ) is deposited on the planarized surface ( FIG. 1 c ), for example by PVD deposition processes, including a first electrically conductive layer 6 , a dielectric layer 7 and a second electrically conductive layer 8 . In the rest of this description and in the claims, these electrically conductive layers 6 and 8 will be referred to as ‘conductive layers’ for reasons of conciseness.
  • the conductive layers may be formed of metal layers or layers of conductive materials, e.g, TiN or TaN.
  • the stack of layers 6 / 7 / 8 is then patterned, to form a MIM-stack 9 ( FIG. 1 d ), which covers at least a portion of the bottom plate 4 .
  • a MIM-stack 9 FIG. 1 d
  • a further IMD layer 10 FIG. 1 e
  • FIG. 1 f is patterned to form at least one opening 11 on top of the MIM-stack, as well as vias 12 towards some of the structures 5 ( FIG. 1 f ).
  • the openings are filled with copper and planarized, resulting in the second metallization layer M 2 , comprising the top plate 13 (which can be perforated as described above for the first metallization layer M 1 , for maintaining flatness), in contact with the second conductive layer 8 of the MIM-stack ( FIG. 1 g ), as well as via connections 14 for connecting the structures 5 with a further metallization layer.
  • the final MIMCAP-structure 50 comprises a portion of the bottom plate 4 , the first conductive layer 6 , the dielectric layer 7 , the second conductive layer 8 and the top plate 13 .
  • the MIMCAP includes the bottom plate 4 , the first conductive layer 6 in contact with the bottom plate 4 , the dielectric layer 7 in contact with the first conductive layer 6 , the second conductive layer 8 in contact with the dielectric layer 7 , and the top plate 13 in contact with the second conductive layer, wherein the bottom plate is part of a first metallization layer and the top plate is part of a second metallization layer in a metallization stack coupled between one or more semiconductor devices and an external power source.
  • the formation of the MIM-stack 9 takes place by multiple patterning processes, wherein in the first patterning step, the first conductive layer 6 remains intact on the surface of the planarized first metallization layer M 1 , while the dielectric 7 and the second conductive layer 8 are patterned to form a stack of these two layers covering at least a portion of the bottom plate 4 .
  • a second patterning step is performed to pattern the first conductive layer 6 and possibly the second conductive layer 8 simultaneously. In this way, the first conductive layer can be used to form additional structures within the first metallization layer M 1 .
  • FIGS. 2 a - 2 e This embodiment is illustrated in FIGS. 2 a - 2 e.
  • FIG. 2 a shows the stage where the stack of layers 6 / 7 / 8 described in relation to FIG. 1 , has been deposited on the planarized first metallization layer M 1 .
  • the structures 15 comprise a part of an inductor pattern in the first metallization layer M 1 , while the MIM-stack also extends over a portion 3 ′ of the IMD 3 of M 1 , with no metal present in the portion.
  • FIG. 2 b shows the result of a first patterning step wherein only the dielectric layer 7 and the second conductive layer 8 are patterned to form a MIM-stack 9 which covers at least a portion of the bottom plate 4 .
  • the MIM-stack 9 comprises the remainder of the dielectric layer 7 , the second conductive layer 8 and a portion of the first conductive layer 6 , where the first conductive layer 6 remains intact on the surface of the first metallization layer M 1 . That is, etching of layers 7 and 8 stops on the first conductive layer 6 , for example, by choosing an etchant having a suitable selectivity between etch rates of the first conductive layer 6 and the dielectric layer 7 .
  • the first conductive layer 6 is patterned, as shown in FIG. 2 c .
  • Portions 20 and 21 of the layer 6 to the left and right of the MIM stack remain.
  • a portion 22 above the inductor structure 15 and covering the entire inductor structure remains as well.
  • a rectangular portion 23 remains on the portion 10 ′ of the IMD.
  • These portions 20 to 23 of the first conductive layer 6 can now serve as additional structural elements in the metallization layout.
  • Deposition and patterning of the second metallization layer M 2 results in the view of FIG. 2 d , once again with the top copper plate 24 on and in contact with the second conductive layer 8 of the MIM-stack.
  • a via 25 is produced for contacting the first conductive layer 6 and thus the bottom plate 4 from the second metallization layer M 2 .
  • Vias 26 are provided for contacting the inductor 15
  • rectangular vias 27 are produced for connecting the rectangular portion 23 of the first conductive layer to the second metallization layer M 2 .
  • the rectangular portion 23 may be integrated as a resistor in the circuit defined within the second metallization layer M 2 .
  • the function of the inductor shaped portion 22 of layer 6 and of the portion 21 to the right of the MIMCAP (contacted by via 25 ) is to provide a possible advantage in the processing of the M 1 and M 2 layers.
  • the etching stops on the first conductive layer 6 (e.g. a TaN layer), and not on the Cu. Stopping on a Cu layer can lead to contamination of the etching chamber, which complicates the process.
  • the presence of the first conductive layer 6 makes it possible to avoid those complications (by patterning the portion 22 ) at least during processing of the M 1 and M 2 layers, which is particularly advantageous given the high copper density of the layers M 1 and M 2 . So even though the invention is not limited (as seen in FIG. 1 for example) to the embodiment wherein portions of the first conductive layer 6 remain on inductors and/or other structures in the M 1 layer, the invention does represent a considerable advantage in providing this possibility.
  • the patterned portion 22 of layer 6 can also serve as at least a part of an inductor (i.e. without the inductor pattern 15 in the M 1 layer). In some embodiments, the patterned layer 22 can serve as a stand-alone inductor without the inductor pattern 14 , in circumstances where the thickness of the inductor pattern 22 is sufficient for serving as a workable inductor.
  • the patterned portions of the first conductive layer 6 may serve as contact portions for structures (such as inductor 15 ) in one of the metallization layers M 1 /M 2 or the portions may themselves play the part of circuit elements in the metallization layers (such as the resistor 23 , or theoretically, the inductor pattern 22 ).
  • the patterning process for patterning the first conductive layer 6 serves also to pattern portions of the second conductive layer 8 that forms the top layer of the MIM stack 9 .
  • this patterning is to the effect that a ring structure 30 (not necessarily circular-shaped) is formed surrounding a central portion 31 of the top conductive layer 8 , in the plane of the MIMCAP.
  • the top copper plate 24 then only contacts the central portion 31 .
  • the ring portion 30 serves to prevent possible shorting between the top and bottom electrodes at the edge of the capacitor.
  • the structure of the MIMCAP of the invention, and its fabrication method allows formation of such a protective ring 30 simultaneously with the patterning of the first conductive layer 6 , and thus provides an economic way of producing complex structures.
  • the first conductive layer 6 remains intact after a first patterning process, as in the embodiments of FIGS. 2 and 3 , however, unlike in the embodiments of FIGS. 2 and 3 , but in the second patterning process, it is only the second conductive layer 8 which is further patterned, for example to form a ring structure 30 , while the first conductive layer 6 still remains intact.
  • Example structures fabricated by this embodiment is illustrated in FIGS. 4 a and 4 b . In these embodiments, there is no separate process of processing a separate bottom plate having dimensions that are in the same order of magnitude as the top plate 13 or 24 .
  • the bottom plate of the MIMCAP is a portion of a larger metal layer in the M 1 -layer.
  • the process of patterning the dielectric layer 7 and the second conductive layer 8 of the MIM-stack, with the first conductive layer 6 remaining intact does not only take place at the location of the eventual MIMCAP above the bottom plate 4 , but similar stacks of portions 7 ′ and 8 ′ formed by patterning the layers 7 and 8 may also remain on other locations.
  • additional stacks 40 including the portions 7 ′ and 8 ′ are produced on the resistor portion 23 .
  • the stacks 40 protect a large portion of the resistor metal during the etching of the dielectric 7 in other areas. This therefore allows a better control of the resistance value of the resistor.
  • the stack 40 may be further provided with a connection 28 to the next metallization layer ( FIG. 5 b ).
  • the IMD material may be formed of silicon oxide (SiO 2 ), a combination of SiO 2 with silicon nitride (Si 3 N 4 ) or a combination of SiO 2 and silicon carbide (SiC).
  • the IMD may be formed of a low-k material.
  • the metal material of the metallization comprises copper.
  • the M 1 and M 2 layers may have thicknesses according to known practice in the domain of damascene processing, e.g. around 1 micron. In some embodiments, the thickness of the M 2 layer may be chosen higher than M 1 given that the CMP process will generally take longer as the topography caused by the MIM-stack patterning needs to be removed.
  • the first and second conductive layer 6 / 8 of the MIM-stack may be formed of, for example, Ta, TaN, Ti, TiN, or other suitable conductive materials.
  • the layers 6 , 7 and 8 preferably have the same thickness, e.g. between about 50 nm and about 100 nm. At least the thickness of the first and second conductive layer 6 and 8 is preferably the same, especially in the embodiment of FIG. 2 , where both layers are etched in the same etching process.
  • the dielectric layer 7 of the MIM-stack may be formed of, for example, silicon oxide (e.g., SiO 2 ), silicon nitride (e.g., Si 3 N 4 ), silicon carbide (e.g., SiC), tantalum oxide (e.g., Ta 2 O 5 ), hafnium oxide (e.g., HfO 2 ), titanium oxide (e.g., TiO 2 ), an ONO-stack (Oxide-nitride-oxide), or any other suitable dielectric material.
  • silicon oxide e.g., SiO 2
  • silicon nitride e.g., Si 3 N 4
  • silicon carbide e.g., SiC
  • tantalum oxide e.g., Ta 2 O 5
  • hafnium oxide e.g., HfO 2
  • titanium oxide e.g., TiO 2
  • ONO-stack Oxide-nitride-oxide
  • an annealing process can be performed prior to performing a CMP process on the first metallization layer M 1 .
  • the annealing temperature is between about 350° C. and about 450° C. The annealing is done to decrease hillocks formation due to stress induced by the subsequent processes (MIM-stack deposition).
  • inventions disclosed herein can be integrated with existing BEOL process schemes.
  • various embodiments of the MIMCAP structures described above can be integrated with an interposer substrate, in particular between the power supply layer the ground layer of such an interposer. This is particularly advantageous due to the large surface that is available for the MIMCAP.
  • a layer being formed, deposited or produced ‘on’ another layer or substrate includes:

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Abstract

The disclosed technology relates generally to a semiconductor device package comprising a metal-insulator-metal capacitor (MIMCAP). In one aspect, the MIMCAP is formed between a first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers formed by single damascene processes. The MIMCAP comprises a bottom plate formed in the first metallization layer, a first conductive layer on and in electrical contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, a second conductive layer on and in contact with the dielectric layer, and a top plate formed in the second metallization layer, on and in electrical contact with the second metal plate. The electrical contacts to the bottom and top plates of the MIMCAP formed in the first and second metallization layer are thereby established without forming separate vias between the plates and the metallization layers. In addition, the first conductive layer of the MIMCAP may extend beyond the surface of the dielectric and the second layer for forming other structures.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims foreign priority to European patent application EP 12194922.6 filed on Nov. 29, 2012, the content of which is incorporated by reference herein in its entirety.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The disclosed technology relates generally to semiconductor processing, and more particularly to integration of a metal-insulator-metal capacitor in the back-end-of-line (BEOL) processing of a semiconductor package.
  • 2. Description of the Related Technology
  • Device downscaling in present day CMOS technology is leading to faster switching speeds of the transistors integrated with a higher density on the semiconductor wafer. However, in the final device, large current spikes may occur due to a large number of ‘simultaneous’ switching events in the circuit within a short period of time, which can cause considerable current-resistance drop and noise over the power supply network. Voltage fluctuation and power supply noise may impact signal integrity, speed and reliability of the devices. It has been shown that the addition of an on-chip decoupling MIMCAP (Metal-Insulator-Metal capacitor) can reduce this problem and enhance circuit performance. The MIMCAP can compensate voltage fluctuations by delivering charges to the power-supply network. However, its capacitance needs to be large enough to be actually efficient. In addition, low resistance and low inductance is needed to enable the efficient application of MIMCAPs at high frequencies. In present day MIMCAP designs, resistance especially is too high for this purpose because of the connections from at least one of the metallization layers to the top and/or the bottom plate of the MIMCAP. Such connections are established by via etching and filling techniques, typically increasing the resistance of the path from the metallization layer(s) to the MIMCAP.
    • SUMMARY OF CERTAIN INVENTIVE ASPECTS
  • The disclosed technology is related to a MIMCAP design that does not suffer from the above-described problem. The technology is particularly related to a MIMCAP structure as disclosed in the appended claims and to a method for producing such a structure. A MIMCAP according to an embodiment is formed between first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers, formed by damascene processes. The stack can support one or more semiconductor devices, which are connected through the metallization layers to an external power source. The MIMCAP comprises a bottom plate in the first metallization layer, a first conductive layer on and in electrical contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, a second conductive layer on and in contact with the dielectric layer, and a top plate in the second metallization layer, on and in electrical contact with the second metal plate. The contacting of the bottom and top plates of the MIMCAP from the first and second metallization layer is thereby established without vias between the plates and the metallization layers. In addition, the first conductive layer of the MIMCAP may extend beyond the surface of the dielectric and the second layer for forming other structures.
  • In one aspect, a semiconductor device package comprises one or more semiconductor devices electrically coupled to a metallization stack comprising a plurality of interconnected metallization layers. The semiconductor device package additionally includes a metal-insulator-metal capacitor formed between a lower layer (M1) of the metallization layers and an upper layer (M2) of the metallization layers, where the lower and upper layers are adjacent metallization layers within the stack. The capacitor includes at least a portion of a bottom plate which forms a part of the lower metallization layer (M1). The capacitor additionally includes at least a portion of a first conductive layer on and in contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, and a second conductive layer on and in contact with the dielectric layer. The capacitor further includes a top plate which forms a part of the upper metallization layer, the top plate being on and in contact with the second conductive layer.
  • According to an embodiment, the first and second conductive layer and the dielectric layer in between the layers have the same size in the plane of the layers.
  • According to another embodiment, the first conductive layer extends beyond the surface of the dielectric layer and the second dielectric layer.
  • In the latter case, the first conductive layer may be patterned in the area outside the area covered by the MIMCAP. The first conductive layer may be patterned to form one or more patterned portions, which serve as contact portions for electrical circuit elements in the lower or upper metallization layer and/or which serve themselves as the electrical circuit elements.
  • According to an embodiment, a patterned portion of the first conductive layer forms a resistor in the upper metallization layer, and wherein a stack of a dielectric layer portion and a top conductive layer portion is present on top of the resistor, the dielectric layer and top conductive layer portion being of the same material and thickness of the dielectric layer and second conductive layer of the capacitor.
  • According to an embodiment, the second conductive layer is surrounded in the plane of the layer by a ring structure of the same material and thickness of the second conductive layer.
  • The first and second metallization layer may be the power supply layer and the ground layer respectively of an interposer substrate carrying one or more integrated circuit devices.
  • The bottom and/or top plate may be provided with perforations through the complete thickness of the plates, the perforations being filled with a dielectric material.
  • The invention is equally related to a method for producing a semiconductor package according to the invention, comprising the processes of:
      • Producing a first metallization layer by a damascene process, the first metallization layer comprising a bottom plate,
      • Depositing a stack of a first conductive layer, a dielectric layer and a second conductive layer on and in contact with the first metallization layer,
      • Patterning at least the second layer and the dielectric layer to form a stack of the first conductive layer or a portion thereof, the dielectric layer and the second conductive layer, which covers at least partially the bottom plate,
      • Producing a second metallization layer by a damascene process, the second metallization layer comprising a top plate which is on and in contact with the second conductive layer of the stack.
  • In the method of the invention, the patterning step may be performed to the effect of forming a stack of the first conductive layer, the dielectric layer and the second conductive layer, the layers being of the same size in the plane of the layers.
  • According to another embodiment, the patterning step is performed to the effect of forming a stack of the dielectric layer and the second conductive layer on top of the first conductive layer, the first conductive layer remaining intact after the patterning step.
  • According to an embodiment, the first conductive layer is further patterned in a second patterning step. During the second patterning step, the first conductive layer and the second conductive layer portion of the stack may be patterned simultaneously.
  • During the second patterning step, the second conductive layer portion of the stack may be patterned to form a ring structure around a central portion of the second conductive layer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1 a to 1 g illustrate a method of fabricating a MIMCAP structure according to one embodiment.
  • FIGS. 2 a to 2 e illustrate a method of fabricating a MIMCAP structure according to another embodiment.
  • FIGS. 3 a to 3 c illustrate a method of fabricating a MIMCAP according to another embodiment.
  • FIGS. 4 a and 4 b illustrate a device structure according to one embodiment.
  • FIGS. 5 a and 5 b illustrate a resistor device that can be fabricated together with a MIMCAP according to one embodiment.
    •  DETAILED DESCRIPTION OF CERTAIN ILLUSTRATIVE EMBODIMENTS
  • As used herein, a metallization layer refers to a layer or a stack of layers including a dielectric material and a pattern of electrically conductive material embedded in the layer or the stack of layers including the dielectric material. Subsequent metallization layers in the stack are isolated from each other except through vertical connections between the electrically conductive material.
  • As used herein, a patterning process refers to a fabrication process in which portions of a layer are removed by etching away the portions while the remainder of the layer is protected by an etch mask, leaving a pattern formed by the remaining parts of the layer. The patterning may take place by known photolithography techniques involving a resist layer, or by hard mask techniques, equally known in the art.
  • FIGS. 1 a-1 g illustrate a method of fabricating a MIMCAP according to one embodiment. In the illustrated embodiment, the MIMCAP is formed between two copper metallization layers produced on a substrate. The substrate may for example be an active or passive interposer substrate onto which various integrated circuit chips are to be assembled. FIG. 1 a shows a base substrate 1, provided with an isolation layer 2 over the substrate. In some embodiments, the base substrate 1 comprises silicon and the isolation layer 2 comprises a layer formed of, for example, silicon oxide, silicon nitride, silicon carbide or a combination (e.g. a stack) of two or three of these materials. Alternatively, in other embodiments, the substrate may comprise a glass substrate (i.e. instead of the combined Si+isolation layer).
  • On the substrate 1, a first metallization layer M1 is provided, which can be formed, for example, by a damascene process as known in the art. A first layer 3 of inter-metal dielectric (IMD) is deposited, and patterned by a patterning step as defined above, to form openings and/or trenches, which can then be lined with a barrier layer for preventing Cu-diffusion into the IMD combined with a copper seed deposited by a suitable deposition technique (such as physical or chemical vapour deposition—PVD or CVD), as known in the art. After that, copper is plated (using electrochemical deposition ECD) to fill openings and/or trenches. The copper which has been plated not only in the openings and trenches but also on top of the IMD, is planarized by a CMP (Chemical Mechanical Polishing) process, which leads to the result shown in FIG. 1 b. The barrier layer is not shown in this drawing for clarity. In the disclosed method, the first metallization layer M1 thus obtained comprises at least one plate 4 which is to form the bottom plate of the MIMCAP. This may be a rectangular plate for example. The bottom plate 4 is preferably provided with perforations (not shown) filled with dielectric, which serve to maintain flatness of the bottom plate during CMP. The perforations are obtained as non-etched IMD portions during the IMD patterning step, onto which the copper is deposited, the copper filling the spaces between the IMD portions.
  • By way of an example, three additional copper structures 5 are shown, which can include, for example, conductors running along a pre-defined pattern in the first metallization layer M1. Then a stack of three layers (6, 7, 8) is deposited on the planarized surface (FIG. 1 c), for example by PVD deposition processes, including a first electrically conductive layer 6, a dielectric layer 7 and a second electrically conductive layer 8. In the rest of this description and in the claims, these electrically conductive layers 6 and 8 will be referred to as ‘conductive layers’ for reasons of conciseness. The conductive layers may be formed of metal layers or layers of conductive materials, e.g, TiN or TaN. The stack of layers 6/7/8 is then patterned, to form a MIM-stack 9 (FIG. 1 d), which covers at least a portion of the bottom plate 4. This is followed by the deposition of a further IMD layer 10 (FIG. 1 e), which is patterned to form at least one opening 11 on top of the MIM-stack, as well as vias 12 towards some of the structures 5 (FIG. 1 f). By another damascene process, the openings are filled with copper and planarized, resulting in the second metallization layer M2, comprising the top plate 13 (which can be perforated as described above for the first metallization layer M1, for maintaining flatness), in contact with the second conductive layer 8 of the MIM-stack (FIG. 1 g), as well as via connections 14 for connecting the structures 5 with a further metallization layer. The final MIMCAP-structure 50 comprises a portion of the bottom plate 4, the first conductive layer 6, the dielectric layer 7, the second conductive layer 8 and the top plate 13.
  • In embodiments of the method described herein, no via connections are formed towards the top or bottom plate of the MIMCAP. According to embodiments, the MIMCAP includes the bottom plate 4, the first conductive layer 6 in contact with the bottom plate 4, the dielectric layer 7 in contact with the first conductive layer 6, the second conductive layer 8 in contact with the dielectric layer 7, and the top plate 13 in contact with the second conductive layer, wherein the bottom plate is part of a first metallization layer and the top plate is part of a second metallization layer in a metallization stack coupled between one or more semiconductor devices and an external power source.
  • According one embodiment, the formation of the MIM-stack 9 takes place by multiple patterning processes, wherein in the first patterning step, the first conductive layer 6 remains intact on the surface of the planarized first metallization layer M1, while the dielectric 7 and the second conductive layer 8 are patterned to form a stack of these two layers covering at least a portion of the bottom plate 4. After that, a second patterning step is performed to pattern the first conductive layer 6 and possibly the second conductive layer 8 simultaneously. In this way, the first conductive layer can be used to form additional structures within the first metallization layer M1.
  • This embodiment is illustrated in FIGS. 2 a-2 e. FIG. 2 a shows the stage where the stack of layers 6/7/8 described in relation to FIG. 1, has been deposited on the planarized first metallization layer M1. The structures 15 comprise a part of an inductor pattern in the first metallization layer M1, while the MIM-stack also extends over a portion 3′ of the IMD 3 of M1, with no metal present in the portion. FIG. 2 b shows the result of a first patterning step wherein only the dielectric layer 7 and the second conductive layer 8 are patterned to form a MIM-stack 9 which covers at least a portion of the bottom plate 4. The MIM-stack 9 comprises the remainder of the dielectric layer 7, the second conductive layer 8 and a portion of the first conductive layer 6, where the first conductive layer 6 remains intact on the surface of the first metallization layer M1. That is, etching of layers 7 and 8 stops on the first conductive layer 6, for example, by choosing an etchant having a suitable selectivity between etch rates of the first conductive layer 6 and the dielectric layer 7.
  • In a second patterning step, the first conductive layer 6 is patterned, as shown in FIG. 2 c. Portions 20 and 21 of the layer 6 to the left and right of the MIM stack remain. Furthermore, a portion 22 above the inductor structure 15 and covering the entire inductor structure remains as well. Finally, a rectangular portion 23 remains on the portion 10′ of the IMD. These portions 20 to 23 of the first conductive layer 6 can now serve as additional structural elements in the metallization layout. Deposition and patterning of the second metallization layer M2 results in the view of FIG. 2 d, once again with the top copper plate 24 on and in contact with the second conductive layer 8 of the MIM-stack. A via 25 is produced for contacting the first conductive layer 6 and thus the bottom plate 4 from the second metallization layer M2. Vias 26 are provided for contacting the inductor 15, while rectangular vias 27, as seen in the top view of FIG. 2 e, are produced for connecting the rectangular portion 23 of the first conductive layer to the second metallization layer M2. In this way, the rectangular portion 23 may be integrated as a resistor in the circuit defined within the second metallization layer M2.
  • The function of the inductor shaped portion 22 of layer 6 and of the portion 21 to the right of the MIMCAP (contacted by via 25) is to provide a possible advantage in the processing of the M1 and M2 layers. When etching the vias 25 and 26 for example, the etching stops on the first conductive layer 6 (e.g. a TaN layer), and not on the Cu. Stopping on a Cu layer can lead to contamination of the etching chamber, which complicates the process. The presence of the first conductive layer 6 makes it possible to avoid those complications (by patterning the portion 22) at least during processing of the M1 and M2 layers, which is particularly advantageous given the high copper density of the layers M1 and M2. So even though the invention is not limited (as seen in FIG. 1 for example) to the embodiment wherein portions of the first conductive layer 6 remain on inductors and/or other structures in the M1 layer, the invention does represent a considerable advantage in providing this possibility.
  • In some embodiments, the patterned portion 22 of layer 6 can also serve as at least a part of an inductor (i.e. without the inductor pattern 15 in the M1 layer). In some embodiments, the patterned layer 22 can serve as a stand-alone inductor without the inductor pattern 14, in circumstances where the thickness of the inductor pattern 22 is sufficient for serving as a workable inductor. In general, the patterned portions of the first conductive layer 6 may serve as contact portions for structures (such as inductor 15) in one of the metallization layers M1/M2 or the portions may themselves play the part of circuit elements in the metallization layers (such as the resistor 23, or theoretically, the inductor pattern 22).
  • In a still further embodiment, the patterning process for patterning the first conductive layer 6 serves also to pattern portions of the second conductive layer 8 that forms the top layer of the MIM stack 9. According to an embodiment illustrated in FIGS. 3 a-3 c, this patterning is to the effect that a ring structure 30 (not necessarily circular-shaped) is formed surrounding a central portion 31 of the top conductive layer 8, in the plane of the MIMCAP. The top copper plate 24 then only contacts the central portion 31. The ring portion 30 serves to prevent possible shorting between the top and bottom electrodes at the edge of the capacitor. The structure of the MIMCAP of the invention, and its fabrication method allows formation of such a protective ring 30 simultaneously with the patterning of the first conductive layer 6, and thus provides an economic way of producing complex structures.
  • According to another embodiment, the first conductive layer 6 remains intact after a first patterning process, as in the embodiments of FIGS. 2 and 3, however, unlike in the embodiments of FIGS. 2 and 3, but in the second patterning process, it is only the second conductive layer 8 which is further patterned, for example to form a ring structure 30, while the first conductive layer 6 still remains intact. Example structures fabricated by this embodiment is illustrated in FIGS. 4 a and 4 b. In these embodiments, there is no separate process of processing a separate bottom plate having dimensions that are in the same order of magnitude as the top plate 13 or 24. The bottom plate of the MIMCAP is a portion of a larger metal layer in the M1-layer.
  • According to an embodiment, the process of patterning the dielectric layer 7 and the second conductive layer 8 of the MIM-stack, with the first conductive layer 6 remaining intact, does not only take place at the location of the eventual MIMCAP above the bottom plate 4, but similar stacks of portions 7′ and 8′ formed by patterning the layers 7 and 8 may also remain on other locations. In embodiments illustrated in FIGS. 5 a and 5 b, additional stacks 40 including the portions 7′ and 8′ are produced on the resistor portion 23. In some embodiments, the stacks 40 protect a large portion of the resistor metal during the etching of the dielectric 7 in other areas. This therefore allows a better control of the resistance value of the resistor. The stack 40 may be further provided with a connection 28 to the next metallization layer (FIG. 5 b).
  • In some embodiments, the IMD material may be formed of silicon oxide (SiO2), a combination of SiO2 with silicon nitride (Si3N4) or a combination of SiO2 and silicon carbide (SiC). In other embodiments, the IMD may be formed of a low-k material. In some embodiments, the metal material of the metallization comprises copper. In some embodiments, the M1 and M2 layers may have thicknesses according to known practice in the domain of damascene processing, e.g. around 1 micron. In some embodiments, the thickness of the M2 layer may be chosen higher than M1 given that the CMP process will generally take longer as the topography caused by the MIM-stack patterning needs to be removed.
  • In some embodiments, the first and second conductive layer 6/8 of the MIM-stack may be formed of, for example, Ta, TaN, Ti, TiN, or other suitable conductive materials. The layers 6, 7 and 8 preferably have the same thickness, e.g. between about 50 nm and about 100 nm. At least the thickness of the first and second conductive layer 6 and 8 is preferably the same, especially in the embodiment of FIG. 2, where both layers are etched in the same etching process.
  • In some embodiments, the dielectric layer 7 of the MIM-stack may be formed of, for example, silicon oxide (e.g., SiO2), silicon nitride (e.g., Si3N4), silicon carbide (e.g., SiC), tantalum oxide (e.g., Ta2O5), hafnium oxide (e.g., HfO2), titanium oxide (e.g., TiO2), an ONO-stack (Oxide-nitride-oxide), or any other suitable dielectric material.
  • According to an embodiment, an annealing process can be performed prior to performing a CMP process on the first metallization layer M1. In one embodiment, the annealing temperature is between about 350° C. and about 450° C. The annealing is done to decrease hillocks formation due to stress induced by the subsequent processes (MIM-stack deposition).
  • The embodiments disclosed herein can be integrated with existing BEOL process schemes. According to an embodiment, for example, various embodiments of the MIMCAP structures described above can be integrated with an interposer substrate, in particular between the power supply layer the ground layer of such an interposer. This is particularly advantageous due to the large surface that is available for the MIMCAP.
  • While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word “comprising” does not exclude other elements or processes, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.
  • The foregoing description details certain embodiments of the invention. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the invention may be practiced in many ways, and is therefore not limited to the embodiments disclosed. It should be noted that the use of particular terminology when describing certain features or aspects of the invention should not be taken to imply that the terminology is being re-defined herein to be restricted to include any specific characteristics of the features or aspects of the invention with which that terminology is associated.
  • Unless specifically specified, the description of a layer being formed, deposited or produced ‘on’ another layer or substrate, includes:
      • the layer being formed, deposited or produced, or formed, deposited or deposited directly on, i.e. in contact with, the other layer/layers and/or the substrate, and
      • the layer being formed, deposited or produced on one or a stack of intermediate layers between the layer and the other layer and/or the substrate.

Claims (16)

What is claimed is:
1. A semiconductor device package comprising:
one or more semiconductor devices electrically coupled to a metallization stack comprising a plurality of interconnected metallization layers; and
a metal-insulator-metal capacitor (MIMCAP) formed between a lower layer of the metallization layers and an upper layer of the metallization layers, the lower and upper layers being adjacent metallization layers within the stack, wherein the MIMCAP comprises:
at least a portion of a bottom plate which forms a part of the lower metallization layer,
at least a portion of a first conductive layer on and in contact with the bottom plate,
a dielectric layer on and in contact with the first conductive layer,
a second conductive layer on and in contact with the dielectric layer, and
a top plate which forms a part of the upper metallization layer, the top plate being on and in contact with the second conductive layer.
2. The semiconductor package of claim 1, wherein the first and second conductive layers and the dielectric layer interposed between the first and second conductive layers have substantially the same coverage area and overlap one another when viewed in a direction perpendicular to a lateral plane of the layers.
3. The semiconductor package of claim 1, wherein the first conductive layer laterally extends beyond the areas of coverage covered by the dielectric layer and the second conductive layer.
4. The semiconductor package of claim 3, wherein the first conductive layer is further patterned in an area outside of an area covered by the MIMCAP.
5. The semiconductor package of claim 4, wherein the first conductive layer is patterned to form one or more patterned portions, wherein the patterned portions serve as contact portions for electrical circuit elements.
6. The semiconductor package of claim 3, wherein the first conductive layer is patterned to form one or more patterned portions, wherein the patterned portions serve as electrical circuit elements formed in at least one of the lower or upper metallization layers.
7. The semiconductor package of claim 6,
wherein a patterned portion of the first conductive layer forms a resistor in the upper metallization layer, and wherein a stack including a dielectric layer portion and a top conductive layer portion is formed on the resistor,
wherein the dielectric layer portion is formed of the same material and has the same thickness as the dielectric layer of the MIMCAP, and
wherein the top conductive layer portion is formed of the same material and has the same thickness as the second conductive layer of the MIMCAP.
8. The semiconductor package of claim 3, wherein the second conductive layer is surrounded in a plane of the second conductive layer by a ring structure formed of the same material and having the same thickness as the second conductive layer.
9. The semiconductor package of claim 1, wherein the lower and upper metallization layers form a power supply layer and a ground layer, respectively, of an interposer substrate carrying the one or more integrated circuit devices.
10. The semiconductor package of claim 1, wherein at least one of the bottom plate and the top plate is provided with perforations formed therethrough, wherein the perforations are at least partially filled with a dielectric material.
11. A method of fabricating a semiconductor package, comprising:
forming a first metallization layer by a damascene process, the first metallization layer comprising a bottom plate;
depositing a stack comprising a first conductive layer in contact with the first metallization layer, a dielectric layer and a second conductive layer;
patterning the stack to remove at least portions of the second conductive layer and the dielectric layer, wherein the stack at least partially covers the bottom plate; and
forming a second metallization layer by a damascene process, the second metallization layer comprising a top plate which is on and in contact with the second conductive layer of the stack.
12. The method of claim 11, wherein patterning the stack comprises forming the stack having each of the first conductive layer, the dielectric layer and the second conductive layer covering substantially the same coverage area and overlapping one another when viewed in a direction perpendicular to a lateral plane of the layers.
13. The method of claim 11, wherein patterning the stack forms a stack including the dielectric layer and the second conductive layer on the first conductive layer, wherein the first conductive layer remains intact after patterning the stack.
14. The method of claim 13, wherein the first conductive layer is further patterned in a second patterning process.
15. The method of claim 14, wherein during the second patterning process, the first conductive layer and the second conductive layer of the stack are patterned simultaneously.
16. The method of claim 14, wherein during the second patterning process, the second conductive layer of the stack is patterned to form a ring structure around a central portion of the second conductive layer.
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CN112259521A (en) * 2020-10-20 2021-01-22 华虹半导体(无锡)有限公司 MIM capacitor for improving contact stress of electrode plate
CN112259521B (en) * 2020-10-20 2022-08-16 华虹半导体(无锡)有限公司 MIM capacitor for improving contact stress of electrode plate

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US10256183B2 (en) 2019-04-09
US20170194246A1 (en) 2017-07-06

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