JP2002280450A - Semiconductor device and method for manufacturing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor integrated circuit device having a dual damascene wiring capable of etching a wiring groove while protecting a lower layer wiring and keeping the shape of a via hole good without using an etching stopper in the case of etching the wiring groove. SOLUTION: The method for manufacturing a semiconductor device includes (a) a process for accumulating an etching stopper film and an inter-layer insulation film on a base including a semiconductor substrate and having a conductive area on a surface, (b) a process for forming the via hole to the semiconductor area through the inter-layer insulation film and the etching stopper film, (c) a process for forming the first barrier metal layer on the bottom surface of the via hole, (d) a process or forming a wiring groove overlapping with the via hole on a plane view at the inter-layer insulation film, and (e) a process for embedding the wring groove and the via hole to form a dual damascene wiring including a second barrier metal layer and a main wiring layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having damascene wiring and a method of manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor integrated circuit device is manufactured by forming a large number of elements in a semiconductor chip and forming a multilayer wiring on the semiconductor chip. The multilayer wiring is formed by a multilayer wiring layer and an interlayer insulating film that insulates the wiring layers. Traditionally, to form electrical connections between different layers,
Before forming an upper wiring layer on the interlayer insulating film, a via hole penetrating the interlayer insulating film is formed. When forming the upper layer wiring, the inside of the via hole is also filled with the wiring layer.

[0003] A wiring pattern is formed by forming a wiring layer on an interlayer insulating film, forming a resist mask thereon, and etching the wiring layer using the resist mask as an etching mask. Deposits and the like on the wiring pattern side walls are removed by an alkaline chemical or the like. Thereafter, in order to insulate between wiring patterns in the same layer and between upper and lower wiring patterns, an interlayer insulating film made of silicon oxide or the like is formed using plasma CVD or the like.

Conventionally, as a wiring material, aluminum (Al), tungsten (W), or the like that can be etched has been used. After the wiring pattern is formed, an antioxidant layer such as TiN may be formed on the main wiring layer of Al or W in order to prevent the surface of the wiring pattern from being oxidized in ashing for removing the resist mask. Done.

[0005] In a semiconductor integrated circuit device, an improvement in integration degree is always required. In order to improve the degree of integration, semiconductor devices are miniaturized and more semiconductor devices are formed in a unit area. As semiconductor elements are miniaturized and the degree of integration is improved, the density of wiring formed thereon is also increased.
As the interconnect density increases, the width of each interconnect and the spacing between adjacent interconnects in the same layer decreases.

If the thickness of the wiring layer is kept the same, a decrease in the wiring width is accompanied by an increase in the resistance. Further, a decrease in the distance between adjacent wirings is accompanied by an increase in capacitance between the wirings. In order to reduce the increase in wiring resistance, it is necessary to increase the thickness of the wiring layer. If the cross-sectional area of the wiring is to be kept constant, the reduction in the wiring width must be compensated for by increasing the wiring layer thickness.

However, when the thickness of the wiring layer is increased, the facing area between the adjacent wirings is increased, and the capacitance between the wirings is further increased. An increase in the wiring resistance and an increase in the capacitance between the wirings decrease the signal transmission speed. In a memory device, since high integration and low power consumption are the main issues, a wiring material such as Al is used as in the past.

In a logic circuit, the operation speed is a major problem, and it is necessary to prevent the signal transmission speed from decreasing as much as possible. For this reason, it is desired to reduce the resistance of the wiring and the associated capacitance. In order to reduce the resistance of the wiring, it has been proposed to use a high melting point metal such as Cu having a lower resistivity than Al as the wiring material. In order to reduce the associated capacitance of wiring, it has been proposed to reduce the dielectric constant of an insulating film for insulating between wirings. For example, as a low dielectric constant insulating film, a silicon oxide film containing fluorine (FSG)
Are used.

It is difficult to pattern the Cu wiring by etching. Therefore, in order to form a pattern of the Cu layer, a groove (trench) is formed in the insulating film, a Cu layer is formed so as to fill the groove, and an unnecessary Cu layer on the insulating film is subjected to chemical mechanical polishing (CMP). A damascene process for removing by means of (1) or the like is used. As a damascene process, a single damascene process and a dual damascene process are known.

In the single damascene process, a photoresist pattern for a via hole is formed on a lower insulating film, the via hole is etched, the photoresist pattern is removed, and the via hole is buried to form a Cu layer. Unnecessary Cu layer is removed by CMP, an upper insulating film is further formed, a photoresist pattern for a wiring groove is formed, a wiring groove is etched in the upper insulating film, and the wiring groove is buried after removing the photoresist pattern. A layer is formed, and an unnecessary Cu layer on the upper insulating film is removed by CMP.

In the dual damascene process, a photoresist pattern for a via hole is formed on an insulating film, the via hole is etched, a photoresist pattern for a wiring groove is formed on the same insulating film, and the wiring groove is etched. To form a Cu layer that backfills the via hole and the wiring groove,
The unnecessary Cu layer on the insulating film is removed by MP.

When the photoresist pattern is removed by ashing after the formation of the via hole, if the lower Cu wiring layer is exposed, the exposed surface of the Cu wiring is oxidized. In order to prevent oxidation of the Cu wiring surface, Cu
After forming the wiring pattern, an oxidation prevention film having a function of an etching stopper is formed to cover the surface of the Cu wiring.
The oxidation stopper film also serving as an etching stopper is made of, for example, Si
It is formed by an N layer.

When the etching stopper / oxidation preventing film is arranged under the insulating film, a via hole is formed by etching, penetrating the insulating film and exposing the etching stopper / oxidation preventing film. At this stage, the photoresist pattern is formed by ashing. Remove. Thereafter, the etching stopper and antioxidant film exposed at the bottom of the via hole is removed. For simplicity,
The oxidation stopper film also serving as an etching stopper is called an etching stopper film (layer).

[0014] Cu has the property of diffusing into an insulating film such as silicon oxide and deteriorating the dielectric properties of the insulating film.
In order to prevent the diffusion of Cu, Ti
A barrier layer such as N or TaN is formed, and a Cu wiring layer is formed thereon. Etching stopper on Cu wiring (Si
The N) film also has a function of preventing the diffusion of Cu.

A method of interposing an etching stopper layer at an intermediate depth of an interlayer insulating film for controlling the depth at the time of etching a wiring groove is known. As an etching stopper layer,
For example, a plasma SiN film is used. After etching the interlayer insulating film above the etching stopper film, the resist mask is ashed to remove the etching stopper film exposed at the bottom of the wiring groove. However, the etching stopper film is exposed on the side surface of the wiring groove, which causes an increase in the capacity between wirings. Therefore, a method of controlling the wiring groove depth without using an etching stopper film has been proposed.

In the dual damascene method, it is advantageous to use a method in which the opening area of the via hole does not change due to the misalignment between the via hole and the wiring groove. For this reason, a method has been proposed in which a via hole is first etched using a resist pattern as an etching mask, and then a wiring groove is etched using the resist pattern as an etching mask (referred to as a first via dual damascene method). In the case of this via method,
Since the wiring groove is etched after the via hole processing, there is a problem that the via hole bottom surface is etched at the time of wiring groove etching. A method is employed in which an organic material is embedded in the via hole to protect the bottom surface of the via hole at the time of etching the wiring groove.

When wiring grooves are etched by burying an organic material in the via hole, it is necessary to control the height of the filling of the organic material. When the filling height of the filling of the organic material is low, the filling of the organic material disappears during the groove etching, and the role of protecting the bottom surface of the via hole becomes insufficient. When the height of the protective filling is high, the protective filling of the organic material serves as a mask, and causes abnormal etching called shadowing. That is,
Although the periphery of the filling is deeply etched, an interlayer insulating film in a portion in contact with the filling is left at this time. The remaining interlayer insulating film has a shape that projects sharply upward after removing the filler. If this etching residue remains around the via hole, Cu
When a high melting point metal layer is formed, defective filling occurs.

Referring to FIG. 5, a dual-damascene via-via method without using an etching stopper layer at the time of etching a wiring groove will be described.

As shown in FIG. 5A, a plasma SiN film s having a thickness of, for example, about 50 nm is formed as an etching stopper film on a base surface having a conductive region L such as Cu wiring on the surface. An interlayer insulating film d made of, for example, fluorine-containing silicate glass (FSG) having a thickness of 1500 nm is formed thereon. On the surface of the interlayer insulating film d, an antireflection film ar formed of, for example, a 50 nm-thick SiN film is formed.

A resist pattern M1 is formed on the anti-reflection film ar.
Create Using the resist pattern M1 as an etching mask, the antireflection film ar and the interlayer insulating film d are etched to form via holes VH, and the etching stopper film s is exposed. At this stage, the resist pattern M1 is removed by ashing.

As shown in FIG. 5B, a filling pp of an organic material is loaded in the via hole VH, and a resist pattern M2 for forming a wiring groove on the antireflection film ar is formed.

As shown in FIG. 5C, using the resist pattern M2 as an etching mask, the anti-reflection film ar and the interlayer insulating film d are etched by a thickness of 800 nm to form a wiring groove W.
Form T. At this time, since the etching stopper film does not exist on the lower surface of the wiring groove WT, the etching of the shoulder of the via hole VH also progresses, and the etching progresses below the upper surface of the protection pad pp of the organic material. At this time, an etching residue x of the interlayer insulating film protruding sharply upward around the protective filling pp is formed.

After the wiring groove etching, the resist pattern M2 and the protection pad pp are removed by ashing, and the anti-reflection film ar and the etching stopper s exposed in the via hole are removed by etching.

FIG. 5D shows a state in which the antireflection film and the etching stopper film of SiN are removed. An etching residue x that protrudes sharply upward is formed around the via hole VH.

As shown in FIG. 5E, for example, a thickness of about 2
A 5 nm TaN film is formed as a barrier metal layer b by sputtering, and subsequently, a Cu layer having a thickness of about 200 nm is formed as a seed layer by sputtering.

Next, a Cu plating layer having a thickness of about 1300 nm is formed on the seed layer to form a Cu main wiring layer. In this plating step, a void vd may be formed around the remaining etching x. When the void vd is formed, the connection resistance from the underlying conductive region L to the wiring increases.

As shown in FIG. 5F, the main wiring layer w and the barrier metal layer b deposited on the upper surface of the interlayer insulating film d are removed by chemical mechanical polishing (CMP). Thus, a dual damascene wiring is formed. When the void vd is formed, the resistance from the conductive region L to the wiring pattern increases.

If the height of the protective padding of the organic material is controlled to be lower than the etching of the shoulder of the via hole in order to prevent the occurrence of voids, the protective padding of the organic material disappears during the etching of the wiring groove, and the via hole is removed. The etching stopper film in the lower part of the hole is etched, which may adversely affect the surface of the underlying conductive region L.

In the case of multi-layer wiring, the wiring rule becomes looser in the upper layer wiring. However, the wiring width and thickness (height) of the upper layer wiring
Becomes larger. That is, it is necessary to form a deep wiring groove. As the deeper wiring groove is etched, the etching amount at the via hole shoulder increases. On the other hand, in order to withstand a long etching time, the height of the protective padding of the organic material also needs to be increased.
Therefore, there is a trade-off relationship between the height of the organic material's protective padding and the generation of the etching residue inside the via hole, and it becomes more difficult for the upper layer wiring.

[0030]

In the case of forming a dual damascene wiring of a via-via type without using an etching stopper film, it is desired to protect the lower portion of the via hole and prevent abnormal etching.

An object of the present invention is to manufacture a semiconductor device which does not use an etching stopper film for etching a wiring groove, causes no etching residue around a via hole, and does not adversely affect the underlying conductive region. Is to provide a way.

Another object of the present invention is to provide a semiconductor device having a structure suitable for being manufactured by the above-described manufacturing method.

[0033]

According to one aspect of the present invention, (a) a step of depositing an etching stopper film and an interlayer insulating film on a base including a semiconductor substrate and having a conductive region on the surface. (B) forming a via hole penetrating the interlayer insulating film and the etching stopper film and reaching the conductive region; and (c) forming a first barrier metal layer on the bottom surface of the via hole. (D) forming a wiring groove in the interlayer insulating film that overlaps with the via hole in plan view;
(E) forming a dual damascene wiring including a second barrier metal layer and a main wiring layer by filling the wiring groove and the via hole.

According to another aspect of the present invention, a base including a semiconductor substrate and having a conductive region on the surface, a stack including an etching stopper film and an interlayer insulating film formed on the base, A wiring groove formed up to the intermediate depth of the interlayer insulating film, and penetrates the remaining thickness of the interlayer insulating film and the etching stopper film from the bottom of the wiring groove,
A second barrier formed by burying the via hole reaching the conductive region, a first barrier metal layer formed on the bottom surface of the via hole, and the via hole and the wiring groove above the first barrier metal layer; A semiconductor device having a dual damascene wiring including a metal layer and a main wiring region is provided.

After the first barrier metal layer is formed on the bottom surface of the via hole, the wiring groove is formed, so that there is no need to load a protective padding of an organic material into the via hole. Since the etching stopper film is protected by the first barrier metal layer without using a protective padding of an organic material, no etching residue is generated in the interlayer insulating film around the via hole, and abnormal etching can be prevented.

Since the etching stopper film is not used to control the etching of the wiring groove, the upper shoulder is cut off with the etching of the wiring groove, and the frontage becomes wide. That is, the cross-sectional shape of the via hole becomes a wine glass shape. Therefore, a wiring structure having high resistance to stress migration can be obtained.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention and a method for manufacturing the same will be described below with reference to the drawings.

As shown in FIG. 1A, a base U having a conductive region L on the surface is prepared. The base U includes a semiconductor substrate, and a plurality of transistors Q are formed in the semiconductor substrate. Note that the conductive region L may be an electrode region of the transistor Q.

An etching stopper film s is formed so as to cover the conductive region L of the base U, and an interlayer insulating film d is formed thereon. The interlayer insulating film can be formed of, for example, silicon oxide, silicon oxide formed from fluorine-containing silicate glass (FSG), hydrogen silsesquioxane (HSQ), silicon oxide formed from tetraethoxysilicate (TEOS), or the like. The etching stopper film s is an interlayer insulating film d
Is a film having a function of an etching stopper for the etching of the substrate, and is formed of, for example, silicon nitride, silicon carbide, or the like.

A mask M1 having an opening for forming a via hole is formed on the interlayer insulating film d. Mask M1
Is formed, for example, with a resist pattern. Mask M1
Are aligned with the conductive region L of the base U.

Using the mask M1 as an etching mask, the interlayer insulating film d is etched. Etching stoppers
Is exposed, the etching is stopped, and the mask M1 is removed by ashing or the like. After that, the etching stopper film s exposed on the bottom surface of the formed via hole VH is removed.

As shown in FIG. 1B, a first layer of TiN, TaN or the like is formed on the bottom surface of the via hole VH thus formed.
The barrier metal b1 is formed. First barrier metal layer b1
Is formed of a material having an extremely low etching rate ratio with respect to the etching of the interlayer insulating film d.

As shown in FIG. 1C, a mask M2 having an opening corresponding to the wiring groove is formed on the surface of the interlayer insulating film d. The opening of the mask M2 desirably completely includes the via hole, and needs to overlap at least the via hole. The mask M2 may be formed of the same material as the first barrier metal layer, or may be formed of a resist or the like. Mask M2
Is used as an etching mask to etch the interlayer insulating film d. A predetermined thickness of the interlayer insulating film d is etched to form a wiring groove WT. At this time, the etching of the shoulder portion of the via hole VH also progresses, and the upper portion of the via hole becomes a wine glass type via hole whose cross-sectional shape gradually expands upward.

In the etching of the wiring groove, since the bottom surface of the via hole is covered with the first barrier metal layer b1, the conductive region L of the base U is prevented from being affected by the etching.

As shown in FIG. 1D, the second barrier metal layer b2 and the main wiring layer w are formed in the via hole VH and the wiring groove WT while leaving the first barrier metal layer b1. For example, a barrier metal layer b2 of TaN, TiN, or the like is formed by sputtering, a Cu seed layer is formed by sputtering, and Cu is plated to form a main wiring layer w.

Thereafter, unnecessary barrier metal layers and main wiring layers deposited on the interlayer insulating film d are removed by CMP, etch back, or the like. The mask M2 is removed by ashing, CMP or the like after the etching of the wiring groove.

According to the above-described process, the bottom surface of the via hole VH is covered with the first barrier metal layer b1 during the wiring etching shown in FIG. Etching stopper film to protect,
There is no need to provide a protective padding of an organic material. Since no protective padding of an organic material is used, there is no occurrence of abnormal etching (residual etching).

FIGS. 2A to 2H are cross-sectional views showing a more specific method for manufacturing a semiconductor device. An etching stopper film s made of a silicon nitride film having a thickness of about 50 nm is formed on a base having a copper wiring L on the surface.
On the etching stopper film s, an interlayer insulating film d made of an FSG film having a thickness of about 1500 nm is formed. An anti-reflection film ar made of a silicon nitride film having a thickness of about 50 nm is formed on the surface of the interlayer insulating film d. On the anti-reflection film ar,
A resist film is applied, exposed, and developed to form a resist pattern M1 having an opening corresponding to the via hole.

Using the resist pattern M1 as an etching mask, etching is performed using CHF ₃ + O ₂ as a main etching gas to etch the silicon nitride antireflection film ar.

Next, using C ₄ F ₈ as a main etching gas,
The interlayer insulating film d is etched to form a via hole VH. The etching is stopped when the etching stopper film s is exposed. To automatically stop etching with an etching stopper film, C _x F _y having a large [C] / [F] ratio
Preferably, a gas is used. For example, C ₄ F ₈ or C ₅ F ₈ gas is used. The resist mask M1 is removed by ashing. In this ashing, oxidation is prevented because the surface of the copper wiring L is covered with the etching stopper film s.

As shown in FIG. 2B, etching of the silicon nitride film is performed using CHF ₃ + O ₂ as an etching gas. The anti-reflection film ar on the surface of the interlayer insulating film d and the etching stopper s exposed on the bottom surface of the via hole VH are removed.

As shown in FIG. 2C, the first barrier metal layer b1 formed from a TiN layer is formed on the surface of the interlayer insulating film d by ionization sputtering (ionized physical vapor deposition iPVD) with a higher directivity from above. About 200n thick
m is formed. Note that a thickness of about 200 is formed on the surface of the interlayer insulating film d.
When a TiN layer having a thickness of 10 nm is formed, a first barrier metal layer b1 having a thickness of about 60 nm is formed on the bottom surface of the via hole. Note that the first barrier metal layer may be formed by stacking Ti / TiN.

The protective filling pp of the organic material is loaded in the via hole VH on which the first barrier metal layer b1 is formed.

As shown in FIG. 2D, a resist film is applied on the surface of the first barrier metal layer b1 formed on the interlayer insulating film d, exposed and developed, and a resist for etching the wiring groove is formed. Create the pattern M2.

As shown in FIG. 2E, etching is performed using the resist pattern M2 as an etching mask and Cl ₂ + BCl ₃ as a main etching gas to form an interlayer insulating film d.
The first barrier metal layer b1 on the surface is etched. The protective filling pp of the organic material has a higher etching rate than the first barrier metal layer, and the protective filling above the via hole VH disappears by etching. However,
The first barrier metal layer b1 disposed under the protection padding pp remains without being etched.

In this etching, the protective filler pp
Since the etching rate is high, abnormal etching hardly occurs. After that, the resist pattern M1 and the protective padding pp
Is removed by ashing or the like. First on the interlayer insulating film d
The hard mask formed of the barrier metal layer b1 remains.

As shown in FIG. 2F, the hard mask of the first barrier metal layer b1 formed on the surface of the interlayer insulating film d is used as an etching mask, and the interlayer insulating film d has a depth of about 80.
Etch 0 nm. In this etching, the etching of the shoulder portion of the via hole VH also proceeds, and the cross section of the upper portion of the via hole VH becomes a wine glass shape. Further, the first barrier metal layer b1 is formed on the bottom surface of the via hole VH, so that the underlying copper wiring L is prevented from being adversely affected by the etching. Thus, the wiring groove WT is formed above the via hole VH.

As shown in FIG. 2G, a second barrier metal layer b2 formed of, for example, a TiN layer having a thickness of about 25 nm is formed on the surfaces of the wiring trenches WT and the via holes VH by ionization sputtering with reduced directivity. Deposited, followed by a thickness of about 25
A seed layer made of a 0 nm Cu layer is formed. Deposition also occurs on the sidewalls of the via holes VH and the wiring trenches WT due to the sputtering with reduced directivity. A Cu layer having a thickness of about 1300 nm is formed on the seed layer by plating to form a main wiring layer w.

As shown in FIG. 2H, the Cu layer w and the barrier metal layers b2 and b1 deposited on the upper surface of the interlayer insulating film d are removed by chemical mechanical polishing (CMP).

Although the case where TiN is used as the barrier metal has been described, the barrier metal can be selected from the group consisting of titanium, a titanium compound, tantalum, and a tantalum compound. The case where Cu is used as the main wiring has been described. Materials selected from the group can be used.

The interlayer insulating film is made of plasma SiO ₂ , phosphorus-containing silicate glass (PSG), boron-phosphorus-containing silicate glass (BPSG), or fluorine-containing silicate glass (F
SG), hydrogen silsequioxane (HSQ), and tetraethoxysilicate (TEOS). The barrier metal layer and the seed metal layer can be deposited by ionized physical vapor deposition, long throw sputtering, collimator sputtering, or the like. It is also effective to combine ionized physical deposition with long throw sputtering.

FIGS. 3A to 3F are cross-sectional views showing a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 3A shows a state similar to FIG. 2C. That is, a via hole VH is formed in the interlayer insulating film d and the etching stopper film s, and a first barrier metal layer b1 of TaN is formed on the bottom surface of the via VH and on the upper surface of the interlayer insulating film d instead of TiN. Further, a protective filling pp of an organic material is loaded in the via hole VH.

As shown in FIG. 3B, the first barrier metal layer b1 on the surface of the interlayer insulating film d is removed by CMP. Thereafter, the protective filling pp in the via hole VH is also removed by ashing or the like. In this embodiment, the protective filling p
p protects the inner surface of the via hole VH in CMP, but is not an essential component.

As shown in FIG. 3C, a resist pattern M2 having an opening of a wiring groove is formed on the upper surface of the interlayer insulating film d.

Using the resist pattern M2 as an etching mask and C ₄ F ₈ as a main etching gas, the interlayer insulating film d is etched to a depth of about 800 nm. In this etching, the etching of the shoulder of the via hole VH also proceeds, and the via hole VH becomes a wine glass shape.

As shown in FIG. 3D, after the etching is completed, the resist pattern M2 is removed by ashing.
At this time, the surface of the underlying copper wiring L is the first barrier metal layer b1
To prevent oxidation.

As shown in FIG. 3E, a second barrier metal layer b2 formed of a TaN layer having a thickness of about 25 nm and a seed layer formed of a Cu layer having a thickness of about 250 nm were formed by ionization sputtering. Film. Subsequently, the thickness of about 13
A 00 nm Cu layer is formed by plating. Thus, the main wiring layer w is formed.

As shown in FIG. 3F, unnecessary main wiring layers w and barrier metal layers b2 deposited on the upper surface of the interlayer insulating film d.
Is removed by CMP.

Also in this embodiment, in the wiring groove etching step shown in FIG. 3C, no protective padding is loaded inside the via hole VH, and no etching abnormality occurs around the via hole VH. Since the bottom surface of the via hole is protected by the first barrier metal layer, it does not adversely affect the underlying wiring.

Since the upper portion of the via hole spreads like a wine glass, the ratio of the volume of the via conductor in the portion in contact with the wiring layer to the portion in contact with the wiring layer is reduced, and stress migration is reduced.

In the embodiment described above, one dual damascene wiring is formed. In an actual semiconductor device, multiple wiring layers are formed, and a plurality of dual damascene structures are formed in each wiring layer.

FIG. 4 is a sectional view showing a configuration example of a semiconductor integrated circuit device. An element isolation region STI is formed on the surface of the silicon substrate 10 by shallow trench isolation.
Are formed, and an active region is defined. In the structure shown in the figure, an n-channel MOS transistor n-MOS is formed in one active region, and a p-channel MOS transistor p-MOS is formed in another active region.

Each transistor has an insulated gate electrode structure on the substrate surface, and n-type or p-type source / drain regions 11 are formed in the substrate on both sides of the gate electrode.
These source / drain regions are the conductive regions in the above embodiment.

A first etch stopper layer 12 and a first interlayer insulating film 15 are formed on the surface of the silicon substrate 10, and the dual damascene first barrier layers 18 and 19 and the main wiring layer 20 are formed in the same manner as in the above embodiment. A wiring structure is formed. These dual damascene wirings also serve as conductive regions in the above-described embodiment with respect to wirings formed thereabove.

In the figure, a lead-out wiring structure is formed on each of the conductive regions 11 at both ends, and another wiring structure for interconnecting the two is formed on the two central conductive regions 11. That is, the two MOS transistors shown in the figure constitute a complementary MOS (CMOS) transistor.

A second etch stopper layer 22 and a second interlayer insulating film 25 are formed on the first wiring layer described above. In this stack, the barrier metal layer 2 is formed as in the first wiring layer.
8, 29, and a dual damascene second wiring structure of the main wiring layer 30 is formed.

Further, the third etch stopper layer 3
Second and third interlayer insulating films 35 are stacked, and a dual damascene third wiring structure including barrier metal layers 38 and 39 and a main wiring layer 40 is formed in the stacked layers.

Further, a fourth etch stopper layer 4
A stack of the second and fourth interlayer insulating films 45 is formed, and a dual damascene fourth wiring structure of the barrier metal layers 48 and 49 and the main wiring layer 50 is formed in the stack. A protective film 52 is formed to cover the surface of the dual damascene wiring structure.

These dual damascene wirings also correspond to the dual damascene wirings of the above embodiment. In this manner, by forming the multilayer wiring structure using the dual damascene wiring structure, it is possible to form a wiring structure with a high degree of integration, small accompanying capacitance, and low wiring resistance.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. A semiconductor integrated circuit device that can operate at high speed using copper wiring has been described.
Dual damascene wiring is also effective for forming aluminum wiring at high density. When the demand for high-speed operation is relaxed, the wiring material, the interlayer insulating film material, and the like can be selected from a wider range.

For example, the interlayer insulating film may be made of a silicon oxide film, a silicon oxide film containing an additive to which fluorine, phosphorus, boron or the like is added, or a silicon oxide film of a different material such as hydrogen silsesquioxane (HSQ) or tetraethoxysilicate (TEOS). It can be selected from a film, a silicon nitride film, a silicon oxynitride film, an inorganic compound film having a siloxane bond, an organic compound film, and the like. In addition to the silicon nitride film, a silicon oxynitride film, silicon carbide (SiC, SiC: H), or the like may be used as the etch stop layer.

The dual damascene wiring can be formed of a metal or a metal compound. Metals include gold, silver, platinum,
Copper, aluminum, tungsten, titanium, tantalum,
Molybdenum or the like, or an alloy thereof can be used. As the metal compound, titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, or the like can be used.

It will be apparent to those skilled in the art that various other modifications, improvements, and combinations are possible.

[0085]

As described above, according to the present invention,
In a semiconductor integrated circuit device having a dual damascene wiring structure, a dual damascene wiring structure having a good via hole shape can be formed without oxidizing the surface of the underlying wiring layer.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a sectional view illustrating the manufacture of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating the manufacture of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a configuration of a semiconductor integrated circuit device.

FIG. 5 is a cross-sectional view illustrating an example of a dual damascene process according to a conventional technique.

[Explanation of symbols]

 U base L conductive region s etching stopper film d interlayer insulating film ar antireflection film M mask VH via hole WT wiring groove b barrier metal layer w main wiring layer

Continued on the front page F-term (reference) 4M104 BB04 BB30 BB32 CC01 DD08 DD16 DD17 DD37 DD51 EE14 EE17 FF22 HH20 5F033 HH07 HH08 HH09 HH11 HH13 HH14 HH18 HH19 HH20 HH21 HH32 HH33 JJ01 JJ19 JJ13 JJ01 JJ19 JJ19 JJ18 JJ19 JJ18 JJ19 JJ19 JJ19 JJ18 JJ18 JJ18 JJ18 JJ01 JJ18 JJ01 JJ18 JJ18 JJ18 JJ18 JJ18 JJ01 JJ18 JJ18 JJ18 JJ19 JJ19 JJ19 JJ18 JJ18 JJ18 JJ18 JJ18 JJ01 JJ19 JJ18 JJ19 JJ18 JJ18 JJ18 JJ18 JJ18 JJ18 KK11 MM02 MM12 MM13 NN03 NN06 NN07 PP15 PP21 PP22 PP26 QQ04 QQ09 QQ10 QQ12 QQ21 QQ25 QQ35 QQ37 QQ48 RR01 RR04 RR06 RR11 RR14 RR15 XX00

Claims (5)

[Claims] (A) depositing an etching stopper film and an interlayer insulating film on a base including a semiconductor substrate and having a conductive region on the surface; and (b) a step of depositing the interlayer insulating film and the etching stopper film. (C) forming a first barrier metal layer on the bottom surface of the via hole; and (d) forming a first barrier metal layer on the bottom surface of the via hole. Forming a wiring groove overlapping the via hole; and (e) forming a dual damascene wiring including a second barrier metal layer and a main wiring layer by filling the wiring groove and the via hole. Manufacturing method. 2. The step (b) includes forming a first resist pattern on the interlayer insulating film, etching the interlayer insulating film using the resist pattern as an etching mask,
Removing the resist pattern, etching the etching stopper film; forming the first barrier metal layer on the bottom surface of the via hole and on the upper surface of the interlayer insulating film in the step (c); Loading a protective filling on the first barrier metal layer in the via hole, forming a second resist pattern on the first barrier metal layer on the upper surface of the interlayer insulating film,
Using the second resist pattern as an etching mask, etching the first barrier metal layer on the upper surface of the interlayer insulating film to form a hard mask, removing the second resist pattern, and using the hard mask as an etching mask to form the hard mask. 2. The method according to claim 1, wherein the insulating film is etched. 3. The step (b) includes forming a first resist pattern on the interlayer insulating film, etching the interlayer insulating film using the resist pattern as an etching mask,
After the resist pattern is removed, the etching stopper film is etched. The step (c) forms the first barrier metal layer on the bottom surface of the via hole and on the upper surface of the interlayer insulating film. Removing the first barrier metal layer, forming a second resist pattern on the exposed upper surface of the interlayer insulating film, and etching the interlayer insulating film using the second resist pattern as an etching mask. Item 2. The method for manufacturing a semiconductor device according to Item 1. 4. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (d), the upper portion of the via hole is etched so as to expand toward the wiring groove simultaneously with the formation of the wiring groove. . 5. A stack including a semiconductor substrate and having a conductive region on the surface, a stack including an etching stopper film and an interlayer insulating film formed on the base, and from the stacked surface to an intermediate depth of the interlayer insulating film. A formed wiring groove; a via hole penetrating from the bottom of the wiring groove to the remaining thickness of the interlayer insulating film and the etching stopper film to reach the conductive region; A semiconductor device, comprising: a first barrier metal layer; and a dual damascene wiring formed by filling the via hole and the wiring groove above the first barrier metal layer and including a second barrier metal layer and a main wiring region.