US20140140445A1 - Apparatus and method for demodulation of fsk signals - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
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- the present invention relates generally to process control systems. More particularly, the present invention relates to an apparatus and method for modulating and demodulating an FSK signal, for example, a HART FSK signal.
- Detectors used in industrial automation are becoming smarter due to advancement in technology.
- field devices used in industrial automation can communicate process variables using a current loop, and a controller can sense the current and interpret the process variable.
- an analog signal When an analog signal is used, only one process variable can be transmitted.
- a digital signal can communicate information using frequency shift keying superimposed on an analog signal, thus increasing the number of process variables that can be sent to a controller using an existing analog signal line.
- HART Highway Addressable Remote Transducer
- FSK Frequency Shift Keying
- HART modem Various techniques have been tried to reduce the cost of the HART modem. For example, some techniques have employed a dedicated HART modem IC. Other techniques and approaches for decoding FSK signals have been software-based and FPGA/CPLD-based. However, each of these known techniques presents drawback and disadvantages.
- AN 2336 discloses a technique for and implementation of a dedicated HART modem IC in a PSoC® platform
- FIG. 1 is a block diagram of a demodulator as disclosed in AN2336.
- the technique and implementation disclosed in AN2336 and shown in FIG. 1 is both CPU-intensive and costly. For example, if implemented with microcontroller software, such a technique can utilize most CPU processing power.
- the comparator circuit as seen in FIG. 1 , can add to the overall cost of the demodulator.
- FIG. 2 is a block diagram of the method disclosed in the '857 publication.
- One of the drawbacks of the technique and implementation disclosed in the '857 publication is that they are CPU-intensive.
- FIG. 3 is a circuit block diagram of the implemented IC. As seen in FIG. 3 , the implementation of this technique requires the use of an A5191 IC and various other discrete components. Accordingly, this technique and implementation is extremely costly.
- FIG. 1 is a block diagram of a demodulator as known in the art
- FIG. 2 is a block diagram of a method for demodulating an FSK signal as known in the art
- FIG. 3 is a circuit block diagram of a HART modem IC as known in the art
- FIG. 4 is a block diagram of a diagram in accordance with disclosed embodiments.
- FIG. 5 is a functional block diagram of a demodulator in accordance with disclosed embodiments.
- FIG. 6 is a functional block diagram of a modulator in accordance with disclosed embodiments.
- FIG. 7 is a timing diagram for a demodulator in accordance with disclosed embodiments.
- FIG. 8 is a timing diagram for a demodulator in accordance with disclosed embodiments.
- FIG. 9 is a timing diagram for a demodulator in accordance with disclosed embodiments.
- FIG. 10 is a timing diagram for a demodulator in accordance with disclosed embodiments.
- FIG. 11 is a block diagram of a smart modem implemented within an application processor in accordance with disclosed embodiments.
- FIG. 12 is a block diagram of a smart modem implemented as a standalone modem in accordance with disclosed embodiments.
- Embodiments disclosed herein include an improved apparatus and method for demodulation of FSK signals.
- FSK signals having fundamental frequencies of 1200 Hz and 2200 Hz can be demodulated, as per HART standards.
- the apparatus and method disclosed herein can use and consume less CPU processing power and memory than in known systems and methods.
- the apparatus and method disclosed herein can also contribute to cost savings.
- Some embodiments disclosed herein can be implemented with executable control software stored on a non-transitory computer readable medium. Some embodiments disclosed herein can also eliminate a dedicated modem IC and, instead, employ filters and limit comparators. These embodiments can be both CPU and cost-friendly. For example, embodiments disclosed herein can minimize the use of a microcontroller's memory, peripherals, and processing and can also minimize the number of hardware parts employed, thus, minimizing costs.
- Embodiments disclosed herein can process digital pulses of an FSK signal to detect digital data contained in the FSK frequencies.
- the HART protocol can define 1200 Hz and 2200 Hz as frequencies that represent logic 1 and logic 0, respectively. For communication purposes, these frequencies can be converted from a frequency signal to a digital logic signal and vice versa.
- a modem for example, a HART modem, can be used to execute such a conversion.
- FIG. 4 is a block diagram of a demodulator 400 in accordance with disclosed embodiments.
- FSK pulses 410 for example, HART FSK pulses
- FSK pulses 410 can be delayed as in 420 .
- one frequency can be delayed while the phase of the second frequency can be retained.
- the delay time of the low frequency signal can be approximately 578.7 ⁇ s.
- embodiments disclosed herein are not so limited. For example, if different frequencies are to be demodulated, then the delay time would vary accordingly.
- the delayed signal can be XORed with the parent signal as in 430 before conversion to digital logic as in 440 .
- FIGS. 5 and 6 are functional block diagrams of a demodulator 500 and modulator 600 , respectively, in accordance with disclosed embodiments.
- an FSK signal for example, a HART FSK signal
- functional blocks 510 , 520 can be implemented with hardware and/or in software stored on a non-transitory computer readable medium.
- functional block 510 can include hardware filters that remove out-of-band interference from an incoming HART FSK signal.
- functional block 510 can include a 2nd order active HPF (high pass filter) and a 1st order passive LPF (low pass filter).
- the HPF can have a cutoff frequency of approximately 900 Hz
- the LPF can have a cutoff frequency of approximately 2400 Hz
- embodiments disclosed herein are not so limited. For example, if different frequencies are to be demodulated, then the cutoff frequencies of the HPF and the LPF would vary accordingly.
- functional block 510 can include a passive notch filter for improved in-band noise rejection.
- the filtered signal that exits functional block 510 can pass through functional block 520 , which can include a zero crossing detector.
- functional block 520 can convert sine wave signals to digital pulses.
- functional blocks 530 , 540 can form a smart modem 550 and can be implemented with executable control software stored on a non-transitory computer readable medium.
- the digital pulses that exit functional block 520 can be fed to a microcontroller GPIO pin that is capable of issuing interrupts on rising and falling edges of a signal.
- FIGS. 7-9 are timing diagrams that depict the processing involved in functional block 530 .
- Exemplary embodiments disclosed herein can employ HART FSK signals, and HART FSK signals can consist of both 1200 Hz and 2200 Hz signals. Accordingly, FIG. 7 is a timing diagram for a 1200 Hz signal, and FIG. 8 is a timing diagram for a 2200 Hz signal.
- Functional block 530 can execute various steps for each of the 1200 Hz and 2200 Hz signal. For example, first, a GPIO hardware interrupt can trigger an ISR (Interrupt Service Routine) at edge rising a. Then, a first variable can be updated with a state of the input waveform.
- ISR Interrupt Service Routine
- a timer for example, a timer located inside hardware associated with the ISR, can be set to predetermined delay time d and be started.
- delay time d can be approximately 578.7 ⁇ s.
- the timer can trigger the ISR.
- edge a can be reproduced as edge a′, and a second variable can be updated with a state of the delayed waveform.
- the first variable corresponding to the state of the input waveform can be XORed with the second variable corresponding to the state of the delayed waveform. Then, the output of the XOR can be stored as a third variable.
- a GPIO hardware interrupt can also trigger an ISR at falling edge b.
- a fourth variable can be updated with a state of the input waveform.
- the ISR timer can be set to predetermined delay time d and be started. After expiration of delay time d, the timer can trigger the ISR. Then, edge b can be reproduced as edge b′, and a fifth variable can be updated with a state of the delayed waveform.
- the fourth variable corresponding to the state of the input waveform can be XORed with the fifth variable corresponding to the state of the delayed waveform. Then, the output of the XOR can be stored as a sixth variable.
- edge a can be reproduced as edge a′, and the second variable can be updated with the state of the delayed waveform, even though the timer has not yet triggered the ISR. Then, when the GPIO hardware interrupt triggers the ISR at rising edge a, the first variable can be updated with the state of the input waveform, and the ISR timer can be set to delay time d.
- edge b can be reproduced as edge b′, and the fifth variable can be updated with the state of the delayed waveform, even though the timer has not yet triggered the ISR. Then, when the GPIO hardware interrupt triggers the ISR at falling edge b, the fourth variable can be updated with the state of the input waveform, and the ISR timer can be set to delay time d.
- the XORed output of functional block 530 can vary between logic 1 and logic 0. However, the XORed output is different when the input waveform is a 2200 Hz signal. For example, as seen in FIG. 8 , when the input waveform is a 2200 Hz signal, the XORed output of functional block 530 can be logic 0 at all times.
- the delayed waveform of a 2200 Hz signal is not delayed by delay time d. Instead, the delayed waveform is terminated before delay time d is completed.
- the vertical lines VL 1 , VL 2 in FIG. 8 illustrate that the time delay between a and a′ and between b and b′ is less than delay time d.
- FIG. 9 is a timing diagram for signal conversion. As seen in FIG. 9 , a higher frequency is converted to logic 0 and a lower frequency is converted to a train of pulses.
- FIG. 10 is a timing diagram that depicts the processing involved in functional block 540 , and, as seen in FIG. 10 , at a second rising edge, the output waveform logic can be made high.
- a second falling edge of the train of pulses can trigger a time delay t and keep the output waveform logic high.
- the time delay t can be approximately 578.7 ⁇ s. If another falling edge is detected before time delay t has expired, the timer can be refreshed and reset to time delay t. When no pulses and/or rising or falling edges are detected after expiration of time delay t, the output waveform logic can be made low.
- a HART FSK signal can represent 1200 bps UART (Universal Asynchronous Receiver Transmitter) data communication.
- the output of functional block 540 can be fed to a UART of a microcontroller.
- the output of functional block 540 which is also the output of the smart modem 550 and of the demodulator 500 , can be fed into the modulator 600 after processing the data using executable control software stored on a non-transitory computer readable medium.
- the HART FSK signal can be processed through the modulator 600 and pass through three functional blocks 610 , 620 , 630 to be modulated.
- functional block 610 can select the FSK signal frequency.
- the functional block 610 can receive information with instructions for when to switch the frequency of the FSK signal.
- Functional block 620 can then pulse-width modulate the signal corresponding to the sine frequencies of the signal.
- functional block 630 can include a 2nd order passive LPF through which the signal can pass to remove high frequency switching noise.
- the smart modem 500 in accordance with embodiments disclosed herein can be implemented with executable control software stored on a non-transitory computer readable medium.
- the non-transitory computer readable medium can be stored on a microcontroller that is implemented in an application processor.
- the non-transitory computer readable medium can be stored on a microcontroller that is implemented with as a stand-alone modem.
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Abstract
Description
- The present invention relates generally to process control systems. More particularly, the present invention relates to an apparatus and method for modulating and demodulating an FSK signal, for example, a HART FSK signal.
- Detectors used in industrial automation are becoming smarter due to advancement in technology. For example, field devices used in industrial automation can communicate process variables using a current loop, and a controller can sense the current and interpret the process variable. When an analog signal is used, only one process variable can be transmitted. However, a digital signal can communicate information using frequency shift keying superimposed on an analog signal, thus increasing the number of process variables that can be sent to a controller using an existing analog signal line.
- Most of detectors known in the art support standard protocols recommended by the industry, but these protocols pose a constraint on the manufacturer of the detector. For example, the manufacturer must use sophisticated chips to implement the standard protocols recommended by the industry, and these sophisticated chips can add to the overall cost of the detector. Furthermore, the protocols must comply with a set of physical layer specifications so that the digital communication superimposed on the analog line does not disturb the overall network of field devices and/or the controller.
- HART (Highway Addressable Remote Transducer) protocol is one example of a widely accepted and implemented communication protocol that is commonly used in the instrumentation and process control industry. The HART protocol is used to communicate digital data and uses an FSK (Frequency Shift Keying) signal of 1200 Hz and 2200 Hz traveling on a conventional 4-20 mA current loop.
- Devices that communicate via the HART protocol must decode and generate FSK signals. Therefore, the integration and implementation of HART capability in these devices is essential. However, modem circuitry that implements and is compliant with the HART protocol can be very expensive, especially in the demodulation section of the modem.
- Various techniques have been tried to reduce the cost of the HART modem. For example, some techniques have employed a dedicated HART modem IC. Other techniques and approaches for decoding FSK signals have been software-based and FPGA/CPLD-based. However, each of these known techniques presents drawback and disadvantages.
- One previously proposed technique is disclosed in Application Note 2336 titled “Simplified FSK Detection” (“AN 2336”). AN 2336 discloses a technique for and implementation of a dedicated HART modem IC in a PSoC® platform, and
FIG. 1 is a block diagram of a demodulator as disclosed in AN2336. The technique and implementation disclosed in AN2336 and shown inFIG. 1 is both CPU-intensive and costly. For example, if implemented with microcontroller software, such a technique can utilize most CPU processing power. Furthermore, the comparator circuit, as seen inFIG. 1 , can add to the overall cost of the demodulator. - Another previously proposed technique is disclosed in U.S. Publication No. 2009/0168857 titled “Micro-Controller With FSK Modem” (“the '857 publication”). The technique disclosed in the '857 publication is primarily based on counting the number of zero crossing instances in a given time period, and
FIG. 2 is a block diagram of the method disclosed in the '857 publication. One of the drawbacks of the technique and implementation disclosed in the '857 publication is that they are CPU-intensive. - Yet another previously proposed technique is the A5191 HRTL HART modem IC manufactured by ON Semiconductor. The A5191HRTL HART modem IC has been widely used in the industry to add HART capability to products, and
FIG. 3 is a circuit block diagram of the implemented IC. As seen inFIG. 3 , the implementation of this technique requires the use of an A5191 IC and various other discrete components. Accordingly, this technique and implementation is extremely costly. - In view of the above, there is a continuing, ongoing need for an improved apparatus and method for demodulation of FSK signals.
-
FIG. 1 is a block diagram of a demodulator as known in the art; -
FIG. 2 is a block diagram of a method for demodulating an FSK signal as known in the art; -
FIG. 3 is a circuit block diagram of a HART modem IC as known in the art; -
FIG. 4 is a block diagram of a diagram in accordance with disclosed embodiments; -
FIG. 5 is a functional block diagram of a demodulator in accordance with disclosed embodiments; -
FIG. 6 is a functional block diagram of a modulator in accordance with disclosed embodiments; -
FIG. 7 is a timing diagram for a demodulator in accordance with disclosed embodiments; -
FIG. 8 is a timing diagram for a demodulator in accordance with disclosed embodiments; -
FIG. 9 is a timing diagram for a demodulator in accordance with disclosed embodiments; -
FIG. 10 is a timing diagram for a demodulator in accordance with disclosed embodiments; -
FIG. 11 is a block diagram of a smart modem implemented within an application processor in accordance with disclosed embodiments; and -
FIG. 12 is a block diagram of a smart modem implemented as a standalone modem in accordance with disclosed embodiments. - While this invention is susceptible of an embodiment in many different forms, there are shown in the drawings and will be described herein in detail specific embodiments thereof with the understanding that the present disclosure is to be considered as an exemplification of the principles of the invention. It is not intended to limit the invention to the specific illustrated embodiments.
- Embodiments disclosed herein include an improved apparatus and method for demodulation of FSK signals. For example, FSK signals having fundamental frequencies of 1200 Hz and 2200 Hz can be demodulated, as per HART standards. The apparatus and method disclosed herein can use and consume less CPU processing power and memory than in known systems and methods. The apparatus and method disclosed herein can also contribute to cost savings.
- Some embodiments disclosed herein can be implemented with executable control software stored on a non-transitory computer readable medium. Some embodiments disclosed herein can also eliminate a dedicated modem IC and, instead, employ filters and limit comparators. These embodiments can be both CPU and cost-friendly. For example, embodiments disclosed herein can minimize the use of a microcontroller's memory, peripherals, and processing and can also minimize the number of hardware parts employed, thus, minimizing costs.
- Embodiments disclosed herein can process digital pulses of an FSK signal to detect digital data contained in the FSK frequencies. For example, in some embodiments disclosed herein, the HART protocol can define 1200 Hz and 2200 Hz as frequencies that represent
logic 1 andlogic 0, respectively. For communication purposes, these frequencies can be converted from a frequency signal to a digital logic signal and vice versa. In some embodiments, a modem, for example, a HART modem, can be used to execute such a conversion. -
FIG. 4 is a block diagram of ademodulator 400 in accordance with disclosed embodiments. As seen inFIG. 4 ,FSK pulses 410, for example, HART FSK pulses, can be delayed as in 420. In embodiments disclosed herein, one frequency can be delayed while the phase of the second frequency can be retained. in exemplary embodiments that employ 1200 Hz and 2200 Hz frequencies, as per the HART standard, the delay time of the low frequency signal can be approximately 578.7 μs. However, embodiments disclosed herein are not so limited. For example, if different frequencies are to be demodulated, then the delay time would vary accordingly. After the delay as in 420, the delayed signal can be XORed with the parent signal as in 430 before conversion to digital logic as in 440. -
FIGS. 5 and 6 are functional block diagrams of ademodulator 500 andmodulator 600, respectively, in accordance with disclosed embodiments. As seen inFIG. 5 , an FSK signal, for example, a HART FSK signal, can be processed through thedemodulator 500 and pass through fourfunctional blocks - In some embodiments,
functional blocks functional block 510 can include hardware filters that remove out-of-band interference from an incoming HART FSK signal. In some embodiments,functional block 510 can include a 2nd order active HPF (high pass filter) and a 1st order passive LPF (low pass filter). In exemplary embodiments that employ 1200 Hz and 2200 Hz frequencies, the HPF can have a cutoff frequency of approximately 900 Hz, and the LPF can have a cutoff frequency of approximately 2400 Hz, However, embodiments disclosed herein are not so limited. For example, if different frequencies are to be demodulated, then the cutoff frequencies of the HPF and the LPF would vary accordingly. - In some embodiments,
functional block 510 can include a passive notch filter for improved in-band noise rejection. The filtered signal that exitsfunctional block 510 can pass throughfunctional block 520, which can include a zero crossing detector. In some embodiments,functional block 520 can convert sine wave signals to digital pulses. - In some embodiments,
functional blocks smart modem 550 and can be implemented with executable control software stored on a non-transitory computer readable medium. The digital pulses that exitfunctional block 520 can be fed to a microcontroller GPIO pin that is capable of issuing interrupts on rising and falling edges of a signal. - For example,
FIGS. 7-9 are timing diagrams that depict the processing involved infunctional block 530. Exemplary embodiments disclosed herein can employ HART FSK signals, and HART FSK signals can consist of both 1200 Hz and 2200 Hz signals. Accordingly,FIG. 7 is a timing diagram for a 1200 Hz signal, andFIG. 8 is a timing diagram for a 2200 Hz signal. -
Functional block 530 can execute various steps for each of the 1200 Hz and 2200 Hz signal. For example, first, a GPIO hardware interrupt can trigger an ISR (Interrupt Service Routine) at edge rising a. Then, a first variable can be updated with a state of the input waveform. - When the hardware interrupt triggers the ISR, a timer, for example, a timer located inside hardware associated with the ISR, can be set to predetermined delay time d and be started. In exemplary embodiments that employ HART FSK signals, delay time d can be approximately 578.7 μs. After expiration of delay time d, the timer can trigger the ISR. Then, edge a can be reproduced as edge a′, and a second variable can be updated with a state of the delayed waveform.
- The first variable corresponding to the state of the input waveform can be XORed with the second variable corresponding to the state of the delayed waveform. Then, the output of the XOR can be stored as a third variable.
- The process described above can be repeated for falling edge b. For example, a GPIO hardware interrupt can also trigger an ISR at falling edge b. Then, a fourth variable can be updated with a state of the input waveform.
- When the hardware interrupt triggers the ISR, the ISR timer can be set to predetermined delay time d and be started. After expiration of delay time d, the timer can trigger the ISR. Then, edge b can be reproduced as edge b′, and a fifth variable can be updated with a state of the delayed waveform.
- The fourth variable corresponding to the state of the input waveform can be XORed with the fifth variable corresponding to the state of the delayed waveform. Then, the output of the XOR can be stored as a sixth variable.
- In embodiments disclosed herein, if the timer has been set to delay time d for rising edge a and delay time d has not yet expired before another rising edge interrupt is detected, then edge a can be reproduced as edge a′, and the second variable can be updated with the state of the delayed waveform, even though the timer has not yet triggered the ISR. Then, when the GPIO hardware interrupt triggers the ISR at rising edge a, the first variable can be updated with the state of the input waveform, and the ISR timer can be set to delay time d.
- Similarly, if the timer has been set to delay time d for falling edge b and delay time d has not yet expired before another falling edge interrupt is detected, then edge b can be reproduced as edge b′, and the fifth variable can be updated with the state of the delayed waveform, even though the timer has not yet triggered the ISR. Then, when the GPIO hardware interrupt triggers the ISR at falling edge b, the fourth variable can be updated with the state of the input waveform, and the ISR timer can be set to delay time d.
- As seen in
FIG. 7 , when the input waveform is a 1200 Hz signal, the XORed output offunctional block 530 can vary betweenlogic 1 andlogic 0. However, the XORed output is different when the input waveform is a 2200 Hz signal. For example, as seen inFIG. 8 , when the input waveform is a 2200 Hz signal, the XORed output offunctional block 530 can belogic 0 at all times. - As further seen in
FIG. 8 , the delayed waveform of a 2200 Hz signal is not delayed by delay time d. Instead, the delayed waveform is terminated before delay time d is completed. The vertical lines VL1, VL2 inFIG. 8 illustrate that the time delay between a and a′ and between b and b′ is less than delay time d. - In accordance with the above,
FIG. 9 is a timing diagram for signal conversion. As seen inFIG. 9 , a higher frequency is converted tologic 0 and a lower frequency is converted to a train of pulses. - Output from
functional block 530 can be fed tofunctional block 540, which can use time delay logic to convert the train of pulses from the XORed output tologic 1.FIG. 10 is a timing diagram that depicts the processing involved infunctional block 540, and, as seen inFIG. 10 , at a second rising edge, the output waveform logic can be made high. - As further seen in
FIG. 10 , a second falling edge of the train of pulses can trigger a time delay t and keep the output waveform logic high. For example, in embodiments that employ HART FSK signals, the time delay t can be approximately 578.7 μs. If another falling edge is detected before time delay t has expired, the timer can be refreshed and reset to time delay t. When no pulses and/or rising or falling edges are detected after expiration of time delay t, the output waveform logic can be made low. - A HART FSK signal can represent 1200 bps UART (Universal Asynchronous Receiver Transmitter) data communication. Accordingly, in exemplary embodiments, the output of
functional block 540 can be fed to a UART of a microcontroller. For example, the output offunctional block 540, which is also the output of thesmart modem 550 and of thedemodulator 500, can be fed into themodulator 600 after processing the data using executable control software stored on a non-transitory computer readable medium. - As seen in
FIG. 6 , the HART FSK signal can be processed through themodulator 600 and pass through threefunctional blocks functional block 610 can select the FSK signal frequency. In some embodiments, thefunctional block 610 can receive information with instructions for when to switch the frequency of the FSK signal. -
Functional block 620 can then pulse-width modulate the signal corresponding to the sine frequencies of the signal. Finally,functional block 630 can include a 2nd order passive LPF through which the signal can pass to remove high frequency switching noise. - The
smart modem 500 in accordance with embodiments disclosed herein can be implemented with executable control software stored on a non-transitory computer readable medium. For example, as seen inFIG. 11 , the non-transitory computer readable medium can be stored on a microcontroller that is implemented in an application processor. Alternatively, as seen inFIG. 12 , the non-transitory computer readable medium can be stored on a microcontroller that is implemented with as a stand-alone modem. - Although a few embodiments have been described in detail above, other modifications are possible. For example, the logic flows described above do not require the particular order described, or sequential order, to achieve desirable results. Other steps may be provided, or steps may be eliminated, from the described flows, and other components may be added to, or removed from, the described systems. Other embodiments may be within the scope of the invention.
- From the foregoing, it will be observed that numerous variations and modifications may be effected without departing from the spirit and scope of the invention. It is to be understood that no limitation with respect to the specific system or method described herein is intended or should be inferred. It is, of course, intended to cover all such modifications as fall within the sprit and scope of the invention.
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9225568B1 (en) * | 2014-12-09 | 2015-12-29 | Freescale Semiconducotr, Inc. | FSK demodulator |
US9281978B1 (en) * | 2014-08-23 | 2016-03-08 | Smart Embedded Systems, Inc. | Energy efficient highway addressable remote transducer soft modem |
US10200163B1 (en) * | 2017-08-22 | 2019-02-05 | Texas Instruments Incorporated | Small and seamless carrier detector |
US20190268038A1 (en) * | 2016-10-13 | 2019-08-29 | Endress+Hauser SE+Co. KG | Method for transferring data between an automation field device and a communication box |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4716376A (en) * | 1985-01-31 | 1987-12-29 | At&T Information Systems Inc. | Adaptive FSK demodulator and threshold detector |
US5450032A (en) * | 1993-03-12 | 1995-09-12 | Matsushita Electric Industrial Co., Ltd. | FSK data demodulator using mixing of quadrature baseband signals |
US6035177A (en) * | 1996-02-26 | 2000-03-07 | Donald W. Moses | Simultaneous transmission of ancillary and audio signals by means of perceptual coding |
US6937666B2 (en) * | 2002-12-20 | 2005-08-30 | Bridgewave Communications, Inc. | Wideband digital radio with transmit modulation cancellation |
US20070053466A1 (en) * | 2005-09-08 | 2007-03-08 | Klostermann Daniel J | Frequency shift keying demodulation technique |
US7372914B2 (en) * | 2000-11-16 | 2008-05-13 | Invensys Systems, Inc. | Control system methods and apparatus for inductive communication across an isolation barrier |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8290030B2 (en) | 2007-12-28 | 2012-10-16 | Spectrum Controls, Inc. | Micro-controller with FSK modem |
-
2012
- 2012-11-16 US US13/678,954 patent/US8750427B1/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4716376A (en) * | 1985-01-31 | 1987-12-29 | At&T Information Systems Inc. | Adaptive FSK demodulator and threshold detector |
US5450032A (en) * | 1993-03-12 | 1995-09-12 | Matsushita Electric Industrial Co., Ltd. | FSK data demodulator using mixing of quadrature baseband signals |
US6035177A (en) * | 1996-02-26 | 2000-03-07 | Donald W. Moses | Simultaneous transmission of ancillary and audio signals by means of perceptual coding |
US7372914B2 (en) * | 2000-11-16 | 2008-05-13 | Invensys Systems, Inc. | Control system methods and apparatus for inductive communication across an isolation barrier |
US6937666B2 (en) * | 2002-12-20 | 2005-08-30 | Bridgewave Communications, Inc. | Wideband digital radio with transmit modulation cancellation |
US20070053466A1 (en) * | 2005-09-08 | 2007-03-08 | Klostermann Daniel J | Frequency shift keying demodulation technique |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9281978B1 (en) * | 2014-08-23 | 2016-03-08 | Smart Embedded Systems, Inc. | Energy efficient highway addressable remote transducer soft modem |
US9225568B1 (en) * | 2014-12-09 | 2015-12-29 | Freescale Semiconducotr, Inc. | FSK demodulator |
US20190268038A1 (en) * | 2016-10-13 | 2019-08-29 | Endress+Hauser SE+Co. KG | Method for transferring data between an automation field device and a communication box |
US10840973B2 (en) * | 2016-10-13 | 2020-11-17 | Endress+Hauser SE+Co. KG | Method for transferring data between an automation field device and a communication box |
US10200163B1 (en) * | 2017-08-22 | 2019-02-05 | Texas Instruments Incorporated | Small and seamless carrier detector |
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