JP3999039B2 - Difference frequency detection circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a difference frequency detection method and a difference frequency detection circuit for detecting a difference frequency between two digital input signals.
[0002]
[Prior art]
In general, when a high frequency signal is detected, in order to increase its sensitivity, it is often converted to an intermediate frequency and processed. At this time, if an attempt is made to perform synchronous detection at an intermediate frequency, an intermediate frequency that is inaccurate and coherent with a high-frequency signal or a local oscillation frequency is required. Here, in general, a multiplier is used to generate an intermediate frequency signal of a difference between two high frequency signals having a high frequency.
[0003]
Further, in a frequency band using a digital circuit, an exclusive OR circuit is used to generate an intermediate frequency signal of the difference from two digital signals.
[0004]
In any circuit that generates these intermediate frequency signals, a low-pass filter or a band-pass filter, an amplifier, a limiter, and the like are generally used after a multiplier and an exclusive OR circuit.
[0005]
[Problems to be solved by the invention]
However, various frequency components are included in the output of the multiplier and the exclusive OR circuit, and there is a problem that it is not easy to reliably extract only the difference frequency.
[0006]
Also, in any circuit that generates these intermediate frequency signals, the bandpass filter must be redesigned in order to change the center frequency of the bandpass filter according to the difference frequency or to make the selectivity severe. was there.
[0007]
An object of the present invention is to provide a difference frequency detection circuit that can reliably extract the difference frequency regardless of the frequencies of two digital input signals.
[0008]
[Means for Solving the Problems]
The present invention is directed to a difference frequency detection circuit that detects a difference frequency between two digital input signals.
[0009]
In the present invention, when detecting the difference frequency between two digital input signals, it is detected that two adjacent rising edges of the other input signal are inserted between two adjacent rising edges of one input signal. 1 pulse is emitted.
[0010]
That is , when two digital input signals are input, the repetition time or period of the signal with the higher frequency is shorter than the repetition period of the signal with the lower frequency. There is always a time when two adjacent rising edges of the higher frequency signal are between two adjacent rising edges of the lower signal. If one pulse is output at this time, the repetition frequency of the output pulse matches the difference frequency between the two digital input signals.
[0011]
If the difference frequency is detected in this way, the difference frequency can be reliably extracted regardless of the frequencies of the two digital input signals.
[0012]
The present invention provides a difference frequency detection circuit for detecting a difference frequency between two digital input signals by the above method, a rising edge extraction circuit for extracting only the rising edge of a digital input signal, a lower bit counter and an upper bit counter. This is realized by using a 2-bit up / down counter.
[0013]
A difference frequency detection circuit of claim 1, two digital input signal is input to the rising edge extraction circuit, the up-down two bits each rising edge signal as the up input and the down input from the rising edge extraction circuit Input to the counter, the output of the upper bit counter of the up / down counter is given as a set input to the lower bit counter and the reset input to the upper bit counter, and the output of the upper bit counter is outputted as a difference frequency output It has become.
[0014]
Such a difference frequency detection circuit can reliably extract the difference frequency regardless of the frequencies of the two digital input signals.
[0015]
The difference frequency detecting circuit according to claim 2, and 2 circuit utilizing the difference frequency detection circuit according to claim 1, namely a first difference frequency detecting circuit a difference frequency detection circuit of claim 1 Two circuits are used as the second difference frequency detection circuit, and a signal having an output waveform duty of 50% is obtained. In this case, two digital input signals are input as they are to the first difference frequency detection circuit, one of the two digital input signals is inverted and the other is input as it is to the second difference frequency detection circuit. , the output signal of the first, second difference frequency detection circuit to have a phase difference of 180 degrees. If these signals are input to the set / reset circuit as a set input and a reset input, and the output of the set / reset circuit is output, a signal having a difference frequency between the two digital input signals can be obtained as an output waveform with a duty of 50%. .
[0016]
DETAILED DESCRIPTION OF THE INVENTION
1 to 3 show a first example of an embodiment of a difference frequency detection circuit according to the present invention, FIG. 1 is a circuit diagram of the difference frequency detection circuit of this example, and FIG. 2 is shown in FIG. The rising edge signals of the two digital input signals in the difference frequency detection circuit, operation waveform diagrams of the lower bit counter and the upper bit counter, and FIG. 3 are operation waveform diagrams of the respective parts of the difference frequency detection circuit of this example.
[0017]
As shown in FIG. 1, the difference frequency detection circuit of this example includes an up input terminal U to which a digital input signal having a high frequency is input as an up input, and a digital input signal having a low frequency, out of two digital input signals. A down input terminal D that is input as a down input. The up input terminal U and the down input terminal D are connected to first and second rising edge extraction circuits 1A and 1B that extract only the rising edge of the input digital input signal. The first and second rising edge extraction circuits 1A and 1B are formed by AND circuits 2A and 2B and knot circuits 3A and 3B. That is, the signals input to the up input terminal U and the down input terminal D are delayed in time directly via one of the input terminals of the corresponding AND circuits 2A and 2B and the other input terminal via the knot circuits 3A and 3B. It is designed to be input. As a result, the AND circuits 2A and 2B rise when an input signal from the corresponding up input terminal U or down input terminal D is input, and immediately fall after a delay time via the knot circuits 3A and 3B, and only the edge of the input signal. Will be taken out.
[0018]
The rising edge signals of the two digital input signals output from the first and second rising edge extraction circuits 1A and 1B are input to the 2-bit up / down counter 4 as an up input and a down input. ing. The 2-bit up / down counter 4 includes a lower bit counter 4A and an upper bit counter 4B.
[0019]
The lower bit counter 4A includes an OR circuit 5 that receives the rising edge signals of the two digital input signals output from the first and second rising edge extraction circuits 1A and 1B, and the output of the OR circuit 5 is T It is composed of a T flip-flop 6 input to a terminal.
[0020]
The upper bit counter 4B includes an AND circuit 7 that receives the output of the first rising edge extraction circuit 1A and the output of the Q terminal of the T flip-flop 6, the output of the second rising edge extraction circuit 1B, An AND circuit 8 that receives the output of the NQ terminal of the flip-flop 6, an OR circuit 9 that receives the outputs of the AND circuits 7 and 8, and a T flip-flop in which the output of the OR circuit 9 is input to the T terminal And 10.
[0021]
Each of the T flip-flops 6 and 10 operates so that the Q output is inverted every time a trigger input enters the T terminal. The NQ output is an inverted output of the Q output.
[0022]
In the 2-bit up / down counter 4, the output of the Q terminal of the T flip-flop 10 in the upper bit counter 4B is given as a set input to the S terminal of the T flip-flop 6 in the lower bit counter 4A and the T bit in the upper bit counter 4B. The R terminal of the flip-flop 10 is given as a reset input, and the output of the Q terminal of the T flip-flop 10 in the upper bit counter 4B is output from the output terminal Out as a difference frequency output.
[0023]
U, D, 4A, 4B in FIG. 2 are the rising edge signals (U, D) of two digital input signals in the difference frequency detection circuit shown in FIG. 1, and the Q terminal of the T flip-flop 6 in the lower bit counter 4A. FIG. 10 is an operation waveform diagram of the Q terminal of the T flip-flop 10 in the upper bit counter 4B.
[0024]
U, D, U ′, D ′, a, b, c, d, e, f, and Out in FIG. 3 are output waveform diagrams of the respective units in FIG.
[0025]
In the difference frequency detection method of this example, when two digital input signals are input as shown in U and D of FIG. 3, the repetition time, that is, the period of the U signal with the higher frequency is D with the lower frequency. Since it is shorter than the repetition period of the signal, the frequency is high between two adjacent rising edges of the D2 and D3 signals of the lower frequency signal D as shown in the figure in some repetitions. There is always a time when two rising edges of the U3 and U4 adjacent signals of the other signal U enter. At this time, when the output of one pulse as shown by Out, repetition frequency of the output pulse Out the two digital input signals U, the frequency of the D _f u, difference frequency _{f d (f} u -f _d ).
[0026]
The operation of the difference frequency detection circuit shown in FIG. 1 that implements such a difference frequency detection method will be described with reference to FIGS.
[0027]
When two digital input signals of rectangular waves indicated by U and D in FIG. 3 are input to the up input terminal U and the down input terminal D of the difference frequency detection circuit shown in FIG. 1, the outputs of the AND circuits 2A and 2B Are edge signals indicated by U ′ and D ′ in FIG.
[0028]
These edge signals are input to the lower bit counter 4A and the upper bit counter 4B.
[0029]
When these edge signals are input to the OR circuit 5 of the lower-order bit counter 4A, the output becomes a in FIG.
[0030]
The output of FIG. 3 a is input to the T terminal of the T flip-flop 6. Upon receiving this input, the T flip-flop 6 outputs the output shown in FIG. 3b from its Q terminal, and outputs the output shown in FIG. 3d from its NQ terminal. The output shown in d of FIG. 3 is an output obtained by inverting the output shown in b of FIG.
[0031]
The outputs shown in FIGS. 3b and 3d are input to the AND circuits 7 and 8 of the upper bit counter 4B together with the edge signals indicated by U ′ and D ′ in FIG. 3 as described above. As a result, the AND circuits 7 and 8 output outputs indicated by c and e in FIG.
[0032]
When these outputs are input to the OR circuit 9, the OR circuit 9 outputs the output indicated by f in FIG.
[0033]
The output of the OR circuit 9 shown in FIG. 3 f is input to the T terminal of the T flip-flop 10. Upon receiving this input, the T flip-flop 10 outputs the output shown at Out in FIG. 3 from its Q terminal.
[0034]
The output shown at Out in FIG. 3 from the T flip-flop 10 is given as a set input to the S terminal of the T flip-flop 6 and as a reset input to the R terminal of the T flip-flop 10.
[0035]
When a set input is given to the S terminal of the T flip-flop 6, the outputs of the Q terminal and the NQ terminal of the T flip-flop 6 change as shown in FIGS.
[0036]
Further, when a reset input is given to the R terminal of the T flip-flop 10, it is output from the Q terminal of the T flip-flop 10, and the output shown at Out in FIG. 3 immediately changes from “1” to “0”.
[0037]
In the operation as described above, the outputs of the Q terminals of the T flip-flops 6 and 10 of the lower bit counter 4A and the upper bit counter 4B are “00” → “01” → “10” with respect to the input from the up input terminal U. Change. However, when the output becomes “10”, the T flip-flops 6 and 10 have feedback of set and reset, so that they are immediately “01” and never “11”.
[0038]
Here, the 2-digit numerical value is a binary notation in which the 1's digit is represented by the lower bit counter 4A and the 10's digit is represented by the upper bit counter 4B.
[0039]
Further, the outputs of the Q terminals of the T flip-flops 6 and 10 of the lower bit counter 4A and the upper bit counter 4B are “10” → “01” → “00” → “11” with respect to the input from the down input terminal D. However, when the output becomes “11”, the T flip-flops 6 and 10 have set / reset feedback, so they immediately become “01”, and the time to become “11” is short.
[0040]
In the above example, the up input terminal U and the down input terminal D have been described as having an input signal having a higher frequency than the down input terminal D for the up input terminal U, but the frequencies of the two input signals are approximate. The input is alternately input to the up input terminal U and the down input terminal D, and reciprocates between “00” and “01”. If the input to the up input terminal U has a higher frequency, there are times when pulses continuously enter from the up input terminal U. At this time, it becomes “10” and immediately returns to “01”. Therefore, the output Out from the T flip-flop 10 outputs one pulse.
[0041]
After that, it reciprocates between “00” and “01”, and one pulse is output from the T flip-flop 10 at the time of continuous input from the up input terminal U.
[0042]
The frequency of this pulse output is equal to the difference between the frequencies of the two digital input signals entering the up input terminal U and the down input terminal D.
[0043]
Conversely, when the frequency of the digital input signal entering the down input terminal D is high, the frequency of the pulse output output from the output Out is equal to half the difference between the input frequencies of the up input terminal U and the down input terminal D. Therefore, in order to correctly output the difference frequency, it is necessary to input a high frequency signal to the input of the up input terminal U.
[0044]
4 and 5 show a second example of the embodiment of the differential frequency detection circuit according to the present invention. FIG. 4 is a circuit diagram of the differential frequency detection circuit of this example, and U1, D1, Out1 in FIG. , U 2, D 2, Out 2, Out 3 are operation waveform diagrams of each part of the differential frequency detection circuit shown in FIG.
[0045]
As shown in FIG. 4, the difference frequency detection circuit of this example has two difference frequency detection circuits shown in FIG. 1, a first difference frequency detection circuit 11 (1) and a second difference frequency detection circuit 11 ( 2), two digital input signals from the input terminals A and B are input to the U1 terminal and D1 terminal of the first differential frequency detection circuit 11 (1), and one of the two digital input signals is a knot circuit. 12 and the other is input to the U2 terminal and D2 terminal of the second difference frequency detection circuit 11 (2) as it is, and the first and second difference frequency detection circuits 11 (1) and 11 (2) Outputs of the Out1 terminal and Out2 terminal are respectively input as a set input to the set input terminal S of the set reset circuit 13 and as a reset input to the reset input terminal R, and the difference frequency output from the Q terminal of the set reset circuit 13 is 50% duty. Output in waveform It has a configuration that.
[0046]
FIG. 5 shows operation waveforms of the respective parts U1, D1, Out1, U2, D2, Out2, Out3 of this difference frequency detection circuit.
[0047]
That is, when a digital input signal indicated by U1 and D1 (frequency is higher than D1 in U1) in FIG. 5 is input to the U1 terminal and D1 terminal of the first differential frequency detection circuit 11 (1), The output of the difference frequency between U1 and D1 shown in Out1 of FIG. 5 is obtained from the Out1 terminal of the first difference frequency detection circuit 11 (1).
[0048]
Similarly, when a digital input signal indicated by U2 and D2 in FIG. 5 (frequency is higher than D2 in U2) is input to the U2 terminal and D2 terminal of the second differential frequency detection circuit 11 (2). The output of the difference frequency between U2 and D2 shown in Out2 of FIG. 5 is obtained from the Out2 terminal of the second difference frequency detection circuit 11 (2). Here, the signal U2 is a signal obtained by inverting the signal U1, and the signal D2 is the same signal as the signal D1.
[0049]
The outputs of the Out1 and Out2 terminals of the first and second differential frequency detection circuits 11 (1) and 11 (2) are reset to the set input terminal S and to the reset input terminal R of the set / reset circuit 13, respectively. When input as an input, the output of the difference frequency between the two digital input signals input to the input terminals A and B from the Q terminal of the set / reset circuit 13 is 50% duty as indicated by Out3 in FIG. Output in waveform.
[0050]
【The invention's effect】
According to the first aspect of the present invention, when it is detected that two adjacent rising edges of the other input signal have entered between two adjacent rising edges of one input signal, one pulse is output. Therefore, the difference frequency can be reliably extracted regardless of the frequencies of the two digital input signals .
[0051]
According to the invention described in claim 2, the difference frequency detecting circuit according to the invention described in claim 1 using two circuits, the phase difference of the output pulse has a configuration such that 180 degrees, 2 Regardless of the frequency of the two digital input signals, it is possible to reliably extract the difference frequency and output a waveform with a duty of 50%.
[0052]
Further, according to these inventions, the difference frequency can be surely extracted regardless of the frequencies of the two digital input signals, so that a new design of the band pass filter for each of the input frequency and the difference frequency as in the prior art. The effects of these inventions are great.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first example of an embodiment of a differential frequency detection circuit according to the present invention.
2 is an operation waveform diagram of rising edge signals of two digital input signals, a lower bit counter, and an upper bit counter in the difference frequency detection circuit shown in FIG. 1;
FIG. 3 is an operation waveform diagram of each part of the difference frequency detection circuit of this example.
FIG. 4 is a circuit diagram showing a second example of an embodiment of a differential frequency detection circuit according to the present invention.
5 is an operation waveform diagram of each part of the difference frequency detection circuit shown in FIG. 4; U1, D1, Out1, U2, U2, D2, Out2, and Out3.
[Explanation of symbols]
1A, 1B First and second rising edge extraction circuits 2A, 2B AND circuit 3A, 3B Not circuit 4 2-bit up / down counter 4A Lower bit counter 4B Upper bit counter 5 OR circuit 6 T flip-flop 7, 8 AND circuit 9 OR circuit 10 T flip-flop 11 (1) 1st difference frequency detection circuit 11 (2) 2nd difference frequency detection circuit 12 Not circuit 13 Set reset circuit

Claims (2)

A rising edge extraction circuit that extracts only rising edges of two digital input signals, and a 2-bit up / down counter that uses the rising edge signals of the two digital input signals output from the rising edge extraction circuit as up inputs and down inputs. The 2-bit up / down counter has a lower bit counter and an upper bit counter, and the output of the upper bit counter is given as a set input to the lower bit counter and as a reset input to the upper bit counter A difference frequency detection circuit, wherein the output of the upper bit counter is provided as a difference frequency output. The difference frequency detection circuit according to claim 1 is used as two circuits, a first difference frequency detection circuit and a second difference frequency detection circuit, and two digital input signals are input to the first difference frequency detection circuit. , One of the two digital input signals is inverted, and the other is directly input to the second difference frequency detection circuit, and the outputs of the first and second difference frequency detection circuits are respectively set to the set reset circuit. A difference frequency detection circuit which is inputted as an input and a reset input and is configured to output an output of the set reset circuit as a difference frequency output.

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