CN112491425A - Flexible configurable radio frequency hardware decoder - Google Patents
Flexible configurable radio frequency hardware decoder Download PDFInfo
- Publication number
- CN112491425A CN112491425A CN202011424099.XA CN202011424099A CN112491425A CN 112491425 A CN112491425 A CN 112491425A CN 202011424099 A CN202011424099 A CN 202011424099A CN 112491425 A CN112491425 A CN 112491425A
- Authority
- CN
- China
- Prior art keywords
- level
- module
- counting
- decoding
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001914 filtration Methods 0.000 claims abstract description 22
- 230000001360 synchronised effect Effects 0.000 claims abstract description 17
- 230000000630 rising effect Effects 0.000 claims description 8
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- LHMQDVIHBXWNII-UHFFFAOYSA-N 3-amino-4-methoxy-n-phenylbenzamide Chemical compound C1=C(N)C(OC)=CC=C1C(=O)NC1=CC=CC=C1 LHMQDVIHBXWNII-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
Abstract
The invention relates to a flexible and configurable radio frequency hardware decoder. The invention aims to provide a flexible and configurable radio frequency hardware decoder which is suitable for multiple coding formats, can quickly switch different coding formats and has high decoding speed. The technical scheme of the invention is as follows: the decoder includes: the filtering module is used for filtering the input signal according to the configured high and low level burr width thresholds; the counting module is used for respectively counting the continuous periods of the high level and the low level of the signal filtered by the filtering module under the driving of a clock signal to obtain a high level count value and a low level count value; and the bit decoding module is used for carrying out bit decoding according to the configured parameter I required by decoding and the high and low level counting values acquired from the counting module, and judging the decoded data to obtain a synchronous head, a bit 0 and a bit 1. The invention is suitable for the field of industrial control, and particularly relates to a wireless remote control and wireless alarm.
Description
Technical Field
The invention relates to a flexible and configurable radio frequency hardware decoder. The wireless remote control alarm is suitable for the field of industrial control, and particularly relates to a wireless remote control and wireless alarm.
Background
In life, more and more devices, electrical appliances, vehicles and the like adopt a remote control mode, and great convenience is provided for life of people. Among them, the radio frequency communication mode is widely applied to the fields of industrial control and the like because of the characteristics of non-directivity, long transmission distance, strong penetrating power and the like.
The radio frequency is a mode for controlling equipment through information transmission of wireless signals, and after the radio frequency signals are received, the radio frequency signals can instruct or drive corresponding equipment to complete various operations. A common rf control system includes a transmitter and a receiver. The transmitter is usually a remote control, and the control information is coded and modulated and transmitted according to a specific format. The receiver needs to receive, demodulate and decode.
Currently, the coding formats used by the transmitters are different, which makes it difficult for a receiver to adapt to the various coding formats. The existing receiver solution is only suitable for a specific coding format, cannot analyze control information in different formats, and mostly adopts a software decoding mode, so that the receiver has the defects of small application range, high replacement cost for different coding formats, low decoding speed and high power consumption. Meanwhile, the remote controller and the alarm have various use environments and need high stability.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the existing problems, the flexible and configurable radio frequency hardware decoder which is suitable for various encoding formats, can rapidly switch different encoding formats and has high decoding speed is provided.
The technical scheme adopted by the invention is as follows: a flexibly configurable radio frequency hardware decoder, characterized in that,
the method comprises the following steps:
the filtering module is used for filtering the input signal according to the configured high and low level burr width thresholds;
the counting module is used for respectively counting the continuous periods of the high level and the low level of the signal filtered by the filtering module under the driving of a clock signal to obtain a high level count value and a low level count value;
the bit decoding module is used for carrying out bit decoding according to the configured parameter I required by decoding and the high and low level counting values acquired from the counting module, and judging the decoded data to obtain a synchronous head, a bit 0 and a bit 1;
the command shift register is used for acquiring the result decoded by the bit decoding module and storing the result as a command;
the command decoding/interruption generating module is used for decoding the command in the command shift register according to the configured parameter II required by decoding, and storing the command into the register module and generating interruption when the command is a legal command;
and the register module is used for storing the high and low level burr width threshold parameters written by the CPU and parameters I and II required by decoding.
The filtering module is configured to:
counting the high level of an input signal through an internal clock, starting counting on the rising edge of the input signal, outputting to be the high level when the count is larger than the high level burr width threshold, and outputting to be the low level after the high level still maintains the high level burr width after the falling edge of the input signal;
after high-level burrs of an input signal are filtered, the low level of the signal is counted through an internal clock, counting is started at the falling edge of the signal, when the counting is larger than the threshold value of the width of the low-level burrs, the low level is output, and the low level is still kept at the width of the low-level burrs after the rising edge of the signal and then is output to be changed into the high level.
The counting module is used for:
inverting the filtered input signal; delaying for two beats under the drive of a clock, accumulating and counting by a low-level counter under the low level of a first beat delay signal, and resetting the low-level counter when the delay signal is at the high level; and when the second beat delay signal is low and the first beat delay signal is high, resetting the high level counter.
The parameters I required by decoding comprise identification 0 highest multiple, identification 0 lowest multiple, identification 1 highest multiple, identification 1 lowest multiple, synchronization highest multiple and synchronization lowest multiple.
The bit decoding module is configured to:
respectively calculating the products of the high-level count value and the highest synchronous multiple and the lowest synchronous multiple; comparing the magnitude relation between the low level count value and the product of the two values; if the low level count value is between the two products, then generating a synchronous indication signal;
respectively calculating the products of the low-level count value and the highest multiple and the lowest multiple of the identification 1; comparing the magnitude relation between the high level counting value and the two products; if the high level count value is between the two products, generating a bit 1 indication signal;
respectively calculating the products of the high-level count value and the highest multiple and the lowest multiple of the identification 0; comparing the magnitude relation between the low level count value and the product of the two values; if the low level count value is between the two products, generating a bit 0 indication signal;
under the clock driving, at the rising edge of the input signal, the effective bit data is stored in the shift register.
And the parameter II required by decoding comprises an alarm encoding and an alarm encoding valid bit.
The invention has the beneficial effects that: the invention realizes the radio frequency hardware decoding which can be configured, stable, fast and has low power consumption by the mutual cooperation of the filtering module, the counting module, the bit decoding module, the command decoding/interruption generating module and the like.
Drawings
Fig. 1 is a schematic structural diagram of the embodiment.
Fig. 2 is a schematic structural diagram of a filtering module in an embodiment.
Fig. 3 is a schematic structural diagram of a counting module in the embodiment.
Fig. 4 is a schematic structural diagram of a bit decoding module in an embodiment.
FIG. 5 is a diagram illustrating a register module according to an embodiment.
Detailed Description
This embodiment is a flexible and configurable rf hardware decoder, comprising: the device comprises a filtering module, a counting module, a bit decoding module, a command shift register, a command decoding/interrupt generating module, a register module and the like.
The filtering module in this embodiment includes a high-level burr filtering module and a low-level burr filtering module, and is configured to filter the input signal according to the configured high-level and low-level burr width thresholds.
In this example, the high-level glitch filtering module counts the high level of the input signal through an internal clock, starts counting on the rising edge of the input signal, outputs the high level when the count is greater than the threshold value of the width of the high-level glitch, and outputs the low level after the high level still maintains the width of the high-level glitch after the falling edge of the input signal.
The low-level burr filtering module is used for counting the low level of the input signal after the input signal passes through the high-level burr filtering module to filter the high-level burr, counting is started at the falling edge of the signal, when the counting is larger than the width threshold value of the low-level burr, the low level is output, and the low level is still kept at the low-level burr width after the rising edge of the signal and then output to be the high level.
The counting module in this embodiment includes a high level counting module and a low level counting module, and is configured to count the duration periods of the high and low levels of the signal filtered by the filtering module, respectively, under the drive of the clock signal, and obtain high and low level count values.
In this example, the counting module inverts the input signal; then two beats are delayed under the drive of a clock; the low level counting module accumulates and counts under the low level of the first beat delay signal, and the low level counting module is cleared when the delay signal is at the high level; and the high-level counting module accumulates and counts under the high level of the second beat delay signal, and clears the high-level counting module when the second beat delay signal is low and the first beat delay signal is high.
The bit decoding module in this embodiment is configured to perform bit decoding according to the configured parameter i required for decoding and the high and low level count values obtained from the counting module, and determine decoded data to obtain a synchronization header, a bit 0, and a bit 1.
The bit decoding module in the embodiment comprises a product module of a high level count value and the upper limit multiple of a 'synchronous head', a product module of the high level count value and the lower limit multiple of the 'synchronous head', a numerical value comparison module and a synchronous indication signal generation module, wherein the product module of the high level count value and the upper limit multiple and the lower limit multiple of the 'synchronous head' respectively calculates the product of the high level count value and the highest multiple and the lowest multiple of the synchronization; comparing the magnitude relation between the low level count value and the two products by a numerical value comparison module; if the low level count value is between the two products, the synchronous indication signal is generated by the synchronous indication signal generation module.
The Bit decoding module in the embodiment further comprises a product module of a low level count value and an upper limit multiple of Bit '1', a product module of a low level count value and a lower limit multiple of Bit '1', a numerical value comparison module and a Bit '1' indication signal generation module, wherein the product module of the low level count value and the upper and lower limit multiples of Bit '1' is used for respectively calculating the product of the low level count value and the highest multiple of identification 1 and the lowest multiple of identification 1; comparing the magnitude relation between the level count value and the two products by a numerical comparison module; if the high level count value is between the two products, a Bit 1 indication signal is generated by the Bit '1' indication signal generation module.
The Bit decoding module in the embodiment further comprises a product module of a high level count value and an upper limit multiple of Bit '0', a product module of the high level count value and a lower limit multiple of Bit '0', a numerical value comparison module and a Bit '0' indication signal generation module, wherein the product module of the high level count value and the upper limit multiple and the lower limit multiple of Bit '0' respectively calculates the product of the high level count value and the highest multiple of identification 0 and the lowest multiple of identification 0; comparing the magnitude relation between the low level count value and the two products by a numerical value comparison module; if the low level count value is between the two products, a Bit 0 indication signal is generated by the Bit 0 indication signal generation module.
In this example, the bit decoding module stores the command shift register data after identifying the valid bit data 0,1, and stores the command shift register data into the register module after identifying the synchronization bit.
The command decoding/interrupt generating module in the embodiment decodes the command of the command shift register according to the configured parameters (the alarm code and the alarm code valid bit), stores the command into the register module and generates the interrupt when the command is a configured legal command.
The register module stores configuration parameters (high level burr width, low level burr width, identification 0 highest multiple, identification 0 lowest multiple, identification 1 highest multiple, identification 1 lowest multiple, synchronous highest multiple, synchronous lowest multiple, alarm coding effective bit and the like) required by decoding and a command obtained by decoding, such as a filtering module, a bit decoding module, a command decoding/interruption generating module and the like. The CPU reads and writes through an APB bus, and the specific implementation method comprises the following steps: the APB interface module processes an APB bus according to an AMBA APB bus protocol, generates a read-write enabling signal and transmits an address and data signal to the decoding module; the decoding module analyzes various configuration data, receives radio frequency receiving data and waits to be read by a CPU.
Claims (6)
1. A flexibly configurable radio frequency hardware decoder, comprising:
the filtering module is used for filtering the input signal according to the configured high and low level burr width thresholds;
the counting module is used for respectively counting the continuous periods of the high level and the low level of the signal filtered by the filtering module under the driving of a clock signal to obtain a high level count value and a low level count value;
the bit decoding module is used for carrying out bit decoding according to the configured parameter I required by decoding and the high and low level counting values acquired from the counting module, and judging the decoded data to obtain a synchronous head, a bit 0 and a bit 1;
the command shift register is used for acquiring the result decoded by the bit decoding module and storing the result as a command;
the command decoding/interruption generating module is used for decoding the command in the command shift register according to the configured parameter II required by decoding, and storing the command into the register module and generating interruption when the command is a legal command;
and the register module is used for storing the high and low level burr width threshold parameters written by the CPU and parameters I and II required by decoding.
2. The flexibly-configurable radio frequency hardware decoder of claim 1, wherein the filtering module is configured to:
counting the high level of an input signal through an internal clock, starting counting on the rising edge of the input signal, outputting to be the high level when the count is larger than the high level burr width threshold, and outputting to be the low level after the high level still maintains the high level burr width after the falling edge of the input signal;
after high-level burrs of an input signal are filtered, the low level of the signal is counted through an internal clock, counting is started at the falling edge of the signal, when the counting is larger than the threshold value of the width of the low-level burrs, the low level is output, and the low level is still kept at the width of the low-level burrs after the rising edge of the signal and then is output to be changed into the high level.
3. The flexibly-configurable radio frequency hardware decoder of claim 1, wherein the counting module is configured to:
inverting the filtered input signal; delaying for two beats under the drive of a clock, accumulating and counting by a low-level counter under the low level of a first beat delay signal, and resetting the low-level counter when the delay signal is at the high level; and when the second beat delay signal is low and the first beat delay signal is high, resetting the high level counter.
4. The flexibly-configurable radio frequency hardware decoder as claimed in claim 1, wherein the parameters i required for decoding include identifying a 0 highest multiple, identifying a 0 lowest multiple, identifying a 1 highest multiple, identifying a 1 lowest multiple, a synchronization highest multiple and a synchronization lowest multiple.
5. The flexibly-configurable radio frequency hardware decoder of claim 4, wherein the bit decoding module is configured to:
respectively calculating the products of the high-level count value and the highest synchronous multiple and the lowest synchronous multiple; comparing the magnitude relation between the low level count value and the product of the two values; if the low level count value is between the two products, then generating a synchronous indication signal;
respectively calculating the products of the low-level count value and the highest multiple and the lowest multiple of the identification 1; comparing the magnitude relation between the high level counting value and the two products; if the high level count value is between the two products, generating a bit 1 indication signal;
respectively calculating the products of the high-level count value and the highest multiple and the lowest multiple of the identification 0; comparing the magnitude relation between the low level count value and the product of the two values; if the low level count value is between the two products, generating a bit 0 indication signal;
under the clock driving, at the rising edge of the input signal, the effective bit data is stored in the shift register.
6. The flexibly-configurable radio frequency hardware decoder according to claim 1, wherein the decoding-required parameters ii comprise an alarm code and an alarm code valid bit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011424099.XA CN112491425B (en) | 2020-12-08 | 2020-12-08 | Flexibly configurable radio frequency hardware decoder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011424099.XA CN112491425B (en) | 2020-12-08 | 2020-12-08 | Flexibly configurable radio frequency hardware decoder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112491425A true CN112491425A (en) | 2021-03-12 |
| CN112491425B CN112491425B (en) | 2024-02-27 |
Family
ID=74940807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011424099.XA Active CN112491425B (en) | 2020-12-08 | 2020-12-08 | Flexibly configurable radio frequency hardware decoder |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112491425B (en) |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1134066A (en) * | 1994-10-14 | 1996-10-23 | 国际商品机器公司 | Flash FM infrared modem |
| JPH09270777A (en) * | 1996-03-29 | 1997-10-14 | Nec Corp | Block synchronization circuit for reception data |
| US5784462A (en) * | 1995-08-28 | 1998-07-21 | Sanyo Electric Co., Ltd. | Digital signal receiver capable of receiving data encrypted and transmitted in online processing |
| EP1347609A1 (en) * | 2002-03-22 | 2003-09-24 | STMicroelectronics S.r.l. | Method and apparatus for decoding Manchester-encoded signals |
| US20060037059A1 (en) * | 2004-08-10 | 2006-02-16 | Ali Corporation | Method of blind channel searching and estimation using a fast fourier transform mechanism |
| US20070071036A1 (en) * | 2005-09-26 | 2007-03-29 | Symbol Technologies, Inc. | Method and apparatus for preamble synchronization in wireless radio frequency identification (RFID) systems |
| CN101201970A (en) * | 2007-10-23 | 2008-06-18 | 无锡市爱芯科微电子有限公司 | Self-adaptive decoding method for wireless remote control receiving chip |
| US20080292024A1 (en) * | 2007-05-22 | 2008-11-27 | Sang Joo Jun | Amplitude-shift-keying (ask) radio-frequency (rf) signal decoding device and method thereof |
| CN101571906A (en) * | 2009-06-02 | 2009-11-04 | 北京大学深圳研究生院 | Decoder and decoding method of RFID receiver |
| US20100122144A1 (en) * | 2008-11-07 | 2010-05-13 | Lg Electronics Inc. | Transmitting/receiving system and method of processing broadcast signal in transmitting/receiving system |
| CN101847200A (en) * | 2010-02-05 | 2010-09-29 | 谭洪舟 | Groove identification device of RFID (Radio Frequency Identification Device) label chip |
| CN105760800A (en) * | 2016-02-05 | 2016-07-13 | 大唐微电子技术有限公司 | Data decoding circuit and data decoding method |
| CN108551433A (en) * | 2018-06-27 | 2018-09-18 | 珠海市微半导体有限公司 | The decoding system and coding/decoding method of BMC codes |
-
2020
- 2020-12-08 CN CN202011424099.XA patent/CN112491425B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1134066A (en) * | 1994-10-14 | 1996-10-23 | 国际商品机器公司 | Flash FM infrared modem |
| US5784462A (en) * | 1995-08-28 | 1998-07-21 | Sanyo Electric Co., Ltd. | Digital signal receiver capable of receiving data encrypted and transmitted in online processing |
| JPH09270777A (en) * | 1996-03-29 | 1997-10-14 | Nec Corp | Block synchronization circuit for reception data |
| EP1347609A1 (en) * | 2002-03-22 | 2003-09-24 | STMicroelectronics S.r.l. | Method and apparatus for decoding Manchester-encoded signals |
| US20060037059A1 (en) * | 2004-08-10 | 2006-02-16 | Ali Corporation | Method of blind channel searching and estimation using a fast fourier transform mechanism |
| US20070071036A1 (en) * | 2005-09-26 | 2007-03-29 | Symbol Technologies, Inc. | Method and apparatus for preamble synchronization in wireless radio frequency identification (RFID) systems |
| US20080292024A1 (en) * | 2007-05-22 | 2008-11-27 | Sang Joo Jun | Amplitude-shift-keying (ask) radio-frequency (rf) signal decoding device and method thereof |
| CN101201970A (en) * | 2007-10-23 | 2008-06-18 | 无锡市爱芯科微电子有限公司 | Self-adaptive decoding method for wireless remote control receiving chip |
| US20100122144A1 (en) * | 2008-11-07 | 2010-05-13 | Lg Electronics Inc. | Transmitting/receiving system and method of processing broadcast signal in transmitting/receiving system |
| CN101571906A (en) * | 2009-06-02 | 2009-11-04 | 北京大学深圳研究生院 | Decoder and decoding method of RFID receiver |
| CN101847200A (en) * | 2010-02-05 | 2010-09-29 | 谭洪舟 | Groove identification device of RFID (Radio Frequency Identification Device) label chip |
| CN105760800A (en) * | 2016-02-05 | 2016-07-13 | 大唐微电子技术有限公司 | Data decoding circuit and data decoding method |
| CN108551433A (en) * | 2018-06-27 | 2018-09-18 | 珠海市微半导体有限公司 | The decoding system and coding/decoding method of BMC codes |
Non-Patent Citations (1)
| Title |
|---|
| 陶康: "长距离射频身份识别装置设计", 《中国优秀硕士学位论文全文数据库信息科技辑》, no. 1, pages 138 - 1297 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112491425B (en) | 2024-02-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101610916B1 (en) | Receiving system for use in near field communication and mode detection method therefore | |
| CN100545882C (en) | The self-adaptive decoding method that is used for wireless remote control receiving chip | |
| CN112511289B (en) | Hardware decoding device supporting one-wire communication and radio frequency | |
| CN103297060A (en) | Decoding circuit suitable for correcting miller code signal at high speed | |
| CN112491425B (en) | Flexibly configurable radio frequency hardware decoder | |
| EP2108225A1 (en) | Communication method and device | |
| KR100512182B1 (en) | Circuit for generating clock signal and decoding data signals in contactless integrated circuit card | |
| CN103595421A (en) | A decoder for TYPE A basic data rate signals transmitted by a decoding card | |
| US20120008720A1 (en) | Amplitude-shift-keying (ask) radio-frequency (rf) signal decoding device and method thereof | |
| US20140140445A1 (en) | Apparatus and method for demodulation of fsk signals | |
| US4675545A (en) | Wave shaping apparatus for eliminating pulse width distortion | |
| CN1862565B (en) | Coding method for passive RF identifying system | |
| CN113438052B (en) | Signal decoding method, device, electronic equipment and storage medium | |
| CN102055481A (en) | Method and device for decoding FM0 and FM0 codes | |
| CN201060549Y (en) | Anti-interference infrared remote controller | |
| CN211018863U (en) | Decoding system of BMC (baseboard management controller) code | |
| CN103595418B (en) | Decode the decoder for the TYPE A 847K data rate signals that card reader is sent | |
| CN110875911B (en) | Communication protocol and communication method for supporting automatic identification of single data packet data bit number | |
| CN103595420A (en) | Decoder for decoding TYPE A signals transmitted by card reader | |
| CN108551366B (en) | Visible light communication method based on LED and mobile phone camera | |
| CN108173553B (en) | Low frequency decoding integrated circuit and TPMS transmitter | |
| CN106817151B (en) | Slave mode transmitting and receiving circuit of active antenna of reader-writer | |
| CN108270706B (en) | Self-synchronization receiving method of BTM demodulation signal | |
| CN110489373B (en) | Serial isolation communication method, device and system | |
| US11454943B2 (en) | Serial isolation communication method, device and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 310015 floor 12, building D, No. 108 Xiangyuan Road, Gongshu District, Hangzhou City, Zhejiang Province Applicant after: Zhongke Computing Technology Innovation Research Institute Address before: 12 / F, building 4, 108 Xiangyuan Road, Gongshu District, Hangzhou City, Zhejiang Province 310015 Applicant before: Institute of digital economy industry, Institute of computing technology, Chinese Academy of Sciences |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |