CN112491425B - Flexibly configurable radio frequency hardware decoder - Google Patents
Flexibly configurable radio frequency hardware decoder Download PDFInfo
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
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Abstract
The invention relates to a flexible and configurable radio frequency hardware decoder. The invention aims to provide a flexible and configurable radio frequency hardware decoder which is applicable to various coding formats, can rapidly switch different coding formats and has high decoding speed. The technical scheme of the invention is as follows: the decoder includes: the filtering module is used for filtering the input signal according to the configured high and low level burr width thresholds; the counting module is used for respectively counting the continuous periods of high and low levels of the signals filtered by the filtering module under the driving of the clock signal to obtain high and low level count values; and the bit decoding module is used for carrying out bit decoding according to the configured parameter I required by decoding and the high and low level count values obtained from the counting module, and judging decoded data to obtain a synchronous head, a bit 0 and a bit 1. The invention is suitable for the field of industrial control, and particularly relates to a wireless remote control and wireless alarm.
Description
Technical Field
The invention relates to a flexible and configurable radio frequency hardware decoder. The wireless remote control and wireless alarm device is suitable for the field of industrial control and particularly relates to a wireless remote control and wireless alarm device.
Background
In life, more and more devices, appliances, vehicles and the like adopt a remote control mode, thereby providing great convenience for the life of people. The radio frequency communication mode is widely applied to the fields of industrial control and the like because of the characteristics of non-directivity, long transmission distance, strong penetrating power and the like.
The radio frequency is to control the equipment in a mode of information transmission through a wireless signal, and after the radio frequency signal is received, the corresponding equipment can be instructed or driven to complete various operations. A common radio frequency control system comprises a transmitter and a receiver. The transmitter is typically a remote control, which encodes and modulates the control information in a particular format. The receiver needs to receive, demodulate and decode.
Currently, the coding formats used by transmitters are different, which makes it difficult for a receiver to adapt to various coding formats. The existing receiver solutions are only suitable for specific coding formats, control information of different formats cannot be analyzed, and a software decoding mode is adopted, so that the defects of small application range, high replacement cost for different coding formats, low decoding speed and high power consumption of the receiver are caused. Meanwhile, the remote controller and the alarm are various in use environments and high in stability.
Disclosure of Invention
The invention aims to solve the technical problems that: aiming at the problems, the flexible and configurable radio frequency hardware decoder which is applicable to various coding formats, can rapidly switch different coding formats and has high decoding speed is provided.
The technical scheme adopted by the invention is as follows: a flexible configurable radio frequency hardware decoder, characterized in that,
comprising the following steps:
the filtering module is used for filtering the input signal according to the configured high and low level burr width thresholds;
the counting module is used for respectively counting the continuous periods of high and low levels of the signals filtered by the filtering module under the driving of the clock signal to obtain high and low level count values;
the bit decoding module is used for carrying out bit decoding according to the configured parameter I required by decoding and the high and low level count values obtained from the counting module, and judging decoded data to obtain a synchronous head, a bit 0 and a bit 1;
the command shift register is used for acquiring the decoded result of the bit decoding module and storing the decoded result as a command;
the command decoding/interrupt generating module decodes the command in the command shift register according to the configured decoding required parameter II, stores the command into the register module and generates an interrupt when the command is a legal command;
and the register module is used for storing the high and low level burr width threshold parameters written by the CPU and parameters I and II required by decoding.
The filtering module is used for:
counting the high level of an input signal through an internal clock, starting counting at the rising edge of the input signal, outputting the high level when the counting is larger than the high level burr width threshold value, and outputting the high level to be changed into the low level after the high level still keeps the high level burr width after the falling edge of the input signal;
after filtering high-level burrs of an input signal, counting the low level of the signal through an internal clock, starting counting at the falling edge of the signal, outputting the signal to be low level when the counting is larger than the threshold value of the width of the low-level burrs, and outputting the signal to be high level after the low level still keeps the width of the low-level burrs after the rising edge of the signal.
The counting module is used for:
inverting the filtered input signal; delaying two beats under the driving of a clock, accumulating and counting by a low-level counter under the low level of a delay signal of a first beat, and resetting the low-level counter when the delay signal is high; the high level counter counts up at the high level of the second beat delay signal, and clears the high level counter when the second beat delay signal is low and the first beat delay signal is high.
The parameters i required for decoding include a recognition 0 highest multiple, a recognition 0 lowest multiple, a recognition 1 highest multiple, a recognition 1 lowest multiple, a synchronization highest multiple, and a synchronization lowest multiple.
The bit decoding module is configured to:
respectively calculating products of the high-level count value and the synchronous highest multiple and the synchronous lowest multiple; comparing the magnitude relation of the low level count value and the product of the low level count value; if the magnitude of the low level count value is between the two products, generating a synchronous indication signal;
respectively calculating products of the low level count value and the highest multiple of the identification 1 and the lowest multiple of the identification 1; comparing the magnitude relation of the high level count value and the product of the high level count value; if the magnitude of the high level count value is between the two products, generating a bit 1 indicating signal;
respectively calculating products of the high level count value and the highest multiple of the identification 0 and the lowest multiple of the identification 0; comparing the magnitude relation of the low level count value and the product of the low level count value; if the magnitude of the low level count value is between the two products, generating a bit 0 indicating signal;
under clock driving, valid bit data is stored in a shift register at the rising edge of an input signal.
The parameters II required by the decoding comprise an alarm code and an alarm code valid bit.
The beneficial effects of the invention are as follows: the invention realizes the radio frequency hardware decoding with configurable, stable, quick and low power consumption by the mutual cooperation of the filtering module, the counting module, the bit decoding module, the command decoding/interrupt generating module and the like.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment.
Fig. 2 is a schematic structural diagram of a filtering module in an embodiment.
Fig. 3 is a schematic diagram of a counting module in an embodiment.
Fig. 4 is a schematic diagram of a bit decoding module in an embodiment.
FIG. 5 is a schematic diagram of a register module according to an embodiment.
Detailed Description
The embodiment is a flexible configurable radio frequency hardware decoder, comprising: a filtering module, a counting module, a bit decoding module, a command shift register, a command decoding/interrupt generating module, a register module and the like.
The filtering module in this embodiment includes a high-level burr filtering module and a low-level burr filtering module, which are configured to filter the input signal according to the configured high-level burr width threshold and low-level burr width threshold.
In this example, the high-level burr filtering module counts the high level of the input signal through the internal clock, starts counting at the rising edge of the input signal, outputs the high level when the count is greater than the threshold value of the high-level burr width, and outputs the high level to become the low level after the high level still keeps the high-level burr width after the falling edge of the input signal.
In this example, the low-level burr filtering module is configured to count the low level of the signal by the internal clock after the high-level burr filtering module filters the high-level burr from the input signal, start counting at the falling edge of the signal, output the signal as the low level when the count is greater than the threshold value of the low-level burr width, and change the output into the high level after the low level still maintains the low-level burr width after the rising edge of the signal.
The counting module in this embodiment includes a high level counting module and a low level counting module, which are configured to count the duration periods of the high level and the low level of the signal filtered by the filtering module under the driving of the clock signal, so as to obtain the count values of the high level and the low level.
The counting module in this example inverts the input signal; then delay two beats under clock drive; the low level counting module counts up under the low level of the first beat of delay signal, and the low level counting module clears when the delay signal is high level; and under the high level of the second beat delay signal, the high level counting module counts up, and when the second beat delay signal is low and the first beat delay signal is high, the high level counting module is cleared.
In this embodiment, the bit decoding module is configured to perform bit decoding according to the configured parameter i required for decoding and the high and low level count values obtained from the counting module, and perform decision on the decoded data to obtain a synchronization header, a bit 0, and a bit 1.
The bit decoding module in the example comprises a product module of a high-level count value and an upper limit multiple of a synchronous head, a product module of the high-level count value and a lower limit multiple of the synchronous head, a numerical comparison module and a synchronous indication signal generation module, and products of the high-level count value and the highest multiple and the lowest multiple of the synchronous are respectively calculated through the product module of the high-level count value and the upper and lower limit multiples of the synchronous head; comparing the magnitude relation of the low level count value and the product of the low level count value through a numerical comparison module; if the magnitude of the low level count value is between the two products, the synchronization indication signal is generated by the synchronization indication signal generating module.
The Bit decoding module in this embodiment further includes a product module of a low level count value and a multiple of the upper limit of Bit "1", a product module of a low level count value and a multiple of the lower limit of Bit "1", a numerical comparison module, and a Bit "1" indication signal generation module, where products of the low level count value and the highest multiple of identification 1 and the lowest multiple of identification 1 are calculated respectively by the product module of the low level count value and the multiple of the upper limit and the lower limit of Bit "1"; comparing the magnitude relation of the high level count value and the product of the high level count value through a numerical comparison module; if the magnitude of the high level count value is between two products, the Bit 1 indication signal is generated by the Bit "1" indication signal generating module.
The Bit decoding module in this embodiment further includes a product module of the high level count value and the upper limit multiple of Bit "0", a product module of the high level count value and the lower limit multiple of Bit "0", a numerical comparison module, and a Bit "0" indication signal generating module, where products of the high level count value and the highest multiple of identification 0 and the lowest multiple of identification 0 are calculated respectively by the product module of the high level count value and the upper and lower limit multiples of Bit "0"; comparing the magnitude relation of the low level count value and the product of the low level count value through a numerical comparison module; if the magnitude of the low level count value is between two products, the Bit 0 indicating signal is generated by the Bit "0" indicating signal generating module.
In this example, the bit decoding module stores the valid bit data 0,1 in the command shift register, and stores the command shift register data in the register module after the sync bit is identified.
The command decoding/interrupt generation module decodes the command of the command shift register according to the configured parameters (alarm code and alarm code valid bit), stores the command into the register module and generates an interrupt when the command is a configured legal command.
The register module stores configuration parameters (high level burr width, low level burr width, identification of 0 highest multiple, identification of 0 lowest multiple, identification of 1 highest multiple, identification of 1 lowest multiple, synchronization highest multiple, synchronization lowest multiple, alarm coding valid bit, etc.) required for decoding by the filtering module, the bit decoding module, the command decoding/interrupt generating module, etc. and decodes the obtained command. The CPU reads and writes through the APB bus, the specific implementation method comprises the following steps: the APB interface module processes the APB bus according to an AMBA APB bus protocol, generates a read-write enabling signal and transmits address and data signals to the decoding module; the decoding module analyzes each item of configuration data, receives radio frequency receiving data and waits for the CPU to read.
Claims (4)
1. A flexible configurable radio frequency hardware decoder, comprising:
the filtering module is used for filtering the input signal according to the configured high and low level burr width thresholds;
the counting module is used for respectively counting the continuous periods of high and low levels of the signals filtered by the filtering module under the driving of the clock signal to obtain high and low level count values;
the bit decoding module is used for carrying out bit decoding according to the configured parameter I required by decoding and the high and low level count values obtained from the counting module, and judging decoded data to obtain a synchronous head, a bit 0 and a bit 1;
the command shift register is used for acquiring the decoded result of the bit decoding module and storing the decoded result as a command;
the command decoding/interrupt generating module decodes the command in the command shift register according to the configured decoding required parameter II, stores the command into the register module and generates an interrupt when the command is a legal command;
the register module is used for storing the high-level burr width threshold value parameters and the low-level burr width threshold value parameters written by the CPU and the parameters I and II required by decoding;
the parameters I required by decoding comprise a recognition 0 highest multiple, a recognition 0 lowest multiple, a recognition 1 highest multiple, a recognition 1 lowest multiple, a synchronization highest multiple and a synchronization lowest multiple;
the bit decoding module is configured to:
respectively calculating products of the high-level count value and the synchronous highest multiple and the synchronous lowest multiple; comparing the magnitude relation of the low level count value and the product of the low level count value; if the magnitude of the low level count value is between the two products, generating a synchronous indication signal;
respectively calculating products of the low level count value and the highest multiple of the identification 1 and the lowest multiple of the identification 1; comparing the magnitude relation of the high level count value and the product of the high level count value; if the magnitude of the high level count value is between the two products, generating a bit 1 indicating signal;
respectively calculating products of the high level count value and the highest multiple of the identification 0 and the lowest multiple of the identification 0; comparing the magnitude relation of the low level count value and the product of the low level count value; if the magnitude of the low level count value is between the two products, generating a bit 0 indicating signal;
under clock driving, valid bit data is stored in a shift register at the rising edge of an input signal.
2. The flexible configurable radio frequency hardware decoder of claim 1, wherein the filtering module is configured to:
counting the high level of an input signal through an internal clock, starting counting at the rising edge of the input signal, outputting the high level when the counting is larger than the high level burr width threshold value, and outputting the high level to be changed into the low level after the high level still keeps the high level burr width after the falling edge of the input signal;
after filtering high-level burrs of an input signal, counting the low level of the signal through an internal clock, starting counting at the falling edge of the signal, outputting the signal to be low level when the counting is larger than the threshold value of the width of the low-level burrs, and outputting the signal to be high level after the low level still keeps the width of the low-level burrs after the rising edge of the signal.
3. The flexible configurable radio frequency hardware decoder of claim 1, wherein the counting module is configured to:
inverting the filtered input signal; delaying two beats under the driving of a clock, accumulating and counting by a low-level counter under the low level of a delay signal of a first beat, and resetting the low-level counter when the delay signal is high; the high level counter counts up at the high level of the second beat delay signal, and clears the high level counter when the second beat delay signal is low and the first beat delay signal is high.
4. The flexible configurable radio frequency hardware decoder of claim 1, wherein said decoding required parameter ii comprises an alarm code and an alarm code valid bit.
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