US20140054683A1 - Trench devices having improved breakdown voltages and method for manufacturing same - Google Patents
Trench devices having improved breakdown voltages and method for manufacturing same Download PDFInfo
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- US20140054683A1 US20140054683A1 US13/646,906 US201213646906A US2014054683A1 US 20140054683 A1 US20140054683 A1 US 20140054683A1 US 201213646906 A US201213646906 A US 201213646906A US 2014054683 A1 US2014054683 A1 US 2014054683A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to improved breakdown voltages in trench devices, and in particular, to trench devices having improved breakdown voltages and method for manufacturing same.
- rectifiers may be comprised of an array of diodes. Each diode has a PN junction which may dissipate power due to the turn on voltage of the PN junction. This turn on voltage of about 0.6V may be reduced by a trenched MOS gate fabricated vertically within a trench to form a vertical MOS device within the semiconductor.
- the MOS device may turn on at a few tenths of a volt, and thereby reduce the voltage drop across the PN junction. This, in turn, reduces the power dissipation associated with that voltage drop.
- the rectifier turns off when a reverse voltage is placed across its terminals.
- the breakdown voltage of a rectifier using trenched gates may be defined by the trenched MOS gate structure.
- the trenched MOS gate is insulated from the cathode region of the diode by a dielectric. During the reverse bias voltage condition, a voltage V forms across this dielectric.
- the trenched gate dielectric may have a voltage breakdown that is lower than the breakdown of the PN junctions of the diodes themselves. This premature breakdown may limit the operational voltages which may be used with the rectifier or may cause reliability problems.
- the present invention solves these and other problems by providing trench devices having improved breakdown voltages and method for manufacturing same.
- the present invention improves breakdown voltages in trench devices.
- the present invention includes a semiconductor device comprising a trenched gate disposed vertically within a trench in a semiconductor substrate and a trenched field region disposed vertically within said trench and below said trenched gate, wherein a lower portion of said trenched field region tapers to disperse an electric field.
- the trenched field region includes a dielectric layer within said lower portion, and wherein said dielectric layer conforms to opposing concave surfaces of said trench which meet at a bottom of said trench field region.
- said lower portion forms a triangular shape, and wherein a bottom of said triangular shape forms an acute angle.
- said lower portion includes a vertical elongated region at a bottom of said lower portion, wherein said vertical elongated region extends said lower portion to further disperse said electric field, and wherein said vertical elongated region has a width that is less than half the width of a widest portion of said trenched field region.
- said trenched field region includes a first material and a dielectric layer, wherein the dielectric layer is between said semiconductor substrate first material, wherein said dielectric layer is on the sidewalk of said trench.
- said first material forms an angle at a bottom of said first material that is greater than an angle formed at a bottom of said trench.
- said dielectric layer has a thickness at a bottom of said lower portion greater than the thickness of the dielectric layer at other portions of said trench.
- the present invention includes a method of manufacturing a semiconductor power device comprising etching a trench in a semiconductor substrate, the trench including a lower portion that tapers, growing a dielectric layer in the trench, wherein the dielectric layer includes a taper conforming to the taper in the lower portion of the trench, and forming a vertical MOSFET on a sidewall of the trench above the lower portion.
- forming the vertical MOSFET comprises removing the dielectric layer above the lower portion of the trench and growing a gate oxide on the sidewalls of the trench.
- forming the vertical MOSFET comprises depositing polysilicon in a portion of the trench above the lower portion.
- forming the vertical MOSFET comprises implanting a dopant in the substrate at a top of said trench.
- the method further comprises depositing a first material in the lower portion of the trench, wherein the dielectric layer is between the first material and the sidewall of the trench, and wherein the dielectric layer has a first thickness that increases toward a bottom of the trench.
- the method further comprises removing a first portion of said dielectric layer in an area above said lower portion and below a top of said first material, removing a portion of said first material such that a depth of said top of said first material is reduced to a first level, removing a second portion of said dielectric layer such that a depth of a top of said dielectric layer is reduced to a second level, and adding a second dielectric layer covering said top of said first material and said top of said dielectric layer.
- said dielectric layer conforms to opposing concave surfaces of said trench that meet at a bottom of said trench.
- said lower portion forms a triangular shape, and wherein a bottom of said triangular shape forms an acute angle.
- etching said trench includes etching a vertical elongated region at a bottom of said lower portion.
- said vertical elongated region extends said lower portion to further disperse said electric field, and wherein said vertical elongated region has a width that is less than half the width of a widest portion of said trenched field region.
- the present invention includes an integrated circuit comprising a plurality of diodes coupled in parallel, each diode of said plurality of diodes comprising, a trenched gate disposed vertically within a trench in a semiconductor substrate, and a trenched field region disposed vertically within said trench and below said trenched gate, wherein a lower portion of said trenched field region tapers to disperse an electric field.
- a reduced thickness of an epitaxial layer of the semiconductor substrate is used that reduces the breakdown voltage improvement achieved from the trench field region.
- the plurality of diodes are spaced to improve R
- the plurality of diodes are spaced to improve integration
- FIG. 1A-1B illustrates a semiconductor power device according to one embodiment of the present invention.
- FIG. 2 illustrates a semiconductor power device according to another embodiment of the present invention
- FIG. 3A-3D illustrateates a method of fabricating a semiconductor power device according to one embodiment of the present invention.
- FIG. 4 illustrates an integrated circuit according to another embodiment of the present invention.
- FIG. 1A-B illustrates a semiconductor power device 100 according to one embodiment of the present invention.
- Semiconductor power device 100 includes diode 123 , diode 124 , and trench 101 .
- Diode 123 includes PN junction 117 between P region 121 and N ⁇ region 125
- Diode 124 includes PN junction 118 between P region 122 and N ⁇ region 125 .
- Trench 101 includes a trenched gate 126 and a trench field region 103 .
- Trench 101 a disposed vertically into the semiconductor substrate.
- the semiconductor substrate may include P regions 121 - 122 , N ⁇ region 125 , and N+ region 102
- Trenched gate 126 is part of vertical N-MOSFETs (n-channel MOS field effect transistors) 119 and 120 within the structure for diodes 123 mid 124 (respectively).
- Trenched gate 126 includes a dielectric layer 116 on both sides of the trench and conductive material 107 .
- Dielectric layer 116 may have width 105 which may be designed to set the threshold voltage of N-MOSFETs 119 and 120 .
- N-MOSFET 119 includes N+ region 114 , P region 121 , N repon 125 , and trenched gate 126 .
- N-MOSFET 120 includes N+ region 115 , P region 122 , N region 125 , and trenched gate 126 .
- N-MOSFETs 119 and 120 may reduce the on voltage of diodes 123 and 124 (respectively).
- a trenched field region 103 extends vertically below the trenched gate 126 .
- Trench 101 is vertical and substantially parallel in the region of N-MOSFETs 119 and 120 and in trenched field region 103 below the N-MOSFETs.
- trench 101 tapers.
- the trenched field region 103 may extend below dashed line 113 to tip 111 .
- Lower portion 104 of the trenched field region 103 has a width that may decrease at trench 101 tapers at taper region 109 .
- the sidewalls of trench 101 include dielectric layer 127 hating a dielectric thickness that increases from the vertical sidewalls toward the taper tip 111 .
- the trenched field region 103 may be filled with a material 108 separated from the trenched gate 126 by a dielectric layer 199 , for example.
- Dielectric thickness 112 at the tip 111 may be greater than dielectric thickness 106 on the vertical sidewall of trench 101 adjacent to taper region 109 or dielectric thickness 110 on the tapered sidewall in taper region 109 .
- the dielectnc thickness 106 may be greater than the dielectric thickness 105 of the N ⁇ MOSFET dielectric layer 116 , which is vertically adjacent to and above dielectric 127 .
- the thickness of the dielectric layer 127 may increase along taper 109 , reaching a maximum thickness at tip 111 , such that dielectric thickness 110 in taper region 109 is greater than dielectric thickness 106 on the vertical sidewall of trench 101 , and the dielectric thickness 112 at the tip 111 is greater than the dielectric thickness 110 .
- the taper 109 and the reduction in overall width of the trenched field region 103 may disperse an electric field when a reverse voltage is placed across PN junctions 117 and 118 .
- the thickness of the dielectric layer 127 toward the tip 111 of the lower portion 104 may increase to further disperse the electric field. This may improve the ability of the power device 100 to tolerate voltages and not breakdown through the dielectric.
- material 108 may be polysillicon.
- dielectric layer 127 may be comprised of a silicon dioxide. Material 108 may be floating and may not directly couple to either P regions 121 - 122 or N ⁇ region 125 .
- trenched field region 101 includes a dielectric layer within lower portion 104 having a shape that conforms to trench 101 within trench field region 103 .
- Trench 101 may have opposing concave surfaces that meet at bottom 111 of the lower portion 104 such that trenched field region 103 tapers to disperse an electric field.
- the lower portion 104 may have a triangular shape. As illustrated in FIG. 1B , the bottom 111 and the tapering sides of the lower portion 104 may form an acute angle 128 and this acute angle may have a value which is less than any other other angle between any two adjacent walls of trenched field region 103 .
- FIG. 1B illustrates trenched field region 103 of FIG. 1A .
- Angle 128 between side walls 129 and 130 is an acute angle. Angle 128 has a value less than the value of angle 131 between side walls 132 and 129 The value of angle 128 is also less than the value of angle 133 between side walls 134 and 130 .
- dielectric layer 127 may conform to a boundary defined by the portion of the trench including trench field region 103 .
- Material 108 may conform to dielectric layer 127 such that angle 137 between walls 135 and 136 of material 108 is greater than angle 128 .
- the trench walls may not be distinictly linear as illustrated here.
- the walls of trench 101 may continuous curved surfaces.
- trench side walls 132 and 129 and sidewalls 134 and 130 are a single curved surfaces which narrows the width of lower portion 104 as the sidewalls approach bottom 111 of trenched field region 103 .
- FIG. 2 illustrates a semiconductor power device 200 according to another embodiment or the present invention.
- Semiconductor 200 is similar to semiconductor device 100 of FIG. 1 A.
- Trench 201 , trench field region 203 , lower region 204 , diode 223 , diode 224 , dashed line 213 , dielectric layer 227 , material 208 , and taper region 209 correspond to trench 101 , trench field region 103 , lower region 104 , diode 123 , diode 124 , dashed line 113 .
- dielectric layer 127 , material 108 , and taper region 109 of FIG. 1A includes a vertical elongated region 202 (e.g., a vertical elongate tip) at the bottom of lower portion 204 of the trench field region 203 .
- Vertical elongated region 202 may have vertical sidewalk (or substantially vertical sidewalls that taper) having a width of 205 . Region 202 may have a length 206 after taper region 209 . During reverse biasing of diodes 223 and 224 , the electrical field may disperse around vertical elongated region 202 so that semiconductor power device 200 has a higher breakdown voltage.
- Vertical elongated region 202 extends into a semiconductor epitaxial layer (e.g., N ⁇ region 125 ).
- the walls of the vertical elongated region 202 may be parallel, as shown, or may have a slight taper.
- the taper may be less than the taper provided in tapered region 209 so that each opposing side of vertically elongated region 202 extends further into the epitaxial layer.
- the width 205 of vertical extended region 202 may be less than half the width of trenched field region 203 or the width of trench 201 .
- Lower portion 204 may include two opposing convex curved surfaces such that the length 206 is extended deeper into the epitaxial layer.
- FIG. 3A-3C illustrates a method of fabricating a semiconductor power device according to one embodiment of the present invention.
- a semiconductor substrate may have a N+ region 311 , an epitaxial N ⁇ region 310 which has been implanted with a P body region 300 .
- a trench 312 may he etched into the semiconductor substrate.
- the etching produces an opening that defines a trenched gate area 313 a distance 318 down, an upper trench field area 314 an additional distance 319 down, and a lower trench field area 315 that extends vertically an additional distance 320 .
- Lower trench field area 315 has a taper sidewall region 316 on one side and a taper sidewall region 317 on the other side at lower trench field area 315 .
- etching the trench may include an etch step to create the vertical elongated region at a bottom of said lower portion of the trench
- an oxide layer 321 may be grown within trench 312 .
- Oxide layer 321 may have a greater thickness at point 323 .
- Oxide layer 321 may also have a greater thickness at a bottom area 324 .
- Oxide layer 321 conforms to the boundary defined by trench 312 .
- polysilicon 325 may deposited within trench 312 over oxide layer 321 .
- the depositing of polysilicon may use chemical vapor deposition (CVD).
- Polysilicon 325 may conform to the oxide layer 323 formed during 302 a .
- the thickness of oxide layer 323 increases toward the bottom of a lower portion of the trench 312 .
- the walls at the bottom of the polysilicon 325 may form as angle which is greater tnan an angle formed by the walls at the bottom of the oxide layer 323 .
- Polysilicon 325 may have top 322 a at level 322 b .
- polysilicon 325 may be etched to have top 322 a at level 322 b .
- a portion of oxide layer 32 may be removed.
- a thinner oxide 341 may extend a depth within the trench to level 342 .
- Level 342 may be lower than top 322 a of polusilicon 325 .
- a wet etch or dip process may be used to remote the portion of oxide layer 321 , and this process may leave oxide layer 321 unchanged below level 342 .
- a portion of polysilicon 325 may be removed such that tap 326 of polysilicon 325 is at level 344 .
- a poly etch process may be used to remove the portion of the polysilicon 325 to obtain a depth at level 344 for top 326 .
- a second portion of the oxide layer 321 may be removed such that thinner oxide 341 is removed. This may result in level 345 of top 327 and top 328 of oxide layer 321 .
- the difference 346 between level 344 and level 345 may be reduced to improve the reliability of the subsequent oxide added during 304 below.
- the polysilicon 325 masks portions of oxide layer 321 when oxide layer 321 may be etched back to level 345 .
- second oxide layer 330 is grown within trench 312 .
- Areas 331 and 332 are portions of the gate oxide.
- Locations 329 and 333 indicate portions of second oxide 330 which have edges due to the difference 346 described in 303 above.
- Level 344 and 345 of 303 are close enough such that abrupt edges are reduced. This reduction of abrupt edges in second oxide layer 330 may improve reliability.
- additional polysilicon 334 is deposited within the remaining area of trench 312 .
- N+ dopant may be implanted at regions 335 and 336 .
- P+ dopant may be implanted at regions 337 and 338 . Also an insalating layer 339 is added. Insulating layer 339 may be a Borophosphosilicate glass (BPSG). Metal layer 340 is added to connect the anodes of the two diodes formed on either side of trench 312 .
- BPSG Borophosphosilicate glass
- FIG. 4 illustrates an integrated circuit 400 according to another embodiment of the present invention.
- Integrated circuit 400 repeats an array such that a plurality of diodes (e.g. diodes 402 - 4 O 9 ) are coupled in parallel with the trenched gates coupled together.
- N+ region 311 , epitaxial N ⁇ region 310 , P body region 309 , regions 335 - 338 , insulating layer 339 , and metal layer 340 may be similar to corresponding elements of FIG. 3A-3D .
- the plurality of diodes in parallel may improve the current density through the power device by increasing the number of paths and cross sectional area in which current may flow from anode to cathode
- An improvement in breakdown voltage may the for a given epitaxial thickness 410 . If the improvement in breakdown voltage due to the trenched field regions of the plurality of diodes (e.g. 402 - 409 ) allows for a margin of variability in this parameter, the improvement may be adjusted down by reducing the epitaxial thickness 410 .
- the reduced epitaxial thickness 410 would mainum an acceptible breakdown voltage and may improve the R of the MOSFET devices created by the trenched gates.
- the given spacing 411 - 413 and the reduced epitaxial layer thickness 410 allows for lower R
- the reduction in epitaxial thickness 410 may be used to improve integration by shrinking the diode structures of the semiconductor power device. In this case, the spacing of the plurality of diodes (e.g. 402 - 409 ) may be decreased such that R is increased and the integration is improved.
- an improvement in breakdown allows for more flexibility in implementing other improvements.
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Abstract
In one embodiment, the present invention includes a semiconductor power device. The semiconductor power device comprises a trenched gate and a trenched field region. The trenched gate is disposed vertically within a trench in a semiconductor substrate. The trenched field, region is disposed vertically within the trench and below the trenched gate. A lower portion of the trenched field region tapers to dispose an electric field.
Description
- The present invention relates to improved breakdown voltages in trench devices, and in particular, to trench devices having improved breakdown voltages and method for manufacturing same.
- Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section
- Some semiconductor power devices use trenching to produce metal-oxide-semiconductor (MOS) devices that increase efficiency. For example, rectifiers may be comprised of an array of diodes. Each diode has a PN junction which may dissipate power due to the turn on voltage of the PN junction. This turn on voltage of about 0.6V may be reduced by a trenched MOS gate fabricated vertically within a trench to form a vertical MOS device within the semiconductor. The MOS device may turn on at a few tenths of a volt, and thereby reduce the voltage drop across the PN junction. This, in turn, reduces the power dissipation associated with that voltage drop. The rectifier turns off when a reverse voltage is placed across its terminals.
- When the rectifier is biased with a reverse voltage, no significant current flows. In some applications the rectifier may experience transient reverse voltages over 70V, and the ability for the rectifier to withstand such transient voltages without breaking down is a measure of reliability. The breakdown voltage of a rectifier using trenched gates may be defined by the trenched MOS gate structure.
- The trenched MOS gate is insulated from the cathode region of the diode by a dielectric. During the reverse bias voltage condition, a voltage V forms across this dielectric. In this case, the trenched gate dielectric may have a voltage breakdown that is lower than the breakdown of the PN junctions of the diodes themselves. This premature breakdown may limit the operational voltages which may be used with the rectifier or may cause reliability problems.
- Thus, there is a need for improved breakdown volumes in trench devices. The present invention solves these and other problems by providing trench devices having improved breakdown voltages and method for manufacturing same.
- Embodiments of the present invention improves breakdown voltages in trench devices. In one embodiment, the present invention includes a semiconductor device comprising a trenched gate disposed vertically within a trench in a semiconductor substrate and a trenched field region disposed vertically within said trench and below said trenched gate, wherein a lower portion of said trenched field region tapers to disperse an electric field.
- In one embodiment, the trenched field region includes a dielectric layer within said lower portion, and wherein said dielectric layer conforms to opposing concave surfaces of said trench which meet at a bottom of said trench field region.
- In one embodiment, said lower portion forms a triangular shape, and wherein a bottom of said triangular shape forms an acute angle.
- In one embodiment, said lower portion includes a vertical elongated region at a bottom of said lower portion, wherein said vertical elongated region extends said lower portion to further disperse said electric field, and wherein said vertical elongated region has a width that is less than half the width of a widest portion of said trenched field region.
- In one embodiment, said trenched field region includes a first material and a dielectric layer, wherein the dielectric layer is between said semiconductor substrate first material, wherein said dielectric layer is on the sidewalk of said trench.
- In one embodiment, said first material forms an angle at a bottom of said first material that is greater than an angle formed at a bottom of said trench.
- In one embodiment, said dielectric layer has a thickness at a bottom of said lower portion greater than the thickness of the dielectric layer at other portions of said trench.
- In another embodiment, the present invention includes a method of manufacturing a semiconductor power device comprising etching a trench in a semiconductor substrate, the trench including a lower portion that tapers, growing a dielectric layer in the trench, wherein the dielectric layer includes a taper conforming to the taper in the lower portion of the trench, and forming a vertical MOSFET on a sidewall of the trench above the lower portion.
- In one embodiment, forming the vertical MOSFET comprises removing the dielectric layer above the lower portion of the trench and growing a gate oxide on the sidewalls of the trench.
- In one embodiment, forming the vertical MOSFET comprises depositing polysilicon in a portion of the trench above the lower portion.
- In one embodiment, forming the vertical MOSFET comprises implanting a dopant in the substrate at a top of said trench.
- In one embodiment, the method further comprises depositing a first material in the lower portion of the trench, wherein the dielectric layer is between the first material and the sidewall of the trench, and wherein the dielectric layer has a first thickness that increases toward a bottom of the trench.
- In one embodiment, the method further comprises removing a first portion of said dielectric layer in an area above said lower portion and below a top of said first material, removing a portion of said first material such that a depth of said top of said first material is reduced to a first level, removing a second portion of said dielectric layer such that a depth of a top of said dielectric layer is reduced to a second level, and adding a second dielectric layer covering said top of said first material and said top of said dielectric layer.
- In one embodiment, said dielectric layer conforms to opposing concave surfaces of said trench that meet at a bottom of said trench.
- In one embodiment, said lower portion forms a triangular shape, and wherein a bottom of said triangular shape forms an acute angle.
- In one embodiment, etching said trench includes etching a vertical elongated region at a bottom of said lower portion.
- In one embodiment, said vertical elongated region extends said lower portion to further disperse said electric field, and wherein said vertical elongated region has a width that is less than half the width of a widest portion of said trenched field region.
- In another embodiment, the present invention includes an integrated circuit comprising a plurality of diodes coupled in parallel, each diode of said plurality of diodes comprising, a trenched gate disposed vertically within a trench in a semiconductor substrate, and a trenched field region disposed vertically within said trench and below said trenched gate, wherein a lower portion of said trenched field region tapers to disperse an electric field.
- In one embodiment, a reduced thickness of an epitaxial layer of the semiconductor substrate is used that reduces the breakdown voltage improvement achieved from the trench field region.
-
- In yet another embodiment, the plurality of diodes are spaced to improve integration
- The following detailed description and accompanying drawings provide a better understanding of the nature and advantages of the present invention.
-
FIG. 1A-1B illustrates a semiconductor power device according to one embodiment of the present invention. -
FIG. 2 illustrates a semiconductor power device according to another embodiment of the present invention -
FIG. 3A-3D ilustrates a method of fabricating a semiconductor power device according to one embodiment of the present invention. -
FIG. 4 illustrates an integrated circuit according to another embodiment of the present invention. - Described herein are techniques for improving breakdown voltages in trench devices. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concept described herein.
-
FIG. 1A-B illustrates a semiconductor power device 100 according to one embodiment of the present invention. Semiconductor power device 100 includesdiode 123, diode 124, andtrench 101.Diode 123 includes PN junction 117 betweenP region 121 and N−region 125, Diode 124 includesPN junction 118 betweenP region 122 and N−region 125. Trench 101 includes a trenchedgate 126 and atrench field region 103. Trench 101 a disposed vertically into the semiconductor substrate. The semiconductor substrate may include P regions 121-122, N−region 125, andN+ region 102 - Trenched
gate 126 is part of vertical N-MOSFETs (n-channel MOS field effect transistors) 119 and 120 within the structure fordiodes 123 mid 124 (respectively). Trenchedgate 126 includes adielectric layer 116 on both sides of the trench andconductive material 107.Dielectric layer 116 may havewidth 105 which may be designed to set the threshold voltage of N-MOSFETs 119 and 120. N-MOSFET 119 includes N+ region 114,P region 121,N repon 125, and trenchedgate 126. N-MOSFET 120 includesN+ region 115,P region 122,N region 125, and trenchedgate 126. N-MOSFETs 119 and 120 may reduce the on voltage ofdiodes 123 and 124 (respectively). - A trenched
field region 103 extends vertically below the trenchedgate 126.Trench 101 is vertical and substantially parallel in the region of N-MOSFETs 119 and 120 and in trenchedfield region 103 below the N-MOSFETs. At alower portion 104,trench 101 tapers. The trenchedfield region 103 may extend below dashedline 113 to tip 111.Lower portion 104 of the trenchedfield region 103 has a width that may decrease attrench 101 tapers attaper region 109. The sidewalls oftrench 101 includedielectric layer 127 hating a dielectric thickness that increases from the vertical sidewalls toward thetaper tip 111. The trenchedfield region 103 may be filled with a material 108 separated from the trenchedgate 126 by adielectric layer 199, for example.Dielectric thickness 112 at thetip 111 may be greater thandielectric thickness 106 on the vertical sidewall oftrench 101 adjacent to taperregion 109 ordielectric thickness 110 on the tapered sidewall intaper region 109. Thedielectnc thickness 106 may be greater than thedielectric thickness 105 of the N−MOSFET dielectric layer 116, which is vertically adjacent to and abovedielectric 127. Additionally, the thickness of thedielectric layer 127 may increase alongtaper 109, reaching a maximum thickness attip 111, such thatdielectric thickness 110 intaper region 109 is greater thandielectric thickness 106 on the vertical sidewall oftrench 101, and thedielectric thickness 112 at thetip 111 is greater than thedielectric thickness 110. - The
taper 109 and the reduction in overall width of the trenchedfield region 103 may disperse an electric field when a reverse voltage is placed acrossPN junctions 117 and 118. The thickness of thedielectric layer 127 toward thetip 111 of thelower portion 104 may increase to further disperse the electric field. This may improve the ability of the power device 100 to tolerate voltages and not breakdown through the dielectric. - In one embodiment,
material 108 may be polysillicon. In another embodimentdielectric layer 127 may be comprised of a silicon dioxide.Material 108 may be floating and may not directly couple to either P regions 121-122 or N−region 125. - In another embodiment, trenched
field region 101 includes a dielectric layer withinlower portion 104 having a shape that conforms to trench 101 withintrench field region 103. Trench 101 may have opposing concave surfaces that meet atbottom 111 of thelower portion 104 such that trenchedfield region 103 tapers to disperse an electric field. - In one embodiment, the
lower portion 104 may have a triangular shape. As illustrated inFIG. 1B , the bottom 111 and the tapering sides of thelower portion 104 may form anacute angle 128 and this acute angle may have a value which is less than any other other angle between any two adjacent walls of trenchedfield region 103. For example,FIG. 1B illustrates trenchedfield region 103 ofFIG. 1A .Angle 128 betweenside walls Angle 128 has a value less than the value ofangle 131 betweenside walls angle 128 is also less than the value ofangle 133 betweenside walls - In another embodiment,
dielectric layer 127 may conform to a boundary defined by the portion of the trench includingtrench field region 103.Material 108 may conform todielectric layer 127 such thatangle 137 betweenwalls material 108 is greater thanangle 128. - In another embodiment, the trench walls (e.g.
side walls trench 101 may continuous curved surfaces. In one embodiment,trench side walls sidewalls lower portion 104 as thesidewalls approach bottom 111 of trenchedfield region 103. -
FIG. 2 illustrates asemiconductor power device 200 according to another embodiment or the present invention.Semiconductor 200 is similar to semiconductor device 100 ofFIG. 1 A. Trench 201,trench field region 203,lower region 204,diode 223, diode 224, dashedline 213, dielectric layer 227,material 208, and taperregion 209 correspond to trench 101,trench field region 103,lower region 104,diode 123, diode 124, dashedline 113.dielectric layer 127,material 108, and taperregion 109 ofFIG. 1A .Semiconductor device 200 includes a vertical elongated region 202 (e.g., a vertical elongate tip) at the bottom oflower portion 204 of thetrench field region 203. - Vertical
elongated region 202 may have vertical sidewalk (or substantially vertical sidewalls that taper) having a width of 205.Region 202 may have alength 206 aftertaper region 209. During reverse biasing ofdiodes 223 and 224, the electrical field may disperse around verticalelongated region 202 so thatsemiconductor power device 200 has a higher breakdown voltage. - Vertical
elongated region 202 extends into a semiconductor epitaxial layer (e.g., N− region 125). The walls of the verticalelongated region 202 may be parallel, as shown, or may have a slight taper. The taper may be less than the taper provided in taperedregion 209 so that each opposing side of vertically elongatedregion 202 extends further into the epitaxial layer. Thewidth 205 of verticalextended region 202 may be less than half the width of trenchedfield region 203 or the width oftrench 201.Lower portion 204 may include two opposing convex curved surfaces such that thelength 206 is extended deeper into the epitaxial layer. -
FIG. 3A-3C illustrates a method of fabricating a semiconductor power device according to one embodiment of the present invention. - At 301, a semiconductor substrate may have a
N+ region 311, an epitaxial N−region 310 which has been implanted with aP body region 300. - At 301, a
trench 312 may he etched into the semiconductor substrate. The etching produces an opening that defines a trenched gate area 313 adistance 318 down, an upper trench field area 314 anadditional distance 319 down, and a lowertrench field area 315 that extends vertically anadditional distance 320. Lowertrench field area 315 has ataper sidewall region 316 on one side and ataper sidewall region 317 on the other side at lowertrench field area 315. In the embodiment ofFIG. 2 , etching the trench may include an etch step to create the vertical elongated region at a bottom of said lower portion of the trench - At 302a, an
oxide layer 321 may be grown withintrench 312.Oxide layer 321 may have a greater thickness atpoint 323.Oxide layer 321 may also have a greater thickness at abottom area 324.Oxide layer 321 conforms to the boundary defined bytrench 312. - At 302 b,
polysilicon 325 may deposited withintrench 312 overoxide layer 321. The depositing of polysilicon may use chemical vapor deposition (CVD).Polysilicon 325 may conform to theoxide layer 323 formed during 302 a. In some embodiments, the thickness ofoxide layer 323 increases toward the bottom of a lower portion of thetrench 312. In this case, the walls at the bottom of thepolysilicon 325 may form as angle which is greater tnan an angle formed by the walls at the bottom of theoxide layer 323.Polysilicon 325 may have top 322 a atlevel 322 b. In some embodiments,polysilicon 325 may be etched to have top 322 a atlevel 322 b. - At 302 c, a portion of oxide layer 32 may be removed. A
thinner oxide 341 may extend a depth within the trench tolevel 342.Level 342 may be lower than top 322 a ofpolusilicon 325. A wet etch or dip process may be used to remote the portion ofoxide layer 321, and this process may leaveoxide layer 321 unchanged belowlevel 342. - At 302 d, a portion of
polysilicon 325 may be removed such thattap 326 ofpolysilicon 325 is atlevel 344. A poly etch process may be used to remove the portion of thepolysilicon 325 to obtain a depth atlevel 344 fortop 326. - At 303, a second portion of the
oxide layer 321 may be removed such thatthinner oxide 341 is removed. This may result inlevel 345 of top 327 and top 328 ofoxide layer 321. Thedifference 346 betweenlevel 344 andlevel 345 may be reduced to improve the reliability of the subsequent oxide added during 304 below. Thepolysilicon 325 masks portions ofoxide layer 321 whenoxide layer 321 may be etched back tolevel 345. - At 304,
second oxide layer 330 is grown withintrench 312.Areas Locations second oxide 330 which have edges due to thedifference 346 described in 303 above.Level second oxide layer 330 may improve reliability. - At 305,
additional polysilicon 334 is deposited within the remaining area oftrench 312. - At 306, N+ dopant may be implanted at
regions - At 307, P+ dopant may be implanted at
regions insalating layer 339 is added. Insulatinglayer 339 may be a Borophosphosilicate glass (BPSG).Metal layer 340 is added to connect the anodes of the two diodes formed on either side oftrench 312. -
FIG. 4 illustrates anintegrated circuit 400 according to another embodiment of the present invention.Integrated circuit 400 repeats an array such that a plurality of diodes (e.g. diodes 402-4O9) are coupled in parallel with the trenched gates coupled together.N+ region 311, epitaxial N−region 310,P body region 309, regions 335-338, insulatinglayer 339, andmetal layer 340 may be similar to corresponding elements ofFIG. 3A-3D . The plurality of diodes in parallel (e.g. diodes 402-409) may improve the current density through the power device by increasing the number of paths and cross sectional area in which current may flow from anode to cathode - An improvement in breakdown voltage may the for a given
epitaxial thickness 410. If the improvement in breakdown voltage due to the trenched field regions of the plurality of diodes (e.g. 402-409) allows for a margin of variability in this parameter, the improvement may be adjusted down by reducing theepitaxial thickness 410. The reducedepitaxial thickness 410 would mainum an acceptible breakdown voltage and may improve the Rof the MOSFET devices created by the trenched gates. In this case, the given spacing 411-413 and the reducedepitaxial layer thickness 410 allows for lower RAdditionally, the reduction inepitaxial thickness 410 may be used to improve integration by shrinking the diode structures of the semiconductor power device. In this case, the spacing of the plurality of diodes (e.g. 402-409) may be decreased such that Ris increased and the integration is improved. In some designs, an improvement in breakdown allows for more flexibility in implementing other improvements. - The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims. other arrangements, embodiments, implementations and equivalents will be evident to those skilled in the art and may be employed without departing from the spirit and scope of the invention as defined by the claims.
Claims (14)
1. A semiconductor device, comprising:
a substrate of semiconductor material having a top surface;
a vertical trench formed in the substrate having an opening at the top surface of the substrate;
the trench having three contiguous sections - a top section, a bottom section, and a tapered transition between the top and the bottom section;
the top section extending to the top surface and with a first trench width measured between two first opposite sidewalls of the substrate material;
the bottom section perpendicular to the top surface and with a second trench width, narrower than the first trench width, measured between two second opposite sidewalls of the substrate material;
the tapered transition section having a varying trench width between the first trench width and the second trench width;
a first section of the top section covered with a first dielectric layer of a first thickness;
a second section of the top section covered with a second dielectric layer of a second thickness thicker than the first thickness; and
the second section bridging the first section and the tapered transition section.
2. The semiconductor device of claim 1 , further comprising:
a first gate material filling the first section of the top trench section; and
a second gate material, electrically insulated from the first gate material, filling the second section of the top trench section.
3. The semiconductor device of claim 1 , further comprising a third dielectric layer with a third thickness greater than the first thickness, covering sidewalls of the transition section of the trench.
4. The semiconductor device of claim 1 , in which the bottom section of the trench is filling with a dielectric material.
5. The semiconductor device of claim 1 , in which the first section vertically bridges two regions of n-type semiconductor material separated by a region of p-type semiconductor material.
6. The semiconductor device of claim 5 , in which one of the two n-type regions is electrically shorted to the p-type region via a metallic element.
7. The semiconductor device of claim 2 , in which the first gate material includes polysilicon.
8. The semiconductor device of claim 2 , in which the second gate material includes polysilicon.
9. The semiconductor device of claim 1 , further comprising a third dielectric layer extending from the second dielectric layer lining sidewalls of the tapered transition section.
10. The semiconductor device of claim 8 , in which the second gate material extends into the tapered section of the trench.
11. The semiconductor device of claim 9 , in which the third dielectric layer extends into the bottom section of the trench.
12. The semiconductor device of claim 1 , in which the bottom section of the trench terminates in a n-type region of the semiconductor substrate.
13. The semiconductor device of claim 5 , in which the first dielectric layer, the two n- type semiconductor regions of, the p-type semiconductor region, and the first gate material form a MOSFET.
14. The semiconductor of claim 1 , in which the first dielectric layer is thermally grown silicon dioxide.
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US13/646,906 US20140054683A1 (en) | 2009-11-17 | 2012-10-08 | Trench devices having improved breakdown voltages and method for manufacturing same |
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US12/620,473 US8314471B2 (en) | 2009-11-17 | 2009-11-17 | Trench devices having improved breakdown voltages and method for manufacturing same |
US13/646,906 US20140054683A1 (en) | 2009-11-17 | 2012-10-08 | Trench devices having improved breakdown voltages and method for manufacturing same |
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US13/646,906 Abandoned US20140054683A1 (en) | 2009-11-17 | 2012-10-08 | Trench devices having improved breakdown voltages and method for manufacturing same |
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US20140252462A1 (en) * | 2013-03-05 | 2014-09-11 | Magnachip Semiconductor, Ltd. | Semiconductor device and method for fabricating the same |
CN105810724A (en) * | 2016-04-29 | 2016-07-27 | 深圳尚阳通科技有限公司 | Shielding gate power device and manufacturing method thereof |
US11276751B2 (en) | 2019-08-07 | 2022-03-15 | Kabushiki Kaisha Toshiba | Semiconductor device, inverter circuit, driving device, vehicle, and elevator |
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CN107871665B (en) * | 2016-09-28 | 2020-04-10 | 台湾半导体股份有限公司 | Field effect transistor with electrode portion sequentially coated by oxide layer and nitride layer and manufacturing method thereof |
JP7230477B2 (en) * | 2018-12-12 | 2023-03-01 | 株式会社デンソー | Manufacturing method of trench gate type switching element |
CN110034182A (en) * | 2019-03-13 | 2019-07-19 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of trench-gate device with shield grid |
CN113571413A (en) * | 2020-04-29 | 2021-10-29 | 芯恩(青岛)集成电路有限公司 | Trench gate structure and forming method |
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Also Published As
Publication number | Publication date |
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CN102064174A (en) | 2011-05-18 |
TW201119037A (en) | 2011-06-01 |
US20110115015A1 (en) | 2011-05-19 |
US8314471B2 (en) | 2012-11-20 |
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