US20130334580A1 - Replacement metal gate processing with reduced interlevel dielectric layer etch rate - Google Patents

Replacement metal gate processing with reduced interlevel dielectric layer etch rate Download PDF

Info

Publication number
US20130334580A1
US20130334580A1 US13/527,828 US201213527828A US2013334580A1 US 20130334580 A1 US20130334580 A1 US 20130334580A1 US 201213527828 A US201213527828 A US 201213527828A US 2013334580 A1 US2013334580 A1 US 2013334580A1
Authority
US
United States
Prior art keywords
layer
gate
ild
gcib
etch rate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/527,828
Inventor
Kangguo Cheng
Junli Wang
Keith Kwong Hon Wong
Chih-Chao Yang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US13/527,828 priority Critical patent/US20130334580A1/en
Priority to CN201310234789.2A priority patent/CN103515244A/en
Publication of US20130334580A1 publication Critical patent/US20130334580A1/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • the present invention relates generally to semiconductor device manufacturing and, more particularly, to implementing replacement metal gate processing with a reduced interlevel dielectric layer (ILD) etch rate.
  • ILD interlevel dielectric layer
  • FETs Field effect transistors
  • MOSFET metal-oxide-semiconductor field effect transistors
  • CMOS Complementary MOS
  • NFET and PFET n-type and p-type FETs are used to fabricate logic and other circuitry.
  • the source and drain regions of an FET are typically formed by adding dopants to targeted regions of a semiconductor body on either side of the channel.
  • a gate structure is formed above the channel, which includes a gate dielectric located over the channel and a gate conductor above the gate dielectric.
  • the gate dielectric is an insulator material, which prevents large leakage currents from flowing into the channel when a voltage is applied to the gate conductor, while allowing the applied gate voltage to set up a transverse electric field in the channel region in a controllable manner.
  • MOS transistors typically include a gate dielectric formed by depositing or by growing silicon dioxide (SiO 2 ) or silicon oxynitride (SiON) over a silicon wafer surface, with doped polysilicon formed over the SiO 2 to act as the gate conductor.
  • SiO 2 silicon dioxide
  • SiON silicon oxynitride
  • MOS transistor performance may be improved by reducing the distance between the source and the drain regions under the gate conductor of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate dielectric that is formed over the semiconductor surface.
  • the thickness of SiO 2 gate dielectrics can be reduced. For example, thin SiO 2 gate dielectrics are prone to gate tunneling leakage currents resulting from direct tunneling of electrons through the thin gate dielectric.
  • High-k dielectric materials having dielectric constants greater than that of SiO 2 (e.g., greater than about 3.9).
  • High-k dielectric materials can be formed in a thicker layer than scaled SiO 2 , and yet still produce equivalent field effect performance.
  • the relative electrical performance of such high-k dielectric materials is often expressed in terms equivalent oxide thickness (EOT), since the high-k material layer may be thicker, while still providing the equivalent electrical effect of a much thinner layer of SiO 2 .
  • EOT equivalent oxide thickness
  • the dielectric constant “k” is higher than silicon dioxide, a thicker high-k dielectric layer can be employed to mitigate tunneling leakage currents, while still achieving the equivalent electrical performance of a thinner layer of thermally grown SiO 2 .
  • semiconductor structure includes an interlevel dielectric (ILD) layer disposed over a semiconductor substrate and a transistor gate structure formed on the substrate; and a shallow gas cluster ion beam (GCIB) layer infused in a top portion of the ILD layer; wherein the GCIB layer has a slower etch rate with respect to the ILD layer.
  • ILD interlevel dielectric
  • GCIB shallow gas cluster ion beam
  • FIG. 1 is a cross sectional view of a processing stage of a high-K, metal gate (HKMG) transistor device using a replacement gate (gate last) technique;
  • HKMG metal gate
  • gate last replacement gate
  • FIG. 2 illustrates the formation of an interlevel dielectric (ILD) layer over the device of FIG. 1 ;
  • ILD interlevel dielectric
  • FIG. 3 illustrates removal of nitride cap and dummy polysilicon portions of the dummy gate stack structure of FIG. 2 ;
  • FIG. 4 illustrates removal of the dummy gate oxide portion of the dummy gate stack structure, as well as a portion of the ILD layer of FIG. 3 ;
  • FIG. 5 illustrates the formation of a gas cluster ion beam (GCIB) layer at the top of the ILD layer prior to dummy gate stack removal, in accordance with an exemplary embodiment
  • FIG. 6 illustrates the removal of the dummy gate stack structure of FIG. 5 , leaving the ILD layer substantially intact;
  • FIG. 7 illustrates the formation of a replacement metal gate structure for the device of FIGS. 6 ;
  • FIG. 8 illustrates an exemplary processor for performing GCIB processing.
  • HKMG high-k metal gate
  • gate first high-k dielectric and metal processing is completed prior to polysilicon gate deposition.
  • the metal gate material is subtractively etched along with the polysilicon gate material prior to source and drain formation.
  • the RMG process architecture avoids the problems of workfunction material stability seen in the gate first architecture.
  • a dummy gate structure is used to self-align the source and drain implant and anneals, followed by stripping out the dummy gate materials and replacing them with the high-k and metal gate materials.
  • advantages of a replacement gate flow include the use of separate PMOS and NMOS metals for work function optimization.
  • the two metals are not exposed to high temperatures, simplifying material selection.
  • the polysilicon gate removal can actually be used to enhance strain techniques, thereby increasing drive currents.
  • an ILD oxide is typically usually used to facilitate the dummy gate removal process after the source/drain and source/drain extensions are defined with the dummy gate in place.
  • an ILD oxide (which is deposited oxide) has a high HF (hydrofluoric acid) etch rate. Due to the high etch rate of ILD oxide, certain HF processing operations during dummy gate stack removal (e.g., HF precleaning before dummy poly removal, as well as HF etching to remove dummy gate oxide) cause recessing/loss of ILD material, which in turn results in variations in the final metal gate height across the wafer. Another issue may be excess metal gate fill material that does not get remove during planarization, which can in turn lead to device shorting.
  • a densification anneal is incompatible with CMOS flow because it will cause excessive dopant diffusion.
  • Another technique may be to perform an ion implantation of a material such as silicon to increase the etch rate of the SiO 2 .
  • the depth of such an ion implantation is difficult to precisely control.
  • undesired dopant atoms may reach locations such as the dummy polysilicon in the gate stack and/or even the source/drain diffusion regions of the substrate.
  • the exemplary embodiments disclosed herein address the above described problems by improving the etch resistivity of the deposited ILD oxide, but without the side effects of a high temperature, dopant diffusing process or a high energy ion implantation process. More specifically, the etch rate of ILD oxide is reduced by a low temperature process, namely a gas cluster ion beam (GCIB) implantation process.
  • GCIB gas cluster ion beam
  • the transistor device 100 includes semiconductor substrate 102 having shallow trench isolation (STI) regions 104 formed therein.
  • the semiconductor substrate 102 includes a semiconductor material, which may be selected from, but is not limited to, silicon, germanium, silicon-germanium alloy, silicon carbon alloy, silicon-germanium-carbon alloy, gallium arsenide, indium arsenide, indium phosphide, III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, and other compound semiconductor materials.
  • the single crystalline silicon-containing semiconductor material may be selected from single crystalline silicon, a single crystalline silicon carbon alloy, a single crystalline silicon germanium alloy, and a single crystalline silicon germanium carbon alloy.
  • the semiconductor material of the semiconductor substrate 102 may be appropriately doped either with p-type dopant atoms or with n-type dopant atoms.
  • the dopant concentration of the semiconductor substrate 102 may range from about 1.0 ⁇ 10 15 atoms/cm 3 to about 1.0 ⁇ 10 19 atoms/cm 3 , and more specifically from about 1.0 ⁇ 10 16 atoms/cm 3 to about 3.0 ⁇ 10 18 atoms/cm 3 , although lesser and greater dopant concentrations are contemplated herein also.
  • the semiconductor substrate 102 may be a bulk substrate, a semiconductor-on-insulator or silicon-on-insulator (SOI) substrate, a hybrid substrate, or a finFET substrate.
  • the STI regions 104 may include an oxide material and be formed by any techniques known in the art, such as by patterning/etching/deposition, implantation, etc.
  • the specific point in processing depicted in FIG. 1 is following dummy gate stack deposition, pattering, sidewall spacer formation, and source/drain region and extension implant.
  • FIG. 1 further illustrates a dummy gate stack formed over the substrate 102 , including a dummy gate oxide layer 106 , a dummy polysilicon layer 108 on the dummy gate oxide layer 106 , and a dummy nitride cap layer 110 on the dummy polysilicon layer 108 .
  • gate sidewall spacers 112 e.g., nitride
  • the definition of the patterned dummy gate stack allows for source and drain extension region implantation, as shown at 114 .
  • the main source and drain extension regions 116 can then be implanted as well.
  • the source/drain regions 116 may also have embedded source/drain stressor layers and/or may comprised raised source/drain for stress enhancement, carrier mobility and/or resistivity reduction purposes (not shown).
  • FIG. 2 illustrates the formation of an interlevel dielectric (ILD) layer 118 over the device of FIG. 1 .
  • ILD interlevel dielectric
  • This may include, for example, a low temperature deposition of an oxide layer such as SiO 2 .
  • the ILD layer 118 is planarized such as by chemical mechanical polishing (CMP), stopping on the dummy nitride cap layer 110 .
  • CMP chemical mechanical polishing
  • FIG. 3 the removal of nitride cap and dummy polysilicon portions of the dummy gate stack structure of FIG. 2 is illustrated.
  • suitable etch chemistries are applied so as to remove the nitride and polysilicon layers.
  • the directional (e.g., RIE) etch of the gate stack material may also result in a reduction in height of the sidewall spacers 112 .
  • the etch chemistry is then altered to remove the dummy gate oxide layer 106 .
  • FIG. 3 the etch chemistry is then altered to remove the dummy gate oxide layer 106 .
  • the removal of dummy gate oxide layer may also causes a significant reduction in the height of the ILD layer, now indicated at 118 ′.
  • Such a condition as depicted in FIG. 4 may lead to device problems such as final metal gate height variations, as well as device shorting.
  • FIG. 5 illustrates the formation of a gas cluster ion beam (GCIB) layer 120 infused at a top portion of the ILD layer 118 prior to dummy gate stack removal, in accordance with an exemplary embodiment.
  • GCIB gas cluster ion beam
  • a surface is bombarded by a beam of high energy, gas phase atomic clusters.
  • the clusters are formed when a high pressure gas (e.g., 10 atmospheres) supersonically expands into a vacuum (e.g., 1 ⁇ 10 -5 Torr), cools, and then condenses into weakly ionized clusters.
  • the ionized clusters are accelerated electrostatically to very high velocities, and are focused into a tight beam that impacts a substrate surface.
  • atoms of a cluster ion impact interact nearly simultaneously with the substrate atoms, which produces results such as surface smoothing, pore sealing, shallow cratering, surface chemistry alterations, thin film deposition, and shallow implantation or infusing, depending upon whether the gas clusters are inert or reactive.
  • a GCIB may include chemical beams of almost any species or mixture, depending on the specific objectives of the processing.
  • Exemplary beams may include, for example, silicon (Si), nitrogen (N) or carbon (C) for film deposition, fluorine (F) for etching, and argon (Ar), N, C, or oxygen (O) for surface modification.
  • a silicon species is used in the GCIB processing to form a silicon rich oxide GCIB layer 120 .
  • the silicon rich oxide GCIB layer 120 has an etch rate of about 5 times slower than that of the SiO 2 ILD layer 118 .
  • the GCIB formation results in the silicon rich oxide GCIB layer 120 having a relatively shallow thickness, on the order of about 10 nm or less. This may be compared to a total ILD layer height of, for example, about 40 nm.
  • the more etch resistant silicon rich oxide GCIB layer 120 allows the ILD layer 118 to remain substantially intact.
  • replacement gate processing may continue as known in the art, including formation and planarization of one or more high-k gate dielectric layers 122 and metal gate layers 124 .
  • the high-K dielectric layer 122 may include a dielectric metal oxide having a dielectric constant that is greater than the dielectric constant (7.5) of silicon nitride, and may be formed by methods well known in the art including, for example, chemical vapor deposition (CVD), ALD, molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), etc.
  • the dielectric metal oxide of the high-k dielectric layer 122 includes a metal and oxygen, and optionally nitrogen and/or silicon.
  • high-k dielectric materials include, but are not limited to: HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , a silicate thereof, and an alloy thereof.
  • Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2.
  • the thickness of the high-k dielectric layer 122 may be from about 1 nm to about 10 nm, and more specifically from about 1.5 nm to about 3 nm.
  • the metal gate layer 124 may be a metal gate material stack that includes one or more layers of metal materials such as, for example, Al, Ta, TaN, W, WN, Ti and TiN, having an appropriate workfunction depending on whether the transistor is an NFET or a PFET device.
  • metal materials such as, for example, Al, Ta, TaN, W, WN, Ti and TiN, having an appropriate workfunction depending on whether the transistor is an NFET or a PFET device.
  • the metal gate layer 124 may include workfunction setting metal layers selected to set the workfunction around the silicon conduction band edge.
  • workfunction setting metal layers may include, for example, optional layers of about 10 ⁇ to about 30 ⁇ thick titanium nitride and about 10 ⁇ to about 30 ⁇ thick tantalum nitride, followed by a non-optional about 10 ⁇ to about 40 ⁇ thick layer of titanium aluminum, which together make up a workfunction setting metal layer portion of the metal gate layer 106 .
  • titanium aluminum nitride, tantalum aluminum, tantalum aluminum nitride, hafnium silicon alloy, hafnium nitride, or tantalum carbide may be used in the workfunction setting metal layer portion in lieu of the titanium aluminum.
  • the metal gate layer 124 may include workfunction setting metal layers selected to set the workfunction around the silicon valence band edge.
  • workfunction setting metal layers may include, for example, optional layers of about 10 ⁇ to about 30 ⁇ thick titanium nitride and about 10 ⁇ to about 30 ⁇ thick tantalum nitride, followed by non-optional layers of about 30 ⁇ to about 70 ⁇ thick titanium nitride and about 10 ⁇ to about 40 ⁇ thick layer of titanium aluminum, which together make up a workfunction setting metal layer portion of the metal gate layer 124 .
  • tungsten, tantalum nitride, ruthenium, platinum, rhenium, iridium, or palladium may be used in the workfunction setting metal layer portion in lieu of the titanium nitride and titanium aluminum nitride, tantalum aluminum, tantalum aluminum nitride, hafnium silicon alloy, hafnium nitride, or tantalum carbide may be deposited instead of the titanium aluminum.
  • a remainder of the metal gate layer 106 may include a fill metal such as aluminum, titanium-doped aluminum, tungsten or copper.
  • FIG. 8 illustrates an exemplary processor 800 for performing GCIB processing as described above.
  • the processor 800 is enclosed in a vacuum vessel 802 having a source chamber 804 and a processing chamber 806 .
  • a differential vacuum pumping chamber 808 to help isolate the downstream regions from the higher pressure upstream regions.
  • the interior of the vacuum vessel 802 is maintained at a vacuum reduced pressure by one or more vacuum pumps 810 .
  • a source gas 812 is introduced through a gas feed tube 814 .
  • Gas clusters 816 are formed by creating a supersonic jet of source gas through a properly shaped nozzle 818 into the source chamber 43 , which is at a substantially reduced pressure.
  • a gas skimmer aperture 820 is used to separate the gas products that have not been converted into a cluster jet from the cluster jet so as to minimize pressure in the downstream regions where such higher pressures would be detrimental (e.g., ionizer 822 , accelerator high voltage electrodes 824 , and processing chamber 806 ).
  • Suitable source gases 812 include, for example, argon, other inert gases, oxygen, nitrogen, oxygen bearing gases such as carbon dioxide, and silicon bearing gases.
  • the ionizer 322 may be an electron impact ionizer that produces thermoelectrons from one or more incandescent filaments and accelerates and directs the electrons causing them to collide with the gas clusters 816 in the gas cluster jet where it passes through the ionizer 822 .
  • the electron impact ejects electrons from the clusters, causing the clusters to become positively ionized.
  • a set of suitably biased high voltage lens electrodes 826 extracts the cluster ions from the ionizer and focuses them to form a gas cluster ion beam.
  • Another set of high voltage accelerator electrodes 824 accelerates the beam to a desired energy, for example, from 1 keV to several tens of keV. The accelerated beam is directed at a substrate 828 for GCIB processing.
  • a mass selector may be utilized for selecting clusters of a certain mass or within a certain range of masses.
  • Such a mass selector can be, for example, a weak transverse magnetic field for deflecting monomer ions and other light ions (e.g., those cluster ions often or fewer atoms or molecules) out of the beam and passing more massive cluster ions.
  • a scanning system 830 is may be used in order to uniformly scan the GCIB across large areas to produce spatially homogeneous results.
  • two pairs of orthogonally oriented electrostatic scan plates 832 and 834 make up scanning system 830 , and having suitable beam scanning voltage waveforms imposed can be utilized to produce a raster or other scanning pattern across the desired area.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure includes an interlevel dielectric (ILD) layer disposed over a semiconductor substrate and a transistor gate structure formed on the substrate; and a shallow gas cluster ion beam (GCIB) layer infused in a top portion of the ILD layer; wherein the GCIB layer has a slower etch rate with respect to the ILD layer.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a continuation of U.S. patent application Ser. No. 13/524,576, filed Jun. 15, 2012, the disclosure of which is incorporated by reference herein in its entirety.
    • BACKGROUND
  • The present invention relates generally to semiconductor device manufacturing and, more particularly, to implementing replacement metal gate processing with a reduced interlevel dielectric layer (ILD) etch rate.
  • Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field effect transistors (MOSFET or MOS), in which a gate structure is energized to create an electric field in an underlying channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. Complementary MOS (CMOS) devices have become widely used in the semiconductor industry, wherein both n-type and p-type (NFET and PFET) FETs are used to fabricate logic and other circuitry.
  • The source and drain regions of an FET are typically formed by adding dopants to targeted regions of a semiconductor body on either side of the channel. A gate structure is formed above the channel, which includes a gate dielectric located over the channel and a gate conductor above the gate dielectric. The gate dielectric is an insulator material, which prevents large leakage currents from flowing into the channel when a voltage is applied to the gate conductor, while allowing the applied gate voltage to set up a transverse electric field in the channel region in a controllable manner. Conventional MOS transistors typically include a gate dielectric formed by depositing or by growing silicon dioxide (SiO2) or silicon oxynitride (SiON) over a silicon wafer surface, with doped polysilicon formed over the SiO2 to act as the gate conductor.
  • Continuing trends in semiconductor device manufacturing include reduction in electrical device feature sizes (i.e., scaling), as well as improvements in device performance in terms of device switching speed and power consumption. MOS transistor performance may be improved by reducing the distance between the source and the drain regions under the gate conductor of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate dielectric that is formed over the semiconductor surface. However, there are electrical and physical limitations on the extent to which the thickness of SiO2 gate dielectrics can be reduced. For example, thin SiO2 gate dielectrics are prone to gate tunneling leakage currents resulting from direct tunneling of electrons through the thin gate dielectric.
  • Accordingly, recent MOS and CMOS transistor scaling efforts have focused on high-k dielectric materials having dielectric constants greater than that of SiO2 (e.g., greater than about 3.9). High-k dielectric materials can be formed in a thicker layer than scaled SiO2, and yet still produce equivalent field effect performance. The relative electrical performance of such high-k dielectric materials is often expressed in terms equivalent oxide thickness (EOT), since the high-k material layer may be thicker, while still providing the equivalent electrical effect of a much thinner layer of SiO2. Because the dielectric constant “k” is higher than silicon dioxide, a thicker high-k dielectric layer can be employed to mitigate tunneling leakage currents, while still achieving the equivalent electrical performance of a thinner layer of thermally grown SiO2.
    • SUMMARY
  • In one aspect, semiconductor structure includes an interlevel dielectric (ILD) layer disposed over a semiconductor substrate and a transistor gate structure formed on the substrate; and a shallow gas cluster ion beam (GCIB) layer infused in a top portion of the ILD layer; wherein the GCIB layer has a slower etch rate with respect to the ILD layer.
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:
  • FIG. 1 is a cross sectional view of a processing stage of a high-K, metal gate (HKMG) transistor device using a replacement gate (gate last) technique;
  • FIG. 2 illustrates the formation of an interlevel dielectric (ILD) layer over the device of FIG. 1;
  • FIG. 3 illustrates removal of nitride cap and dummy polysilicon portions of the dummy gate stack structure of FIG. 2;
  • FIG. 4 illustrates removal of the dummy gate oxide portion of the dummy gate stack structure, as well as a portion of the ILD layer of FIG. 3;
  • FIG. 5 illustrates the formation of a gas cluster ion beam (GCIB) layer at the top of the ILD layer prior to dummy gate stack removal, in accordance with an exemplary embodiment;
  • FIG. 6 illustrates the removal of the dummy gate stack structure of FIG. 5, leaving the ILD layer substantially intact;
  • FIG. 7 illustrates the formation of a replacement metal gate structure for the device of FIGS. 6; and
  • FIG. 8 illustrates an exemplary processor for performing GCIB processing.
    •  DETAILED DESCRIPTION
  • With respect to high-k metal gate (HKMG) technology, the two main approaches for introducing a metal gate into the standard CMOS process flow are a “gate first” process or a “gate last” process. The latter is also referred to as a “replacement gate” or replacement metal gate (RMG) process. In a gate first process, high-k dielectric and metal processing is completed prior to polysilicon gate deposition. The metal gate material is subtractively etched along with the polysilicon gate material prior to source and drain formation.
  • The RMG process architecture, on the other hand, avoids the problems of workfunction material stability seen in the gate first architecture. Here, a dummy gate structure is used to self-align the source and drain implant and anneals, followed by stripping out the dummy gate materials and replacing them with the high-k and metal gate materials. Although this process is more complex than the gate first technique, advantages of a replacement gate flow include the use of separate PMOS and NMOS metals for work function optimization. In addition, the two metals are not exposed to high temperatures, simplifying material selection. Further, the polysilicon gate removal can actually be used to enhance strain techniques, thereby increasing drive currents.
  • In current replacement metal gate (RMG) processing, an ILD oxide is typically usually used to facilitate the dummy gate removal process after the source/drain and source/drain extensions are defined with the dummy gate in place. In this regard, an ILD oxide (which is deposited oxide) has a high HF (hydrofluoric acid) etch rate. Due to the high etch rate of ILD oxide, certain HF processing operations during dummy gate stack removal (e.g., HF precleaning before dummy poly removal, as well as HF etching to remove dummy gate oxide) cause recessing/loss of ILD material, which in turn results in variations in the final metal gate height across the wafer. Another issue may be excess metal gate fill material that does not get remove during planarization, which can in turn lead to device shorting.
  • One possible way to reduce the etch rate of a deposited oxide is by high temperature annealing (i.e., a densification anneal). However, such a high temperature anneal is incompatible with CMOS flow because it will cause excessive dopant diffusion. Another technique may be to perform an ion implantation of a material such as silicon to increase the etch rate of the SiO2. Here, however, the depth of such an ion implantation is difficult to precisely control. As a result, undesired dopant atoms may reach locations such as the dummy polysilicon in the gate stack and/or even the source/drain diffusion regions of the substrate.
  • Accordingly, the exemplary embodiments disclosed herein address the above described problems by improving the etch resistivity of the deposited ILD oxide, but without the side effects of a high temperature, dopant diffusing process or a high energy ion implantation process. More specifically, the etch rate of ILD oxide is reduced by a low temperature process, namely a gas cluster ion beam (GCIB) implantation process.
  • Referring initially to FIG. 1, there is shown a cross sectional view of a processing stage of a high-K, metal gate (HKMG) transistor device 100 using a replacement gate (gate last) technique. The transistor device 100 includes semiconductor substrate 102 having shallow trench isolation (STI) regions 104 formed therein. The semiconductor substrate 102 includes a semiconductor material, which may be selected from, but is not limited to, silicon, germanium, silicon-germanium alloy, silicon carbon alloy, silicon-germanium-carbon alloy, gallium arsenide, indium arsenide, indium phosphide, III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, and other compound semiconductor materials. Where the semiconductor material of the semiconductor substrate 102 is a single crystalline silicon-containing semiconductor material, the single crystalline silicon-containing semiconductor material may be selected from single crystalline silicon, a single crystalline silicon carbon alloy, a single crystalline silicon germanium alloy, and a single crystalline silicon germanium carbon alloy.
  • The semiconductor material of the semiconductor substrate 102 may be appropriately doped either with p-type dopant atoms or with n-type dopant atoms. The dopant concentration of the semiconductor substrate 102 may range from about 1.0×1015 atoms/cm3 to about 1.0×1019 atoms/cm3, and more specifically from about 1.0×1016 atoms/cm3 to about 3.0×1018 atoms/cm3, although lesser and greater dopant concentrations are contemplated herein also. In addition, the semiconductor substrate 102 may be a bulk substrate, a semiconductor-on-insulator or silicon-on-insulator (SOI) substrate, a hybrid substrate, or a finFET substrate.
  • The STI regions 104 may include an oxide material and be formed by any techniques known in the art, such as by patterning/etching/deposition, implantation, etc. The specific point in processing depicted in FIG. 1 is following dummy gate stack deposition, pattering, sidewall spacer formation, and source/drain region and extension implant. Thus, FIG. 1 further illustrates a dummy gate stack formed over the substrate 102, including a dummy gate oxide layer 106, a dummy polysilicon layer 108 on the dummy gate oxide layer 106, and a dummy nitride cap layer 110 on the dummy polysilicon layer 108. In addition, gate sidewall spacers 112 (e.g., nitride) are formed adjacent the dummy gate stack.
  • In accordance with a replacement gate process flow, the definition of the patterned dummy gate stack allows for source and drain extension region implantation, as shown at 114. Once the gate sidewall spacers 112 are in place, the main source and drain extension regions 116 can then be implanted as well. It should be appreciated that, in addition to the specific structures depicted in the embodiment of FIG. 1, the source/drain regions 116 may also have embedded source/drain stressor layers and/or may comprised raised source/drain for stress enhancement, carrier mobility and/or resistivity reduction purposes (not shown).
  • FIG. 2 illustrates the formation of an interlevel dielectric (ILD) layer 118 over the device of FIG. 1. This may include, for example, a low temperature deposition of an oxide layer such as SiO2. Following deposition of the oxide ILD material, the ILD layer 118 is planarized such as by chemical mechanical polishing (CMP), stopping on the dummy nitride cap layer 110. At this point, the device is ready for dummy gate removal and HKMG formation.
  • Referring now to FIG. 3, the removal of nitride cap and dummy polysilicon portions of the dummy gate stack structure of FIG. 2 is illustrated. Here, suitable etch chemistries are applied so as to remove the nitride and polysilicon layers. Although not specifically depicted in FIG. 3, the directional (e.g., RIE) etch of the gate stack material (including the dummy nitride cap) may also result in a reduction in height of the sidewall spacers 112. Upon removal of the dummy polysilicon, the etch chemistry is then altered to remove the dummy gate oxide layer 106. However, as shown, in FIG. 4, due to the high etch rate of the ILD oxide material 118 (and perhaps also due to HF exposure during precleaning prior to the dummy polysilicon removal), the removal of dummy gate oxide layer may also causes a significant reduction in the height of the ILD layer, now indicated at 118′. Such a condition as depicted in FIG. 4 may lead to device problems such as final metal gate height variations, as well as device shorting.
  • Accordingly, FIG. 5 illustrates the formation of a gas cluster ion beam (GCIB) layer 120 infused at a top portion of the ILD layer 118 prior to dummy gate stack removal, in accordance with an exemplary embodiment. In GCIB processing, a surface is bombarded by a beam of high energy, gas phase atomic clusters. The clusters are formed when a high pressure gas (e.g., 10 atmospheres) supersonically expands into a vacuum (e.g., 1×10-5 Torr), cools, and then condenses into weakly ionized clusters. The ionized clusters are accelerated electrostatically to very high velocities, and are focused into a tight beam that impacts a substrate surface. As opposed to a more dispersed ion implant process, atoms of a cluster ion impact interact nearly simultaneously with the substrate atoms, which produces results such as surface smoothing, pore sealing, shallow cratering, surface chemistry alterations, thin film deposition, and shallow implantation or infusing, depending upon whether the gas clusters are inert or reactive.
  • A GCIB may include chemical beams of almost any species or mixture, depending on the specific objectives of the processing. Exemplary beams may include, for example, silicon (Si), nitrogen (N) or carbon (C) for film deposition, fluorine (F) for etching, and argon (Ar), N, C, or oxygen (O) for surface modification. In the embodiment depicted, a silicon species is used in the GCIB processing to form a silicon rich oxide GCIB layer 120. The silicon rich oxide GCIB layer 120 has an etch rate of about 5 times slower than that of the SiO2 ILD layer 118. In addition to being a low temperature (e.g., room temperature) infusion process, the GCIB formation results in the silicon rich oxide GCIB layer 120 having a relatively shallow thickness, on the order of about 10 nm or less. This may be compared to a total ILD layer height of, for example, about 40 nm.
  • Accordingly, as shown in FIG. 6, upon removal of the dummy gate structure, including the nitride cap, polysilicon and gate oxide layers, the more etch resistant silicon rich oxide GCIB layer 120 allows the ILD layer 118 to remain substantially intact. Finally, as shown in FIG. 7, replacement gate processing may continue as known in the art, including formation and planarization of one or more high-k gate dielectric layers 122 and metal gate layers 124. In some examples, the high-K dielectric layer 122 may include a dielectric metal oxide having a dielectric constant that is greater than the dielectric constant (7.5) of silicon nitride, and may be formed by methods well known in the art including, for example, chemical vapor deposition (CVD), ALD, molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), etc. In an exemplary embodiment, the dielectric metal oxide of the high-k dielectric layer 122 includes a metal and oxygen, and optionally nitrogen and/or silicon. Specific examples of high-k dielectric materials include, but are not limited to: HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. The thickness of the high-k dielectric layer 122 may be from about 1 nm to about 10 nm, and more specifically from about 1.5 nm to about 3 nm.
  • The metal gate layer 124, while schematically illustrated as a single layer in FIG. 7, may be a metal gate material stack that includes one or more layers of metal materials such as, for example, Al, Ta, TaN, W, WN, Ti and TiN, having an appropriate workfunction depending on whether the transistor is an NFET or a PFET device.
  • In one specific embodiment of an NFET device, the metal gate layer 124 may include workfunction setting metal layers selected to set the workfunction around the silicon conduction band edge. Such workfunction setting metal layers may include, for example, optional layers of about 10 Å to about 30 Å thick titanium nitride and about 10 Å to about 30 Å thick tantalum nitride, followed by a non-optional about 10 Å to about 40 Å thick layer of titanium aluminum, which together make up a workfunction setting metal layer portion of the metal gate layer 106. Alternatively, titanium aluminum nitride, tantalum aluminum, tantalum aluminum nitride, hafnium silicon alloy, hafnium nitride, or tantalum carbide may be used in the workfunction setting metal layer portion in lieu of the titanium aluminum.
  • In one specific embodiment of a PFET device, the metal gate layer 124 may include workfunction setting metal layers selected to set the workfunction around the silicon valence band edge. Here, such workfunction setting metal layers may include, for example, optional layers of about 10 Å to about 30 Å thick titanium nitride and about 10 Å to about 30 Å thick tantalum nitride, followed by non-optional layers of about 30 Å to about 70 Å thick titanium nitride and about 10 Å to about 40 Å thick layer of titanium aluminum, which together make up a workfunction setting metal layer portion of the metal gate layer 124. Alternatively, tungsten, tantalum nitride, ruthenium, platinum, rhenium, iridium, or palladium may be used in the workfunction setting metal layer portion in lieu of the titanium nitride and titanium aluminum nitride, tantalum aluminum, tantalum aluminum nitride, hafnium silicon alloy, hafnium nitride, or tantalum carbide may be deposited instead of the titanium aluminum. Regardless of the specific workfunction setting metal layers used in either an NFET or a PFET device, a remainder of the metal gate layer 106 may include a fill metal such as aluminum, titanium-doped aluminum, tungsten or copper.
  • Finally, FIG. 8 illustrates an exemplary processor 800 for performing GCIB processing as described above. The processor 800 is enclosed in a vacuum vessel 802 having a source chamber 804 and a processing chamber 806. Although not required, it may sometimes be desirable to also employ a differential vacuum pumping chamber 808 to help isolate the downstream regions from the higher pressure upstream regions. The interior of the vacuum vessel 802 is maintained at a vacuum reduced pressure by one or more vacuum pumps 810. A source gas 812 is introduced through a gas feed tube 814. Gas clusters 816 are formed by creating a supersonic jet of source gas through a properly shaped nozzle 818 into the source chamber 43, which is at a substantially reduced pressure.
  • Cooling resulting from the expansion causes the gas to condense into clusters of, for example, from several to several thousand atoms or molecules. A gas skimmer aperture 820 is used to separate the gas products that have not been converted into a cluster jet from the cluster jet so as to minimize pressure in the downstream regions where such higher pressures would be detrimental (e.g., ionizer 822, accelerator high voltage electrodes 824, and processing chamber 806). Suitable source gases 812 include, for example, argon, other inert gases, oxygen, nitrogen, oxygen bearing gases such as carbon dioxide, and silicon bearing gases. After the cluster jet has been formed, the clusters 816 are ionized in an ionizer 822. The ionizer 322 may be an electron impact ionizer that produces thermoelectrons from one or more incandescent filaments and accelerates and directs the electrons causing them to collide with the gas clusters 816 in the gas cluster jet where it passes through the ionizer 822. The electron impact ejects electrons from the clusters, causing the clusters to become positively ionized.
  • A set of suitably biased high voltage lens electrodes 826 extracts the cluster ions from the ionizer and focuses them to form a gas cluster ion beam. Another set of high voltage accelerator electrodes 824 accelerates the beam to a desired energy, for example, from 1 keV to several tens of keV. The accelerated beam is directed at a substrate 828 for GCIB processing. Although not specifically illustrated in FIG. 8, is a mass selector may be utilized for selecting clusters of a certain mass or within a certain range of masses. Such a mass selector can be, for example, a weak transverse magnetic field for deflecting monomer ions and other light ions (e.g., those cluster ions often or fewer atoms or molecules) out of the beam and passing more massive cluster ions.
  • Since the silicon rich layer infusion application contemplates processing of large diameter wafers with spatially uniform results, a scanning system 830 is may be used in order to uniformly scan the GCIB across large areas to produce spatially homogeneous results. In this regard, two pairs of orthogonally oriented electrostatic scan plates 832 and 834 make up scanning system 830, and having suitable beam scanning voltage waveforms imposed can be utilized to produce a raster or other scanning pattern across the desired area.
  • While the invention has been described with reference to a preferred embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (8)

1. A semiconductor structure, comprising:
an interlevel dielectric (ILD) layer disposed over a semiconductor substrate and a planarized replacement transistor gate structure formed on the substrate; and
a shallow gas cluster ion beam (GCIB) layer infused in a top portion of the ILD layer;
wherein the GOB layer has a slower etch rate with respect to the ILD layer.
2. The structure of claim 1, wherein the ILD layer comprises an oxide layer.
3. The structure of claim 2, wherein the transistor gate structure comprises a high-K dielectric layer and a metal gate layer.
4. The structure of claim 3, wherein the etch rate of the GCIB is about 5 times slower than that of the ILD layer.
5. The structure of claim 4, wherein the GCIB comprises a silicon rich oxide.
6. The structure of claim 5, wherein the GCIB layer has a thickness of about 10 nanometers (nm) or less.
7. The structure of claim 6, wherein the ILD layer has a thickness of about 40 nm.
8. The structure of claim 1, further comprising a channel region defined in the semiconductor substrate, below the planarized replacement transistor gate structure, wherein the channel region is free from ions of the shallow GCIB layer infused in the top portion of the ILD layer.
US13/527,828 2012-06-15 2012-06-20 Replacement metal gate processing with reduced interlevel dielectric layer etch rate Abandoned US20130334580A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US13/527,828 US20130334580A1 (en) 2012-06-15 2012-06-20 Replacement metal gate processing with reduced interlevel dielectric layer etch rate
CN201310234789.2A CN103515244A (en) 2012-06-15 2013-06-14 Replacement metal gate processing with reduced interlevel dielectric layer etch rate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/524,576 US8546209B1 (en) 2012-06-15 2012-06-15 Replacement metal gate processing with reduced interlevel dielectric layer etch rate
US13/527,828 US20130334580A1 (en) 2012-06-15 2012-06-20 Replacement metal gate processing with reduced interlevel dielectric layer etch rate

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US13/524,576 Continuation US8546209B1 (en) 2012-06-15 2012-06-15 Replacement metal gate processing with reduced interlevel dielectric layer etch rate

Publications (1)

Publication Number Publication Date
US20130334580A1 true US20130334580A1 (en) 2013-12-19

Family

ID=49229823

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/524,576 Expired - Fee Related US8546209B1 (en) 2012-06-15 2012-06-15 Replacement metal gate processing with reduced interlevel dielectric layer etch rate
US13/527,828 Abandoned US20130334580A1 (en) 2012-06-15 2012-06-20 Replacement metal gate processing with reduced interlevel dielectric layer etch rate

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US13/524,576 Expired - Fee Related US8546209B1 (en) 2012-06-15 2012-06-15 Replacement metal gate processing with reduced interlevel dielectric layer etch rate

Country Status (2)

Country Link
US (2) US8546209B1 (en)
CN (1) CN103515244A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105137518A (en) * 2015-08-25 2015-12-09 浙江大学 Color optical filter insensitive to incident angle and preparation method for the same
US9722076B2 (en) * 2015-08-29 2017-08-01 Taiwan Semiconductor Manufacturning Co., Ltd. Method for manufacturing semiconductor device with contamination improvement
CN107845576A (en) * 2016-09-19 2018-03-27 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN108122983A (en) * 2016-11-30 2018-06-05 台湾积体电路制造股份有限公司 For the structure for manufacturing the technique of multi-gated transistor and generating
CN108875098A (en) * 2017-05-10 2018-11-23 中国科学院微电子研究所 A kind of chemical mechanical polishing technology modeling method and apparatus of high-k/metal gate

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8941177B2 (en) * 2012-06-27 2015-01-27 International Business Machines Corporation Semiconductor devices having different gate oxide thicknesses
US8927359B2 (en) * 2013-02-21 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-composition dielectric for semiconductor device
CN104465984B (en) * 2013-09-17 2017-08-25 中芯国际集成电路制造(北京)有限公司 MTJ and forming method thereof
CN104681428A (en) * 2013-11-26 2015-06-03 中芯国际集成电路制造(上海)有限公司 Transistor structure and forming method thereof
CN104733294A (en) * 2013-12-18 2015-06-24 中芯国际集成电路制造(上海)有限公司 Semiconductor device and forming method thereof
CN105845627A (en) * 2015-01-14 2016-08-10 中芯国际集成电路制造(上海)有限公司 Semiconductor device, manufacturing method therefor, and electronic device
KR102410146B1 (en) * 2015-06-26 2022-06-16 삼성전자주식회사 Fabricating method of semiconductor device
US9570318B1 (en) 2015-07-22 2017-02-14 International Business Machines Corporation High-k and p-type work function metal first fabrication process having improved annealing process flows
US9577102B1 (en) 2015-09-25 2017-02-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming gate and finFET
CN106847694B (en) 2015-12-03 2019-09-27 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor devices
US10115624B2 (en) * 2016-06-30 2018-10-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method of semiconductor integrated circuit fabrication
CN107680956B (en) 2016-08-02 2019-12-03 中芯国际集成电路制造(北京)有限公司 Static discharge ESD protective device and the method for protecting circuit
KR102575420B1 (en) 2016-10-05 2023-09-06 삼성전자주식회사 Semiconductor devices and methods of manufacturing the same
US10020401B2 (en) * 2016-11-29 2018-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for straining a transistor gate through interlayer dielectric (ILD) doping schemes
KR102564326B1 (en) 2018-10-29 2023-08-08 삼성전자주식회사 Semiconductor devices and method of the same
CN113539826A (en) * 2020-04-17 2021-10-22 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN112289681A (en) * 2020-10-28 2021-01-29 上海华力集成电路制造有限公司 Method for removing amorphous silicon layer in groove

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5869394A (en) 1996-10-29 1999-02-09 Mosel Vitelic, Inc. Teos-ozone planarization process
US6331227B1 (en) 1999-12-14 2001-12-18 Epion Corporation Enhanced etching/smoothing of dielectric surfaces
US6607950B2 (en) * 2000-03-30 2003-08-19 Interuniversitair Microelektronic Centrum (Imec) MIS transistors with a metal gate and high-k dielectric and method of forming
EP1348227B1 (en) 2000-12-26 2006-08-16 Epion Corporation Charging control and dosimetry system and method for gas cluster ion beam
US7115511B2 (en) 2002-11-08 2006-10-03 Epion Corporation GCIB processing of integrated circuit interconnect structures
US20040229452A1 (en) 2003-05-15 2004-11-18 Johnston Steven W. Densifying a relatively porous material
US7071122B2 (en) 2003-12-10 2006-07-04 International Business Machines Corporation Field effect transistor with etched-back gate dielectric
EP1807859A2 (en) 2004-10-25 2007-07-18 TEL Epion Inc. Ionizer and method for gas-cluster ion-beam formation
US20070184656A1 (en) * 2004-11-08 2007-08-09 Tel Epion Inc. GCIB Cluster Tool Apparatus and Method of Operation
US7138308B2 (en) * 2004-12-14 2006-11-21 International Business Machines Corporation Replacement gate with TERA cap
US7405152B2 (en) 2005-01-31 2008-07-29 International Business Machines Corporation Reducing wire erosion during damascene processing
US7504135B2 (en) 2005-02-03 2009-03-17 Samsung Electronics Co., Ltd Method of fabricating a manganese diffusion barrier
US7186992B2 (en) 2005-02-07 2007-03-06 Hewlett-Packard Development Company, L.P. Method of fabricating a polarizing layer on an interface
US20060292762A1 (en) * 2005-06-22 2006-12-28 Epion Corporation Replacement gate field effect transistor with germanium or SiGe channel and manufacturing method for same using gas-cluster ion irradiation
US7709345B2 (en) 2006-03-07 2010-05-04 Micron Technology, Inc. Trench isolation implantation
US7838428B2 (en) * 2006-03-23 2010-11-23 International Business Machines Corporation Method of repairing process induced dielectric damage by the use of GCIB surface treatment using gas clusters of organic molecular species
US20080076191A1 (en) 2006-09-22 2008-03-27 Texas Instruments Incorporated GCIB smoothing of the contact level to improve PZT films
US20080090402A1 (en) 2006-09-29 2008-04-17 Griselda Bonilla Densifying surface of porous dielectric layer using gas cluster ion beam
US8026135B2 (en) * 2007-08-15 2011-09-27 Texas Instruments Incorporated Formation of shallow junctions by diffusion from a dielectric doped by cluster or molecular ion beams
US8298432B2 (en) 2007-09-28 2012-10-30 Tel Epion Inc. Method and system for adjusting beam dimension for high-gradient location specific processing
US8293126B2 (en) 2007-09-28 2012-10-23 Tel Epion Inc. Method and system for multi-pass correction of substrate defects
US7696495B2 (en) 2007-09-28 2010-04-13 Tel Epion Inc. Method and device for adjusting a beam property in a gas cluster ion beam system
US7790559B2 (en) * 2008-02-27 2010-09-07 International Business Machines Corporation Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes
CN101276790A (en) * 2008-05-21 2008-10-01 友达光电股份有限公司 Method for preparing thin-film transistor array substrate and liquid crystal display panel
US20090314963A1 (en) * 2008-06-24 2009-12-24 Tel Epion Inc. Method for forming trench isolation
US7939392B2 (en) * 2008-10-06 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method for gate height control in a gate last process
US8304033B2 (en) * 2009-02-04 2012-11-06 Tel Epion Inc. Method of irradiating substrate with gas cluster ion beam formed from multiple gas nozzles
US8097860B2 (en) 2009-02-04 2012-01-17 Tel Epion Inc. Multiple nozzle gas cluster ion beam processing system and method of operating
US20100193898A1 (en) 2009-02-04 2010-08-05 Tel Epion Inc. Method for forming trench isolation using gas cluster ion beam processing
US7968422B2 (en) 2009-02-09 2011-06-28 Tel Epion Inc. Method for forming trench isolation using a gas cluster ion beam growth process
US8226835B2 (en) 2009-03-06 2012-07-24 Tel Epion Inc. Ultra-thin film formation using gas cluster ion beam processing
US7982196B2 (en) * 2009-03-31 2011-07-19 Tel Epion Inc. Method for modifying a material layer using gas cluster ion beam processing
US7985690B2 (en) * 2009-06-04 2011-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for a gate last process
US8288271B2 (en) 2009-11-02 2012-10-16 International Business Machines Corporation Method for reworking antireflective coating over semiconductor substrate
US8992785B2 (en) * 2010-01-15 2015-03-31 Tel Epion Inc. Method for modifying an etch rate of a material layer using energetic charged particles
US8193094B2 (en) * 2010-06-21 2012-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Post CMP planarization by cluster ION beam etch
CN102479722B (en) * 2010-11-30 2014-03-12 中芯国际集成电路制造(北京)有限公司 Method for manufacturing transistor
US8334198B2 (en) * 2011-04-12 2012-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a plurality of gate structures
US20120326230A1 (en) * 2011-06-22 2012-12-27 International Business Machines Corporation Silicon on insulator complementary metal oxide semiconductor with an isolation formed at low temperature
US20130115773A1 (en) * 2011-11-04 2013-05-09 Globalfoundries Inc. Prevention of ILD Loss in Replacement Gate Technologies by Surface Treatmen

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105137518A (en) * 2015-08-25 2015-12-09 浙江大学 Color optical filter insensitive to incident angle and preparation method for the same
US9722076B2 (en) * 2015-08-29 2017-08-01 Taiwan Semiconductor Manufacturning Co., Ltd. Method for manufacturing semiconductor device with contamination improvement
US11004973B2 (en) 2015-08-29 2021-05-11 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device with contamination improvement
US10312366B2 (en) 2015-08-29 2019-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with contamination improvement
CN107845576A (en) * 2016-09-19 2018-03-27 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
US10177006B2 (en) 2016-11-30 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Process for making multi-gate transistors and resulting structures
KR20180062337A (en) * 2016-11-30 2018-06-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Process for making multi-gate transistors and resulting structures
KR101996139B1 (en) * 2016-11-30 2019-07-03 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Process for making multi-gate transistors and resulting structures
US10361094B2 (en) 2016-11-30 2019-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Process for making multi-gate transistors and resulting structures
TWI685031B (en) * 2016-11-30 2020-02-11 台灣積體電路製造股份有限公司 Transistor and method of forming the same
US10854471B2 (en) 2016-11-30 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Process for making multi-gate transistors and resulting structures
CN108122983A (en) * 2016-11-30 2018-06-05 台湾积体电路制造股份有限公司 For the structure for manufacturing the technique of multi-gated transistor and generating
US11532485B2 (en) 2016-11-30 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Process for making multi-gate transistors and resulting structures
CN108875098A (en) * 2017-05-10 2018-11-23 中国科学院微电子研究所 A kind of chemical mechanical polishing technology modeling method and apparatus of high-k/metal gate

Also Published As

Publication number Publication date
US8546209B1 (en) 2013-10-01
CN103515244A (en) 2014-01-15

Similar Documents

Publication Publication Date Title
US8546209B1 (en) Replacement metal gate processing with reduced interlevel dielectric layer etch rate
US9680015B2 (en) Dual epitaxy CMOS processing using selective nitride formation for reduced gate pitch
US10103264B2 (en) Channel strain control for nonplanar compound semiconductor devices
US8530974B2 (en) CMOS structure having multiple threshold voltage devices
US9484359B2 (en) MOSFET with work function adjusted metal backgate
US6621114B1 (en) MOS transistors with high-k dielectric gate insulator for reducing remote scattering
US8062946B2 (en) Strained channel transistor structure with lattice-mismatched zone and fabrication method thereof
US8421132B2 (en) Post-planarization UV curing of stress inducing layers in replacement gate transistor fabrication
TWI476823B (en) Semiconductor device and method for maunfacturing semiconductor device with metal gate
US9899270B2 (en) Methods for manufacturing semiconductor devices
US20160163603A1 (en) Pfet gate stack materials having improved threshold voltage, mobility and nbti performance
US20090114995A1 (en) Complementary semiconductor device and method of manufacturing the same
US20070069298A1 (en) Mobility enhancement by strained channel CMOSFET with single workfunction metal-gate and fabrication method thereof
US8384162B2 (en) Device having adjustable channel stress and method thereof
US9449887B2 (en) Method of forming replacement gate PFET having TiALCO layer for improved NBTI performance
US8592911B2 (en) Asymmetric semiconductor device having a high-k/metal gate and method of manufacturing the same
US10056261B2 (en) P type MOSFET
US20170309723A1 (en) Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or iii-v channel of semiconductor device
CN103377930A (en) Semiconductor structure and manufacturing method thereof
US20230063388A1 (en) Semiconductor arrangement and method of making
US20120329228A1 (en) Method for forming a strained semiconductor channel
US11728383B2 (en) Localized stressor formation by ion implantation
US20130328135A1 (en) Preventing fully silicided formation in high-k metal gate processing

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001

Effective date: 20150629

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001

Effective date: 20150910