CN105845627A - Semiconductor device, manufacturing method therefor, and electronic device - Google Patents
Semiconductor device, manufacturing method therefor, and electronic device Download PDFInfo
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- CN105845627A CN105845627A CN201510019286.2A CN201510019286A CN105845627A CN 105845627 A CN105845627 A CN 105845627A CN 201510019286 A CN201510019286 A CN 201510019286A CN 105845627 A CN105845627 A CN 105845627A
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Abstract
The invention relates to a semiconductor device, a manufacturing method, and an electronic device. The method comprises the steps: S1, providing a semiconductor substrate, and forming a virtual grid structure on the semiconductor substrate, wherein the virtual grid structure comprises a virtual grid dielectric layer; S2, depositing a first interlayer dielectric layer on the semiconductor substrate till the first interlayer dielectric layer reaches the a part below the top of the virtual grid structure; S3, forming a second interlayer dielectric layer on the first interlayer dielectric layer till the second interlayer dielectric layer reaches the a part above the top of the virtual grid structure, wherein the second interlayer dielectric layer and the virtual grid dielectric layer have a bigger etching selection ratio; S4, executing a flattening step till the virtual grid structure, and then removing the virtual grid structure. The method not only can reduce the loss of the interlayer dielectric layers in a process of removing a virtual grid electrode, but also can avoid a groove in a flattening process, and further improves the performance and yield of the semiconductor device.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of semiconductor device and system thereof
Preparation Method, electronic installation.
Background technology
Along with the development of semiconductor technology, the raising of performance of integrated circuits is mainly by constantly contracting
The size of little IC-components, to improve what its speed realized.At present, high device is pursued close
The semi-conductor industry of degree, high-performance and low cost has advanced to nanotechnology process node, particularly
When dimensions of semiconductor devices drops to lower Nano grade, the preparation of semiconductor device receives various physics
The restriction of the limit.
When the size of semiconductor device drops to lower Nano grade, gate critical dimension (gate in device
CD) 24nm it is reduced into accordingly.Along with the reduction of technology node, traditional gate dielectric layer constantly becomes
Thin, transistor leakage amount increases therewith, causes the problems such as semiconductor device power wastage.On solving
Stating problem, avoid high-temperature process simultaneously, prior art provides a kind of and high-K metal gate is substituted
The solution of polysilicon gate.
" post tensioned unbonded prestressed concrete (high-K&gate last) " technique is to form one of high-K metal gate mainly at present
Technique.The method using " post tensioned unbonded prestressed concrete (high-K&gate last) " technique to form high-K metal gate includes:
Substrate is provided, described substrate is formed virtual grid structure (dummy gate) and is positioned at described substrate
The interlayer dielectric layer of the described virtual grid structure of upper covering；Using described virtual grid structure as stop-layer, right
Described interlayer dielectric layer carries out CMP process；Groove is formed after removing described virtual grid structure；
Finally to described trench fill high K dielectric and metal level, to form high-K metal gate.
Along with constantly reducing of semiconductor device, in said method during removing described dummy gate such as
The loss of what described interlayer dielectric layer of reduction, and how to avoid the occurrence of recessed in interlayer dielectric layer flatening
Groove, it is thus achieved that even curface, becomes the huge challenge in logical device preparation process.
Therefore, how to put down middle acquisition of metal gates preparation and other techniques (such as Finfet technique)
Smooth surface becomes the problem needing to solve, although having in prior art by injecting in interlayer dielectric layer
The methods such as ion improve the loss of interlayer dielectric layer, but described method not only complex steps, increase work
Skill step, and technical process is difficult to control, so needing further to change current preparation method
Enter, in order to eliminate the problems referred to above.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will be in specific embodiment party
Formula part further describes.The Summary of the present invention is not meant to attempt to limit
Go out key feature and the essential features of technical scheme required for protection, more do not mean that and attempt really
The protection domain of fixed technical scheme required for protection.
The present invention is in order to overcome the problem of presently, there are, it is provided that the preparation method of a kind of semiconductor device,
Including:
Step S1: Semiconductor substrate is provided, is formed with dummy gate structure on the semiconductor substrate,
Wherein, described dummy gate structure includes dummy gate dielectric layer；
Step S2: deposit the first interlayer dielectric layer on the semiconductor substrate to described dummy gate structure
Below top；
Step S3: form the second interlayer dielectric layer on described first interlayer dielectric layer to described dummy gate
More than structural top, wherein, the forming method of described second interlayer dielectric layer is: continue deposition described the
One interlayer dielectric layer in situ doping C, to form described second interlayer dielectric layer；Or deposition is rich in silicon
Interlayer dielectric layer, to form described second interlayer dielectric layer；Or deposition is rich in the interlayer dielectric layer of silicon former
Position doping C, to form described second interlayer dielectric layer；
Step S4: perform planarisation step extremely described dummy gate structure, then remove described dummy gate
Structure.
Alternatively, the described interlayer dielectric layer rich in silicon selects the oxide rich in silicon.
Alternatively, between described step S3 and described step S4, may further include the described second layer
Between deposit the step of dielectric layer between third layer on dielectric layer, to cover described second interlayer dielectric layer.
Alternatively, in described step S4, select, with described second interlayer dielectric layer, there is bigger etching ratio
Wet etching remove described dummy gate dielectric layer.
Alternatively, described step S4 includes:
Step S41: select dry etching to remove part described dummy gate dielectric layer；
Step S42: selection and described second interlayer dielectric layer have the wet etching of bigger etching ratio and remove
Remaining described gate dielectric.
Alternatively, in described step S2, deposit described first interlayer dielectric layer to close to described virtual grid
Electrode structure top.
Alternatively, described method still further comprises the step forming high-K metal gate, described high karat gold
Belong to grid and include the high-K metal gate in plane and FinFET technique.
Alternatively, in described step S1, described Semiconductor substrate is formed with fleet plough groove isolation structure,
To form NMOS area and PMOS area in described Semiconductor substrate.
Present invention also offers a kind of semiconductor device prepared based on above-mentioned method.
Present invention also offers a kind of electronic installation, including above-mentioned semiconductor device.
In order to reduce the loss of interlayer dielectric layer during removing dummy gate, and control interlayer Jie
Cave in during electric layer CMP, the invention provides the preparation side of a kind of new semiconductor device
Method, described method first deposit interlayer dielectric to dummy gate height close proximity, then followed by
Adulterate during continuous interlevel dielectric deposition C in situ, or deposition is rich in the oxide skin(coating) of silicon, or
Adulterate during deposition is rich in the oxide skin(coating) of silicon C in situ, described doping C or the dielectric of silicon
Layer has bigger etching selectivity with described dummy gate, is possible not only in the mistake removing dummy gate
Journey reduces the loss amount of interlayer dielectric layer, it is also possible in planarization process, avoid the occurrence of groove, enter
One step improves performance and the yield of semiconductor device.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.In accompanying drawing
Show embodiments of the invention and description thereof, be used for explaining assembly of the invention and principle.At accompanying drawing
In,
Fig. 1 a-1d is the preparation process signal of semiconductor device described in the present invention one specifically implements
Figure；
Fig. 2 is the process chart of the preparation of semiconductor device described in the present invention one specifically implements.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention the most thoroughly
Understand.It is, however, obvious to a person skilled in the art that the present invention can be without one
Or multiple these details and be carried out.In other example, in order to avoid obscuring with the present invention,
Technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and should not be construed as being limited to this
In propose embodiment.On the contrary, it is open thoroughly with complete to provide these embodiments to make, and incite somebody to action this
The scope of invention fully passes to those skilled in the art.In the accompanying drawings, in order to clear, Ceng He district
Size and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
It should be understood that when element or layer be referred to as " ... on ", " with ... adjacent ", " being connected to " or " coupling
Conjunction is arrived " other element or during layer, its can directly on other element or layer, adjacent thereto, connect
Or be coupled to other element or layer, or element between two parties or layer can be there is.On the contrary, claimed when element
For " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other yuan
When part or layer, the most there is not element between two parties or layer.Although it should be understood that can use term first,
Two, the various element of third description, parts, district, floor and/or part, these elements, parts, district,
Layer and/or part should not be limited by these terms.These terms be used merely to distinguish an element, parts,
District, floor or part and another element, parts, district, floor or part.Therefore, without departing from the present invention
Under teaching, the first element discussed below, parts, district, floor or part be represented by the second element,
Parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ... under ",
" ... on ", " above " etc., here can describe for convenience and be used thus in description figure
A shown element or feature and other element or the relation of feature.It should be understood that except shown in figure
Orientation beyond, spatial relationship term is intended to also include the different orientation of device in using and operating.Example
As, if the device upset in accompanying drawing, then, it is described as " below other element " or " its it
Under " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, example
Property term " ... below " and " ... under " upper and lower two orientations can be included.Device can additionally take
Correspondingly explained to (90-degree rotation or other orientation) and spatial description language as used herein.
The purpose of term as used herein is only that description specific embodiment and the limit not as the present invention
System.When using at this, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to include plural number
Form, unless context is expressly noted that other mode.It is also to be understood that term " forms " and/or " including ",
When using in this specification, determine described feature, integer, step, operation, element and/or parts
Existence, but be not excluded for one or more other feature, integer, step, operation, element, parts
And/or group existence or interpolation.When using at this, term "and/or" includes any of relevant Listed Items
And all combinations.
In order to thoroughly understand the present invention, detailed step and detailed knot will be proposed in following description
Structure, in order to explaination technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but
In addition to these describe in detail, the present invention can also have other embodiments.
Embodiment 1
The present invention is to solve problems of the prior art, it is provided that a kind of new semiconductor device
Preparation method, below in conjunction with the accompanying drawings the method for the invention is further described.
Wherein, Fig. 1 a-1d is the preparation process of semiconductor device described in the present invention one specifically implements
Schematic diagram.
First, perform step 101, it is provided that Semiconductor substrate 101, formed on the semiconductor substrate
Dummy gate structure 103.
Specifically, as shown in Figure 1a, semi-conductive substrate 101, described Semiconductor substrate are first provided
101 can be at least one in the following material being previously mentioned: silicon, silicon-on-insulator (SOI), absolutely
Stacking SiGe (S-SiGeOI), germanium on insulator on stacking silicon (SSOI), insulator on edge body
Silicon (SiGeOI) and germanium on insulator (GeOI) etc..
Additionally, active area can be defined in Semiconductor substrate 101.Can also wrap on the active region
Containing other active device, for convenience, do not indicate in shown figure.
Then in described Semiconductor substrate, form fleet plough groove isolation structure, described fleet plough groove isolation structure
Forming method can select method commonly used in the prior art, first, in Semiconductor substrate 101
On sequentially form the first oxide skin(coating) and the first nitride layer.Then, perform dry etch process, depend on
Secondary perform etching to form groove to the first nitride layer, the first oxide skin(coating) and Semiconductor substrate.Tool
Body ground, can form the figuratum photoresist layer of tool on the first nitride layer, with this photoresist layer be
Mask carries out dry etching to the first nitride layer, to transfer a pattern to the first nitride layer, and with
Photoresist layer and the first nitride layer are that the first oxide skin(coating) and Semiconductor substrate are performed etching by mask,
To form groove.Certainly can also use other method to form groove, owing to this technique thinks ability
Known to territory, the most no longer it is described further.
Then, in groove, shallow trench isolated material is filled, to form fleet plough groove isolation structure.Specifically
Ground, can on the first nitride layer and groove in formed shallow trench isolated material, described shallow trench every
Can be silicon oxide, silicon oxynitride and/or other existing advanced low-k materials from material；Execution
Learn mechanical milling tech and stop on the first nitride layer, to form described fleet plough groove isolation structure.
Described Semiconductor substrate can be divided into NMOS area by the isolation of the most described shallow trench
And PMOS area.
Then, in described Semiconductor substrate 101 formed dummy gate structure 103, below exemplary
The forming method that described dummy gate structure is described, but described method is not limited to this example:
It is sequentially depositing dummy gate dielectric layer, dummy gate material layer on the semiconductor substrate, the most right
Described dummy gate dielectric layer, dummy gate material layer perform etching and obtain dummy gate.
Wherein, described dummy gate dielectric layer can select silicon dioxide, and its forming method can be heavy
Semiconductor substrate described in long-pending silicon dioxide material layer or high-temperature oxydation forms described gate dielectric,
Described gate material layers can include silicon or polysilicon layer.
As preferably, described method may further include the both sides of described dummy gate and forms skew side
Wall (offset spacer).The material of described offset side wall e.g. silicon nitride, silicon oxide or nitrogen oxidation
The insulant such as silicon.Along with diminishing further of device size, the channel length of device is more and more less,
It is more and more less that the particle of source-drain electrode injects the degree of depth, and the effect of offset side wall is to improve the crystalline substance formed
The channel length of body pipe, reduces short-channel effect and the hot carrier's effect caused due to short-channel effect.
The technique forming offset side wall in grid structure both sides can be chemical gaseous phase deposition.
Alternatively, forming clearance wall on the offset side wall of described dummy gate, the most described clearance wall can
Think that a kind of in silicon oxide, silicon nitride, silicon oxynitride or they combinations are constituted.As the present embodiment
One in embodiment, described clearance wall is that silicon oxide, silicon nitride collectively constitute, specifically comprises the processes of:
Form the first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer on a semiconductor substrate, so
Rear employing engraving method forms clearance wall.
Perform step 102, deposit the first interlayer dielectric layer 102 to described dummy gate structure top with
Under.
Specifically, as shown in Figure 1 b, in this step, the first interlayer dielectric layer 102 is deposited to several
The height identical with described dummy gate structure, the most described first interlayer dielectric layer is positioned at described void
Below plan top portions of gates, but the top of the most described dummy gate structure.
Alternatively, described first interlayer dielectric layer apart from the distance at described dummy gate structure top is
1-10nm。
Wherein, described first interlayer dielectric layer selects conventional dielectric material, such as, can select oxidation
Thing, such as SiO2, it should be understood that, the first interlayer dielectric layer is not limited to this material.
Owing to described first interlayer dielectric layer and described dummy gate dielectric layer etch select ratio close,
The described first substantial amounts of loss of interlayer dielectric layer can be caused during removing dummy gate dielectric layer, with
The first conventional for Shi Xuanyong interlayer dielectric layer can occur what interlayer dielectric layer caved in ask in planarization process
Topic, in order to solve this problem, is forming second on first interlayer dielectric layer at dummy gate top
Interlayer dielectric layer.
Perform step 103, described first interlayer dielectric layer is formed the second interlayer dielectric layer 104, with
Cover described first interlayer dielectric layer and described dummy gate structure, wherein, described second interlayer dielectric layer
With described dummy gate dielectric layer, there is bigger etching selectivity.
Specifically, as shown in Figure 1 b, the method wherein forming described second interlayer dielectric layer 104 includes continuing
Described first interlayer dielectric layer of continuous deposition the C that adulterates in situ in this process, to be formed rich in described in C
Second interlayer dielectric layer.
Or, the method forming described second interlayer dielectric layer 104 includes depositing the interlayer dielectric rich in silicon
Layer, in this process by regulating the ratio of interlayer dielectric layer deposition raw material, such as, increases silicon-containing material
Gas ratio, to increase the content of silicon in described interlayer dielectric layer.
Or, further, adulterate during deposition is rich in the interlayer dielectric layer of silicon C the most in situ,
During interlevel dielectric deposition, regulate the ratio of interlayer dielectric layer deposition raw material, such as, increase siliceous
The gas ratio of raw material, is passed through carbonaceous gas source simultaneously, to increase containing of silicon and C in described interlayer dielectric layer
Amount, to form described second interlayer dielectric layer.
Further, the described interlayer dielectric layer rich in silicon selects the oxide rich in silicon.
The present invention regulates the composition in described second interlayer dielectric layer, increase silicon or C by said method
Content, to change the etching performance of described second interlayer dielectric layer, reducing in follow-up planarization and
Loss in etching process.
In this step, described second interlayer dielectric layer is completely covered described interlayer dielectric layer, additionally, also
Can be with dummy gate structure described in covering part.
Performing step 104, dielectric layer between deposition third layer, to cover described second interlayer dielectric layer.
Concrete, as shown in Figure 1 b, between the most described third layer, dielectric layer can be selected pure
Oxide, selects identical material with the first interlayer dielectric layer in step 102.
Wherein, between the most described third layer, the thickness of dielectric layer is not limited to a certain numerical value model
Enclose, can be designed as required.
Perform step 105, perform planarisation step and stop to described dummy gate structure.
Specifically, as illustrated in figure 1 c, dielectric layer and described is planarized between described third layer in this step
Second interlayer dielectric layer, stops at described dummy gate structure, to expose described dummy gate structure.
Due in described second interlayer dielectric layer rich in silicon or C, therefore in this planarization process not
There will be depressed phenomenon of the prior art.
Perform step 106, remove described dummy gate structure.
Concrete, as shown in Figure 1 d, following two step can be comprised in this step:
First-selection, removes described dummy gate, to form virtual opening, is lost by dry method in this step
Carve or wet etching removes described dummy gate, N can be selected the most in the present invention2In conduct erosion
Carve atmosphere, it is also possible to be simultaneously introduced other a small amount of gas such as CF4、CO2、O2, described etching pressure can
Thinking 50-200mTorr, power is 200-600W, and the most described etching period is 5-80s.
Then remove described dummy gate dielectric layer, can select in the present invention and be situated between with described second interlayer
Electric layer has the wet etching of bigger etching ratio and removes described dummy gate dielectric layer.
Alternatively, it is also possible to first select dry etching to remove part described dummy gate dielectric layer；Then:
Selection and described second interlayer dielectric layer have the wet etching of bigger etching ratio and remove remaining described grid
Dielectric layer.
In this step, due to described second dielectric layer and described dummy gate dielectric layer, there is bigger erosion
Carve and select ratio, the most described second interlayer dielectric layer will not be caused damage.
Performing step 107, form high K dummy gate, described high-K metal gate includes plane and FinFET
High-K metal gate.
Specifically, in described virtual opening, high k dielectric layer, wherein said high k dielectric are first deposited
Layer can select dielectric material commonly used in the art, such as at Hf02Middle introducing Si, Al, N, La,
The elements such as Ta also optimize the hafnium etc. that the ratio of each element obtains.
The method forming described high k dielectric layer can be physical gas-phase deposition or ald work
Skill.In an embodiment of the present invention, forming HfAlON gate dielectric in a groove, its thickness is
15 to 60 angstroms.
Then forming cover layer on high k dielectric layer, described cover layer can select TiN, further,
Diffusion impervious layer can also be formed on described cover layer, can be TaN layer or AlN layer.At this
In a bright embodiment, CVD reaction chamber carries out described TaN layer or the deposition of AlN layer,
Selected process conditions include that pressure is 1-100 Torr, and temperature is 500-1000 degree Celsius.Deposited
TaN layer or AlN layer there is the thickness of 10-50 angstrom.
Eventually forming conductive layer, described conductive layer can be aluminium lamination, it is also possible to be copper or tungsten layer.At this
One embodiment of invention use Al form described conductive layer, can be with the side of CVD or PVD
Method deposits.After this conductive layer is formed, anneal under 300-500 degree celsius temperature.
Its time reacted in containing nitrogen environment is 10-60 minute.
Finally perform planarisation step to described interlayer dielectric layer.
So far, the introduction of correlation step prepared by the semiconductor device of the embodiment of the present invention is completed.Upper
After stating step, it is also possible to including other correlation step, here is omitted.Further, except above-mentioned step
Outside Zhou, the preparation method of the present embodiment can also be among each step above-mentioned or between different step
Including other steps, these steps all can be realized, the most not by various techniques of the prior art
Repeat again.
In order to reduce the loss of interlayer dielectric layer during removing dummy gate, and control interlayer Jie
Cave in during electric layer CMP, the invention provides the preparation side of a kind of new semiconductor device
Method, described method first deposit interlayer dielectric to dummy gate height close proximity, then followed by
Adulterate during continuous interlevel dielectric deposition C in situ, or deposition is rich in the oxide skin(coating) of silicon, or
Adulterate during deposition is rich in the oxide skin(coating) of silicon C in situ, described doping C or the dielectric of silicon
Layer has bigger etching selectivity with described dummy gate, is possible not only in the mistake removing dummy gate
Journey reduces the loss amount of interlayer dielectric layer, it is also possible in planarization process, avoid the occurrence of groove, enter
One step improves performance and the yield of semiconductor device.
With reference to Fig. 2, illustrated therein is the present invention and prepare the process chart of described semiconductor device, use
In schematically illustrating the flow process of whole manufacturing process, comprise the following steps:
Step S1: Semiconductor substrate is provided, is formed with dummy gate structure on the semiconductor substrate,
Wherein, described dummy gate structure includes dummy gate dielectric layer；
Step S2: deposit the first interlayer dielectric layer on the semiconductor substrate to described dummy gate structure
Below top；
Step S3: form the second interlayer dielectric layer on described first interlayer dielectric layer to described dummy gate
More than structural top, wherein, the forming method of described second interlayer dielectric layer is: continue deposition described the
One interlayer dielectric layer in situ doping C, to form described second interlayer dielectric layer；Or deposition is rich in silicon
Interlayer dielectric layer, to form described second interlayer dielectric layer；Or deposition is rich in the interlayer dielectric layer of silicon former
Position doping C, to form described second interlayer dielectric layer；
Step S4: perform planarisation step extremely described dummy gate structure, then remove described dummy gate
Structure.
Embodiment 2
Present invention also offers a kind of semiconductor device, described semiconductor device is selected described in embodiment 1
Prepared by method.By interlayer dielectric layer described in the semiconductor device that the method for the invention prepares flat
During smoothization, loss amount is the least, simultaneously will not be to institute during removing described dummy gate structure
State interlayer dielectric layer to cause damage, further increase performance and the yield of device.
Embodiment 3
Present invention also offers a kind of electronic installation, including the semiconductor device described in embodiment 2.Wherein,
Semiconductor device is the semiconductor device described in embodiment 2, or according to the preparation method described in embodiment 1
The semiconductor device obtained.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book,
Game machine, television set, VCD, DVD, navigator, photographing unit, video camera, recording pen, MP3,
Any electronic product such as MP4, PSP or equipment, it is possible to for any centre including described semiconductor device
Product.The electronic installation of the embodiment of the present invention, owing to employing above-mentioned semiconductor device, thus has
Better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment
It is only intended to citing and descriptive purpose, and is not intended to limit the invention to described scope of embodiments
In.In addition it will be appreciated by persons skilled in the art that and the invention is not limited in above-described embodiment, root
Can also make more kinds of variants and modifications according to the teachings of the present invention, these variants and modifications all fall within this
Within inventing scope required for protection.Protection scope of the present invention by the appended claims and etc.
Effect scope is defined.
Claims (10)
1. a preparation method for semiconductor device, including:
Step S1: Semiconductor substrate is provided, is formed with dummy gate structure on the semiconductor substrate,
Wherein, described dummy gate structure includes dummy gate dielectric layer；
Step S2: deposit the first interlayer dielectric layer on the semiconductor substrate to described dummy gate structure
Below top；
Step S3: form the second interlayer dielectric layer on described first interlayer dielectric layer to described dummy gate
More than structural top, wherein, the forming method of described second interlayer dielectric layer is: continue deposition described the
One interlayer dielectric layer in situ doping C, to form described second interlayer dielectric layer, or deposition is rich in silicon
Interlayer dielectric layer, to form described second interlayer dielectric layer；Or deposition is rich in the interlayer dielectric layer of silicon former
Position doping C, to form described second interlayer dielectric layer；
Step S4: perform planarisation step extremely described dummy gate structure, then remove described dummy gate
Structure.
Method the most according to claim 1, it is characterised in that the described interlayer dielectric layer rich in silicon
Select the oxide rich in silicon.
Method the most according to claim 1, it is characterised in that in described step S3 and described step
May further include between rapid S4 and on described second interlayer dielectric layer, deposit the step of dielectric layer between third layer
Suddenly, to cover described second interlayer dielectric layer.
Method the most according to claim 1, it is characterised in that in described step S4, selects
The wet etching with described second interlayer dielectric layer with bigger etching ratio removes described dummy gate dielectric
Layer.
Method the most according to claim 1, it is characterised in that described step S4 includes:
Step S41: select dry etching to remove part described dummy gate dielectric layer；
Step S42: selection and described second interlayer dielectric layer have the wet etching of bigger etching ratio and remove
Remaining described gate dielectric.
Method the most according to claim 1, it is characterised in that in described step S2, deposition
Described first interlayer dielectric layer is to close to described dummy gate structure top.
Method the most according to claim 1, it is characterised in that described method still further comprises shape
Becoming the step of high-K metal gate, described high-K metal gate includes the height in plane and FinFET technique
Karat gold belongs to grid.
Method the most according to claim 1, it is characterised in that in described step S1, described
Semiconductor substrate is formed with fleet plough groove isolation structure, to form nmos area in described Semiconductor substrate
Territory and PMOS area.
9. the semiconductor device prepared based on the method one of claim 1 to 8 Suo Shu.
10. an electronic installation, including the semiconductor device described in claim 9.
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| WO2019003078A1 (en) * | 2017-06-30 | 2019-01-03 | International Business Machines Corporation | Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning |
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|---|---|---|---|---|
| WO2019003078A1 (en) * | 2017-06-30 | 2019-01-03 | International Business Machines Corporation | Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning |
| US10243079B2 (en) | 2017-06-30 | 2019-03-26 | International Business Machines Corporation | Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning |
| GB2579463A (en) * | 2017-06-30 | 2020-06-24 | Ibm | Utilizing multiplayer gate spacer to reduce erosion of semiconductor fin during spacer patterning |
| US10790393B2 (en) | 2017-06-30 | 2020-09-29 | International Business Machines Corporation | Utilizing multilayer gate spacer to reduce erosion of semiconductor Fin during spacer patterning |
| GB2579463B (en) * | 2017-06-30 | 2022-03-02 | Ibm | Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning |
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Application publication date: 20160810 |