US20070069298A1 - Mobility enhancement by strained channel CMOSFET with single workfunction metal-gate and fabrication method thereof - Google Patents

Mobility enhancement by strained channel CMOSFET with single workfunction metal-gate and fabrication method thereof Download PDF

Info

Publication number
US20070069298A1
US20070069298A1 US11/324,085 US32408505A US2007069298A1 US 20070069298 A1 US20070069298 A1 US 20070069298A1 US 32408505 A US32408505 A US 32408505A US 2007069298 A1 US2007069298 A1 US 2007069298A1
Authority
US
United States
Prior art keywords
pmosfet
nmosfet
region
cmosfet
overlying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/324,085
Inventor
Shin-Chii Lu
Yu-Ming Lin
Min-Hung Lee
Zing-Way Pei
Wen Hsieh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Industrial Technology Research Institute ITRI
Original Assignee
Industrial Technology Research Institute ITRI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Industrial Technology Research Institute ITRI filed Critical Industrial Technology Research Institute ITRI
Assigned to INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE reassignment INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HSIEH, WEN YI, LEE, MIN-HUNG, LIN, YU-MING, LU, SHIN-CHII, PEI, ZING-WAY
Publication of US20070069298A1 publication Critical patent/US20070069298A1/en
Priority to US12/185,740 priority Critical patent/US7741169B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to complementary metal-oxide-semiconductor (CMOS) technology. More particularly, it relates to combining a compressively strained SiGe channel of a PMOSFET with a local tensile strained Si channel of an NMOSFET, such that a band gap narrowing of the CMOSFET and improving holes and electrons mobility of the PMOSFET and NMOSFET, respectively.
  • CMOS complementary metal-oxide-semiconductor
  • the density of integrated circuits continues to increase and feature size thereof continues to scale down, improving the performance of IC devices and lowering manufacturing costs.
  • Shorter channel length causes gate electrodes to lose channel controllability due to the short channel effect (SCE).
  • This controllability problem can be solved by reducing the thickness of the gate dielectric layer (silicon dioxide), and this decreases the operating voltage and increases driving current. As a result, the leakage current is significantly increased with a direct tunneling effect, and the controllability issue still exists.
  • high-k materials are much thicker than that of silicon dioxide under the same capacitance.
  • high-k materials serving as a gate dielectric layer the electric filed in dielectric is lower under a same bias voltage, thereby decreasing the current leakage.
  • High-k gate dielectrics are therefore considered to be a promising solution for replacing conventional silicon dioxide.
  • Semiconductor technology includes high-temperature processes, such as activation annealing after ion implantations.
  • poly-Si has been widely used as gate material due to its thermal budget and interface properties with silicon dioxide.
  • the poly-Si has issues of poly depletion and sheet resistance.
  • introduction of metal-gates has become a mainstream method for reducing the described problems.
  • threshold voltages of PMOSFET and NMOSFET have to be oppositely symmetric.
  • dual metal-gate electrodes or ion implantation to tune work function is applied.
  • the former is a complex process, and the latter is limited by solid solubility.
  • a method for reducing the channel effective band gap in a single workfunction metal gate, band gap offset of strained Si and strained SiGe channels are disclosed in IEEE EDL, vol. 25-6, pp. 402-404, entitled “Strained-Si-Strained-SiGe Dual-Channel Layer Structure as CMOS Substrate for Single Workfunction Metal-gate Technology”, published in June 2004.
  • a compressively strained Si 0.4 Ge 0.6 layer as a hole channel and a tensile strained Si layer as an electron channel are formed sequentially on a Si 0.7 Ge 0.3 virtual substrate, wherein the Si layer of a PMOSFET is thicker than that of the NMOSFET to make sure that the reversion channel in the compressively strained SiGe layer.
  • tensile strained Si (region I), compressively strained Si 0.4 Ge 0.6 (region II), relaxed Si 0.7 Ge 0.3 buffer (region III), and bulk Si (region IV) are used as channels with different energy gaps.
  • the tensile strained Si enhances electron mobility significantly in NMOSFET.
  • the tensile strained Si cannot significantly improve the hole mobility in PMOSFET.
  • Using compressively strained Si 0.4 Ge 0.6 as a hole channel can enhance the operational speed of the PMOSFET. Therefore, the cited paper applies the Si 0.4 Ge 0.6 and the tensile-strained Si as channels of the PMOSFET and the NMOSFET, respectively, such that the effective band gap is narrower than the bulk Si by 0.5 eV (from 1.1 eV to 0.6 eV).
  • An ideal oppositely symmetrical threshold voltage of the PMOSFET and the NMOSFET can be obtained by a single metal-gate of 4.5 eV workfunction.
  • This method requires a SiGe virtual substrate that leads increasing costs and the thickness of the ultra-thin Si cap layer overlying the PMOSFET is difficult to control.
  • Presently strained channel engineering mainly comprises global strain and local strain.
  • Disadvantages of the global strain include high cost, low hole mobility, and high defect density in the SiGe virtue substrate.
  • the disadvantage of the local strain is difficult in process control.
  • U.S. Pat. No. 6,784,507 discloses a structure of CMOSFET and BiCMOSFET, which includes a PMOSFET having a compressively strained SiGe channel, and an NMOSFET having a Si channel.
  • a compressively strained SiGe channel is used for enhancing the hole mobility of the PMOSFET, but the electron mobility of the NMOSFET is not improved.
  • a method and a device for mobility enhancement by strained channel CMOSFET with single workfunction metal-gate are provided; wherein a PMOSFET channel is compressively strained for improving hole mobility, and an NMOSFET channel is tensile strain for enhancing electron mobility.
  • An exemplary embodiment of the present invention uses a compressively strained channel, for narrowing the band gap.
  • the method for fabricating a mobility enhancement by strained channel CMOSFET with single workfunction metal gate of the invention comprises: providing a semiconductor substrate is formed with regions of a PMOSFET and an NMOSFET. A compressively strained film is formed overlying the PMOSFET channel, and then gate dielectric layers are formed on the NMOSFET region and the compressively strained film, respectively. Gate electrodes are formed on the gate dielectric layers, and a cap layer is then formed overlying the NMOSFET region for producing a local tensile stress on a channel of the NMOSFET.
  • the mobility enhancement by strained channel CMOSFET comprising a semiconductor substrate with an isolation region for defining regions of a PMOSFET and an NMOSFET.
  • a compressively strained film is overlying the PMOSFET region as a channel of the PMOSFET.
  • a gate dielectric layer is on the NMOSFET region and the compressively strained film, respectively.
  • Gate electrodes are on the gate dielectric layers.
  • a cap layer is overlying the NMOSFET region for producing a local tensile stress on a channel of the NMOSFET.
  • the present invention combines a PMOSFET compressively strained channel and an NMOSFET tensile strained channel.
  • the compressively strained channel enhances the PMOSFET hole mobility, and the tensile stress enhances the NMOSFET electron mobility.
  • the single workfunction metal gate of the invention is not only used alone but also with high-k materials.
  • FIG. 1 is a schematic diagram showing the band diagram of tensile strained Si, compressively strained Si 0.4 Ge 0.6 , relaxed Si 0.7 Ge 0.3 buffer, and bulk Si.
  • FIG. 2A-2E are cross sections of semiconductor structures that illustrate processing required to fabricate a mobility enhancement by strained channel CMOSFET with single workfunction metal gate.
  • a mobility enhancement by strained channel CMOSFET with single workfunction metal gate will be described here in greater detail.
  • Some embodiments of the invention, such as the exemplary embodiments described can potentially improve the hole and electron mobility of the PMOSFET and the NMOSFET, respectively.
  • the single workfunction metal gate is further combined with high-k materials. In some embodiments, this can be accomplished by forming a compressively strained SiGe channel in the PMOSFET region, and a tensile cap layer in the NMOSFET region to produce a local tensile stress on the NMOSFET channel.
  • FIG. 2A is a schematic diagram of an embodiment of the CMOSFET of the present invention.
  • a semiconductor substrate 10 preferably a Si substrate is provided.
  • the semiconductor substrate 10 has isolation regions 12 (shallow trench isolation, STI) to define the PMOSFET region 14 and the NMOSFET region 16 .
  • the PMOSFET region 14 and the NMOSFET region 16 can be doped to be a n-type well and a p-type well, respectively.
  • An amorphous layer is formed overlying the substrate 10 and the isolation region 12 , preferably a pad oxide.
  • the amorphous layer on the NMOSFET region remains as an amorphous layer 18 , and the amorphous layer on the PMOSFET is removed to expose the PMOSFET region 14 .
  • a compressively strained film 20 is then formed on the PMOSFET region 14 .
  • the amorphous layer 18 can be used as a mask to form the compressively strained film 20 by selective epitaxy.
  • the selective epitaxy means a film is selectively grown on a surface with a specific morphology.
  • the semiconductor substrate of the PMOSFET region 14 has an lattice surface morphology, while that of the NMOSFET region 16 is an amorphous layer 18 . Accordingly, the selective epitaxy occurs only on the PMOSFET region 14 , but poly or amorphous film of poor quality may sometimes grow on the amorphous layer 18 .
  • the methods for forming the compressively strained film 20 comprise forming a SiGe film by plasma enhanced chemical vapor deposition (PECVD), ultra high vacuum chemical vapor deposition (UHV/CVD), rapid thermal chemical vapor deposition (RTCVD), or molecular beam epitaxy (MBE).
  • PECVD plasma enhanced chemical vapor deposition
  • UHV/CVD ultra high vacuum chemical vapor deposition
  • RTCVD rapid thermal chemical vapor deposition
  • MBE molecular beam epitaxy
  • Compressive stress of the SiGe film on the Si substrate relates to its Ge concentration. Increasing the Ge concentration of the SiGe film will enhance the hole mobility of the PMOSFET. When the Ge concentration is higher, the critical thickness of the SiGe film is thinner. If a thickness of the SiGe film is thicker than the critical thickness, the SiGe will become relaxed and defects will occur. On the other hand, if the thickness of the SiGe film is too thin, the holes will transport in the Si substrate without enhancement by the compressively strained film.
  • the SiGe film has a Ge concentration from 0.1% to 100% with a thickness from 1 nm to 500 nm. The preferred thickness is thinner than the critical thickness to avoid the film being relaxed and defects.
  • the amorphous layer 18 and the poly or amorphous film of poor quality (if any) on the NMOSFET region 16 are then removed. Only the SiGe film 20 on the PMOSFET region 14 is retained.
  • a gate dielectric layer is then deposited on both the NMOSFET region 16 and the compressively strained film 20 .
  • a conventional method of forming a gate dielectric layer on the Si substrate is thermal oxidation, but this is not suitable for SiGe films.
  • the preferred method for forming the gate dielectric layer in the present invention is deposition, preferably of high-k materials such as ZrO 2 , HfO 2 , TiO 2 , Ta 2 O 5 , Al 2 O 3 , La 2 O 3 , SiON, or other materials having a dielectric constant higher than that of SiO 2 .
  • the gate electrode layer is deposited on the gate dielectric layer.
  • the gate electrode layer may comprise conventional materials such as poly-Si, poly-SiGe; materials having a Fermi level corresponding to the mid-gap of the semiconductor substrate such as TiN, Ti, TaN, Ta, W; or other materials have a suitable workfunction.
  • TiN is suitable for use as gate electrodes due to its adhesion, matured manufacturing process, and thermal stability. Sometimes a W or Al layer may be provided on the TiN gate electrode to reduce resistance.
  • the gate electrode layer is patterned by lithography and anisotropic etching for forming gate electrodes 24 .
  • the gate electrodes are formed in ring-FET structure as a close-loop.
  • the close-loop comprises circle, rectangle, or other suitable shapes.
  • the drain and source of the ring-FET are separated by the close-loop, such that current leakage can be reduced efficiently.
  • the present invention is not limited to the above ring-FET structure, but can be a conventional FET structure as shown in FIG. 2E .
  • the gate dielectric layer not masked by the gate electrodes is removed by anisotropic etching.
  • a cap layer is formed overlying the NMOSFET region and the PMOSFET region to produce a tensile stress on a channel of the NMOSFET.
  • the cap layer comprises, but is not limited to nitride as SiN.
  • the cap layer has a thickness from 1 nm to 1 ⁇ m. According to the present invention, those skilled in the art can choose other suitable materials for producing a tensile stress on the channel of the NMOSFET.
  • Ge ions may be doped to the cap layer 28 to form a dopped Ge cap layer 34 so as to prevent the compressively strained SiGe channel 20 of the PMOSFET region from being affected by the tensile strain of the cap layer 28 .
  • cap layer 34 on the PMOSFET region can be selectively removed by lithography and etching, leaving the cap layer 34 on the NMOSFET region to produce tensile stress only on the NMOSFET channel.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to complementary metal-oxide-semiconductor (CMOS) technology. More particularly, it relates to combining a compressively strained SiGe channel of a PMOSFET with a local tensile strained Si channel of an NMOSFET, such that a band gap narrowing of the CMOSFET and improving holes and electrons mobility of the PMOSFET and NMOSFET, respectively.
  • 2. Description of the Related Art
  • The density of integrated circuits (IC) continues to increase and feature size thereof continues to scale down, improving the performance of IC devices and lowering manufacturing costs. Shorter channel length causes gate electrodes to lose channel controllability due to the short channel effect (SCE). This controllability problem can be solved by reducing the thickness of the gate dielectric layer (silicon dioxide), and this decreases the operating voltage and increases driving current. As a result, the leakage current is significantly increased with a direct tunneling effect, and the controllability issue still exists.
  • The physical thickness of high-k materials is much thicker than that of silicon dioxide under the same capacitance. With high-k materials serving as a gate dielectric layer, the electric filed in dielectric is lower under a same bias voltage, thereby decreasing the current leakage. High-k gate dielectrics are therefore considered to be a promising solution for replacing conventional silicon dioxide.
  • Semiconductor technology includes high-temperature processes, such as activation annealing after ion implantations. In the conventional art, poly-Si has been widely used as gate material due to its thermal budget and interface properties with silicon dioxide. When IC dimensions decrease, the poly-Si has issues of poly depletion and sheet resistance. In deep submicron CMOSFET technology, introduction of metal-gates has become a mainstream method for reducing the described problems.
  • To design a high speed CMOSFET with lower power loss, threshold voltages of PMOSFET and NMOSFET have to be oppositely symmetric. To obtain a tunable work function of metal gate in a CMOS, dual metal-gate electrodes or ion implantation to tune work function is applied. The former, however, is a complex process, and the latter is limited by solid solubility.
  • A method for reducing the channel effective band gap in a single workfunction metal gate, band gap offset of strained Si and strained SiGe channels are disclosed in IEEE EDL, vol. 25-6, pp. 402-404, entitled “Strained-Si-Strained-SiGe Dual-Channel Layer Structure as CMOS Substrate for Single Workfunction Metal-gate Technology”, published in June 2004. In this method, a compressively strained Si0.4Ge0.6 layer as a hole channel and a tensile strained Si layer as an electron channel are formed sequentially on a Si0.7Ge0.3 virtual substrate, wherein the Si layer of a PMOSFET is thicker than that of the NMOSFET to make sure that the reversion channel in the compressively strained SiGe layer. As shown in FIG. 1, tensile strained Si (region I), compressively strained Si0.4Ge0.6 (region II), relaxed Si0.7Ge0.3 buffer (region III), and bulk Si (region IV) are used as channels with different energy gaps. The tensile strained Si enhances electron mobility significantly in NMOSFET. However, the tensile strained Si cannot significantly improve the hole mobility in PMOSFET. Using compressively strained Si0.4Ge0.6 as a hole channel can enhance the operational speed of the PMOSFET. Therefore, the cited paper applies the Si0.4Ge0.6 and the tensile-strained Si as channels of the PMOSFET and the NMOSFET, respectively, such that the effective band gap is narrower than the bulk Si by 0.5 eV (from 1.1 eV to 0.6 eV). An ideal oppositely symmetrical threshold voltage of the PMOSFET and the NMOSFET can be obtained by a single metal-gate of 4.5 eV workfunction. This method requires a SiGe virtual substrate that leads increasing costs and the thickness of the ultra-thin Si cap layer overlying the PMOSFET is difficult to control.
  • Presently strained channel engineering mainly comprises global strain and local strain. Disadvantages of the global strain include high cost, low hole mobility, and high defect density in the SiGe virtue substrate. The disadvantage of the local strain is difficult in process control.
  • U.S. Pat. No. 6,784,507 discloses a structure of CMOSFET and BiCMOSFET, which includes a PMOSFET having a compressively strained SiGe channel, and an NMOSFET having a Si channel. A compressively strained SiGe channel is used for enhancing the hole mobility of the PMOSFET, but the electron mobility of the NMOSFET is not improved.
  • An improvement of mobility enhancement by strained channel CMOSFET with single workfunction metal-gate and a fabrication method is called for.
    • BRIEF SUMMARY OF INVENTION
  • According to the invention, a method and a device for mobility enhancement by strained channel CMOSFET with single workfunction metal-gate are provided; wherein a PMOSFET channel is compressively strained for improving hole mobility, and an NMOSFET channel is tensile strain for enhancing electron mobility.
  • An exemplary embodiment of the present invention uses a compressively strained channel, for narrowing the band gap.
  • The method for fabricating a mobility enhancement by strained channel CMOSFET with single workfunction metal gate of the invention comprises: providing a semiconductor substrate is formed with regions of a PMOSFET and an NMOSFET. A compressively strained film is formed overlying the PMOSFET channel, and then gate dielectric layers are formed on the NMOSFET region and the compressively strained film, respectively. Gate electrodes are formed on the gate dielectric layers, and a cap layer is then formed overlying the NMOSFET region for producing a local tensile stress on a channel of the NMOSFET.
  • The mobility enhancement by strained channel CMOSFET, comprising a semiconductor substrate with an isolation region for defining regions of a PMOSFET and an NMOSFET. A compressively strained film is overlying the PMOSFET region as a channel of the PMOSFET. A gate dielectric layer is on the NMOSFET region and the compressively strained film, respectively. Gate electrodes are on the gate dielectric layers. A cap layer is overlying the NMOSFET region for producing a local tensile stress on a channel of the NMOSFET.
  • The present invention combines a PMOSFET compressively strained channel and an NMOSFET tensile strained channel. The compressively strained channel enhances the PMOSFET hole mobility, and the tensile stress enhances the NMOSFET electron mobility.
  • The single workfunction metal gate of the invention is not only used alone but also with high-k materials.
    • BRIEF DESCRIPTION OF DRAWINGS
  • The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
  • FIG. 1 is a schematic diagram showing the band diagram of tensile strained Si, compressively strained Si0.4Ge0.6, relaxed Si0.7Ge0.3 buffer, and bulk Si.
  • FIG. 2A-2E are cross sections of semiconductor structures that illustrate processing required to fabricate a mobility enhancement by strained channel CMOSFET with single workfunction metal gate.
    • DETAILED DESCRIPTION OF INVENTION
  • The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
  • A mobility enhancement by strained channel CMOSFET with single workfunction metal gate will be described here in greater detail. Some embodiments of the invention, such as the exemplary embodiments described can potentially improve the hole and electron mobility of the PMOSFET and the NMOSFET, respectively. The single workfunction metal gate is further combined with high-k materials. In some embodiments, this can be accomplished by forming a compressively strained SiGe channel in the PMOSFET region, and a tensile cap layer in the NMOSFET region to produce a local tensile stress on the NMOSFET channel.
  • Referring now to the drawings, FIG. 2A is a schematic diagram of an embodiment of the CMOSFET of the present invention. As shown in FIG. 2A, a semiconductor substrate 10, preferably a Si substrate is provided. The semiconductor substrate 10 has isolation regions 12 (shallow trench isolation, STI) to define the PMOSFET region 14 and the NMOSFET region 16. The PMOSFET region 14 and the NMOSFET region 16 can be doped to be a n-type well and a p-type well, respectively. An amorphous layer is formed overlying the substrate 10 and the isolation region 12, preferably a pad oxide. The amorphous layer on the NMOSFET region remains as an amorphous layer 18, and the amorphous layer on the PMOSFET is removed to expose the PMOSFET region 14.
  • As shown in FIG. 2B, a compressively strained film 20 is then formed on the PMOSFET region 14. In preferred embodiment of the present invention, the amorphous layer 18 can be used as a mask to form the compressively strained film 20 by selective epitaxy. The selective epitaxy means a film is selectively grown on a surface with a specific morphology. In this preferred embodiment, the semiconductor substrate of the PMOSFET region 14 has an lattice surface morphology, while that of the NMOSFET region 16 is an amorphous layer 18. Accordingly, the selective epitaxy occurs only on the PMOSFET region 14, but poly or amorphous film of poor quality may sometimes grow on the amorphous layer 18.
  • In preferred embodiment of the present invention, the methods for forming the compressively strained film 20 comprise forming a SiGe film by plasma enhanced chemical vapor deposition (PECVD), ultra high vacuum chemical vapor deposition (UHV/CVD), rapid thermal chemical vapor deposition (RTCVD), or molecular beam epitaxy (MBE).
  • Compressive stress of the SiGe film on the Si substrate relates to its Ge concentration. Increasing the Ge concentration of the SiGe film will enhance the hole mobility of the PMOSFET. When the Ge concentration is higher, the critical thickness of the SiGe film is thinner. If a thickness of the SiGe film is thicker than the critical thickness, the SiGe will become relaxed and defects will occur. On the other hand, if the thickness of the SiGe film is too thin, the holes will transport in the Si substrate without enhancement by the compressively strained film. In a preferred embodiment of the present invention, the SiGe film has a Ge concentration from 0.1% to 100% with a thickness from 1 nm to 500 nm. The preferred thickness is thinner than the critical thickness to avoid the film being relaxed and defects.
  • The amorphous layer 18 and the poly or amorphous film of poor quality (if any) on the NMOSFET region 16 are then removed. Only the SiGe film 20 on the PMOSFET region 14 is retained.
  • As shown in FIG. 2C, a gate dielectric layer is then deposited on both the NMOSFET region 16 and the compressively strained film 20. A conventional method of forming a gate dielectric layer on the Si substrate is thermal oxidation, but this is not suitable for SiGe films. The preferred method for forming the gate dielectric layer in the present invention is deposition, preferably of high-k materials such as ZrO2, HfO2, TiO2, Ta2O5, Al2O3, La2O3, SiON, or other materials having a dielectric constant higher than that of SiO2.
  • As shown in FIG. 2D, the gate electrode layer is deposited on the gate dielectric layer. The gate electrode layer may comprise conventional materials such as poly-Si, poly-SiGe; materials having a Fermi level corresponding to the mid-gap of the semiconductor substrate such as TiN, Ti, TaN, Ta, W; or other materials have a suitable workfunction. TiN is suitable for use as gate electrodes due to its adhesion, matured manufacturing process, and thermal stability. Sometimes a W or Al layer may be provided on the TiN gate electrode to reduce resistance.
  • As shown in FIG. 2D, the gate electrode layer is patterned by lithography and anisotropic etching for forming gate electrodes 24. In a preferred embodiment of the present invention, the gate electrodes are formed in ring-FET structure as a close-loop. The close-loop comprises circle, rectangle, or other suitable shapes. The drain and source of the ring-FET are separated by the close-loop, such that current leakage can be reduced efficiently.
  • It should be noted that the present invention is not limited to the above ring-FET structure, but can be a conventional FET structure as shown in FIG. 2E. The gate dielectric layer not masked by the gate electrodes is removed by anisotropic etching.
  • As shown in FIG. 2E, a cap layer is formed overlying the NMOSFET region and the PMOSFET region to produce a tensile stress on a channel of the NMOSFET. In a preferred embodiment of the present invention, the cap layer comprises, but is not limited to nitride as SiN. The cap layer has a thickness from 1 nm to 1 μm. According to the present invention, those skilled in the art can choose other suitable materials for producing a tensile stress on the channel of the NMOSFET.
  • In addition, Ge ions may be doped to the cap layer 28 to form a dopped Ge cap layer 34 so as to prevent the compressively strained SiGe channel 20 of the PMOSFET region from being affected by the tensile strain of the cap layer 28.
  • Furthermore, the cap layer 34 on the PMOSFET region can be selectively removed by lithography and etching, leaving the cap layer 34 on the NMOSFET region to produce tensile stress only on the NMOSFET channel.
  • While the invention has been described by way of examples and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (32)

1. A method of forming a complementary MOSFET consisting of a PMOSFET and an NMOSFET, comprising:
providing a semiconductor substrate with regions of a PMOSFET and an NMOSFET;
forming a compressively strained film overlying the PMOSFET channel;
forming gate dielectric layers on the NMOSFET region and the compressively strained film, respectively;
forming gate electrodes on the gate dielectric layers; and
forming a cap layer overlying the NMOSFET region for producing a local tensile stress on a channel of the NMOSFET.
2. The method as claimed in claim 1, wherein formation of the compressively strained film overlying the PMOSFET region comprises:
forming an amorphous layer overlying the semiconductor substrate, including the PMOSFET and the NMOSFET regions;
removing the amorphous layer overlying the PMOSFET region; and
forming the compressively strained film overlying the PMOSFET region by selective epitaxy.
3. The method as claimed in claim 2, further comprising removing the amorphous layer overlying the NMOSFET.
4. The method as claimed in claim 2, wherein the amorphous layer comprises an oxide layer.
5. The method as claimed in claim 1, wherein the semiconductor substrate comprises Si.
6. The method as claimed in claim 1, wherein the compressively strained film comprises a SiGe epitaxial layer.
7. The method as claimed in claim 6, wherein the SiGe epitaxial layer has a Ge concentration from 0.1% to 100%.
8. The method as claimed in claim 6, wherein the SiGe epitaxial layer has a thickness from 1 nm to 500 nm.
9. The method as claimed in claim 1, wherein the PMOSFET region is a n-type well, and the NMOSFET region is a p-type well.
10. The method as claimed in claim 1, wherein the gate dielectric layers have a dielectric constant higher than that of silicon dioxide.
11. The method as claimed in claim 1, wherein the gate dielectric layers comprise ZrO2, HfO2, TiO2, Ta2O5, Al2O3, La2O3, SiON.
12. The method as claimed in claim 1, wherein the gate electrodes have a Fermi level corresponding to a mid-gap of the semiconductor substrate.
13. The method as claimed in claim 12, wherein the gate electrodes comprise poly-Si, poly-SiGe, or metals.
14. The method as claimed in claim 13, wherein the metals comprise TiN, Ti, TaN, Ta, or W.
15. The methods as claimed in claim 1, wherein the cap layer comprises SiN.
16. The method as claimed in claim 15, wherein the cap layer has a thickness from 1 nm to 1 μm.
17. The method as claimed in claim 1, wherein the cap layer is further formed overlying the PMOSFET region, and further doped with Ge ions at positions overlying the PMOSFET, such that the channel of the PMOSFET is substantially free of a tensile stress.
18. The method as claimed in claim 1, wherein the cap layer is further formed overlying the PMOSFET region, and the method further comprises removing the cap layer formed overlying the PMOSFET region.
19. A CMOSFET, comprising:
a semiconductor substrate with an isolation region for defining regions of a PMOSFET and an NMOSFET;
a compressively strained film overlying the PMOSFET region as a channel of the PMOSFET;
gate dielectric layers on the NMOSFET region and the compressively strained film, respectively;
gate electrodes on the gate dielectric layers; and
a cap layer overlying the NMOSFET region for producing a local tensile stress on a channel of the NMOSFET.
20. The CMOSFET as claimed in claim 19, wherein the semiconductor substrate comprises Si.
21. The CMOSFET as claimed in claim 19, wherein the compressively strained film comprises a SiGe epitaxial layer.
22. The CMOSFET as claimed in claim 21, wherein the compressively strained film has a Ge concentration from 0.1% to 100%.
23. The CMOSFET as claimed in claim 21, wherein the SiGe epitaxial layer has a thickness from 1 nm to 500 nm.
24. The CMOSFET as claimed in claim 19, wherein the PMOSFET region is a n-type well and the NMOSFET region is a p-type well.
25. The CMOSFET as claimed in claim 19, wherein the gate dielectric layers have a dielectric constant higher than that of silicon dioxide.
26. The CMOSFET as claimed in claim 19, wherein the gate dielectric layers comprise ZrO2, HfO2, TiO2, Ta2O5, Al2O3, La2O3, SiON.
27. The CMOSFET as claimed in claim 19, wherein the gate electrodes have a Fermi level corresponding to a mid-gap of the semiconductor substrate.
28. The CMOSFET as claimed in claim 27, wherein the gate electrodes comprise poly-Si, poly-SiGe, or metals.
29. The CMOSFET as claimed in claim 28, wherein the metals comprise TiN, Ti, TaN, Ta, or W.
30. The CMOSFET as claimed in claim 19, wherein the cap layer comprises SiN.
31. The CMOSFET as claimed in claim 19, wherein the cap layer has a thickness from 1 nm to 1 μm.
32. The CMOSFET as claimed in claim 19, wherein the cap layer is further formed overlying the PMOSFET region, and further doped with Ge ions at positions overlying the PMOSFET region, such that the channel of the PMOSFET is substantially free of a tensile stress.
US11/324,085 2005-09-23 2005-12-29 Mobility enhancement by strained channel CMOSFET with single workfunction metal-gate and fabrication method thereof Abandoned US20070069298A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/185,740 US7741169B2 (en) 2005-09-23 2008-08-04 Mobility enhancement by strained channel CMOSFET with single workfunction metal-gate and fabrication method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TWTW94133084 2005-09-23
TW094133084A TWI267926B (en) 2005-09-23 2005-09-23 A new method for high mobility enhancement strained channel CMOS with single workfunction metal-gate

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/185,740 Division US7741169B2 (en) 2005-09-23 2008-08-04 Mobility enhancement by strained channel CMOSFET with single workfunction metal-gate and fabrication method thereof

Publications (1)

Publication Number Publication Date
US20070069298A1 true US20070069298A1 (en) 2007-03-29

Family

ID=37892813

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/324,085 Abandoned US20070069298A1 (en) 2005-09-23 2005-12-29 Mobility enhancement by strained channel CMOSFET with single workfunction metal-gate and fabrication method thereof
US12/185,740 Expired - Fee Related US7741169B2 (en) 2005-09-23 2008-08-04 Mobility enhancement by strained channel CMOSFET with single workfunction metal-gate and fabrication method thereof

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/185,740 Expired - Fee Related US7741169B2 (en) 2005-09-23 2008-08-04 Mobility enhancement by strained channel CMOSFET with single workfunction metal-gate and fabrication method thereof

Country Status (3)

Country Link
US (2) US20070069298A1 (en)
JP (1) JP2007088400A (en)
TW (1) TWI267926B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070066077A1 (en) * 2005-09-22 2007-03-22 Yasushi Akasaka Method for manufacturing semiconductor device
US20090072312A1 (en) * 2007-09-14 2009-03-19 Leland Chang Metal High-K (MHK) Dual Gate Stress Engineering Using Hybrid Orientation (HOT) CMOS
EP2191504A1 (en) * 2007-09-07 2010-06-02 Freescale Semiconductor, Inc. Dual gate oxide device integration
US20100193860A1 (en) * 2009-01-30 2010-08-05 Thilo Scheiper Short channel transistor with reduced length variation by using amorphous electrode material during implantation
USRE45955E1 (en) * 2009-01-21 2016-03-29 Freescale Semiconductor, Inc. Dual high-K oxides with SiGe channel

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7666730B2 (en) * 2007-06-29 2010-02-23 Freescale Semiconductor, Inc. Method for forming a dual metal gate structure
US7445981B1 (en) * 2007-06-29 2008-11-04 Freescale Semiconductor, Inc. Method for forming a dual metal gate structure
EP2061076A1 (en) * 2007-11-13 2009-05-20 Interuniversitair Micro-Elektronica Centrum Vzw Dual work function device with stressor layer and method for manufacturing the same
DE102008063402B4 (en) * 2008-12-31 2013-10-17 Advanced Micro Devices, Inc. Reducing the threshold voltage fluctuation in transistors with a channel semiconductor alloy by reducing the deposition nonuniformities
US7943460B2 (en) * 2009-04-20 2011-05-17 International Business Machines Corporation High-K metal gate CMOS
US9209180B2 (en) * 2010-02-10 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Field effect transistor with conduction band electron channel and uni-terminal response
US8669617B2 (en) * 2010-12-23 2014-03-11 Intel Corporation Multi-gate transistors
US8211775B1 (en) 2011-03-09 2012-07-03 United Microelectronics Corp. Method of making transistor having metal gate
US8519487B2 (en) 2011-03-21 2013-08-27 United Microelectronics Corp. Semiconductor device
US8941184B2 (en) 2011-12-16 2015-01-27 International Business Machines Corporation Low threshold voltage CMOS device
US8648388B2 (en) 2012-02-15 2014-02-11 International Business Machines Corporation High performance multi-finger strained silicon germanium channel PFET and method of fabrication
US9209252B2 (en) * 2013-12-18 2015-12-08 Taiwan Semiconductor Manufacturing Company Limited Formation of nickel silicon and nickel germanium structure at staggered times
US9373638B1 (en) 2015-01-15 2016-06-21 International Business Machines Corporation Complementary metal-oxide silicon having silicon and silicon germanium channels
US9685553B2 (en) * 2015-06-22 2017-06-20 Globalfoundries Inc. Generating tensile strain in bulk finFET channel
US9755017B1 (en) 2016-03-01 2017-09-05 International Business Machines Corporation Co-integration of silicon and silicon-germanium channels for nanosheet devices

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6784507B2 (en) * 2001-09-28 2004-08-31 Texas Instruments Incorporated Gate structure and method
US6882025B2 (en) * 2003-04-25 2005-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Strained-channel transistor and methods of manufacture
US6939814B2 (en) * 2003-10-30 2005-09-06 International Business Machines Corporation Increasing carrier mobility in NFET and PFET transistors on a common wafer
US6984564B1 (en) * 2004-06-24 2006-01-10 International Business Machines Corporation Structure and method to improve SRAM stability without increasing cell area or off current
US7202120B2 (en) * 2005-02-24 2007-04-10 Fujitsu Limited Semiconductor integrated circuit device and fabrication process thereof

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590517A (en) * 1991-09-30 1993-04-09 Toshiba Corp Semiconductor device and manufacture thereof
JP2001160594A (en) * 1999-09-20 2001-06-12 Toshiba Corp Semiconductor device
JP2005057301A (en) * 2000-12-08 2005-03-03 Renesas Technology Corp Semiconductor device and method of manufacturing same
JP2003086708A (en) * 2000-12-08 2003-03-20 Hitachi Ltd Semiconductor device and manufacturing method thereof
US6762469B2 (en) 2002-04-19 2004-07-13 International Business Machines Corporation High performance CMOS device structure with mid-gap metal gate
JP2004221114A (en) 2003-01-09 2004-08-05 Seiko Epson Corp Method for fabricating semiconductor device
JP2004235345A (en) * 2003-01-29 2004-08-19 Fujitsu Ltd Semiconductor device and manufacturing method thereof
US6927414B2 (en) * 2003-06-17 2005-08-09 International Business Machines Corporation High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof
US7662689B2 (en) * 2003-12-23 2010-02-16 Intel Corporation Strained transistor integration for CMOS
US7645687B2 (en) * 2005-01-20 2010-01-12 Chartered Semiconductor Manufacturing, Ltd. Method to fabricate variable work function gates for FUSI devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6784507B2 (en) * 2001-09-28 2004-08-31 Texas Instruments Incorporated Gate structure and method
US6882025B2 (en) * 2003-04-25 2005-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Strained-channel transistor and methods of manufacture
US6939814B2 (en) * 2003-10-30 2005-09-06 International Business Machines Corporation Increasing carrier mobility in NFET and PFET transistors on a common wafer
US6984564B1 (en) * 2004-06-24 2006-01-10 International Business Machines Corporation Structure and method to improve SRAM stability without increasing cell area or off current
US7202120B2 (en) * 2005-02-24 2007-04-10 Fujitsu Limited Semiconductor integrated circuit device and fabrication process thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070066077A1 (en) * 2005-09-22 2007-03-22 Yasushi Akasaka Method for manufacturing semiconductor device
US7622340B2 (en) * 2005-09-22 2009-11-24 Tokyo Electron Limited Method for manufacturing semiconductor device
EP2191504A1 (en) * 2007-09-07 2010-06-02 Freescale Semiconductor, Inc. Dual gate oxide device integration
EP2191504A4 (en) * 2007-09-07 2012-09-05 Freescale Semiconductor Inc Dual gate oxide device integration
US20090072312A1 (en) * 2007-09-14 2009-03-19 Leland Chang Metal High-K (MHK) Dual Gate Stress Engineering Using Hybrid Orientation (HOT) CMOS
US20100159684A1 (en) * 2007-09-14 2010-06-24 International Business Machines Corporation Metal High-K (MHK) Dual Gate Stress Engineering Using Hybrid Orientation (HOT) CMOS
USRE45955E1 (en) * 2009-01-21 2016-03-29 Freescale Semiconductor, Inc. Dual high-K oxides with SiGe channel
US20100193860A1 (en) * 2009-01-30 2010-08-05 Thilo Scheiper Short channel transistor with reduced length variation by using amorphous electrode material during implantation
WO2010088257A3 (en) * 2009-01-30 2010-11-04 Global Foundries Inc. Short channel transistor with reduced length variation by using amorphous electrode material during implantation
US8241977B2 (en) 2009-01-30 2012-08-14 Globalfoundries Inc. Short channel transistor with reduced length variation by using amorphous electrode material during implantation

Also Published As

Publication number Publication date
US7741169B2 (en) 2010-06-22
TW200713469A (en) 2007-04-01
TWI267926B (en) 2006-12-01
JP2007088400A (en) 2007-04-05
US20080311713A1 (en) 2008-12-18

Similar Documents

Publication Publication Date Title
US7741169B2 (en) Mobility enhancement by strained channel CMOSFET with single workfunction metal-gate and fabrication method thereof
US10269970B2 (en) Gradient ternary or quaternary multiple-gate transistor
KR100911743B1 (en) Semiconductor Devices and Methods of Manufacture Thereof
US7005333B2 (en) Transistor with silicon and carbon layer in the channel region
TWI476822B (en) Dual metal and dual dielectric integration for metal high-k fets
JP5669954B2 (en) Structure and method for Vt tuning and short channel control with high K / metal gate MOSFETs.
JP5089576B2 (en) Gate electrode metal / metal nitride double layer CMOS and semiconductor structures in self-aligned and positively scaled CMOS devices
US7863695B2 (en) Complementary MISFET semiconductor device having an atomic density ratio aluminum/lanthanum (Al/La) in the gate insulating layer of PMIS is larger than that of the NMIS
JP5199104B2 (en) Low threshold voltage semiconductor device having dual threshold voltage control means
US20100109044A1 (en) Optimized Compressive SiGe Channel PMOS Transistor with Engineered Ge Profile and Optimized Silicon Cap Layer
US20160163603A1 (en) Pfet gate stack materials having improved threshold voltage, mobility and nbti performance
US9881921B2 (en) Fabricating a dual gate stack of a CMOS structure
US20060163672A1 (en) High performance CMOS device design
US20080050898A1 (en) Semiconductor devices and methods of manufacture thereof
US20120012939A1 (en) Semiconductor device and method of manufacturing the same
US9196475B2 (en) Methods for fabricating integrated circuits including fluorine incorporation
KR101811713B1 (en) Methods of forming cmos transistors using tensile stress layers and hydrogen plasma treatment
US9666487B2 (en) Method for manufacturing germanium-based CMOS comprising forming silicon cap over PMOS region having a thickness less than that over NMOS region
US9449887B2 (en) Method of forming replacement gate PFET having TiALCO layer for improved NBTI performance
US7812413B2 (en) MOSFET devices and methods for making them
Yokoyama et al. Ultrathin body InGaAs-on-insulator metal–oxide–semiconductor field-effect transistors with InP passivation layers on Si substrates fabricated by direct wafer bonding
US20060214207A1 (en) Semiconductor device and manufacturing method thereof
WO2013155760A1 (en) Semiconductor structure and manufacturing method thereof
US8729639B2 (en) Semiconductor device and method for producing the same
Yamaguchi et al. High performance dual metal gate CMOS with high mobility and low threshold voltage applicable to bulk CMOS technology

Legal Events

Date Code Title Description
AS Assignment

Owner name: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LU, SHIN-CHII;LIN, YU-MING;LEE, MIN-HUNG;AND OTHERS;REEL/FRAME:017209/0285

Effective date: 20050927

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION