US20130306296A1 - Semiconductor module radiator plate fabrication method, radiator plate, and semiconductor module using the same - Google Patents
Semiconductor module radiator plate fabrication method, radiator plate, and semiconductor module using the same Download PDFInfo
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- US20130306296A1 US20130306296A1 US13/950,928 US201313950928A US2013306296A1 US 20130306296 A1 US20130306296 A1 US 20130306296A1 US 201313950928 A US201313950928 A US 201313950928A US 2013306296 A1 US2013306296 A1 US 2013306296A1
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- radiator plate
- insulating substrates
- semiconductor module
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- 239000004065 semiconductor Substances 0.000 title claims description 43
- 238000000034 method Methods 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 132
- 238000005476 soldering Methods 0.000 claims abstract description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000001816 cooling Methods 0.000 description 35
- 229910000679 solder Inorganic materials 0.000 description 12
- 239000004020 conductor Substances 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4878—Mechanical treatment, e.g. deforming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23P—METAL-WORKING NOT OTHERWISE PROVIDED FOR; COMBINED OPERATIONS; UNIVERSAL MACHINE TOOLS
- B23P15/00—Making specific metal objects by operations not covered by a single other subclass or a group in this subclass
- B23P15/26—Making specific metal objects by operations not covered by a single other subclass or a group in this subclass heat exchangers or the like
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F28—HEAT EXCHANGE IN GENERAL
- F28F—DETAILS OF HEAT-EXCHANGE AND HEAT-TRANSFER APPARATUS, OF GENERAL APPLICATION
- F28F3/00—Plate-like or laminated elements; Assemblies of plate-like or laminated elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/4935—Heat exchanger or boiler making
- Y10T29/49366—Sheet joined to sheet
Definitions
- the embodiments discussed herein are related to a semiconductor module radiator plate fabrication method, a radiator plate, and a semiconductor module using such a radiator plate.
- FIG. 7 is a fragmentary sectional view of a semiconductor module.
- a semiconductor module 500 includes a radiator plate 51 , a back electrode film 53 of an insulating substrate with a conductive pattern (hereinafter simply referred to as the insulating substrate 56 ) which is adhered to the radiator plate 51 with solder 52 between, a semiconductor chip 57 adhered to a conductive pattern 55 formed over the insulating substrate 56 with solder between, a bonding wire 59 which connects a surface electrode (not illustrated) of the semiconductor chip 57 and the conductive pattern 55 , a wiring conductor 60 one end of which is connected to the conductive pattern 55 , a lead-out terminal 61 to which the other end of the wiring conductor 60 is adhered, a resin case 62 to which the lead-out terminal 61 is adhered, and gel 63 with which the resin case 62 is filled.
- Clamp holes 64 are made in the radiator plate 51 of the semiconductor module 500 for fixing the radiator plate 51 onto a cooling fin (not illustrated).
- the above insulating substrate 56 includes the back electrode film 53 , an insulating plate which is a ceramic plate or the like, and the conductive pattern 55 formed over its surface. In many cases, the back electrode film 53 and the conductive pattern 55 are formed by the use of copper foil or the like.
- FIG. 8 is a fragmentary sectional view of the semiconductor module fixed onto a cooling fin.
- the semiconductor module 500 is fixed onto a cooling fin 65 by inserting bolts or the like (not illustrated) into the clamp holes 64 made in a periphery of the radiator plate 51 .
- FIG. 9 is a schematic sectional view of a flat radiator plate to which two insulating substrates of the same shape are soldered.
- each insulating substrate 56 is obtained by forming the back electrode film 53 on the back of the insulating plate 54 , such as a ceramic plate, and forming the conductive pattern 55 on the front of the insulating plate 54 .
- the linear expansion coefficient of the radiator plate 51 made of copper or aluminum is higher than that of each insulating substrate 56 , so the radiator plate 51 to which the insulating substrates 56 are soldered curves due to a bimetal effect so that it will be convex on an insulating substrate (insulating substrates 56 ) side.
- a curve 67 which is convex on the insulating substrate (insulating substrates 56 ) side is formed on a back 66 of the radiator plate 51 . If the radiator plate 51 is attached in this state to the flat cooling fin 65 , there will be a big gap 68 in the center of the radiator plate 51 , resulting in a decrease in heat radiation efficiency. Measures to prevent this will now be described.
- FIG. 10 is a schematic sectional view of a concave curve formed for canceling out the convex curve of the radiator plate illustrated in FIG. 9 .
- a reverse curve 69 is formed in advance so that the center of the radiator plate 51 will be concave on the insulating substrate (insulating substrates 56 ) side (which is referred to as reverse curving or initial curving).
- This reverse curve 69 is formed rather sharp so that the radiator plate 51 will not become convex on the insulating substrate (insulating substrates 56 ) side even after soldering.
- the sharp concave curve 74 becomes a gentle concave curve (not illustrated).
- the radiator plate 73 to which the insulating substrates 71 and 72 are soldered is attached to a cooling fin (not illustrated). As a result, there appears no gap between the radiator plate 73 and the cooling fin.
- the radiator plate 51 curves left-right symmetrically as a result of the soldering so that its center will be convex on the insulating substrate (insulating substrates 56 ) side.
- a bottom 69 a of the concave curve 69 which cancels out this curve is positioned at the center of the radiator plate 51 , so the concave curve 69 formed on the radiator plate 51 may be managed at a depth at the center of the radiator plate 51 . As a result, management can be exercised easily.
- two insulating substrates of different shapes are soldered to a radiator plate will be described.
- FIG. 12 is a schematic sectional view of a radiator plate to which two insulating substrates of different shapes are soldered.
- insulating substrates and 82 of different shapes are adhered to a flat radiator plate 83 by the use of solder 84 , left-hand and right-hand portions of a convex curve 85 which appears on an insulating substrate (insulating substrates 81 and 82 ) side after the soldering differ in curvature. Therefore, in order to cancel out the difference in curvature, a concave curve 86 left-hand and right-hand portions of which differ in curvature, that is to say, curvatures of the left-hand and right-hand portions of which are R 3 and R 4 , respectively, may be formed in advance on the radiator plate 83 .
- the radiator plate 83 is deformed into the radiator plate 83 having a concave curve 87 a bottom 87 a of which is positioned under the insulating substrate 82 .
- the curve 86 the left-hand and right-hand portions of which differ in curvature, that is to say, the curvatures of the left-hand and right-hand portions of which are R 3 and R 4 , respectively, may be formed on the radiator plate 83 for canceling out the convex curve 85 which appears as a result of soldering the insulating substrates 81 and 82 of different shapes. Accordingly, the management of the curve 86 is complex.
- FIGS. 13A and 13B are schematic views of the radiator plate of FIG. 12 before and after being fixed onto a cooling fin.
- FIG. 13A is a schematic view of the radiator plate before being fixed onto the cooling fin.
- FIG. 13B is a schematic view of the radiator plate after being fixed onto the cooling fin.
- the reference sign 92 in FIGS. 13A and 13B indicates a clamp hole.
- the bottom 87 a of the concave curve 87 is positioned under the rigid insulating substrate 82 having high rigidity.
- an end portion of the insulating substrate 82 is lifted up between the insulating substrates 81 and 82 and a gap tends to appear at a contact surface 91 between the radiator plate 83 and a cooling fin 90 .
- a curve corresponding to each of the insulating substrates 71 and 72 is formed without taking a curve of the entire radiator plate 73 into consideration. This may lead to considerable curve deformation of the entire radiator plate 73 . If considerable initial curving is performed, the following problems, for example, tend to arise. A semiconductor chip mounted over the insulating substrate 71 or 72 at assembly time shifts, or a void appears in solder between the insulating substrate 71 or 72 and the radiator plate 73 .
- the insulating substrates 71 and 72 are simply placed over the radiator plate 73 . Therefore, as described in FIGS. 13A and 13B , the bottom of the concave curve may be positioned under the rigid insulating substrate 72 having high rigidity. In that case, stress concentrates in the clearance 75 between the insulating substrates 71 and 72 having low rigidity and a crack tends to appear in solder by which the insulating substrate 72 is adhered to the radiator plate 73 . In addition, an end portion of the insulating substrate 72 is lifted up in the clearance 75 between the insulating substrates 71 and 72 and a gap tends to appear between the radiator plate 73 and the cooling fin.
- Japanese Laid-open Patent Publication No. 2008-91959 does not state that when the insulating substrates of different shapes are soldered to the radiator plate in order to prevent the above troubles, a bottom of the curve (initial curving) formed on the radiator plate before the soldering is positioned under clearance between the insulating substrate.
- a semiconductor module radiator plate fabrication method which includes: soldering a plurality of insulating substrates of different shapes to a flat radiator plate, and forming a convex curve on an insulating substrate side of the radiator plate; obtaining a first concave curve by reversing the convex curve; setting a second concave curve on an insulating substrate side of a radiator plate after soldering, a bottom of the second concave curve being positioned under clearance between the plurality of insulating substrates; adding the first curve and the second curve to calculate a third concave curve on the insulating substrate side; and forming the third curve on a flat plate to form a radiator plate before soldering.
- FIG. 1 illustrates a semiconductor module radiator plate fabrication method according to a first example, where (a) to (d) are fragmentary sectional views of steps indicated in order;
- FIG. 2 is a fragmentary plan view which illustrates a state in which, as a result of soldering two insulating substrates of different shapes to a flat radiator plate, a convex curve is formed on an insulating substrate side of the radiator plate;
- FIGS. 3A and 3B are views which illustrate the structure of a semiconductor module radiator plate according to a second example, FIG. 3A being a fragmentary plan view which illustrates the structure of a semiconductor module radiator plate according to a second example, FIG. 3B being a fragmentary sectional view taken along lines X-X of FIG. 3A ;
- FIGS. 4A and 4B are views for describing a concrete method for fabricating the radiator plate illustrated in FIGS. 3A and 3B , FIG. 4A being a view which illustrates a flat plate put between dies, FIG. 4B being a view which illustrates a radiator plate fabricated by pressing the flat plate between the dies;
- FIG. 5 illustrates fragmentary sectional views of a semiconductor module according to a third example, where (a) is a fragmentary sectional view of an entire semiconductor module, and (b) is a fragmentary sectional view of a curve of a back of the radiator plate of (a);
- FIG. 6 illustrates fragmentary sectional views of the semiconductor module radiator plate of FIG. 5 fixed onto a cooling fin by the use of clamp holes, where (a) is a fragmentary sectional view of the whole of the semiconductor module and a cooling fin, (b) is a fragmentary sectional view of the curve of the back of the radiator plate, and (c) is a fragmentary sectional view which illustrates the back of the radiator plate in a flat state after fixing the radiator plate onto a cooling fin;
- FIG. 7 is a fragmentary sectional view of a semiconductor module
- FIG. 8 is a fragmentary sectional view of the semiconductor module fixed onto a cooling fin
- FIG. 9 is a schematic sectional view of a flat radiator plate to which two insulating substrates of the same shape are soldered;
- FIG. 10 is a schematic sectional view of a concave curve formed for canceling out the convex curve of the radiator plate illustrated in FIG. 9 ;
- FIG. 11 is a schematic sectional view of a curve of a radiator plate before soldering insulating substrates of different shapes to the radiator plate, which is described in Japanese Laid-open Patent Publication No. 2007-88045;
- FIG. 12 is a schematic sectional view of a radiator plate to which two insulating substrates different shapes are soldered.
- FIGS. 13A and 13B are schematic views of the radiator plate of FIG. 12 before and after being fixed onto a cooling fin
- FIG. 13A being a schematic view of the radiator plate before being fixed onto the cooling fin
- FIG. 13B being a schematic view of the radiator plate after being fixed onto the cooling fin.
- FIG. 1 illustrates a semiconductor module radiator plate fabrication method according to a first example, and parts (a) to (d) of FIG. 1 are fragmentary sectional views of steps indicated in order.
- a case where two insulating substrates of different shapes are soldered to a radiator plate is taken as an example.
- the topmost figure illustrates the arrangement of two insulating substrates 1 and 2 of different shapes and a radiator plate 3 .
- each radiator plate is indicated uniformly by the numeral 3 .
- the flat radiator plate 3 and the two insulating substrates 1 and 2 of different shapes which differ in area are prepared for data acquisition.
- the insulating substrates 1 and 2 are soldered to determined positions on one of the radiator plate 3 .
- a convex curve 4 with a top 4 a formed on an insulating substrate (insulating substrates 1 and 2 ) side of the radiator plate 3 is measured.
- the shape from above of each of the insulating substrates 1 and 2 and the radiator plate 3 is rectangular.
- each of the insulating substrates 1 and 2 is arranged so that its one side will be parallel to a long side of the radiator plate 3 .
- the top 4 a of the convex curve 4 is positioned under the large insulating substrate 2 .
- the distance L 11 between the top 4 a and a reference point 5 a on a small insulating substrate 1 side is longer than the distance L 21 between the top 4 a and a reference point 5 b on a large insulating substrate 2 side.
- the intersections on a back 15 side of the radiator plate 3 of straight lines (in a Y direction) which connect the centers of clamp holes 5 made in a periphery of the radiator plate 3 and a straight line drawn in an X direction through the top 4 a of the curve 4 are used as reference points 5 a and 5 b for measurement, scanning is performed on an X-X line which connects the reference points 5 a and 5 b by the use of a probe of a measuring device (not illustrated), and a depth profile is obtained.
- a probe of a measuring device not illustrated
- a concave curve is obtained as a first curve 6 by moving the measured convex curve 4 illustrated in part (a) of FIG. 1 upside down (concave curve obtained by reversing the curve 4 with respect to the X-X line or an X-Y plane including the reference points 5 a and 5 b ).
- a bottom 6 a of the first curve 6 is positioned under the large insulating substrate 2 .
- a curvature R 11 of a portion of the first curve 6 for which the distance (L 11 ) between the bottom 6 a of the first curve 6 and the reference point 5 a is longer is smaller than a curvature R 21 of a portion of the first curve 6 for which the distance (L 21 ) between the bottom 6 a of the first curve 6 and the reference point 5 b is shorter. That is to say, curvature R 11 (gentle curve) ⁇ curvature R 21 (sharp curve).
- a concave curve of the radiator plate 3 to be realized at the time of soldering the insulating substrates 1 and 2 to the determined positions is specified.
- the specified concave curve is set as a second curve 7 .
- the second curve 7 is specified so that a bottom 7 a of the second curve 7 will be positioned under clearance 8 between the two insulating substrates 1 and 2 and so that the second curve 7 will be concave on the insulating substrate (insulating substrates 1 and 2 ) side.
- the second curve 7 is practically identical to a third curve 11 formed at the time of actually soldering the insulating substrates 1 and 2 of different shapes to the radiator plate 3 .
- the bottom 7 a of the second curve 7 be positioned under clearance between, for example, the insulating substrates 1 and 2 which are near the center of the radiator plate 3 .
- two straight lines 9 and 10 may be drawn between the bottom 7 a of the second curve 7 and the reference points 5 a and 5 b.
- a second plane is obtained as a surface.
- the radiator plate 3 is concavely curved downward by the two straight lines 9 and 10 , then clearance appears at the time of fixing the radiator plate 3 onto a cooling fin. It is preferable to avoid the appearance of clearance.
- the second curve 7 is represented by the two straight lines 9 and 10 , then the relationship “curvature R 1 ⁇ curvature R 2 ” regarding a third curve 11 illustrated in part (d) of FIG. 1 becomes more significant.
- a profile of the second curve 7 is superimposed on a profile of the first curve 6 .
- an addition is performed to calculate a profile of the third concave curve 11 .
- a bottom 11 a of the third curve 11 is positioned near the bottom 6 a of the first curve 6 .
- the third curve 11 has a shape for canceling out a convex curve formed on the insulating substrate (insulating substrates 1 and 2 ) side at the time of soldering and for forming the second concave curve 7 .
- the third curve 11 is a curve of the radiator plate 3 before soldering (initial curving).
- a curvature R 1 of a portion of the third curve 11 for which the distance (L 1 ) between the bottom 11 a of the third curve 11 and the reference point 5 a is longer is smaller than a curvature R 2 of a portion of the third curve 11 for which the distance (L 2 ) between the bottom 11 a of the third curve 11 and the reference point 5 b is shorter. That is to say, curvature R 1 (gentle curve) ⁇ curvature R 2 (sharp curve).
- the position of the bottom 11 a of the third curve 11 is approximately identical to that of the bottom 6 a of the first curve 6 .
- the radiator plate 3 having a fourth curve 21 close to the second curve 7 is obtained.
- This radiator plate 3 is included in a semiconductor module.
- the shape of the third curve 11 is determined from a curve of the entire radiator plate 3 .
- curves are determined according to insulating substrates and these curves are combined to determine an entire curve.
- the third curve 11 does not become too sharp. Accordingly, when the radiator plate 3 is fixed onto the cooling fin, it is possible to prevent a crack from appearing in solder between the insulating substrates 1 and 2 and the radiator plate 3 .
- the third curve is calculated from the first curve 6 found by the experiment and the set second curve 7 . Therefore, the management of the third curve 11 is not so complex as the management of conventional curves and is easy.
- FIGS. 3A and 3B are views which illustrate the structure of a semiconductor module radiator plate according to a second example.
- FIG. 3A is a fragmentary plan view which illustrates the structure of a semiconductor module radiator plate according to a second example.
- FIG. 3B is a fragmentary sectional view taken along lines X-X of FIG. 3A .
- Part (d) of FIG. 1 illustrates only the curve in the X direction.
- the fabrication method according to the first example is extended to a surface.
- a curve in the Y direction is also measured by the same technique and a two-dimensional curve illustrated in FIG. 3A is obtained.
- a bottom 11 a of the two-dimensional curve is the same as the bottom 11 a of the third curve 11 .
- the third curve 11 is also used as a two-dimensional curve.
- the numeral 16 in FIG. 3A indicates a contour line of the third curve 11 .
- the bottom 11 a of the third curve 11 is positioned near the bottom 6 a of the above first curve 6 and a curvature R 1 of a portion of the third curve 11 for which the distance (L 1 ) between the bottom 11 a of the third curve 11 and the reference point 5 a is longer is smaller than a curvature R 2 of a portion of the third curve 11 for which the distance (L 2 ) between the bottom 11 a of the third curve 11 and the reference point 5 b is shorter (R 1 ⁇ R 2 ).
- FIGS. 4A and 4B are views for describing a concrete method for fabricating the radiator plate illustrated in FIGS. 3A and 3B .
- FIG. 4A is a view which illustrates a flat plate put between dies.
- FIG. 4B is a view which illustrates a radiator plate fabricated by pressing the flat plate between the dies.
- a concave die 17 and a convex die 18 each having the above third curve 11 are made.
- a flat plate 19 made of copper or a copper alloy is put between the concave die 17 and the convex die 18 and is pressed between them. By doing so, the radiator plate having the third curve 11 is fabricated.
- the clamp holes 5 are made in the periphery of the radiator plate 3 .
- the straight lines which connect the centers of the clamp holes 5 are needed for determining the reference points 5 a and 5 b (see FIGS. 2 and 3 ) used for measuring the curvatures R 1 and R 2 of the third curve 11 .
- FIG. 5 illustrates fragmentary sectional views of a semiconductor module according to a third example.
- Part (a) of FIG. 5 is a fragmentary sectional view of an entire semiconductor module.
- Part (b) of FIG. 5 is a fragmentary sectional view of a curve of a back of the radiator plate of part (a) of FIG. 5 .
- the radiator plate 3 illustrated in FIGS. 3A and 3B is used in a semiconductor module 100 .
- the semiconductor module 100 includes the radiator plate 3 , insulating substrates with a conductive pattern (above insulating substrates 1 and 2 ) back conductive films (not illustrated) of which are adhered to the radiator plate 3 with solder 25 between, semiconductor chips 27 adhered to a conductive pattern (not illustrated) of the radiator plate 3 with solder 26 between, bonding wires 28 which connect surface electrodes (not illustrated) of the semiconductor chips 27 and the conductive patterns, wiring conductors 29 one end of each of which is connected to a conductive pattern, lead-out terminals 30 to each of which the other end of each of the wiring conductor 29 is adhered, a resin case 31 to which the lead-out terminals 30 are adhered, and gel 32 with which the resin case 31 is filled.
- the insulating substrates 1 and 2 are soldered to the radiator plate 3 having the third curve. By doing so, a bottom 21 a of the fourth concave curve 21 of the radiator plate 3 is positioned under the clearance 8 between the insulating substrates 1 and 2 .
- the fourth curve 21 is very close to the above second curve 7 .
- FIG. 6 illustrates fragmentary sectional views of the semiconductor module radiator plate of FIG. 5 fixed onto a cooling fin by the use of clamp holes.
- Part (a) of FIG. 6 is a fragmentary sectional view of the whole of the semiconductor module and a cooling fin.
- Part (b) of FIG. 6 is a fragmentary sectional view of the curve of the back of the radiator plate.
- Part (c) of FIG. 6 is a fragmentary sectional view which illustrates the back of the radiator plate in a flat state after fixing the radiator plate onto a cooling fin.
- the bottom 21 a of the fourth concave curve 21 of the radiator plate 3 is positioned under the clearance 8 between the insulating substrates 1 and 2 , so the radiator plate 3 having low rigidity is pressed against a cooling fin 33 with the bottom 21 a of the fourth curve 21 and the clamp holes 5 of the radiator plate 3 as supporting points. At this time there is no supporting point (bottom 21 a of the fourth curve 21 ) in the insulating substrate 2 having high rigidity. As a result, the whole of the back 15 of the radiator plate 3 adheres closely to the cooling fin 33 and the appearance of a gap between the radiator plate 3 and the cooling fin 33 is prevented.
- the shape of the third curve 11 is determined from a curve of the entire radiator plate 3 , so the third curve 11 does not become too sharp. Accordingly, when the radiator plate 3 is fixed onto the cooling fin 33 , the appearance of a crack in the solder 25 between the insulating substrates 1 and 2 and the radiator plate 3 is prevented.
- a material for the above radiator plate 3 is copper, a copper alloy (C19220 or C19210, for example), or the like. Furthermore, insulating plates made of alumina, aluminum nitride, silicon nitride, or the like are used as the insulating substrates 1 and 2 mounted over the radiator plate 3 .
- a third concave curve is formed in advance on an insulating substrate side of the radiator plate.
- the third curve is determined by adding a second concave curve which is expected at the time of actually soldering the insulating substrates of different shapes to the radiator plate to a first concave curve obtained by moving upside down a convex curve which appears at the time of soldering the insulating substrates of different shapes to a flat radiator plate.
- a bottom of the third curve is positioned under a large insulating substrate and a curvature of a portion of the third curve for which the distance between this bottom and a reference point determined on the basis of the clamping of the radiator plate is longer is made smaller than a curvature of a portion of the third curve for which the distance between the bottom and a reference point determined on the basis of the clamping of the radiator plate is shorter.
- a bottom of a concave portion of the radiator plate is positioned between the insulating substrates.
- the third curve is calculated from a first curve found by actual measurement and the set second curve. Accordingly, the management of the third curve is not so complex as the management of conventional curves and is easy.
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Abstract
When insulating substrates of different shapes are soldered to a radiator plate, a third concave curve is previously formed on an insulating substrate side of the radiator plate. The third curve is determined by adding a second concave curve which is expected at the time of actually soldering the insulating substrates to the radiator plate to a first concave curve obtained by moving upside down a convex curve which appears at the time of soldering the insulating substrates to a flat radiator plate. A bottom of the third curve is positioned under the large insulating substrate, and a curvature of a portion where the distance between the bottom and a reference point of the radiator plate is longer is made smaller than a curvature of a portion where the distance between the bottom and a reference point of the radiator plate is shorter.
Description
- This application is a continuation application of International Application PCT/JP2011/070035 filed on Sep. 2, 2011 which designated the U.S., which claims priority to Japanese Patent Application No. 2011-024610, filed on Feb. 8, 2011, the entire contents of which are incorporated herein by reference.
- The embodiments discussed herein are related to a semiconductor module radiator plate fabrication method, a radiator plate, and a semiconductor module using such a radiator plate.
-
FIG. 7 is a fragmentary sectional view of a semiconductor module. Asemiconductor module 500 includes aradiator plate 51, aback electrode film 53 of an insulating substrate with a conductive pattern (hereinafter simply referred to as the insulating substrate 56) which is adhered to theradiator plate 51 withsolder 52 between, asemiconductor chip 57 adhered to aconductive pattern 55 formed over theinsulating substrate 56 with solder between, abonding wire 59 which connects a surface electrode (not illustrated) of thesemiconductor chip 57 and theconductive pattern 55, awiring conductor 60 one end of which is connected to theconductive pattern 55, a lead-outterminal 61 to which the other end of thewiring conductor 60 is adhered, aresin case 62 to which the lead-outterminal 61 is adhered, andgel 63 with which theresin case 62 is filled.Clamp holes 64 are made in theradiator plate 51 of thesemiconductor module 500 for fixing theradiator plate 51 onto a cooling fin (not illustrated). The aboveinsulating substrate 56 includes theback electrode film 53, an insulating plate which is a ceramic plate or the like, and theconductive pattern 55 formed over its surface. In many cases, theback electrode film 53 and theconductive pattern 55 are formed by the use of copper foil or the like. -
FIG. 8 is a fragmentary sectional view of the semiconductor module fixed onto a cooling fin. Thesemiconductor module 500 is fixed onto acooling fin 65 by inserting bolts or the like (not illustrated) into theclamp holes 64 made in a periphery of theradiator plate 51. -
FIG. 9 is a schematic sectional view of a flat radiator plate to which two insulating substrates of the same shape are soldered. As illustrated inFIG. 7 , eachinsulating substrate 56 is obtained by forming theback electrode film 53 on the back of theinsulating plate 54, such as a ceramic plate, and forming theconductive pattern 55 on the front of theinsulating plate 54. The linear expansion coefficient of theradiator plate 51 made of copper or aluminum is higher than that of eachinsulating substrate 56, so theradiator plate 51 to which theinsulating substrates 56 are soldered curves due to a bimetal effect so that it will be convex on an insulating substrate (insulating substrates 56) side. That is to say, acurve 67 which is convex on the insulating substrate (insulating substrates 56) side is formed on aback 66 of theradiator plate 51. If theradiator plate 51 is attached in this state to theflat cooling fin 65, there will be abig gap 68 in the center of theradiator plate 51, resulting in a decrease in heat radiation efficiency. Measures to prevent this will now be described. -
FIG. 10 is a schematic sectional view of a concave curve formed for canceling out the convex curve of the radiator plate illustrated inFIG. 9 . - In order to cancel out the convex
curve 67 illustrated inFIG. 9 , areverse curve 69 is formed in advance so that the center of theradiator plate 51 will be concave on the insulating substrate (insulating substrates 56) side (which is referred to as reverse curving or initial curving). Thisreverse curve 69 is formed rather sharp so that theradiator plate 51 will not become convex on the insulating substrate (insulating substrates 56) side even after soldering. - When the
insulating substrates 56 are soldered to theradiator plate 51 by which thereverse curve 69 indicated by a dashed line is formed, theconvex curve 67 illustrated inFIG. 9 is canceled out and acurve 70 which is concave on the insulating substrate (insulating substrates 56) side is formed. When theradiator plate 51 is attached in this state to thecooling fin 65 by the use of theclamp holes 64, the center of the radiator plate 51 (bottom 70 a of the concave curve 70) touches thecooling fin 65, both ends of theradiator plate 51 are pressed against thecooling fin 65 with the bottom 70 a as a supporting point, and the whole of theback 66 of theradiator plate 51 adheres to thecooling fin 65. - Furthermore, according to Japanese Laid-open Patent Publication No. 2007-88045, as illustrated in
FIG. 11 , ifinsulating substrates radiator plate 73, asharp curve 74 includingconcave curves insulating substrates radiator plate 73. It is assumed that the sizes of thecurves insulating substrates radiator plate 73, the sharpconcave curve 74 becomes a gentle concave curve (not illustrated). Theradiator plate 73 to which theinsulating substrates radiator plate 73 and the cooling fin. - In addition, according to Japanese Laid-open Patent Publication No. 2008-91959 (not illustrated), when an insulating substrate is adhered to a radiator plate by the use of solder, a concave curve (reverse curve) is formed in advance on an insulating substrate side of the radiator plate and then the insulating substrate is soldered. By doing so, the radiator plate is kept in a reversely curved state (having a concave curve on the insulating substrate side) even after the soldering. By attaching the radiator plate in a reversely curved state to a cooling fin, there appears no gap between the radiator plate and the cooling fin.
- In
FIG. 10 , if the insulatingsubstrates 56 soldered to theradiator plate 51 have the same shape and are arranged left-right symmetrically, then theradiator plate 51 curves left-right symmetrically as a result of the soldering so that its center will be convex on the insulating substrate (insulating substrates 56) side. A bottom 69 a of theconcave curve 69 which cancels out this curve is positioned at the center of theradiator plate 51, so theconcave curve 69 formed on theradiator plate 51 may be managed at a depth at the center of theradiator plate 51. As a result, management can be exercised easily. Next, a case where two insulating substrates of different shapes are soldered to a radiator plate will be described. -
FIG. 12 is a schematic sectional view of a radiator plate to which two insulating substrates of different shapes are soldered. When insulating substrates and 82 of different shapes are adhered to aflat radiator plate 83 by the use ofsolder 84, left-hand and right-hand portions of aconvex curve 85 which appears on an insulating substrate (insulatingsubstrates 81 and 82) side after the soldering differ in curvature. Therefore, in order to cancel out the difference in curvature, aconcave curve 86 left-hand and right-hand portions of which differ in curvature, that is to say, curvatures of the left-hand and right-hand portions of which are R3 and R4, respectively, may be formed in advance on theradiator plate 83. - When the insulating
substrates radiator plate 83 having thecurve 86, theradiator plate 83 is deformed into theradiator plate 83 having aconcave curve 87 a bottom 87 a of which is positioned under the insulatingsubstrate 82. - With the method of forming the concave curve in this way, a position at which the left-hand and right-hand portions of the
curve 86 which differ in curvature, that is to say, the curvatures of which are R3 and R4, respectively, connect deviates from the center and becomes unclear. Accordingly, it is difficult to manage thecurve 86. - Furthermore, the
curve 86 the left-hand and right-hand portions of which differ in curvature, that is to say, the curvatures of the left-hand and right-hand portions of which are R3 and R4, respectively, may be formed on theradiator plate 83 for canceling out theconvex curve 85 which appears as a result of soldering the insulatingsubstrates curve 86 is complex. -
FIGS. 13A and 13B are schematic views of the radiator plate ofFIG. 12 before and after being fixed onto a cooling fin.FIG. 13A is a schematic view of the radiator plate before being fixed onto the cooling fin.FIG. 13B is a schematic view of the radiator plate after being fixed onto the cooling fin. Thereference sign 92 inFIGS. 13A and 13B indicates a clamp hole. - As illustrated in
FIG. 13A , the bottom 87 a of theconcave curve 87 is positioned under the rigid insulatingsubstrate 82 having high rigidity. As a result, stress concentrates inclearance 88 having low rigidity between the insulatingsubstrates FIG. 13B , acrack 89 tends to appear in thesolder 84, or a crack (not illustrated) tends to appear in the insulatingsubstrate substrate 82 is lifted up between the insulatingsubstrates contact surface 91 between theradiator plate 83 and a coolingfin 90. - According to Japanese Laid-open Patent Publication No. 2007-88045, a curve corresponding to each of the insulating
substrates entire radiator plate 73 into consideration. This may lead to considerable curve deformation of theentire radiator plate 73. If considerable initial curving is performed, the following problems, for example, tend to arise. A semiconductor chip mounted over the insulatingsubstrate substrate radiator plate 73. - Furthermore, the insulating
substrates radiator plate 73. Therefore, as described inFIGS. 13A and 13B , the bottom of the concave curve may be positioned under the rigid insulatingsubstrate 72 having high rigidity. In that case, stress concentrates in theclearance 75 between theinsulating substrates insulating substrate 72 is adhered to theradiator plate 73. In addition, an end portion of theinsulating substrate 72 is lifted up in theclearance 75 between theinsulating substrates radiator plate 73 and the cooling fin. - Furthermore, Japanese Laid-open Patent Publication No. 2008-91959 does not state that when the insulating substrates of different shapes are soldered to the radiator plate in order to prevent the above troubles, a bottom of the curve (initial curving) formed on the radiator plate before the soldering is positioned under clearance between the insulating substrate.
- According to an aspect of the embodiments to be discussed herein, there is provided a semiconductor module radiator plate fabrication method which includes: soldering a plurality of insulating substrates of different shapes to a flat radiator plate, and forming a convex curve on an insulating substrate side of the radiator plate; obtaining a first concave curve by reversing the convex curve; setting a second concave curve on an insulating substrate side of a radiator plate after soldering, a bottom of the second concave curve being positioned under clearance between the plurality of insulating substrates; adding the first curve and the second curve to calculate a third concave curve on the insulating substrate side; and forming the third curve on a flat plate to form a radiator plate before soldering.
- The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention.
-
FIG. 1 illustrates a semiconductor module radiator plate fabrication method according to a first example, where (a) to (d) are fragmentary sectional views of steps indicated in order; -
FIG. 2 is a fragmentary plan view which illustrates a state in which, as a result of soldering two insulating substrates of different shapes to a flat radiator plate, a convex curve is formed on an insulating substrate side of the radiator plate; -
FIGS. 3A and 3B are views which illustrate the structure of a semiconductor module radiator plate according to a second example,FIG. 3A being a fragmentary plan view which illustrates the structure of a semiconductor module radiator plate according to a second example,FIG. 3B being a fragmentary sectional view taken along lines X-X ofFIG. 3A ; -
FIGS. 4A and 4B are views for describing a concrete method for fabricating the radiator plate illustrated inFIGS. 3A and 3B ,FIG. 4A being a view which illustrates a flat plate put between dies,FIG. 4B being a view which illustrates a radiator plate fabricated by pressing the flat plate between the dies; -
FIG. 5 illustrates fragmentary sectional views of a semiconductor module according to a third example, where (a) is a fragmentary sectional view of an entire semiconductor module, and (b) is a fragmentary sectional view of a curve of a back of the radiator plate of (a); -
FIG. 6 illustrates fragmentary sectional views of the semiconductor module radiator plate ofFIG. 5 fixed onto a cooling fin by the use of clamp holes, where (a) is a fragmentary sectional view of the whole of the semiconductor module and a cooling fin, (b) is a fragmentary sectional view of the curve of the back of the radiator plate, and (c) is a fragmentary sectional view which illustrates the back of the radiator plate in a flat state after fixing the radiator plate onto a cooling fin; -
FIG. 7 is a fragmentary sectional view of a semiconductor module; -
FIG. 8 is a fragmentary sectional view of the semiconductor module fixed onto a cooling fin; -
FIG. 9 is a schematic sectional view of a flat radiator plate to which two insulating substrates of the same shape are soldered; -
FIG. 10 is a schematic sectional view of a concave curve formed for canceling out the convex curve of the radiator plate illustrated inFIG. 9 ; -
FIG. 11 is a schematic sectional view of a curve of a radiator plate before soldering insulating substrates of different shapes to the radiator plate, which is described in Japanese Laid-open Patent Publication No. 2007-88045; -
FIG. 12 is a schematic sectional view of a radiator plate to which two insulating substrates different shapes are soldered; and -
FIGS. 13A and 13B are schematic views of the radiator plate ofFIG. 12 before and after being fixed onto a cooling fin,FIG. 13A being a schematic view of the radiator plate before being fixed onto the cooling fin,FIG. 13B being a schematic view of the radiator plate after being fixed onto the cooling fin. - Embodiments will be described by the following examples.
-
FIG. 1 illustrates a semiconductor module radiator plate fabrication method according to a first example, and parts (a) to (d) ofFIG. 1 are fragmentary sectional views of steps indicated in order. A case where two insulating substrates of different shapes are soldered to a radiator plate is taken as an example. The topmost figure illustrates the arrangement of two insulatingsubstrates radiator plate 3. In the following description each radiator plate is indicated uniformly by thenumeral 3. - First the
flat radiator plate 3 and the two insulatingsubstrates substrates radiator plate 3. As illustrated in part (a) ofFIG. 1 , aconvex curve 4 with a top 4 a formed on an insulating substrate (insulatingsubstrates 1 and 2) side of theradiator plate 3 is measured. In this case, the shape from above of each of the insulatingsubstrates radiator plate 3 is rectangular. Furthermore, each of the insulatingsubstrates radiator plate 3. - The top 4 a of the
convex curve 4 is positioned under the large insulatingsubstrate 2. The distance L11 between the top 4 a and areference point 5 a on a smallinsulating substrate 1 side is longer than the distance L21 between the top 4 a and areference point 5 b on a largeinsulating substrate 2 side. - As illustrated in
FIG. 2 , to measure theconvex curve 4, the intersections on a back 15 side of theradiator plate 3 of straight lines (in a Y direction) which connect the centers ofclamp holes 5 made in a periphery of theradiator plate 3 and a straight line drawn in an X direction through the top 4 a of thecurve 4 are used asreference points reference points - Next, as illustrated in part (b) of
FIG. 1 , a concave curve is obtained as afirst curve 6 by moving the measuredconvex curve 4 illustrated in part (a) ofFIG. 1 upside down (concave curve obtained by reversing thecurve 4 with respect to the X-X line or an X-Y plane including thereference points first curve 6 is positioned under the large insulatingsubstrate 2. A curvature R11 of a portion of thefirst curve 6 for which the distance (L11) between the bottom 6 a of thefirst curve 6 and thereference point 5 a is longer is smaller than a curvature R21 of a portion of thefirst curve 6 for which the distance (L21) between the bottom 6 a of thefirst curve 6 and thereference point 5 b is shorter. That is to say, curvature R11 (gentle curve)<curvature R21 (sharp curve). - Next, as illustrated in part (c) of
FIG. 1 , a concave curve of theradiator plate 3 to be realized at the time of soldering the insulatingsubstrates second curve 7. In this case, thesecond curve 7 is specified so that a bottom 7 a of thesecond curve 7 will be positioned underclearance 8 between the two insulatingsubstrates second curve 7 will be concave on the insulating substrate (insulatingsubstrates 1 and 2) side. Thesecond curve 7 is practically identical to athird curve 11 formed at the time of actually soldering the insulatingsubstrates radiator plate 3. When three or more insulating substrates are soldered to theradiator plate 3, it is desirable that the bottom 7 a of thesecond curve 7 be positioned under clearance between, for example, the insulatingsubstrates radiator plate 3. - Furthermore, as indicated by dotted lines, two
straight lines 9 and 10 may be drawn between the bottom 7 a of thesecond curve 7 and thereference points radiator plate 3 is concavely curved downward by the twostraight lines 9 and 10, then clearance appears at the time of fixing theradiator plate 3 onto a cooling fin. It is preferable to avoid the appearance of clearance. If thesecond curve 7 is represented by the twostraight lines 9 and 10, then the relationship “curvature R1<curvature R2” regarding athird curve 11 illustrated in part (d) ofFIG. 1 becomes more significant. - Next, as illustrated in part (d) of
FIG. 1 , a profile of thesecond curve 7 is superimposed on a profile of thefirst curve 6. By doing so, an addition is performed to calculate a profile of the thirdconcave curve 11. A bottom 11 a of thethird curve 11 is positioned near the bottom 6 a of thefirst curve 6. Thethird curve 11 has a shape for canceling out a convex curve formed on the insulating substrate (insulatingsubstrates 1 and 2) side at the time of soldering and for forming the secondconcave curve 7. Thethird curve 11 is a curve of theradiator plate 3 before soldering (initial curving). A curvature R1 of a portion of thethird curve 11 for which the distance (L1) between the bottom 11 a of thethird curve 11 and thereference point 5 a is longer is smaller than a curvature R2 of a portion of thethird curve 11 for which the distance (L2) between the bottom 11 a of thethird curve 11 and thereference point 5 b is shorter. That is to say, curvature R1 (gentle curve)<curvature R2 (sharp curve). - In addition, the position of the bottom 11 a of the
third curve 11 is approximately identical to that of the bottom 6 a of thefirst curve 6. - When the insulating
substrates radiator plate 3 having thethird curve 11, then theradiator plate 3 having a fourth curve 21 (seeFIG. 5 ) close to thesecond curve 7 is obtained. Thisradiator plate 3 is included in a semiconductor module. - For the sake of simplicity one dimension has been described above, but in reality concave curves are two-dimensionally measured to obtain the
first curve 6, thesecond curve 7, and thethird curve 11. - In this example, as stated above, the shape of the
third curve 11 is determined from a curve of theentire radiator plate 3. With Japanese Laid-open Patent Publication No. 2007-88045, curves are determined according to insulating substrates and these curves are combined to determine an entire curve. In this example, on the other hand, thethird curve 11 does not become too sharp. Accordingly, when theradiator plate 3 is fixed onto the cooling fin, it is possible to prevent a crack from appearing in solder between the insulatingsubstrates radiator plate 3. - Furthermore, as stated above, the third curve is calculated from the
first curve 6 found by the experiment and the setsecond curve 7. Therefore, the management of thethird curve 11 is not so complex as the management of conventional curves and is easy. -
FIGS. 3A and 3B are views which illustrate the structure of a semiconductor module radiator plate according to a second example.FIG. 3A is a fragmentary plan view which illustrates the structure of a semiconductor module radiator plate according to a second example.FIG. 3B is a fragmentary sectional view taken along lines X-X ofFIG. 3A . - Part (d) of
FIG. 1 illustrates only the curve in the X direction. In this example, however, the fabrication method according to the first example is extended to a surface. A curve in the Y direction is also measured by the same technique and a two-dimensional curve illustrated inFIG. 3A is obtained. A bottom 11 a of the two-dimensional curve is the same as the bottom 11 a of thethird curve 11. In this case, it is assumed that thethird curve 11 is also used as a two-dimensional curve. The numeral 16 inFIG. 3A indicates a contour line of thethird curve 11. - On the
radiator plate 3 inFIGS. 3A and 3B on which the thirdconcave curve 11 is formed, the bottom 11 a of thethird curve 11 is positioned near the bottom 6 a of the abovefirst curve 6 and a curvature R1 of a portion of thethird curve 11 for which the distance (L1) between the bottom 11 a of thethird curve 11 and thereference point 5 a is longer is smaller than a curvature R2 of a portion of thethird curve 11 for which the distance (L2) between the bottom 11 a of thethird curve 11 and thereference point 5 b is shorter (R1<R2). One reason for this is that the curvature R11 of the portion of thefirst curve 6 in part (b) ofFIG. 1 for which the distance (L11) between the bottom 6 a of thefirst curve 6 and thereference point 5 a is longer is smaller than the curvature R21 of the portion of thefirst curve 6 for which the distance (L21) between the bottom 6 a of thefirst curve 6 and thereference point 5 b is shorter. -
FIGS. 4A and 4B are views for describing a concrete method for fabricating the radiator plate illustrated inFIGS. 3A and 3B .FIG. 4A is a view which illustrates a flat plate put between dies.FIG. 4B is a view which illustrates a radiator plate fabricated by pressing the flat plate between the dies. Aconcave die 17 and aconvex die 18 each having the abovethird curve 11 are made. Aflat plate 19 made of copper or a copper alloy is put between theconcave die 17 and theconvex die 18 and is pressed between them. By doing so, the radiator plate having thethird curve 11 is fabricated. The clamp holes 5 are made in the periphery of theradiator plate 3. - The straight lines which connect the centers of the clamp holes 5 are needed for determining the
reference points FIGS. 2 and 3 ) used for measuring the curvatures R1 and R2 of thethird curve 11. -
FIG. 5 illustrates fragmentary sectional views of a semiconductor module according to a third example. Part (a) ofFIG. 5 is a fragmentary sectional view of an entire semiconductor module. Part (b) ofFIG. 5 is a fragmentary sectional view of a curve of a back of the radiator plate of part (a) ofFIG. 5 . Theradiator plate 3 illustrated inFIGS. 3A and 3B is used in asemiconductor module 100. - The
semiconductor module 100 includes theradiator plate 3, insulating substrates with a conductive pattern (above insulatingsubstrates 1 and 2) back conductive films (not illustrated) of which are adhered to theradiator plate 3 withsolder 25 between,semiconductor chips 27 adhered to a conductive pattern (not illustrated) of theradiator plate 3 withsolder 26 between,bonding wires 28 which connect surface electrodes (not illustrated) of the semiconductor chips 27 and the conductive patterns, wiringconductors 29 one end of each of which is connected to a conductive pattern, lead-outterminals 30 to each of which the other end of each of thewiring conductor 29 is adhered, aresin case 31 to which the lead-outterminals 30 are adhered, andgel 32 with which theresin case 31 is filled. - The insulating
substrates radiator plate 3 having the third curve. By doing so, a bottom 21 a of the fourthconcave curve 21 of theradiator plate 3 is positioned under theclearance 8 between the insulatingsubstrates fourth curve 21 is very close to the abovesecond curve 7. -
FIG. 6 illustrates fragmentary sectional views of the semiconductor module radiator plate ofFIG. 5 fixed onto a cooling fin by the use of clamp holes. Part (a) ofFIG. 6 is a fragmentary sectional view of the whole of the semiconductor module and a cooling fin. Part (b) ofFIG. 6 is a fragmentary sectional view of the curve of the back of the radiator plate. Part (c) ofFIG. 6 is a fragmentary sectional view which illustrates the back of the radiator plate in a flat state after fixing the radiator plate onto a cooling fin. - The bottom 21 a of the fourth
concave curve 21 of theradiator plate 3 is positioned under theclearance 8 between the insulatingsubstrates radiator plate 3 having low rigidity is pressed against a coolingfin 33 with the bottom 21 a of thefourth curve 21 and the clamp holes 5 of theradiator plate 3 as supporting points. At this time there is no supporting point (bottom 21 a of the fourth curve 21) in the insulatingsubstrate 2 having high rigidity. As a result, the whole of theback 15 of theradiator plate 3 adheres closely to the coolingfin 33 and the appearance of a gap between theradiator plate 3 and the coolingfin 33 is prevented. - As stated above, in this embodiment the shape of the
third curve 11 is determined from a curve of theentire radiator plate 3, so thethird curve 11 does not become too sharp. Accordingly, when theradiator plate 3 is fixed onto the coolingfin 33, the appearance of a crack in thesolder 25 between the insulatingsubstrates radiator plate 3 is prevented. - A material for the
above radiator plate 3 is copper, a copper alloy (C19220 or C19210, for example), or the like. Furthermore, insulating plates made of alumina, aluminum nitride, silicon nitride, or the like are used as the insulatingsubstrates radiator plate 3. - According to the present invention, when insulating substrates of different shapes are soldered to a radiator plate, a third concave curve is formed in advance on an insulating substrate side of the radiator plate. The third curve is determined by adding a second concave curve which is expected at the time of actually soldering the insulating substrates of different shapes to the radiator plate to a first concave curve obtained by moving upside down a convex curve which appears at the time of soldering the insulating substrates of different shapes to a flat radiator plate. A bottom of the third curve is positioned under a large insulating substrate and a curvature of a portion of the third curve for which the distance between this bottom and a reference point determined on the basis of the clamping of the radiator plate is longer is made smaller than a curvature of a portion of the third curve for which the distance between the bottom and a reference point determined on the basis of the clamping of the radiator plate is shorter.
- A bottom of a concave portion of the radiator plate is positioned between the insulating substrates. As a result, when the radiator plate is attached to a cooling fin, a crack does not appear in solder. In addition, a gap between the radiator plate and the cooling fin is made narrow. Accordingly, heat radiation properties can be improved.
- Furthermore, the third curve is calculated from a first curve found by actual measurement and the set second curve. Accordingly, the management of the third curve is not so complex as the management of conventional curves and is easy.
- All examples and conditional language provided herein are intended for the pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
Claims (7)
1. A semiconductor module radiator plate fabrication method comprising:
soldering a plurality of insulating substrates of different shapes to a flat radiator plate, and forming a convex curve on an insulating substrate side of the radiator plate;
obtaining a first concave curve by reversing the convex curve;
setting a second concave curve on an insulating substrate side of a radiator plate after soldering, a bottom of the second concave curve being positioned under clearance between the plurality of insulating substrates;
adding the first curve and the second curve to calculate a third concave curve on the insulating substrate side; and
forming the third curve on a flat plate to form a radiator plate before soldering.
2. A semiconductor module radiator plate having, on a side on which a plurality of insulating substrates of different shapes are soldered, a third concave curve obtained by adding a first concave curve obtained by reversing a convex curve formed, by soldering the plurality of insulating substrates of different shapes to a flat radiator plate, on an insulating substrate side of the radiator plate and a second concave curve which is set on an insulating substrate side of a radiator plate after soldering and a bottom of which is positioned under clearance between the plurality of insulating substrates.
3. The semiconductor module radiator plate according to claim 2 , wherein:
a bottom of the third curve is positioned under an insulating substrate which is the largest in area of the plurality of insulating substrates of different shapes; and
a curvature of a portion of the third curve positioned under an insulating substrate which is the smallest in area of the plurality of insulating substrates of different shapes is smaller than a curvature of a portion of the third curve positioned under the insulating substrate which is the largest in area of the plurality of insulating substrates of different shapes.
4. The semiconductor module radiator plate according to claim 3 , wherein a material is copper or a copper alloy.
5. A semiconductor module comprising:
a plurality of insulating substrates of different shapes; and
a semiconductor module radiator plate having, on a side on which the plurality of insulating substrates of different shapes are soldered, a third concave curve obtained by adding a first concave curve obtained by reversing a convex curve formed, by soldering the plurality of insulating substrates of different shapes to a flat radiator plate, on an insulating substrate side of the radiator plate and a second concave curve which is set on an insulating substrate side of a radiator plate after soldering and a bottom of which is positioned under clearance between the plurality of insulating substrates.
6. The semiconductor module according to claim 5 , wherein:
the curve of the semiconductor module radiator plate is concave on the insulating substrate side; and
a bottom of the concave curve is positioned under clearance between the plurality of insulating substrates.
7. The semiconductor module according to claim 6 , wherein a material for insulating plates used as the plurality of insulating substrates is alumina, aluminum nitride, or silicon nitride.
Priority Applications (1)
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US15/276,444 US10262874B2 (en) | 2011-02-08 | 2016-09-26 | Semiconductor module radiator plate fabrication method, radiator plate, and semiconductor module using the same |
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JP2011024610 | 2011-02-08 | ||
JP2011-024610 | 2011-02-08 | ||
PCT/JP2011/070035 WO2012108073A1 (en) | 2011-02-08 | 2011-09-02 | Method for manufacturing heat dissipating plate for semiconductor module, said heat dissipating plate, and semiconductor module using said heat dissipating plate |
Related Parent Applications (1)
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PCT/JP2011/070035 Continuation WO2012108073A1 (en) | 2011-02-08 | 2011-09-02 | Method for manufacturing heat dissipating plate for semiconductor module, said heat dissipating plate, and semiconductor module using said heat dissipating plate |
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US15/276,444 Division US10262874B2 (en) | 2011-02-08 | 2016-09-26 | Semiconductor module radiator plate fabrication method, radiator plate, and semiconductor module using the same |
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US20130306296A1 true US20130306296A1 (en) | 2013-11-21 |
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US13/950,928 Abandoned US20130306296A1 (en) | 2011-02-08 | 2013-07-25 | Semiconductor module radiator plate fabrication method, radiator plate, and semiconductor module using the same |
US15/276,444 Active 2031-11-20 US10262874B2 (en) | 2011-02-08 | 2016-09-26 | Semiconductor module radiator plate fabrication method, radiator plate, and semiconductor module using the same |
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US15/276,444 Active 2031-11-20 US10262874B2 (en) | 2011-02-08 | 2016-09-26 | Semiconductor module radiator plate fabrication method, radiator plate, and semiconductor module using the same |
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US (2) | US20130306296A1 (en) |
EP (1) | EP2674971B1 (en) |
JP (1) | JP5601384B2 (en) |
CN (1) | CN103339723B (en) |
WO (1) | WO2012108073A1 (en) |
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US20170011935A1 (en) * | 2011-02-08 | 2017-01-12 | Fuji Electric Co., Ltd. | Semiconductor module radiator plate fabrication method, radiator plate, and semiconductor module using the same |
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JP2018195717A (en) * | 2017-05-17 | 2018-12-06 | 富士電機株式会社 | Semiconductor module, semiconductor module base plate and semiconductor device manufacturing method |
JP2019054069A (en) * | 2017-09-14 | 2019-04-04 | 株式会社東芝 | Semiconductor device |
JP7086109B2 (en) * | 2018-01-10 | 2022-06-17 | 住友電気工業株式会社 | Manufacturing method of composite member, heat dissipation member, semiconductor device, and composite member |
US10679920B2 (en) * | 2018-01-22 | 2020-06-09 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device having semiconductor package in a wiring board opening |
WO2022085192A1 (en) * | 2020-10-23 | 2022-04-28 | 三菱電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
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Also Published As
Publication number | Publication date |
---|---|
US10262874B2 (en) | 2019-04-16 |
US20170011935A1 (en) | 2017-01-12 |
CN103339723A (en) | 2013-10-02 |
EP2674971B1 (en) | 2021-04-07 |
JPWO2012108073A1 (en) | 2014-07-03 |
WO2012108073A1 (en) | 2012-08-16 |
EP2674971A4 (en) | 2017-12-27 |
EP2674971A1 (en) | 2013-12-18 |
JP5601384B2 (en) | 2014-10-08 |
CN103339723B (en) | 2016-03-09 |
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