US20130297992A1 - Data processing device and data processing method - Google Patents

Data processing device and data processing method Download PDF

Info

Publication number
US20130297992A1
US20130297992A1 US13/996,108 US201113996108A US2013297992A1 US 20130297992 A1 US20130297992 A1 US 20130297992A1 US 201113996108 A US201113996108 A US 201113996108A US 2013297992 A1 US2013297992 A1 US 2013297992A1
Authority
US
United States
Prior art keywords
parity check
code
parity
check matrix
column
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/996,108
Other languages
English (en)
Inventor
Makiko YAMAMOTO
Yuji Shinohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Saturn Licensing LLC
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Assigned to SONY CORPORATION reassignment SONY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHINOHARA, YUJI, YAMAMOTO, MAKIKO
Publication of US20130297992A1 publication Critical patent/US20130297992A1/en
Assigned to SATURN LICENSING LLC reassignment SATURN LICENSING LLC ASSIGNMENT OF THE ENTIRE INTEREST SUBJECT TO AN AGREEMENT RECITED IN THE DOCUMENT Assignors: SONY CORPORATION
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6552—DVB-T2
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes

Definitions

  • variable node operation and the check node operation are repeatedly performed.
  • the information bits are encoded into the code word whose code length is 16200 bits and code rate is 8/15 based on the parity check matrix of the LDPC (low density parity check) code.
  • the encoded LDPC code includes the information bit and the parity bit
  • the parity check matrix includes the information matrix part corresponding to the information bit and the parity matrix part corresponding to the parity bit
  • the information matrix part is represented by the parity check matrix initial value table
  • the parity check matrix initial value table is the table indicating the position of the element 1 of the information matrix part for each 360 columns as
  • FIG. 37 is a view illustrating an example of the parity check matrix initial value table in which the code rate is 1/3 and the code length is 16200.
  • FIG. 41 is a view illustrating an example of the parity check matrix initial value table in which the code rate is 8/15 and the code length is 16200.
  • FIG. 18B illustrates a first interchanging scheme
  • FIG. 18C illustrates a second interchanging scheme
  • FIG. 18D illustrates a third interchanging scheme, respectively.
  • the mb code bits are allocated to mb symbol bits of successive b symbols in the interchanging process.
  • the i+1-th bit from the highest-order bit of the mb symbol bits of the successive b symbols is represented as the bit (symbol bit) y i for convenience of description.
  • the writing start position of the first column out of the eight columns of the memory 31 is set to the position whose address is 0, the writing start position of the second column is set to the position whose address is 0, the writing start position of the third column is set to the position whose address is 2, the writing start position of the fourth column is set to the position whose address is 4, the writing start position of the fifth column is set to the position whose address is 4, the writing start position of the sixth column is set to the position whose address is 5, the writing start position of the seventh column is set to the position whose address is 7, and the writing start position of the eighth column is set to the position whose address is 7.
  • the writing start position of the first column out of the four columns of the memory 31 is set to the position whose address is 0, the writing start position of the second column is set to the position whose address is 2, the writing start position of the third column is set to the position whose address is 3, and the writing start position of the fourth column is set to the position whose address is 3.
  • the information bit read unit 614 reads (extracts) the information bits as many as the information length K from the LDPC target data supplied to the LDPC encoder 115 .
  • the LDPC code of a shorter code length may make the memory required for the decoding of the LDPC code and the delay smaller as compared to those of the LDPC code of a longer code length, so that it is appropriate to adopt the 16 k-bit LDPC code whose code length is shorter of the LDPC codes of the two code lengths specified in DVB-T.2 in the digital broadcasting for the mobile terminal.
  • the LDPC code obtained using the parity check matrix H obtained from the parity check matrix initial value table in FIGS. 35 to 43 is a high-performance LDPC code.
  • the LDPC code whose code length N is 16 k (hereinafter, also referred to as a standard 16 k code) of the same code rate is specified in DVB-T.2.
  • the LDPC decoder 155 performs LDPC decoding of the LDPC code from the QAM decoder 154 and supplies the LDPC target data (herein, a BCH code) obtained as a result to a BCH decoder 156 .
  • the LDPC decoder 166 performs the LDPC decoding of the LDPC code from the bit deinterleaver 165 and supplies the LDPC target data (herein, the BCH code) obtained as a result to a BCH decoder 167 .
  • FIG. 56 is a block diagram illustrating a configuration example of the decoding device, which performs such decoding.
  • the constitutive matrix whose weight is 2 or larger the data corresponding to the position of 1 of the unit matrix, the quasi-unit matrix, and the shift matrix whose weight is 1 (the message corresponding to the edge belonging to the unit matrix, the quasi-unit matrix, or the shift matrix) when the constitutive matrix is represented as the sum of a plurality of the P ⁇ P unit matrix whose weight is 1, the quasi-unit matrix in which one or more of the elements 1 of the unit matrix is set to 0, and the shift matrix obtained by the cyclic shift of the unit matrix or the quasi-unit matrix is stored in the same address (same FIFO out of the FIFOs 304 1 to 304 18 ).
  • the program may be processed by one computer or processed by a plurality of computers. Further, the program may be transferred to a remote computer to be executed.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Error Detection And Correction (AREA)
US13/996,108 2010-12-28 2011-12-22 Data processing device and data processing method Abandoned US20130297992A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2010-292210 2010-12-28
JP2010292210 2010-12-28
JP2011-005189 2011-01-13
JP2011005189A JP5630278B2 (ja) 2010-12-28 2011-01-13 データ処理装置、及びデータ処理方法
PCT/JP2011/079928 WO2012090882A1 (fr) 2010-12-28 2011-12-22 Dispositif de traitement de données et procédé de traitement de données

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/079928 A-371-Of-International WO2012090882A1 (fr) 2010-12-28 2011-12-22 Dispositif de traitement de données et procédé de traitement de données

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/971,706 Continuation US10361724B2 (en) 2010-12-28 2018-05-04 Data processing device and data processing method for improving resistance to error of data

Publications (1)

Publication Number Publication Date
US20130297992A1 true US20130297992A1 (en) 2013-11-07

Family

ID=46382988

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/996,108 Abandoned US20130297992A1 (en) 2010-12-28 2011-12-22 Data processing device and data processing method
US15/971,706 Active US10361724B2 (en) 2010-12-28 2018-05-04 Data processing device and data processing method for improving resistance to error of data

Family Applications After (1)

Application Number Title Priority Date Filing Date
US15/971,706 Active US10361724B2 (en) 2010-12-28 2018-05-04 Data processing device and data processing method for improving resistance to error of data

Country Status (5)

Country Link
US (2) US20130297992A1 (fr)
EP (2) EP2660983B1 (fr)
JP (1) JP5630278B2 (fr)
CN (1) CN103339862B (fr)
WO (1) WO2012090882A1 (fr)

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140040707A1 (en) * 2011-04-28 2014-02-06 Sony Corporation Data processing device and data processing method
US20140082452A1 (en) * 2011-06-15 2014-03-20 Sony Corporation Data processing device and data processing method
US20140201593A1 (en) * 2013-01-16 2014-07-17 Maxlinear, Inc. Efficient Memory Architecture for Low Density Parity Check Decoding
US20150082118A1 (en) * 2013-09-18 2015-03-19 Samsung Electronics Co., Ltd. Transmitting apparatus and puncturing method thereof
US9026884B2 (en) 2011-05-27 2015-05-05 Sony Corporation Data processing device and data processing method
US20150128012A1 (en) * 2011-05-18 2015-05-07 Mihail Petrov Parallel bit interleaver
US20150214982A1 (en) * 2014-01-29 2015-07-30 Electronics And Telecommunications Research Institute Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same
US20160134304A1 (en) * 2013-05-02 2016-05-12 Sony Corporation Data processing device and data processing method
US9362952B2 (en) 2013-06-14 2016-06-07 Samsung Electronics Co., Ltd. Apparatuses and methods for encoding and decoding of parity check codes
US20160344496A1 (en) * 2015-05-19 2016-11-24 Samsung Electronics Co., Ltd. Transmitting apparatus and mapping method thereof
US9553609B2 (en) * 2015-01-20 2017-01-24 Electronics And Telecommunications Research Institute Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and quadrature phase shift keying, and bit interleaving method using same
US10361805B2 (en) * 2015-05-19 2019-07-23 Samsung Electronics Co., Ltd. Transmitting apparatus and mapping method thereof
US10374635B2 (en) * 2014-02-20 2019-08-06 Shanghai National Engineering Research Center Of Digital Television Co., Ltd. Interleaving and mapping method and deinterleaving and demapping method for LDPC codeword
US10432225B2 (en) 2013-06-12 2019-10-01 Saturn Licensing Llc Data processing device and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio
US10530389B2 (en) 2013-02-08 2020-01-07 Saturn Licensing Llc Data processing apparatus and data processing method
US10804934B2 (en) 2013-02-08 2020-10-13 Saturn Licensing Llc Data processing apparatus and data processing method
US10979073B2 (en) * 2013-10-07 2021-04-13 Electronics And Telecommunications Research Institute Low density parity check encoder having length of 64800 and code rate of 7/15, and low density parity check encoding method using the same
US10979074B2 (en) * 2014-08-14 2021-04-13 Electronics And Telecommunications Research Institute Low density parity check encoder having length of 16200 and code rate of 3/15, and low density parity check encoding method using the same
US11012091B2 (en) * 2017-03-13 2021-05-18 Sony Corporation Transmitting apparatus and transmission method, receiving apparatus and reception method, and program
CN113595559A (zh) * 2016-12-20 2021-11-02 三星电子株式会社 用于通信系统中的信道编码/解码的装置和方法
US11196448B2 (en) * 2015-03-02 2021-12-07 Samsung Electronics Co., Ltd. Transmitter and parity permutation method thereof
US20220045695A1 (en) * 2015-03-02 2022-02-10 Samsung Electronics Co., Ltd. Transmitter and parity permutation method thereof
US20220140843A1 (en) * 2014-02-13 2022-05-05 Electronics And Telecommunications Research Institute Modulator and modulation method using non-uniform 16-symbol signal constellation for low-density parity check codeword having 4/15 code rate

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5630283B2 (ja) * 2011-01-19 2014-11-26 ソニー株式会社 データ処理装置、及び、データ処理方法
JP5630282B2 (ja) * 2011-01-19 2014-11-26 ソニー株式会社 データ処理装置、及び、データ処理方法
JP5672489B2 (ja) * 2011-02-08 2015-02-18 ソニー株式会社 データ処理装置、及び、データ処理方法
KR102146803B1 (ko) * 2013-06-14 2020-08-21 삼성전자주식회사 패리티 검사 부호의 부호화 장치, 그의 부호화 방법, 복호화 장치 및 그의 복호화 방법
US20160204800A1 (en) * 2013-09-20 2016-07-14 Sony Corporation Data processing device and data processing method
KR20160060029A (ko) * 2013-09-20 2016-05-27 소니 주식회사 데이터 처리 장치 및 데이터 처리 방법
KR101929296B1 (ko) 2013-09-20 2018-12-17 소니 주식회사 데이터 처리 장치 및 데이터 처리 방법
CA2924783A1 (fr) * 2013-09-26 2015-04-02 Sony Corporation Dispositif et procede de traitement de donnees
CN105594130A (zh) * 2013-09-26 2016-05-18 索尼公司 数据处理装置和数据处理方法
JPWO2015045899A1 (ja) * 2013-09-26 2017-03-09 ソニー株式会社 データ処理装置、及びデータ処理方法
KR20160064092A (ko) * 2013-09-26 2016-06-07 소니 주식회사 데이터 처리 장치 및 데이터 처리 방법
EP3051706A4 (fr) * 2013-09-26 2017-06-14 Sony Corporation Dispositif de traitement des données et procédé de traitement des données
EP3051703A4 (fr) * 2013-09-26 2017-06-07 Sony Corporation Dispositif de traitement de données et procédé de traitement de données
US20160211868A1 (en) * 2013-09-26 2016-07-21 Sony Corporation Data processing device and data processing method
CN103780355B (zh) * 2014-02-20 2017-01-11 西华大学 一种适用于导频通信系统的ldpc码信息位替换方法
CN105099615B (zh) * 2014-05-22 2020-08-07 上海数字电视国家工程研究中心有限公司 Ldpc码字的交织映射方法及解交织解映射方法
CN108631913B (zh) * 2017-03-23 2020-10-27 华为技术有限公司 一种基于准循环低密度校验码的交织方法及相关设备
WO2018203725A1 (fr) * 2017-05-04 2018-11-08 Samsung Electronics Co., Ltd. Un procédé et appareil de codage/décodage de canal dans un système de communication ou de diffusion

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090210767A1 (en) * 2008-02-18 2009-08-20 Samsung Electronics Co., Ltd. Apparatus and method for encoding and decoding channel in a communication system using low-density parity-check codes
US20100325512A1 (en) * 2007-11-26 2010-12-23 Sony Corporation Data processing apparatus and data processing method
US8261152B2 (en) * 2007-09-10 2012-09-04 Samsung Electronics Co., Ltd. Apparatus and method for channel encoding/decoding in communication system using variable-length LDPC codes
US8402337B2 (en) * 2007-11-26 2013-03-19 Sony Corporation Data processing apparatus and data processing method as well as encoding apparatus and encoding method
US20130227378A1 (en) * 2010-12-07 2013-08-29 Sony Corporation Data processing device and data processing method
US20130254617A1 (en) * 2010-09-03 2013-09-26 Sony Corporation Data processing device and data processing method
US20130290816A1 (en) * 2011-01-19 2013-10-31 Sony Corporation Data-processing device and data-processing method
US20130305113A1 (en) * 2011-01-19 2013-11-14 Sony Corporation Data-processing device and data-processing method
US20140040707A1 (en) * 2011-04-28 2014-02-06 Sony Corporation Data processing device and data processing method
US20140047295A1 (en) * 2011-05-27 2014-02-13 Sony Corporation Data processing device and data processing method
US20140082452A1 (en) * 2011-06-15 2014-03-20 Sony Corporation Data processing device and data processing method

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4224777B2 (ja) 2003-05-13 2009-02-18 ソニー株式会社 復号方法および復号装置、並びにプログラム
TW201010295A (en) * 2007-11-26 2010-03-01 Sony Corp Data processing device and data processing method
TWI497920B (zh) 2007-11-26 2015-08-21 Sony Corp Data processing device and data processing method
TW200947880A (en) * 2007-11-26 2009-11-16 Sony Corp Data process device and data process method
JP2009224320A (ja) 2008-02-18 2009-10-01 Sumitomo Chemical Co Ltd ナトリウム二次電池
JP2009224820A (ja) * 2008-02-22 2009-10-01 Sony Corp 符号化装置、及び符号化方法
WO2009116204A1 (fr) * 2008-03-18 2009-09-24 ソニー株式会社 Dispositif de traitement de données et procédé de traitement de données
JP2012151656A (ja) * 2011-01-19 2012-08-09 Sony Corp データ処理装置、及び、データ処理方法
JP2012151655A (ja) * 2011-01-19 2012-08-09 Sony Corp データ処理装置、及び、データ処理方法

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8261152B2 (en) * 2007-09-10 2012-09-04 Samsung Electronics Co., Ltd. Apparatus and method for channel encoding/decoding in communication system using variable-length LDPC codes
US20100325512A1 (en) * 2007-11-26 2010-12-23 Sony Corporation Data processing apparatus and data processing method
US8402337B2 (en) * 2007-11-26 2013-03-19 Sony Corporation Data processing apparatus and data processing method as well as encoding apparatus and encoding method
US20090210767A1 (en) * 2008-02-18 2009-08-20 Samsung Electronics Co., Ltd. Apparatus and method for encoding and decoding channel in a communication system using low-density parity-check codes
US20130254617A1 (en) * 2010-09-03 2013-09-26 Sony Corporation Data processing device and data processing method
US20130227378A1 (en) * 2010-12-07 2013-08-29 Sony Corporation Data processing device and data processing method
US20130290816A1 (en) * 2011-01-19 2013-10-31 Sony Corporation Data-processing device and data-processing method
US20130305113A1 (en) * 2011-01-19 2013-11-14 Sony Corporation Data-processing device and data-processing method
US20140040707A1 (en) * 2011-04-28 2014-02-06 Sony Corporation Data processing device and data processing method
US20140047295A1 (en) * 2011-05-27 2014-02-13 Sony Corporation Data processing device and data processing method
US20140082452A1 (en) * 2011-06-15 2014-03-20 Sony Corporation Data processing device and data processing method

Cited By (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140040707A1 (en) * 2011-04-28 2014-02-06 Sony Corporation Data processing device and data processing method
US9077380B2 (en) * 2011-04-28 2015-07-07 Sony Corporation Data processing device and data processing method
US9385755B2 (en) 2011-05-18 2016-07-05 Panasonic Corporation Parallel bit interleaver
US11894861B2 (en) 2011-05-18 2024-02-06 Panasonic Holdings Corporation Parallel bit interleaver
US11496157B2 (en) 2011-05-18 2022-11-08 Panasonic Holdings Corporation Parallel bit interleaver
US10355715B2 (en) 2011-05-18 2019-07-16 Panasonic Corporation Parallel bit interleaver
US20150128012A1 (en) * 2011-05-18 2015-05-07 Mihail Petrov Parallel bit interleaver
US11070236B2 (en) 2011-05-18 2021-07-20 Panasonic Corporation Parallel bit interleaver
US9026884B2 (en) 2011-05-27 2015-05-05 Sony Corporation Data processing device and data processing method
US9135108B2 (en) * 2011-06-15 2015-09-15 Sony Corporation Data processing device and data processing method
US20140082452A1 (en) * 2011-06-15 2014-03-20 Sony Corporation Data processing device and data processing method
US9213593B2 (en) * 2013-01-16 2015-12-15 Maxlinear, Inc. Efficient memory architecture for low density parity check decoding
US20140201593A1 (en) * 2013-01-16 2014-07-17 Maxlinear, Inc. Efficient Memory Architecture for Low Density Parity Check Decoding
US11218170B2 (en) 2013-02-08 2022-01-04 Saturn Licensing Llc Data processing apparatus and data processing method
US10804934B2 (en) 2013-02-08 2020-10-13 Saturn Licensing Llc Data processing apparatus and data processing method
US11177832B2 (en) 2013-02-08 2021-11-16 Saturn Licensing Llc Data processing apparatus and data processing method
US10530389B2 (en) 2013-02-08 2020-01-07 Saturn Licensing Llc Data processing apparatus and data processing method
US20160134304A1 (en) * 2013-05-02 2016-05-12 Sony Corporation Data processing device and data processing method
US9838037B2 (en) * 2013-05-02 2017-12-05 Sony Corporation Data processing device and data processing method
US10432225B2 (en) 2013-06-12 2019-10-01 Saturn Licensing Llc Data processing device and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio
US11082065B2 (en) 2013-06-12 2021-08-03 Saturn Licensing Llc Data processing apparatus and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio
US9362952B2 (en) 2013-06-14 2016-06-07 Samsung Electronics Co., Ltd. Apparatuses and methods for encoding and decoding of parity check codes
US20150082118A1 (en) * 2013-09-18 2015-03-19 Samsung Electronics Co., Ltd. Transmitting apparatus and puncturing method thereof
US20220360282A1 (en) * 2013-10-07 2022-11-10 Electronics And Telecommunications Research Institute Low density parity check encoder having length of 64800 and code rate of 7/15, and low density parity check encoding method using the same
US11916572B2 (en) * 2013-10-07 2024-02-27 Electronics And Telecommunications Research Institute Low density parity check encoder having length of 64800 and code rate of 7/15, and low density parity check encoding method using the same
US10979073B2 (en) * 2013-10-07 2021-04-13 Electronics And Telecommunications Research Institute Low density parity check encoder having length of 64800 and code rate of 7/15, and low density parity check encoding method using the same
US11424763B2 (en) * 2013-10-07 2022-08-23 Electronics And Telecommunications Research Institute Low density parity check encoder having length of 64800 and code rate of 7/15, and low density parity check encoding method using the same
US10419031B2 (en) * 2014-01-29 2019-09-17 Electronics And Telecommunications Research Institute Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same
US20170117923A1 (en) * 2014-01-29 2017-04-27 Electronics And Telecommunications Research Institute Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same
US9577678B2 (en) * 2014-01-29 2017-02-21 Electronics And Telecommunications Research Institute Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same
US20150214982A1 (en) * 2014-01-29 2015-07-30 Electronics And Telecommunications Research Institute Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same
US11764808B2 (en) * 2014-02-13 2023-09-19 Electronics And Telecommunications Research Institute Modulator and modulation method using non-uniform 16-symbol signal constellation for low-density parity check codeword having 4/15 code rate
US20230378978A1 (en) * 2014-02-13 2023-11-23 Electronics And Telecommunications Research Institute Modulator and modulation method using non-uniform 16-symbol signal constellation for low-density parity check codeword having 4/15 code rate
US20220140843A1 (en) * 2014-02-13 2022-05-05 Electronics And Telecommunications Research Institute Modulator and modulation method using non-uniform 16-symbol signal constellation for low-density parity check codeword having 4/15 code rate
US10374635B2 (en) * 2014-02-20 2019-08-06 Shanghai National Engineering Research Center Of Digital Television Co., Ltd. Interleaving and mapping method and deinterleaving and demapping method for LDPC codeword
US20220302927A1 (en) * 2014-08-14 2022-09-22 Electronics And Telecommunications Research Institute Low density parity check encoder having length of 16200 and code rate of 3/15, and low density parity check encoding method using the same
US10979074B2 (en) * 2014-08-14 2021-04-13 Electronics And Telecommunications Research Institute Low density parity check encoder having length of 16200 and code rate of 3/15, and low density parity check encoding method using the same
US11387846B2 (en) * 2014-08-14 2022-07-12 Electronics And Telecommunications Research Institute Low density parity check encoder having length of 16200 and code rate of 3/15, and low density parity check encoding method using the same
US11711096B2 (en) * 2014-08-14 2023-07-25 Electronics And Telecommunications Research Institute Low density parity check encoder having length of 16200 and code rate of 3/15, and low density parity check encoding method using the same
US20230318625A1 (en) * 2014-08-14 2023-10-05 Electronics And Telecommunications Research Institute Low density parity check encoder having length of 16200 and code rate of 3/15, and low density parity check encoding method using the same
US9553609B2 (en) * 2015-01-20 2017-01-24 Electronics And Telecommunications Research Institute Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and quadrature phase shift keying, and bit interleaving method using same
US10419030B2 (en) * 2015-01-20 2019-09-17 Electronics And Telecommunications Research Institute Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and quadrature phase shift keying, and bit interleaving method using same
US20170093431A1 (en) * 2015-01-20 2017-03-30 Electronics And Telecommunications Research Institute Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and quadrature phase shift keying, and bit interleaving method using same
US11196448B2 (en) * 2015-03-02 2021-12-07 Samsung Electronics Co., Ltd. Transmitter and parity permutation method thereof
US20220045695A1 (en) * 2015-03-02 2022-02-10 Samsung Electronics Co., Ltd. Transmitter and parity permutation method thereof
US11777523B2 (en) * 2015-03-02 2023-10-03 Samsung Electronics Co., Ltd. Transmitter and parity permutation method thereof
US11095385B2 (en) 2015-05-19 2021-08-17 Samsung Electronics Co., Ltd. Transmitting apparatus and mapping method thereof
US10491320B2 (en) 2015-05-19 2019-11-26 Samsung Electronics Co., Ltd. Transmitting apparatus and mapping method thereof
US10673554B2 (en) 2015-05-19 2020-06-02 Samsung Electronics Co., Ltd. Transmitting apparatus and mapping method thereof
US10361805B2 (en) * 2015-05-19 2019-07-23 Samsung Electronics Co., Ltd. Transmitting apparatus and mapping method thereof
US10277350B2 (en) 2015-05-19 2019-04-30 Samsung Electronics Co., Ltd. Transmitting apparatus and mapping method thereof
US11811497B2 (en) 2015-05-19 2023-11-07 Samsung Electronics Co., Ltd. Transmitting apparatus and mapping method thereof
US9762346B2 (en) * 2015-05-19 2017-09-12 Samsung Electronics Co., Ltd. Transmitting apparatus and mapping method thereof
US20160344496A1 (en) * 2015-05-19 2016-11-24 Samsung Electronics Co., Ltd. Transmitting apparatus and mapping method thereof
CN113595559A (zh) * 2016-12-20 2021-11-02 三星电子株式会社 用于通信系统中的信道编码/解码的装置和方法
US11012091B2 (en) * 2017-03-13 2021-05-18 Sony Corporation Transmitting apparatus and transmission method, receiving apparatus and reception method, and program

Also Published As

Publication number Publication date
CN103339862A (zh) 2013-10-02
US10361724B2 (en) 2019-07-23
EP2660983A4 (fr) 2016-03-09
US20180254783A1 (en) 2018-09-06
EP3352377B1 (fr) 2023-02-01
JP5630278B2 (ja) 2014-11-26
WO2012090882A1 (fr) 2012-07-05
EP2660983A1 (fr) 2013-11-06
JP2012151520A (ja) 2012-08-09
EP3352377A1 (fr) 2018-07-25
EP2660983B1 (fr) 2018-01-24
CN103339862B (zh) 2017-08-22

Similar Documents

Publication Publication Date Title
US10361724B2 (en) Data processing device and data processing method for improving resistance to error of data
US11218170B2 (en) Data processing apparatus and data processing method
US11177832B2 (en) Data processing apparatus and data processing method
US9106263B2 (en) Data processing device and data processing method
US20180294822A1 (en) Data processing apparatus and data processing method
US20160233889A1 (en) Data processing device and data processing method
US20160211868A1 (en) Data processing device and data processing method
US20180287638A1 (en) Data processing device and data processing method
US20130311850A1 (en) Data processing device and data processing method
US20160233890A1 (en) Data processing device and data processing method
US10972128B2 (en) Data processing device and data processing method
US20160261288A1 (en) Data processing device and data processing method
US11012098B2 (en) Data processing device and data processing method
US10951241B2 (en) Data processing device and data processing method
US20160315636A1 (en) Data processing device and data processing method
US10659080B2 (en) Data processing device and data processing method
US20150358032A1 (en) Data processing device and data processing method
US20160197625A1 (en) Data processing device and data processing method
US20150349802A1 (en) Data processing device and data processing method
US20160211866A1 (en) Data processing device and data processing method
US20190379401A1 (en) Transmission method and reception device
US20190363735A1 (en) Transmission method and reception device
US20160204801A1 (en) Data processing device and data processing method
US20160126978A1 (en) Data processing device and data processing method

Legal Events

Date Code Title Description
AS Assignment

Owner name: SONY CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YAMAMOTO, MAKIKO;SHINOHARA, YUJI;REEL/FRAME:030651/0312

Effective date: 20130605

AS Assignment

Owner name: SATURN LICENSING LLC, NEW YORK

Free format text: ASSIGNMENT OF THE ENTIRE INTEREST SUBJECT TO AN AGREEMENT RECITED IN THE DOCUMENT;ASSIGNOR:SONY CORPORATION;REEL/FRAME:041391/0037

Effective date: 20150911

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION