US20130285135A1 - Semiconductor Device with Semiconductor Fins and Floating Gate - Google Patents
Semiconductor Device with Semiconductor Fins and Floating Gate Download PDFInfo
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- US20130285135A1 US20130285135A1 US13/460,336 US201213460336A US2013285135A1 US 20130285135 A1 US20130285135 A1 US 20130285135A1 US 201213460336 A US201213460336 A US 201213460336A US 2013285135 A1 US2013285135 A1 US 2013285135A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 130
- 229910052751 metal Inorganic materials 0.000 claims description 5
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- 238000005240 physical vapour deposition Methods 0.000 description 2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/04—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using optical elements ; using other beam accessed elements, e.g. electron or ion beam
- G11C13/048—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using optical elements ; using other beam accessed elements, e.g. electron or ion beam using other optical storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Definitions
- a floating gate field-effect transistor is typically a planar transistor having a floating gate situated over a channel and a control gate situated over the floating gate.
- the floating gate is electrically insulated from the control gate and the channel, and charge may be stored in the floating gate.
- Fowler-Nordheim tunneling and hot-carrier injection are two approaches that can be utilized to modify the amount of charge stored in the floating gate. The charge stored in the floating gate can remain even when there is no power being applied to the floating gate FET.
- floating gate FETs have been utilized in various applications. As one example, floating gate FETs have been utilized as digital storage elements in erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory. As other examples, floating gate FETs have been utilized as neuronal computational elements in neural networks, analog storage elements, electronic potentiometers, and single-transistor digital-to-analog converters (DACs).
- EPROM erasable programmable read-only memory
- EEPROM electrically erasable programmable read-only memory
- flash memory As other examples, floating gate FETs have been utilized as neuronal computational elements in neural networks, analog storage elements, electronic potentiometers, and single-transistor digital-to-analog converters (DACs).
- DACs digital-to-analog converters
- the present disclosure is directed to semiconductor device with semiconductor fins and floating gate, substantially as shown in and/or described in connection with at least one of the figures, and as set forth more completely in the claims.
- FIG. 1A illustrates a perspective view of an exemplary semiconductor device.
- FIG. 1B illustrates a top view of an exemplary semiconductor device.
- FIG. 1C illustrates a schematic diagram of an exemplary semiconductor device.
- FIG. 2 shows a process flow diagram illustrating an exemplary process for fabricating a semiconductor device.
- FIG. 3A illustrates a cross-sectional view of a portion of an exemplary wafer during processing.
- FIG. 3B illustrates a cross-sectional view of a portion of an exemplary wafer during processing.
- FIG. 3C illustrates a cross-sectional view of a portion of an exemplary wafer during processing.
- FIG. 1A illustrates a perspective view of an exemplary semiconductor device 100 .
- FIG. 1B illustrates a top view of the exemplary semiconductor device 100 .
- FIG. 1C illustrates a schematic diagram 140 of the exemplary semiconductor device 100 .
- the semiconductor device 100 includes a substrate 102 , a dielectric layer 104 , semiconductor fins 106 a and 106 b , a floating gate 120 , electrodes 122 a and 122 b , and dielectric regions 124 a , 124 b , 124 c , and 124 d.
- the substrate 102 includes semiconductor material, such as single-crystal semiconductor material.
- the substrate 102 is a silicon substrate and more particularly is monocrystalline silicon.
- the substrate 102 is a P type substrate. It is noted that in other implementations, the substrate 102 is an N type substrate or is undoped. Also, in other implementations, the substrate 102 is a semiconductor on insulator substrate, such as a silicon on insulator substrate (SOI).
- SOI silicon on insulator substrate
- the semiconductor fins 106 a and 106 b include semiconductor material, and in the present implementation are silicon.
- the semiconductor fins 106 a and 106 b are formed in and on the substrate 102 .
- the semiconductor fin 106 a is situated between the floating gate 120 and the electrode 122 a .
- the semiconductor fin 106 b is situated between the floating gate 120 and the electrode 122 b .
- the semiconductor fin 106 a includes a source 108 a , a drain 110 a , and a channel 112 a that is situated between the source 108 a and the drain 110 a .
- the semiconductor fin 106 b includes a source 108 b , a drain 110 b , and a channel 112 b that is situated between the source 108 b and the drain 110 b .
- the semiconductor fin 106 a is situated between the dielectric region 124 a and the dielectric region 124 b . More particularly, the channel 112 a of the semiconductor fin 106 a is situated between the dielectric region 124 a and the dielectric region 124 b .
- the semiconductor fin 106 b is situated between the dielectric region 124 c and the dielectric region 124 d . More particularly, the channel 112 b of the semiconductor fin 106 b is situated between the dielectric region 124 c and the dielectric region 124 d.
- the sources 108 a and 108 b , the drains 110 a and 110 b , and the channels 112 a and 112 b are doped regions of the semiconductor fins 106 a and 106 b .
- FIG. 1A shows an implementation where the sources 108 a and 108 b and the drains 110 a and 110 b are N type and the channels 112 a and 112 b are P type.
- the sources 108 a and 108 b , the drains 110 a and 110 b , and the channels 112 a and 112 b can be doped differently than what is shown in FIG. 1A and furthermore, can be doped differently with respect to one another.
- the sources 108 a and 108 b and the drains 110 a and 110 b are P type and the channels 112 a and 112 b are N type.
- the channels 112 a and 112 b have a similar doping profile as the substrate 102 , however, the channels 112 a and 112 b can have a different doping profile than the substrate 102 and/or one another.
- the dielectric layer 104 is situated over the substrate 102 .
- the dielectric layer 104 includes one or more dielectric materials, such as silicon dioxide.
- the dielectric layer 104 is a shallow trench isolation (STI) layer and underlies the floating gate 120 and the electrodes 122 a and 122 b.
- STI shallow trench isolation
- the electrode 122 a is situated adjacent to, but is electrically insulated from the channel 112 a of the semiconductor fin 106 a .
- the electrode 122 b is situated adjacent to, but electrically insulated from the channel 112 b of the semiconductor fin 106 b .
- the floating gate 120 is situated between the semiconductor fin 106 a and the semiconductor fin 106 b .
- the dielectric region 124 b is situated between the floating gate 120 and the semiconductor fin 106 a .
- the dielectric region 124 c is situated between the floating gate 120 and the semiconductor fin 106 b .
- the floating gate 120 is electrically insulated from the channel 112 a of the semiconductor fin 106 a and the channel 112 b of the semiconductor fin 106 b.
- the electrodes 122 a and 122 b and the floating gate 120 include conductive material.
- Conductive material suitable for the electrodes 122 a and 122 b and the floating gate 120 include gate material for field-effect transistors (FETs), such as finFETs.
- FETs field-effect transistors
- the electrodes 122 a and 122 b and the floating gate 120 each include a metal.
- suitable metals for the electrodes 122 a and 122 b and the floating gate 120 include, but are not limited to, tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), molybdenum (Mo), ruthenium (Ru), and tantalum carbide nitride (TaCN).
- the electrodes 122 a and 122 b and the floating gate 120 include the same conductive material as one another. Also, in some implementations, at least one of the electrodes 122 a and 122 b and the floating gate 120 includes different conductive material than at least one other of the electrodes 122 a and 122 b and the floating gate 120 .
- the dielectric region 124 a is situated between the electrode 122 a and the channel 112 a of semiconductor fin 106 a .
- the dielectric region 124 b is situated between the channel 112 a of semiconductor fin 106 a and the floating gate 120 .
- the dielectric region 124 c is situated between the floating gate 120 and the channel 112 b of the semiconductor fin 106 b .
- the dielectric region 124 d is situated between the channel 112 b of the semiconductor fin 106 b and the electrode 122 b.
- the dielectric regions 124 a , 124 b , 124 c , and 124 d include dielectric material.
- Dielectric material suitable for the dielectric regions 124 a , 124 b , 124 e , and 124 d include gate dielectric material for FETs, such as finFETs.
- the dielectric regions 124 a , 124 b , 124 c , and 124 d each include high-k dielectric material.
- high-k dielectric material for the dielectric regions 124 a , 124 b , 124 c , and 124 d include, as specific examples, hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), chromium oxide (CrO 2 ), and the like
- the dielectric regions 124 a , 124 b , 124 c , and 124 d include the same dielectric material as one another. Also, in some implementations, at least one of the dielectric regions 124 a , 124 b , 124 c , and 124 d includes different dielectric material than at least one other of the dielectric regions 124 a , 124 b , 124 c , and 124 d . In the present implementation, the dielectric regions 124 a , 124 b , 124 c , and 124 d are separate dielectric layers.
- the dielectric regions 124 a , 124 b , 124 c , and 124 d can be part of a common dielectric layer.
- the dielectric regions 124 a and 124 b can be part of a common dielectric layer, which extends over the semiconductor fin 106 a .
- the dielectric regions 124 a and 124 b can be part of a common dielectric layer, which extends over the semiconductor fin 106 a.
- the semiconductor device 100 can be configured for many applications including, as one example, a digital storage element in erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory.
- EPROM erasable programmable read-only memory
- EEPROM electrically erasable programmable read-only memory
- flash memory As other examples, the semiconductor device 100 can be configured as a neuronal computational element in neural networks, an analog storage element, an electronic potentiometer, and a single-transistor digital-to-analog converter (DAC).
- the semiconductor device 100 can be utilized with other semiconductor devices, which may be formed in the semiconductor fins 106 a and/or 106 b . In certain applications, the semiconductor fins 106 a and/or 106 b are doped differently than what is shown in FIGS. 1A and 1B .
- the schematic diagram 140 in FIG. 1C corresponds to the semiconductor device 100 of the implementation shown in FIGS. 1A and 1B .
- the schematic diagram 140 includes a fin terminal A 1 corresponding to the source 108 a of the semiconductor fin 106 a , a fin terminal B 1 corresponding to the drain 110 a of the semiconductor fin 106 a , and an electrode terminal C 1 corresponding to the electrode 122 a .
- the schematic diagram 140 also includes a fin terminal A 2 corresponding to the source 108 b of the semiconductor fin 106 b , a fin terminal B 2 corresponding to the drain 110 b of the semiconductor fin 106 b , and an electrode terminal C 2 corresponding to the electrode 122 b.
- the semiconductor fin 106 a and/or the semiconductor fin 106 b can be configured as a control gate. Any of the fin terminals A 1 , A 2 , B 1 , and B 2 can correspond to a control gate situated in the semiconductor fin 106 a or the semiconductor fin 106 b . Where the semiconductor fin 106 a and/or the semiconductor fin 106 b are doped differently, only one or more of the fin terminals A 1 , A 2 , B 1 , and B 2 may correspond to a control gate.
- the semiconductor device 100 can be a programmable non-volatile memory device.
- the control gate can be configured to control the channel 112 a or 112 b based on a programmed state of the floating gate 120 . The programmed state can be achieved, for example, utilizing Fowler-Nordheim tunneling or hot-carrier injection.
- the fin terminal A 1 corresponds to the control gate
- the fin terminal A 2 corresponds to a source
- the fin terminal B 2 corresponds to a drain of a programmable non-volatile memory device.
- At least one of the electrode terminals C 1 and C 2 can be coupled to ground.
- the fin terminal B 1 can be shorted to the fin terminal A 1 , for example, by an electrode or by other means, such as through the channel 112 a .
- the electrode terminal C 1 is configured to invert the channel 112 a to short the fin terminal A 1 and the fin terminal B 1 .
- the channel 112 a is doped to short the fin terminal A 1 and the fin terminal B 1 .
- FIG. 2 shows a process flow diagram illustrating a process 200 for fabricating a semiconductor device, such as the semiconductor device 100 . It is noted that the semiconductor device 100 , as well as other semiconductor devices in accordance with the present disclosure, can be fabricated utilizing processes other than the process 200 . Also, while applicable for fabricating different semiconductor devices, for illustrative purposes, the process 200 is described with respect to the semiconductor device 100 presented above with respect to FIGS. 1A , 1 B, and 1 C.
- the implementation illustrated by the process 200 can be performed on a processed wafer.
- the processed wafer can correspond to the semiconductor device 100 prior to formation of the electrodes 122 a and 122 b and the floating gate 120 .
- the processed wafer may include any of the other constituents of the semiconductor device 100 , or at least some of those constituents may be formed later.
- the process 200 includes forming a conductive layer (e.g., 328 ) over first and second semiconductor fins (e.g., 306 a and 306 b ) ( 270 in FIG. 2 ).
- a conductive layer e.g., 328
- first and second semiconductor fins e.g., 306 a and 306 b
- FIG. 3A illustrates a cross-sectional view of a portion of an exemplary wafer during processing. More particularly, FIG. 3A illustrates a cross-sectional view of a portion of a wafer 370 during processing.
- the cross-sectional view illustrated in FIG. 3A can correspond to a cross section 3 - 3 of the semiconductor device 100 in FIGS. 1A and 1B during processing.
- the wafer 370 includes a substrate 302 , a dielectric layer 304 , semiconductor fins 306 a and 306 b , channels 312 a and 312 b , dielectric regions 324 a , 324 b , 324 c , and 324 d , and a conductive layer 328 .
- the substrate 302 , the dielectric layer 304 , the semiconductor fins 306 a and 306 b , the channels 312 a and 312 b , and the dielectric regions 324 a , 324 b , 324 c , and 324 d correspond to the substrate 102 , the dielectric layer 104 , the semiconductor fins 106 a and 106 b , the channels 112 a and 112 b , and the dielectric regions 124 a , 124 b , 124 c , and 124 d in the semiconductor device 100 .
- the conductive layer 328 is formed over the semiconductor fins 306 a and 306 b , and may also be formed over the substrate 302 , the dielectric layer 304 , the channels 312 a and 312 b , and the dielectric regions 324 a , 324 b , 324 c , and 324 d .
- the conductive layer 328 can include conductive material, such as those described above with respect to the electrodes 122 a and 122 b , and the floating gate 120 .
- the conductive layer 328 can be formed over the semiconductor fins 306 a and 306 b by depositing one or more layers of conductive material, such as a metal, over the semiconductor fins 306 a and 306 b .
- the deposition can utilize physical vapor deposition (PVD), chemical vapor deposition (CVD), or another deposition technique.
- PVD physical vapor deposition
- CVD chemical vapor deposition
- the deposited one or more layers of conductive material can then be planarized utilizing chemical mechanical planarization (CMP) or another planarization technique, resulting in the wafer 370 shown in FIG. 3A .
- CMP chemical mechanical planarization
- the process 200 includes forming a mask (e.g., 334 ) over the conductive layer (e.g., 328 ) ( 272 in FIG. 2 ).
- a mask e.g., 334
- the conductive layer e.g., 328
- FIG. 3B illustrates a cross-sectional view of a portion of an exemplary wafer during processing. More particularly, FIG. 3B illustrates a cross-sectional view of a portion of a wafer 372 during processing.
- the cross-sectional view illustrated in FIG. 3B can correspond to the cross section 3 - 3 of the semiconductor device 100 in FIGS. 1A and 1B during processing.
- the wafer 372 includes a mask 334 formed over the conductive layer 328 .
- the mask 334 exposes a region 336 of the conductive layer 328 that overlies the semiconductor fins 306 a and 306 b .
- the mask 334 can include photoresist.
- the mask 334 can be formed over the conductive layer 328 by applying photoresist to the wafer 370 of FIG. 3A over the conductive layer 328 .
- the photoresist can be patterned to expose the region 336 of the conductive layer 328 , resulting in the wafer 372 shown in FIG. 3B .
- the process 200 includes etching the conductive layer (e.g., 328 ) using the mask (e.g., 334 ) to form a floating gate (e.g., 320 ) situated between the first and second semiconductor fins (e.g., 306 a and 306 b ) ( 274 in FIG. 2 ).
- FIG. 3C illustrates a cross-sectional view of a portion of an exemplary wafer during processing. More particularly, FIG. 3C illustrates a cross-sectional view of a portion of a wafer 374 during processing.
- the cross-sectional view illustrated in FIG. 3C can correspond to the cross section 3 - 3 of the semiconductor device 100 in FIGS. 1A and 1B during processing.
- the wafer 374 includes a floating gate 320 , an electrode 322 a , and an electrode 322 b .
- the floating gate 320 , the electrode 322 a , and the electrode 322 b correspond to the floating gate 120 , the electrode 122 a , and the electrode 122 b in the semiconductor device 100 .
- the floating gate 320 can be formed by etching the conductive layer 328 of the wafer 372 using the mask 334 of the wafer to form the floating gate 320 situated between the semiconductor fins 306 a and 306 b . Subsequently, the mask 334 can be removed, resulting in the wafer 374 shown in FIG. 3C .
- the etching of the conductive layer 328 can also form the electrodes 322 a and 322 b .
- the etching of the conductive layer 328 can also remove portions of dielectric material that forms the dielectric regions 324 a , 324 b , 324 c , and 324 d and can expose top portions of the semiconductor fins 306 a and 306 b .
- dielectric material that forms the dielectric regions 324 a , 324 b , 324 c , and 324 d may be etched separately from the conductive layer 328 or may not be etched.
- Additional processing can be performed on the wafer 374 to result in the semiconductor device 100 .
- This additional processing may include formation of contacts and silicide for the contacts.
- the process 200 provides for fabrication of semiconductor devices, such as the semiconductor device 100 , which can be a programmable non-volatile memory device.
- the process 200 can be integrated into processes for fabrication of one or more fin FETs. In some implementations, this intergration only requires an addition of the mask 334 for etching the conductive layer 328 . However, the mask 334 may also be utilized for fabricating finFETs or other components.
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Abstract
Description
- A floating gate field-effect transistor (FET) is typically a planar transistor having a floating gate situated over a channel and a control gate situated over the floating gate. The floating gate is electrically insulated from the control gate and the channel, and charge may be stored in the floating gate. Fowler-Nordheim tunneling and hot-carrier injection are two approaches that can be utilized to modify the amount of charge stored in the floating gate. The charge stored in the floating gate can remain even when there is no power being applied to the floating gate FET.
- Floating gate FETs have been utilized in various applications. As one example, floating gate FETs have been utilized as digital storage elements in erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory. As other examples, floating gate FETs have been utilized as neuronal computational elements in neural networks, analog storage elements, electronic potentiometers, and single-transistor digital-to-analog converters (DACs).
- The present disclosure is directed to semiconductor device with semiconductor fins and floating gate, substantially as shown in and/or described in connection with at least one of the figures, and as set forth more completely in the claims.
-
FIG. 1A illustrates a perspective view of an exemplary semiconductor device. -
FIG. 1B illustrates a top view of an exemplary semiconductor device. -
FIG. 1C illustrates a schematic diagram of an exemplary semiconductor device. -
FIG. 2 shows a process flow diagram illustrating an exemplary process for fabricating a semiconductor device. -
FIG. 3A illustrates a cross-sectional view of a portion of an exemplary wafer during processing. -
FIG. 3B illustrates a cross-sectional view of a portion of an exemplary wafer during processing. -
FIG. 3C illustrates a cross-sectional view of a portion of an exemplary wafer during processing. - The following description contains specific information pertaining to implementations in the present disclosure. The drawings in the present application and their accompanying detailed description are directed to merely exemplary implementations. Unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals. Moreover, the drawings and illustrations in the present application are generally not to scale, and are not intended to correspond to actual relative dimensions.
-
FIG. 1A illustrates a perspective view of anexemplary semiconductor device 100.FIG. 1B illustrates a top view of theexemplary semiconductor device 100.FIG. 1C illustrates a schematic diagram 140 of theexemplary semiconductor device 100. Thesemiconductor device 100 includes asubstrate 102, adielectric layer 104,semiconductor fins floating gate 120,electrodes dielectric regions - In the
semiconductor device 100, thesubstrate 102 includes semiconductor material, such as single-crystal semiconductor material. In the present implementation, thesubstrate 102 is a silicon substrate and more particularly is monocrystalline silicon. In the implementation shown, thesubstrate 102 is a P type substrate. It is noted that in other implementations, thesubstrate 102 is an N type substrate or is undoped. Also, in other implementations, thesubstrate 102 is a semiconductor on insulator substrate, such as a silicon on insulator substrate (SOI). - The semiconductor fins 106 a and 106 b include semiconductor material, and in the present implementation are silicon. The
semiconductor fins substrate 102. Thesemiconductor fin 106 a is situated between thefloating gate 120 and theelectrode 122 a. Thesemiconductor fin 106 b is situated between thefloating gate 120 and theelectrode 122 b. Thesemiconductor fin 106 a includes asource 108 a, adrain 110 a, and achannel 112 a that is situated between thesource 108 a and thedrain 110 a. Thesemiconductor fin 106 b includes asource 108 b, adrain 110 b, and achannel 112 b that is situated between thesource 108 b and thedrain 110 b. Thesemiconductor fin 106 a is situated between thedielectric region 124 a and thedielectric region 124 b. More particularly, thechannel 112 a of thesemiconductor fin 106 a is situated between thedielectric region 124 a and thedielectric region 124 b. Thesemiconductor fin 106 b is situated between thedielectric region 124 c and thedielectric region 124 d. More particularly, thechannel 112 b of thesemiconductor fin 106 b is situated between thedielectric region 124 c and thedielectric region 124 d. - The
sources drains channels semiconductor fins FIG. 1A shows an implementation where thesources drains channels sources drains channels FIG. 1A and furthermore, can be doped differently with respect to one another. In some implementations, for example, thesources drains channels channels substrate 102, however, thechannels substrate 102 and/or one another. - Also in the implementation shown, the
dielectric layer 104 is situated over thesubstrate 102. Thedielectric layer 104 includes one or more dielectric materials, such as silicon dioxide. In the present implementation, thedielectric layer 104 is a shallow trench isolation (STI) layer and underlies thefloating gate 120 and theelectrodes - The
electrode 122 a is situated adjacent to, but is electrically insulated from thechannel 112 a of thesemiconductor fin 106 a. Theelectrode 122 b is situated adjacent to, but electrically insulated from thechannel 112 b of thesemiconductor fin 106 b. Thefloating gate 120 is situated between thesemiconductor fin 106 a and thesemiconductor fin 106 b. Also, thedielectric region 124 b is situated between thefloating gate 120 and thesemiconductor fin 106 a. Thedielectric region 124 c is situated between the floatinggate 120 and thesemiconductor fin 106 b. Thus, the floatinggate 120 is electrically insulated from thechannel 112 a of thesemiconductor fin 106 a and thechannel 112 b of thesemiconductor fin 106 b. - The
electrodes gate 120 include conductive material. Conductive material suitable for theelectrodes gate 120 include gate material for field-effect transistors (FETs), such as finFETs. In the present implementation, theelectrodes gate 120 each include a metal. Specific examples of suitable metals for theelectrodes gate 120 include, but are not limited to, tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), molybdenum (Mo), ruthenium (Ru), and tantalum carbide nitride (TaCN). In some implementations, theelectrodes gate 120 include the same conductive material as one another. Also, in some implementations, at least one of theelectrodes gate 120 includes different conductive material than at least one other of theelectrodes gate 120. - The
dielectric region 124 a is situated between theelectrode 122 a and thechannel 112 a ofsemiconductor fin 106 a. Thedielectric region 124 b is situated between thechannel 112 a ofsemiconductor fin 106 a and the floatinggate 120. Thedielectric region 124 c is situated between the floatinggate 120 and thechannel 112 b of thesemiconductor fin 106 b. Thedielectric region 124 d is situated between thechannel 112 b of thesemiconductor fin 106 b and theelectrode 122 b. - In the
semiconductor device 100, thedielectric regions dielectric regions dielectric regions dielectric regions - In some implementations, the
dielectric regions dielectric regions dielectric regions dielectric regions dielectric regions dielectric regions semiconductor fin 106 a. Similarly, thedielectric regions semiconductor fin 106 a. - The
semiconductor device 100 can be configured for many applications including, as one example, a digital storage element in erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory. As other examples, thesemiconductor device 100 can be configured as a neuronal computational element in neural networks, an analog storage element, an electronic potentiometer, and a single-transistor digital-to-analog converter (DAC). Furthermore, thesemiconductor device 100 can be utilized with other semiconductor devices, which may be formed in thesemiconductor fins 106 a and/or 106 b. In certain applications, thesemiconductor fins 106 a and/or 106 b are doped differently than what is shown inFIGS. 1A and 1B . - The schematic diagram 140 in
FIG. 1C corresponds to thesemiconductor device 100 of the implementation shown inFIGS. 1A and 1B . The schematic diagram 140 includes a fin terminal A1 corresponding to thesource 108 a of thesemiconductor fin 106 a, a fin terminal B1 corresponding to thedrain 110 a of thesemiconductor fin 106 a, and an electrode terminal C1 corresponding to theelectrode 122 a. The schematic diagram 140 also includes a fin terminal A2 corresponding to thesource 108 b of thesemiconductor fin 106 b, a fin terminal B2 corresponding to thedrain 110 b of thesemiconductor fin 106 b, and an electrode terminal C2 corresponding to theelectrode 122 b. - The
semiconductor fin 106 a and/or thesemiconductor fin 106 b can be configured as a control gate. Any of the fin terminals A1, A2, B 1, and B2 can correspond to a control gate situated in thesemiconductor fin 106 a or thesemiconductor fin 106 b. Where thesemiconductor fin 106 a and/or thesemiconductor fin 106 b are doped differently, only one or more of the fin terminals A1, A2, B1, and B2 may correspond to a control gate. Thesemiconductor device 100 can be a programmable non-volatile memory device. The control gate can be configured to control thechannel gate 120. The programmed state can be achieved, for example, utilizing Fowler-Nordheim tunneling or hot-carrier injection. - In one configuration, the fin terminal A1 corresponds to the control gate, the fin terminal A2 corresponds to a source, and the fin terminal B2 corresponds to a drain of a programmable non-volatile memory device. At least one of the electrode terminals C1 and C2 can be coupled to ground. The fin terminal B1 can be shorted to the fin terminal A1, for example, by an electrode or by other means, such as through the
channel 112 a. In some implementations, the electrode terminal C1 is configured to invert thechannel 112 a to short the fin terminal A1 and the fin terminal B1. In some implementations, thechannel 112 a is doped to short the fin terminal A1 and the fin terminal B1. -
FIG. 2 shows a process flow diagram illustrating aprocess 200 for fabricating a semiconductor device, such as thesemiconductor device 100. It is noted that thesemiconductor device 100, as well as other semiconductor devices in accordance with the present disclosure, can be fabricated utilizing processes other than theprocess 200. Also, while applicable for fabricating different semiconductor devices, for illustrative purposes, theprocess 200 is described with respect to thesemiconductor device 100 presented above with respect toFIGS. 1A , 1B, and 1C. - The implementation illustrated by the
process 200 can be performed on a processed wafer. The processed wafer can correspond to thesemiconductor device 100 prior to formation of theelectrodes gate 120. However, the processed wafer may include any of the other constituents of thesemiconductor device 100, or at least some of those constituents may be formed later. - Referring now to
FIG. 2 andFIG. 3A , theprocess 200 includes forming a conductive layer (e.g., 328) over first and second semiconductor fins (e.g., 306 a and 306 b) (270 inFIG. 2 ). -
FIG. 3A illustrates a cross-sectional view of a portion of an exemplary wafer during processing. More particularly,FIG. 3A illustrates a cross-sectional view of a portion of awafer 370 during processing. The cross-sectional view illustrated inFIG. 3A can correspond to a cross section 3-3 of thesemiconductor device 100 inFIGS. 1A and 1B during processing. - As shown in
FIG. 3A , thewafer 370 includes asubstrate 302, adielectric layer 304,semiconductor fins channels dielectric regions conductive layer 328. Thesubstrate 302, thedielectric layer 304, thesemiconductor fins channels dielectric regions substrate 102, thedielectric layer 104, thesemiconductor fins channels dielectric regions semiconductor device 100. - The
conductive layer 328 is formed over thesemiconductor fins substrate 302, thedielectric layer 304, thechannels dielectric regions conductive layer 328 can include conductive material, such as those described above with respect to theelectrodes gate 120. Theconductive layer 328 can be formed over thesemiconductor fins semiconductor fins wafer 370 shown inFIG. 3A . - Referring now to
FIG. 2 andFIG. 3B , theprocess 200 includes forming a mask (e.g., 334) over the conductive layer (e.g., 328) (272 inFIG. 2 ). -
FIG. 3B illustrates a cross-sectional view of a portion of an exemplary wafer during processing. More particularly,FIG. 3B illustrates a cross-sectional view of a portion of awafer 372 during processing. The cross-sectional view illustrated inFIG. 3B can correspond to the cross section 3-3 of thesemiconductor device 100 inFIGS. 1A and 1B during processing. - As shown in
FIG. 3B , thewafer 372 includes amask 334 formed over theconductive layer 328. Themask 334 exposes aregion 336 of theconductive layer 328 that overlies thesemiconductor fins mask 334 can include photoresist. Themask 334 can be formed over theconductive layer 328 by applying photoresist to thewafer 370 ofFIG. 3A over theconductive layer 328. The photoresist can be patterned to expose theregion 336 of theconductive layer 328, resulting in thewafer 372 shown inFIG. 3B . - Referring now to
FIG. 2 andFIG. 3C , theprocess 200 includes etching the conductive layer (e.g., 328) using the mask (e.g., 334) to form a floating gate (e.g., 320) situated between the first and second semiconductor fins (e.g., 306 a and 306 b) (274 inFIG. 2 ). -
FIG. 3C illustrates a cross-sectional view of a portion of an exemplary wafer during processing. More particularly,FIG. 3C illustrates a cross-sectional view of a portion of awafer 374 during processing. The cross-sectional view illustrated inFIG. 3C can correspond to the cross section 3-3 of thesemiconductor device 100 inFIGS. 1A and 1B during processing. - As shown in
FIG. 3C , thewafer 374 includes a floating gate 320, an electrode 322 a, and anelectrode 322 b. The floating gate 320, the electrode 322 a, and theelectrode 322 b correspond to the floatinggate 120, theelectrode 122 a, and theelectrode 122 b in thesemiconductor device 100. - The floating gate 320 can be formed by etching the
conductive layer 328 of thewafer 372 using themask 334 of the wafer to form the floating gate 320 situated between thesemiconductor fins mask 334 can be removed, resulting in thewafer 374 shown inFIG. 3C . The etching of theconductive layer 328 can also form theelectrodes 322 a and 322 b. Furthermore, the etching of theconductive layer 328 can also remove portions of dielectric material that forms thedielectric regions semiconductor fins dielectric regions dielectric regions conductive layer 328 or may not be etched. - Additional processing can be performed on the
wafer 374 to result in thesemiconductor device 100. This additional processing may include formation of contacts and silicide for the contacts. Thus, theprocess 200 provides for fabrication of semiconductor devices, such as thesemiconductor device 100, which can be a programmable non-volatile memory device. Theprocess 200 can be integrated into processes for fabrication of one or more fin FETs. In some implementations, this intergration only requires an addition of themask 334 for etching theconductive layer 328. However, themask 334 may also be utilized for fabricating finFETs or other components. - From the above description it is manifest that various techniques can be used for implementing the concepts described in the present application without departing from the scope of those concepts. Moreover, while the concepts have been described with specific reference to certain implementations, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the scope of those concepts. As such, the described implementations are to be considered in all respects as illustrative and not restrictive. It should also be understood that the present application is not limited to the particular implementations described above, but many rearrangements, modifications, and substitutions are possible without departing from the scope of the present disclosure.
Claims (20)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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US13/460,336 US8816421B2 (en) | 2012-04-30 | 2012-04-30 | Semiconductor device with semiconductor fins and floating gate |
KR1020120106959A KR101356405B1 (en) | 2012-04-30 | 2012-09-26 | Semiconductor device with semiconductor fins and floating gate |
CN201220509796.XU CN202905723U (en) | 2012-04-30 | 2012-09-27 | Semiconductor device and programmable non-volatile memory device |
CN201210369636.4A CN103378166B (en) | 2012-04-30 | 2012-09-27 | Semiconductor device and programmable nonvolatile storage device |
TW101137661A TWI463667B (en) | 2012-04-30 | 2012-10-12 | Semiconductor device with semiconductor fins and floating gate |
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US13/460,336 US8816421B2 (en) | 2012-04-30 | 2012-04-30 | Semiconductor device with semiconductor fins and floating gate |
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US20130285135A1 true US20130285135A1 (en) | 2013-10-31 |
US8816421B2 US8816421B2 (en) | 2014-08-26 |
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US13/460,336 Active 2032-05-23 US8816421B2 (en) | 2012-04-30 | 2012-04-30 | Semiconductor device with semiconductor fins and floating gate |
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US (1) | US8816421B2 (en) |
KR (1) | KR101356405B1 (en) |
CN (2) | CN202905723U (en) |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI713205B (en) * | 2018-10-11 | 2020-12-11 | 秉堯 沈 | Memory device for operating with logic transistor and method of operating the same |
TWI844711B (en) | 2019-07-29 | 2024-06-11 | 南韓商矽工廠股份有限公司 | Schottky barrier diode |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US8816421B2 (en) * | 2012-04-30 | 2014-08-26 | Broadcom Corporation | Semiconductor device with semiconductor fins and floating gate |
US8895446B2 (en) * | 2013-02-18 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin deformation modulation |
CN104124210B (en) * | 2013-04-28 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
CN104241289B (en) * | 2013-06-20 | 2018-11-13 | 中国科学院微电子研究所 | Memory device and its manufacturing method |
US9391170B2 (en) * | 2013-08-22 | 2016-07-12 | Broadcom Corporation | Three-dimensional field-effect transistor on bulk silicon substrate |
WO2018194293A1 (en) * | 2017-04-19 | 2018-10-25 | 경북대학교산학협력단 | Semiconductor device and manufacturing method therefor |
US11586898B2 (en) * | 2019-01-29 | 2023-02-21 | Silicon Storage Technology, Inc. | Precision programming circuit for analog neural memory in deep learning artificial neural network |
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US4380057A (en) * | 1980-10-27 | 1983-04-12 | International Business Machines Corporation | Electrically alterable double dense memory |
ATE481736T1 (en) * | 2002-12-19 | 2010-10-15 | Ibm | FINFET SRAM CELL WITH INVERTED FINFET THIN FILM TRANSISTORS |
US6958512B1 (en) * | 2004-02-03 | 2005-10-25 | Advanced Micro Devices, Inc. | Non-volatile memory device |
KR100654535B1 (en) | 2005-05-18 | 2006-12-05 | 인터내셔널 비지네스 머신즈 코포레이션 | Finfet sram cell using inverted finfet thin film transistors |
TWI263310B (en) * | 2005-09-28 | 2006-10-01 | Powerchip Semiconductor Corp | Non-volatile memory and fabricating method thereof |
US7763932B2 (en) * | 2006-06-29 | 2010-07-27 | International Business Machines Corporation | Multi-bit high-density memory device and architecture and method of fabricating multi-bit high-density memory devices |
JP2009004691A (en) * | 2007-06-25 | 2009-01-08 | Fujitsu Microelectronics Ltd | Semiconductor device |
KR20090017041A (en) * | 2007-08-13 | 2009-02-18 | 삼성전자주식회사 | Nonvolatile memory device and method of fabricating the same |
JP2010034266A (en) | 2008-07-29 | 2010-02-12 | Renesas Technology Corp | Double gate semiconductor device and method of manufacturing the same |
US8816421B2 (en) * | 2012-04-30 | 2014-08-26 | Broadcom Corporation | Semiconductor device with semiconductor fins and floating gate |
-
2012
- 2012-04-30 US US13/460,336 patent/US8816421B2/en active Active
- 2012-09-26 KR KR1020120106959A patent/KR101356405B1/en not_active IP Right Cessation
- 2012-09-27 CN CN201220509796.XU patent/CN202905723U/en not_active Withdrawn - After Issue
- 2012-09-27 CN CN201210369636.4A patent/CN103378166B/en active Active
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI713205B (en) * | 2018-10-11 | 2020-12-11 | 秉堯 沈 | Memory device for operating with logic transistor and method of operating the same |
TWI844711B (en) | 2019-07-29 | 2024-06-11 | 南韓商矽工廠股份有限公司 | Schottky barrier diode |
Also Published As
Publication number | Publication date |
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KR20130122501A (en) | 2013-11-07 |
US8816421B2 (en) | 2014-08-26 |
TW201344907A (en) | 2013-11-01 |
KR101356405B1 (en) | 2014-01-27 |
CN202905723U (en) | 2013-04-24 |
CN103378166A (en) | 2013-10-30 |
CN103378166B (en) | 2017-03-01 |
TWI463667B (en) | 2014-12-01 |
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