JP2009004691A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure which can increase current drive capability without increasing an occupied area of an element in a semiconductor device of a so-called Mirrorbit(R) transistor array. <P>SOLUTION: A plurality of projecting parts 23 with triangular-shaped cross-section, in which ridgelines 23c extend in a predetermined direction, are formed in parallel to one another in an upper surface of a semiconductor substrate 21. A diffusion region 22, which constitutes source/drain, is formed so as to extend in a direction orthogonal to the projecting part 23. In the upper part of the projecting parts and the diffusion region, a gate insulating film 24 which has a tunnel film which consists of oxide, a trap film which consists of nitride, and a top film which consists of oxide, is formed. The gate electrode 25 is formed so as to extend in the longitudinal direction of the projecting part 23 above two inclined surfaces 23a and 23b of the projecting part 23. Thereby, a gate area (channel area) can be increased without expanding the gate electrode 25 in a channel width direction, and current drive capability can be increased. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a field effect transistor, and more particularly to a semiconductor device in which a plurality of transistors are arranged with high integration.

  For the purpose of high integration of semiconductor devices, various proposals have been made on the structure and arrangement of the channel, gate insulating film, gate electrode, and source electrode of a MOS field effect transistor (MOSFET) constituting the semiconductor device. In order to miniaturize the MOSFET, it is necessary to miniaturize the gate electrode (and the channel portion), which causes a short channel effect such as a decrease in transistor current control capability (current drive capability) and an increase in leakage current. Problem arises.

  As a transistor structure that hardly causes such a problem, a technique related to a Fin type FET is known (for example, Patent Document 1). The fin-type FET has a channel portion formed as a convex portion, and a gate electrode is disposed so as to cover the periphery of the channel portion, thereby reducing the area occupied by the transistor (area on the plane) while reducing the area of the gate electrode. That is, it is possible to increase the current drive capability and prevent the short channel effect by increasing the channel area. In particular, it is effective to form fins so as to increase the channel width from the viewpoint of improving the current driving capability.

  On the other hand, for high integration of flash memory, a technique is known in which the gate portion of a transistor constituting the flash memory has a MONOS structure (for example, Non-Patent Document 1). In the MONOS structure, a metal (metal or polycrystalline silicon, etc.) layer, an oxide layer, a nitride layer, an oxide layer, and the gate from the gate of the transistor are sequentially arranged from the top. It has a laminated structure composed of a silicon (silicon) layer, and information is recorded by accumulating charges in the trap level of the nitride layer. Unlike a general floating gate structure, the MONOS structure has excellent charge retention characteristics, and malfunction due to miniaturization such as a decrease in capacitive coupling between the control gate and the floating gate and an increase in capacitive coupling between adjacent gates. Since it does not occur, it is advantageous for miniaturization of a flash memory transistor.

  As a technique related to a flash memory in which this MONOS structure is applied to a fin-type FET, there is a technique disclosed in Non-Patent Document 1. FIG. 1 is a perspective view showing the structure of a flash memory disclosed in Non-Patent Document 1. FIG. In FIG. 1, a convex fin 103 is formed on the surface of a silicon substrate 101, and a gate insulating film 104 made of oxide-nitride-oxide is formed so as to cover the fin 103, and the gate insulating film 104 A gate electrode 105 is formed on the upper portion of the gate electrode 105. A source and a drain are formed in a portion of the fin 103 sandwiching the gate electrode 105. The channel of the transistor is formed on the surface of the fin 103 covered with the gate electrode 105. The gate electrode 105 (word line) is formed in a direction orthogonal to the fin 103, that is, in the channel width direction of the transistor. A flash memory in which such a MONOS structure is combined with a fin-type FET has a wider channel width (gate width) than a floating gate type flash memory having a flat gate portion so far. Therefore, the short channel effect is suppressed, and it is possible to easily cope with the miniaturization in combination with the charge retention characteristics of the MONOS structure.

  In addition, a technique is known in which the operation of a memory cell in a flash memory is multi-valued so that the capacity recorded in one memory cell is 2 bits. As a structure of a semiconductor device that enables such multi-valued memory cells, a TwinMONOS (registered trademark) type transistor array (hereinafter also referred to as a TwinMONOS structure), a Mirrorbit (registered trademark) type transistor array (hereinafter referred to as a mirror). (Also referred to as a bit structure) is known (for example, Non-Patent Document 2 and Non-Patent Document 3).

  FIG. 2 is a bird's-eye view (schematic diagram) showing the TwinMONOS structure, and FIG. 3 is a view of the TwinMONOS structure as viewed from above. As shown in FIG. 2, in the flash memory device 200 having the TwinMONOS structure, two control gates 205 are formed on both sides of a word gate 206 extending in the x-axis direction (channel width direction), and an oxide is formed below the control gate 205. A gate insulating film 204 made of a material-nitride-oxide is formed. The source and drain (diffusion region 202) are formed on the side portion of the control gate 205 and connected to the upper bit line 209 by a contact 207 arranged in a checkered pattern, as shown by the hatched portion 202 in FIG. . The transistor is formed so that the channel length direction is the y-axis direction in FIGS. In the TwinMONOS structure, the source and drain can be switched by changing the voltage applied to the bit line 209, and charges can be separately accumulated in the gate insulating film 204 under the two control gates 205. Also, by detecting the threshold voltage by switching the source and drain, the charge accumulation state of the gate insulating film 204 under each control gate 205 can be detected, and the recording capacity per unit cell is 2 bits. be able to.

  FIG. 4 is a perspective view showing a mirror bit structure, and FIG. 5 is a cross-sectional view of a memory cell having a mirror bit structure. As shown in FIGS. 4 and 5, in the flash memory device having a mirror bit structure, a diffusion region 302 is formed on a semiconductor substrate 301 extending in a predetermined direction, and a gate insulating film 304 is formed on the diffusion region 302. Thus, a gate electrode 305 is formed. As shown in FIG. 5, in the cross section of the transistor constituting the memory cell, the diffusion region 302 constitutes the source and drain, and the gate insulating film 304 has a stacked structure of oxide, nitride, and oxide. In the case of a general NAND type transistor array or NOR type transistor array, the gate electrode (word line) extends in the channel width direction, and the source and drain are divided in the channel length direction of the transistor. In contrast, in the mirror bit structure, as shown in FIG. 4, the source and drain (diffusion region 302; bit line) extend linearly in the channel width direction (x-axis direction), and the gate electrode 305 (word line) is the channel. It extends linearly in the long direction (y-axis direction). Then, by changing the voltage applied between adjacent diffusion regions 302, the source and drain of the transistor can be switched to operate. For this reason, as shown by the shaded portion in FIG. 5, charges can be separately accumulated in the vicinity of the diffusion region 202 of the nitride film, and the charge accumulation state in these portions can be detected by a predetermined reading operation. In this way, the mirror bit structure can also have a storage capacity of 2 bits per unit cell, similarly to the TwinMONOS structure. Further, since the diffusion region 302 extends linearly, it is not necessary to form a contact for each cell, and the structure is simpler than the TwinMONOS structure, which is advantageous for high integration.

  In addition, a technique for dispersing silicon nanocrystals between oxide layers of a gate insulating film is known as a technique for high integration of a flash memory (for example, Non-Patent Document 4).

Prior art document information that is considered to be related to the invention of this application includes the following.
JP-A-8-88285 Suk-Kang Sung, 8 others, “Fully Integrated SONOS Flash Memory Cell Array with BT-FinFET Structure”, Silicon Nanoelectronics Workshop, Kyoto, 2005 Tomoko Ogura, 6 others, “Embedded Twin MONOS Flash Memories with 4ns and 15ns Fast Access Times”, 2003 Symposium on VLSI Circuits Digest of Technical Papers, 2003 Spansion LLC, “SpansionTM Flash Memory with MirrorbitTM Technology”, [online], 2004, Spansion LLC, [April 6, 2007 search], Internet <URL: http://www.spansion.com/technology/mirrorbit /spansion-generic-mirrorbit.pdf> Yi Shi, 3 others, “Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals”, Journal of Applied Physics, August 15, 1998, Volume 84, Number 4, p.2358 -2360

  The transistors of Non-Patent Document 2 and Non-Patent Document 3 that disclose the mirror bit structure and the TwinMONOS structure do not have a fin structure. Therefore, when semiconductor devices having these structures are miniaturized (highly integrated), problems such as a short channel effect such as a decrease in channel width and a decrease in current driving capability and an increase in leakage current due to a decrease in channel length occur. . Therefore, it is considered to apply a fin structure to a transistor with a mirror bit structure or a TwinMONOS structure.

  Consider a case where a transistor is a fin type with a mirror bit structure. In order to widen the channel width from the viewpoint of current drive capability, it is necessary to form the fin so that its longitudinal direction is the channel length direction (y-axis direction in FIG. 4). FIG. 6 is a diagram showing a cross section of the gate electrode when the transistor is a fin type in the mirror bit structure. In this case, it is necessary to form the gate electrode 305 so as to cover the periphery of the fin 303 as shown in FIG. Therefore, it is necessary to separate the gate electrode 305 for each fin 303. The pitch of the gate electrode 305 is a distance of a × 2 + b + d, where a is the total thickness of the gate electrode 305 and the gate insulating film 304, b is the width of the fin 303, and d is a separation width d for separating the gate electrode. Necessary. On the other hand, in the mirror bit structure using the conventional planar type transistor, the pitch of the gate electrodes may be b + d. Therefore, if the transistor is a fin type in the mirror bit structure, the pitch of the gate electrode needs to be increased by the thickness of the gate electrode and the gate insulating film. As a result, the area occupied by the transistor becomes larger.

  When a fin structure is applied to the TwinMONOS transistor array, it is necessary to form the fin so that the channel length direction and the fin longitudinal direction coincide with each other in order to increase the channel width from the viewpoint of improving the current driving capability. In FIG. 2, the fin is formed so that its longitudinal direction extends in the y-axis direction, and it is not necessary to separate the control gate 205 for each fin, and there is a problem when the fin structure is applied to the mirror bit structure. Does not occur. However, in the TwinMONOS structure, it is necessary to form a contact between adjacent gate electrodes. When compared with the same wiring width, the occupied area becomes larger than the mirror bit structure.

  An object of the present invention is to provide a structure capable of improving a current driving capability and suppressing a short channel effect without increasing an area occupied by a transistor in a semiconductor device having a mirror bit type transistor array. is there.

  According to an aspect of the present invention, there is provided a semiconductor substrate and a cross section perpendicular to the longitudinal direction, which is formed on the upper surface of the semiconductor substrate, extends in a predetermined direction, and is disposed in parallel with each other at a predetermined interval. The triangular first protrusion and a region formed by introducing predetermined impurities into the upper surface of the semiconductor substrate, extending in a direction perpendicular to the longitudinal direction of the first protrusion, and A plurality of diffusion regions arranged in parallel with each other at a predetermined interval in the longitudinal direction of the first protrusion, a gate insulating film formed on the semiconductor substrate, and on the gate insulating film, A gate electrode formed so as to extend above a part of two inclined surfaces straddling the ridge line of the first protrusion, and to extend linearly in the longitudinal direction of the first protrusion; Provided is a semiconductor device characterized by comprising

  In the present invention, in a semiconductor device including a so-called mirror bit type transistor array, a channel portion of a transistor is formed above two inclined surfaces straddling the ridge line of the first protrusion having a triangular cross section. As a result, the channel width is increased as compared with the conventional planar type transistor, the current driving capability is improved, and the channel is covered with the gate electrode on a plurality of surfaces, thereby suppressing the short channel effect. Further, since the gate electrode is formed only above the inclined surface of the first protrusion, it does not increase in the channel width direction. As a result, the current driving capability can be improved and the short channel effect can be suppressed without increasing the area occupied by the transistor (planar area), and further miniaturization and higher integration of the semiconductor device can be achieved. it can.

  According to another aspect of the present invention, there is provided a semiconductor device in which diffusion regions serving as source and drain wirings are linearly formed on a semiconductor substrate. As a result, the distance in the current transport direction of the diffusion region (source and drain wiring) is shortened, and an increase in electrical resistance is suppressed. In this case, as a means for forming the diffusion region in a straight line on the substrate, the diffusion region is formed on the upper surface of the semiconductor substrate, extends in a direction perpendicular to the longitudinal direction of the first protrusion, and is spaced from each other at a predetermined interval. A plurality of second protrusions arranged in parallel may be provided, and the diffusion region may be formed on an upper portion of the second protrusion. According to such a configuration, the diffusion region can be formed linearly along the upper portion of the second protrusion.

  Furthermore, in the present invention, the gate insulating film may have a three-layer structure of an oxide tunnel film, a nitride trap film, and an oxide top film in order from the semiconductor substrate side. Thus, a nonvolatile semiconductor memory device that can store information of a plurality of bits in one transistor is obtained.

  Furthermore, in the present invention, adjacent channels may be separated by a valley-like portion formed by adjacent inclined surfaces of the adjacent first protrusions. As a result, the channels are separated by grooves having a triangular cross section, and the channels can be more reliably separated even if the semiconductor device is miniaturized.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
FIG. 7 is a top view showing the semiconductor device according to the first embodiment of the present invention. FIG. 13 is a perspective view showing the semiconductor device according to the first embodiment of the present invention. FIG. 14 is a cross-sectional view taken along the line E-E ′ of FIG. 7, showing a cross section of the semiconductor device according to the first embodiment. FIG. 15 is a cross-sectional view taken along the line CC ′ of FIG. 7, showing a cross section of the semiconductor device according to the first embodiment. FIG. 16 is a cross-sectional view taken along the line DD ′ of FIG. 7, showing a cross section of the semiconductor device according to the first embodiment.

  As shown in FIGS. 7 and 13, the semiconductor device 20 according to the first embodiment of the present invention relates to a nonvolatile semiconductor memory device, and is a p-well formed on a silicon substrate (hereinafter referred to as a semiconductor substrate). A plurality of first protrusions 23 are formed in parallel on the surface of 21. The upper surface of the first protrusion 23 is constituted by two inclined surfaces (a first inclined surface 23a and a second inclined surface 23b), and a cross section perpendicular to the longitudinal direction is triangular. As illustrated in FIGS. 13 and 15, the first protrusion includes a ridge line 23 c, and the ridge line 23 c extends in the channel length direction (y-axis direction) of the semiconductor device 20. The adjacent first protrusions 23 are connected to each other by inclined surfaces (first and second inclined surfaces 23a and 23b), and a valley portion is formed at an intermediate position between the adjacent ridge lines 23c. The first inclined surface 23a and the second inclined surface 23b are made of a silicon (111) surface, and the inclination thereof is constant. Therefore, the height of the first protrusion 23 is proportional to its width. The width of the first projecting portion 23 is determined by the pitch of the first convex portion 26 described later, and can be about twice the minimum processing dimension (for example, 65 nm) in the manufacturing process.

  The gate insulating film 24 is formed so as to uniformly cover the upper surface of the semiconductor substrate 21 on which the first protrusions 23 are formed. A tunnel oxide film (for example, a silicon oxide film having a thickness of about 10 nm) is sequentially formed from the semiconductor substrate side 21. A nitride film (for example, a SiN film having a thickness of about 10 nm) and an oxide film (for example, a silicon oxide film or an aluminum oxide film having a thickness of about 10 nm) are formed, and has a stacked gate structure having a so-called ONO structure.

  As shown in FIG. 7, the diffusion region 22 is formed on the surface of the semiconductor substrate 21 on which the first protrusion 23 is formed, in a direction perpendicular to the ridge line 23c of the first protrusion 23 (channel width direction; x-axis direction). ). The width of the diffusion region 22 and the interval between the adjacent diffusion regions 22 can be set to a minimum processing dimension (for example, 65 nm) in the manufacturing process. Since the diffusion region 22 is formed along the surface of the first protrusion 23, the longitudinal direction (current transport direction; x-axis direction) is in the vertical direction of the semiconductor substrate 21 as shown in FIG. It is bent.

  As shown in FIG. 7, the gate electrode 25 passes through the upper part of the diffusion region 22 and extends in the channel length direction (y-axis direction), and constitutes a word line of the semiconductor device 20. As shown in FIGS. 13, 15, and 16, the gate electrode 25 is formed on the gate insulating film 24 and is insulated from the diffusion region 22 and the semiconductor substrate 21. The gate electrode 25 is formed above the inclined surfaces (first and second inclined surfaces 23a and 23b) in the vicinity of the ridge line 23c of the first protrusion 23. As shown in FIGS. 15 and 16, the gate electrodes 25 adjacent to each other are separated by a valley portion formed by the first inclined surface 23a and the second inclined surface 23b. The width of the gate electrode 25 and the interval between the parts separated from the adjacent gate electrode 25 can be made equal to the minimum processing dimension (for example, 65 nm) in the manufacturing process. Approximately twice the size. The thickness of the gate electrode 25 can be about 100 nm. For the gate electrode 25, for example, n-type polycrystalline silicon, nickel silicide, tantalum nitride, tungsten, or the like can be used.

  The cross section cut along the first ridgeline of the semiconductor device 20 according to the first embodiment has the structure shown in FIG. That is, diffusion regions 22 (bit lines BL 1 and bit lines BL 2) are formed on the surface of the semiconductor substrate 21 with a constant pitch, and a gate insulating film 24 having an ONO structure is formed on the semiconductor substrate 21. Furthermore, a gate electrode 25 (word line WL1) is formed in the channel length direction on the upper part. One transistor Tr11 is formed in a portion surrounded by a broken line in FIG. 14, and this constitutes one memory cell of the semiconductor device 20.

  Next, a manufacturing process of the semiconductor device according to the present embodiment will be described with reference to FIGS. FIG. 8 is a perspective view showing a state in the process of manufacturing the semiconductor device according to the first embodiment of the present invention, and a perspective view showing a state immediately after the first convex portion 26 is formed on the upper surface of the semiconductor substrate 21. It is. FIG. 9 is a view showing a state in the process of manufacturing the semiconductor device according to the first embodiment of the present invention, and is a perspective view showing a state immediately after the anisotropic etching process is finished. FIG. 10 is a view showing a state in the process of manufacturing the semiconductor device according to the first embodiment of the present invention, and is a perspective view showing a state immediately after the gate insulating film 24 is formed. FIG. 11 is a view showing a state in the process of manufacturing the semiconductor device according to the first embodiment of the present invention, and is a perspective view showing a state immediately after the diffusion region 22 is formed. FIG. 12 is a view showing a state in the process of manufacturing the semiconductor device according to the first embodiment of the present invention, and is a perspective view showing a state immediately after the polycrystalline silicon film 29 is formed above the semiconductor substrate 22. .

  First, steps required until a structure shown in FIG. A p-type well is formed on the upper surface of the silicon substrate with the silicon (100) surface exposed on the upper surface, and this is used as the semiconductor substrate 21. Thereafter, a resist film (not shown) is formed on the surface of the semiconductor substrate 21 by photolithography, and then the semiconductor substrate 21 is etched in the vertical direction by anisotropic ion etching or the like, as shown in FIG. Striped convex portions (first convex portions 26) extending in the <0-11> direction (the y-axis direction in the drawing) are formed on the surface of the semiconductor substrate 21. In the present specification, a convex portion having a rectangular cross section extending in the direction in which the gate electrode 25 is formed is referred to as a “first convex portion” for convenience. The upper surface of the first convex portion 26 is a (100) plane. Further, the (011) plane is exposed on the side surface of the first convex portion 26. The present embodiment is not limited to this, and the direction of the first convex portion 26 may be a <011> direction that is 90 degrees different from the above-described <0-11> direction. The side surface of the portion 26 is a (0-11) plane.

  Next, an anisotropic etching agent such as a KOH (potassium hydroxide) solution or a TMAH (Tetra Methyl Ammonium Hydroxide) solution is applied to the semiconductor substrate 21 on which the first convex portion 26 is formed. Anisotropic etching is performed using With respect to the above-mentioned anisotropic etching agent, the silicon single crystal proceeds faster in the <100> direction and the <110> direction, and the etching in the <111> direction is particularly slow. Therefore, as shown in FIG. Two inclined surfaces composed of (111) planes appear on the upper portion of 21, and a first protrusion 23 is formed. In the present specification, the inclined surfaces constituting the upper surface of the first projecting portion 23 are referred to as a first inclined surface 23a and a second inclined surface 23b for convenience, and are formed on the uppermost portion of the first projecting portion 23. The ridge line is called a ridge line 23c. As shown in FIG. 9, the first ridge line 23c extends in the <0-11> direction. When the convex portion is formed in the <011> direction, the ridge line 23c extends in the <011> direction.

  Next, the gate insulating film 24 is uniformly formed on the upper surface of the semiconductor substrate 22 on which the first protrusions 23 are formed. First, a tunnel oxide film (for example, a silicon oxide film) is formed on the semiconductor substrate 21. The tunnel oxide film can be formed by thermal oxidation of the semiconductor substrate 21 or a CVD method. Next, a film (trap layer) made of a nitride (eg, a silicon nitride film) is formed on the tunnel oxide film. The nitride film can be formed by a CVD method or the like. Further, a film (top layer) made of an oxide (for example, silicon oxide or aluminum oxide) is formed on the nitride film. The top layer can be formed by a CVD method, a thermal oxidation method, or the like. Through the above processing, the gate insulating film 24 is uniformly formed on the upper surface of the semiconductor substrate 21 as shown in FIG.

Next, steps required until a structure shown in FIG. A mask 28 (for example, a resist film, a silicon oxide film, a silicon nitride film, etc.) is formed above the semiconductor substrate 24 on which the gate insulating film 24 is formed. Thereafter, the mask 28 is flattened, and then the mask 28 is removed only in a portion where the diffusion region 22 is formed by a photolithography method or the like. As shown in FIG. 11, the portion where the mask 28 is removed is formed to extend in a direction perpendicular to the first protrusion 23. The width of the portion from which the mask 28 has been removed can be approximately the same as the minimum processing dimension (for example, 65 nm) in the manufacturing process. Thereafter, an impurity (for example, As ⁺ ions) is implanted into the portion where the mask 28 is removed by an ion implantation method or the like, thereby forming a diffusion region 22 made of an n-type semiconductor region on the upper surface of the semiconductor substrate 21. At this time, heat treatment may be appropriately performed. In the above example, the diffusion region 22 is formed after the gate insulating film 24 is formed. However, the present embodiment is not limited to this, and the gate insulating film 24 is formed after the diffusion region 22 is formed first. May be.

Next, steps required until a structure shown in FIGS. 12 to 13 is formed will be described. After the diffusion region 22 is formed by the above-described process, the mask 28 is removed. Thereafter, a polycrystalline silicon film 29 is uniformly formed over the semiconductor substrate 21 by CVD or the like, and an impurity (for example, As ⁺ ions) is implanted therein by ion implantation, thereby forming the gate electrode 25 n. A type polycrystalline silicon film 29 is formed. Thereby, the structure shown in FIG. 12 is formed.

  Next, after planarizing the polycrystalline silicon film 29, the n-type polycrystalline silicon film 29 is formed in the vertical direction by leaving a portion where the gate electrode 25 is to be formed by photolithography, anisotropic ion etching, or the like. Etch into. Thereby, as shown in FIG. 13, the gate electrode 25 is formed above the first and second inclined surfaces 23a and 23b in the vicinity of the ridge line 23c of the first protrusion 23. Thereafter, although not particularly shown, interlayer insulating films, contacts, wiring layers, and the like are formed, and the semiconductor device 20 according to the first embodiment is completed.

  FIG. 17 is a diagram showing an equivalent circuit of the semiconductor device according to the embodiment of the present invention. In the figure, WL represents a word line, and the gate electrode 25 corresponds to this. BL represents a bit line, and the diffusion region 22 corresponds to this. As shown in FIG. 17, the transistor Tr11 constituting the memory cell of the semiconductor device 20 has a gate connected to the word line WL1, and a source and a drain connected to the bit line BL1 and the bit line BL2. The transistor Tr11 can operate by switching the source and drain by switching the voltages of the bit line BL1 and the bit line BL2.

  The operation of the semiconductor device according to the present embodiment will be described using the memory cell of the transistor Tr11 shown in FIGS. 14 and 17 as an example. First, when writing information, the bit line BL1 is grounded while a predetermined write voltage is applied to the word line WL1, and a predetermined voltage is applied to the bit line BL2. As a result, hot electrons are generated in the vicinity of the bit line BL2, passing through the tunnel oxide film of the gate insulating film 24, trapping electrons in the nitride film in the vicinity of the bit line BL2, and writing information. If the bit line BL2 is grounded while a write voltage is applied to the word line WL1 and a predetermined voltage is applied to the bit line BL1, electrons are trapped in the nitride film near the bit line BL1 and information is written. .

  Next, in the read operation, a predetermined read voltage is applied to the word line WL1, the bit line BL1 is grounded, and a predetermined positive voltage is applied to the bit line BL2 (BL1 is a source and BL2 is a drain). At this time, the amount of current flowing through the channel of the transistor Tr11 is greatly influenced by the charge in the nitride film in the vicinity of the bit line BL1 (source side), and is hardly affected by the charge accumulation state on the bit line BL2 side (drain side). . Therefore, when the transistor Tr11 is turned on, it is detected that a predetermined amount of charge is not accumulated in the nitride film near the bit line BL1 (source side), and when the transistor Tr11 is not turned on, the bit line BL1 is turned on. It is detected that a predetermined amount of charge is accumulated in the nitride film in the vicinity (source side). In addition, the bit line BL2 is grounded with a predetermined read voltage applied to the word line WL1, and a predetermined positive voltage is applied to the bit line BL1 (using BL2 as a source and BL1 as a drain) to detect conduction of the transistor Tr11. By doing so, it is detected whether or not a predetermined amount of charge is accumulated in the nitride film near the bit line BL2 (source side).

  In the erase operation, a hot hole is generated near the bit line BL2 in the channel region by applying an erase voltage between the word line WL1 and the bit line BL2 with the bit line BL1 open. By injecting holes into the nitride film, the charges in the nitride are neutralized and information is erased. The charge trapped in the nitride in the vicinity of the bit line BL1 is erased by applying an erase voltage between the word line WL1 and the bit line BL1 with the bit line BL2 open.

  18A is a cross-sectional view of the gate (channel) portion of the semiconductor device according to the embodiment of the present invention, and FIG. 18B is a cross-sectional view of the gate (channel) portion of the comparative example in which the fin has a rectangular shape. It is sectional drawing.

  In the semiconductor device 20 of the present embodiment, as shown in FIG. 18A, the ridge line 23c extends in the channel length direction, the first protrusion 23 having a triangular cross section is provided, and an inclined surface near the ridge line 23c. A gate electrode 25 is formed above 23a and 23b. As a result, when compared with semiconductor devices manufactured with the same minimum processing dimensions, the channel width is wider than that in the case of using a conventional planar transistor, and the current driving capability is improved. Moreover, since the channels of the inclined surfaces are controlled by the gate electrodes not only from above but also from the sides, the short channel effect is suppressed. Furthermore, since the cross section of the first protrusion 23 is triangular, the pitch of the gate electrodes 25 is made narrower than when a fin type transistor having a rectangular cross section as shown in FIG. 18B is used. In addition, the area occupied by the memory cell (area occupying a planar shape) can be reduced.

(Second Embodiment)
The semiconductor device according to the second embodiment of the present invention relates to a nonvolatile semiconductor memory device, and is characterized in that a diffusion region is formed by extending linearly without bending in the vertical direction of the semiconductor substrate. The semiconductor device according to this embodiment will be described below with reference to FIGS.

  FIG. 19 is a top view showing a semiconductor device according to the second embodiment of the present invention. FIG. 23 is a perspective view showing a semiconductor device according to the second embodiment of the present invention. FIG. 24 is a cross-sectional view taken along line FF ′ of FIG. 19, showing a cross section of the semiconductor device according to the second embodiment. FIG. 25 is a cross-sectional view taken along the line HH ′ of FIG. 19, showing a cross section of the semiconductor device according to the second embodiment. In each of the above drawings, the x-axis direction coincides with the channel width direction of the transistor constituting the memory cell, the y-axis direction coincides with the channel length direction of the transistor, and the z-axis coincides with the vertical direction of the semiconductor substrate.

  The semiconductor device 30 according to the second embodiment also relates to a nonvolatile semiconductor memory device. As shown in FIGS. 19 and 23, a diffusion region 32 extends in the channel width direction (x-axis direction) on the upper surface of the semiconductor substrate 31. The gate electrode 35 extends over the diffusion region 32 and extends in the channel length direction (y-axis direction).

  On the upper surface of the semiconductor substrate 31 of the second embodiment, a first protrusion 33 formed to extend in the channel length direction (y-axis direction) and a first protrusion formed to extend in the channel width direction (x-axis direction). Two protrusions 37 are formed. The semiconductor substrate 31 of the present embodiment is made of silicon single crystal, and the upper part thereof is substantially parallel to the (100) plane. The first protrusion 33 extends on the semiconductor substrate 31 in the silicon <0-11> direction or the silicon <011> direction, and the second protrusion 37 extends in a direction orthogonal to the first protrusion. Yes. As shown in FIG. 23, the upper surface of the first projecting portion 33 is constituted by first and second inclined surfaces 33a and 33b, and the cross section perpendicular to the longitudinal direction is triangular. In addition, the first ridge line 33c formed by the inclined surfaces 33a and 33b extends in the channel length direction (y-axis direction). As shown in FIGS. 19 and 24, the upper surface of the second protrusion 37 is formed by a third inclined surface 37a and a fourth inclined surface 37b, and its ridgeline (referred to as a second ridgeline for convenience) 37c. Extends in the channel width direction (x-axis direction). The inclined surfaces 33a, 33b, 37a and 37b are made of a silicon (111) surface.

  The diffusion region 32 is formed on the upper surface of the semiconductor substrate 31 in the vicinity of the second ridge line 37c along the ridge line direction (for example, <011> direction). As shown in FIG. 23, the diffusion region 32 is formed from the second ridge line 37c to a predetermined depth and extends in the direction of the ridge line 37c. 19 has a structure shown in FIG. 25. As shown in FIG. 25, the diffusion region 32 of the present embodiment is different from the diffusion region 22 of the first embodiment. , Formed in a straight line without bending in the z-axis direction. As a result, the length of the diffusion region 32 serving as the source and drain wirings in the current transport direction is shortened, and the electrical resistance of the wiring part is reduced.

  The gate insulating film 34 is uniformly formed on the semiconductor substrate 31 including the diffusion region 32. The structure of the gate insulating film 34, such as the film thickness and material, can be the same as that of the gate insulating film 24 of the first embodiment.

  The gate electrode 35 is formed on the gate insulating film 34 as shown in FIGS. As shown in FIG. 23, the gate electrode 35 is formed above the inclined surfaces 33a and 33b in the vicinity of the ridge line 33c of the first protrusion 33 so as to extend in the direction of the first ridge line 33c. Adjacent gate electrodes 35 are separated from each other by a valley portion formed by the first inclined surface and the second inclined surface except for a portion intersecting the second projecting portion 37. The cross section of the center position in the width direction of the gate electrode 35 (the GG ′ line in FIG. 19) is the same as that in FIG. Further, the cross section of the position slightly off the center in the width direction of the gate electrode 35 (the FF ′ line in FIG. 19) is as shown in FIG. 24. The gate electrode 35 is formed on the gate insulating film 34, It is formed so as to pass over the diffusion region 32.

  Next, a method for manufacturing the semiconductor device 30 of this embodiment will be described. 20 to 22 are views showing structures in the process of manufacturing the semiconductor device 30 of the present embodiment. In the figure, the x-axis indicates the channel width direction of the transistor, the y-axis indicates the channel length direction of the transistor, and the z-axis indicates the vertical direction of the semiconductor substrate 31. First, steps required until a structure shown in FIG. 20 is formed will be described. A p-type well is formed in a silicon substrate with the silicon (100) surface exposed on the upper surface, and this is used as a semiconductor substrate 31. Thereafter, a resist film (not shown) in which rectangular openings are provided in a checkered pattern is formed on the semiconductor substrate 31 by photolithography, and the semiconductor is formed by anisotropic ion etching or the like using this resist film as a mask. The substrate 31 is etched. Thereafter, the resist film is removed. Thereby, as shown in FIG. 20, the unevenness | corrugation by which the recessed part was arrange | positioned in the checkered pattern form on the surface of the semiconductor substrate 31 is formed. The upper surface of the unevenness is formed by the (100) surface, and the (011) surface and the (0-11) surface are exposed on the side surfaces of the convex portion (and the concave portion). In the structure shown in FIG. 20, the portion extending in the y-axis direction surrounded by the broken line 36a among the convex portions on the surface is referred to as the first convex portion 36a for convenience and the x-axis direction surrounded by the broken line 36b. The portion extending to is referred to as a second convex portion 36b for convenience.

  Next, steps required until a structure shown in FIG. The structure shown in FIG. 20 is anisotropically etched using an anisotropic etchant such as KOH (potassium hydroxide) or TMAH (Tetra Methyl Ammonium Hydroxide). Since the etching in the <100> direction and the <110> direction proceeds faster than the anisotropic etching agent described above, and the etching in the <111> direction becomes particularly slow, as shown in FIG. Irregularities having an inclined surface consisting of (111) plane are formed. By this step, the first protrusion 33 in which the ridge line 33c extends linearly in the <0-11> direction and the ridge line 37c in a straight line in the <011> direction (a direction orthogonal to the ridge line of the first protrusion). A second projecting portion 37 that extends is formed.

  Next, steps required until a structure shown in FIG. A gate insulating film 34 is uniformly formed on the upper surface of the structure shown in FIG. The gate insulating film 34 is produced, for example, by sequentially forming an oxide (such as SiO), a nitride (such as SiN), and an oxide (such as SiO) from the substrate side by a CVD method, a thermal oxidation method, or the like.

Next, a mask 38 is uniformly formed on the gate insulating film 34. The mask 38 is processed by a photolithographic method or the like to form a pattern of the mask 38 from which a portion near the second ridge line 37c is removed as shown in FIG. Thereafter, an impurity (for example, As ⁺ ) is implanted into the surface of the semiconductor substrate 31 in the vicinity of the second ridge line by ion implantation to form a diffusion region 32. The structure of FIG. 22 is formed by the above process. In the above example, the diffusion region 32 is formed by ion implantation after the gate insulating film 34 is formed. However, the diffusion region 32 may be formed first, and then the gate insulating film 34 may be formed.

  Next, the mask 38 is removed from the structure of FIG. 22, and a polycrystalline silicon film 29 is formed on the gate insulating film 34. Ions are implanted into this polycrystalline silicon film to form n-type polycrystalline silicon. Next, a striped mask (not shown) extending in the direction of the first protrusion 33 (y-axis direction) is formed on the n-type polycrystalline silicon film 29. Thereafter, the n-type polycrystalline silicon film 29 is etched in the vertical direction by anisotropic ion etching or the like, and the other portion is removed while leaving the portion extending in the vicinity of the first ridge line 33c, whereby the gate electrode 35 is removed. Is formed. Then, the structure shown in FIG. 23 is completed by removing the mask. Thereafter, although not particularly shown, an interlayer insulating film, a contact, a wiring layer, and the like are formed, and the semiconductor device 30 is completed.

  The equivalent circuit and read / write operations of the semiconductor device 30 according to the present embodiment are the same as those of the semiconductor device 20 according to the first embodiment.

  According to the semiconductor device 30 of the present embodiment, the first protrusion 33 having the inclined surfaces 33a and 33b is formed, and the gate electrode 35 is formed above the inclined surface in the vicinity of the ridge line 33c. Compared with a planar transistor, the channel width is widened and current driving capability can be improved. Moreover, since the channels of the inclined surfaces are controlled by the gate electrodes not only from above but also from the sides, the short channel effect is suppressed.

  Further, a ridge line 37 c formed in the upper part of the semiconductor substrate 31 extends linearly, and a second projecting portion 37 disposed in a direction orthogonal to the first projecting portion 33 is provided. Since the diffusion region 32 is formed in the upper part of the second protrusion 37 near the ridge line 37c, the diffusion region 32 is formed in a straight line. In the semiconductor device 30, since the diffusion region 32 also serves as the source and drain wiring, the length in the current transport direction is shorter than the diffusion region 22 of the first embodiment bent in the vertical direction shown in FIG. Therefore, in the semiconductor device 30 of this embodiment, an increase in electrical resistance in the source and drain wiring is suppressed as compared with the semiconductor device according to the first embodiment.

(Third embodiment)
The third embodiment of the present invention is characterized in that the diffusion regions constituting the source and drain wirings are formed in a straight line, and the constriction is formed in the protruding portion where the diffusion regions are formed.

  FIG. 26 is a top view showing a semiconductor device according to the third embodiment of the present invention. FIG. 32 is a perspective view showing a semiconductor device according to the third embodiment of the present invention. 27 to 31 are perspective views showing a state during the manufacture of the semiconductor device according to the third embodiment of the present invention. FIG. 32 is a perspective view showing a part of a semiconductor device according to the third embodiment of the present invention. In each of the above drawings, the x axis coincides with the channel width direction and the bit line direction of the transistor to be formed, the y axis coincides with the channel length direction and the word line direction of the transistor to be formed, and the z axis represents the semiconductor. It corresponds to the vertical direction of the substrate.

  When the semiconductor device 40 according to the present embodiment is viewed from the top, as shown in FIG. 26, the diffusion region 42 constituting the source and drain lines (bit lines) is formed extending in the x-axis direction, and the gate electrode 45 (word Line) extends in the y-axis direction. As shown in FIG. 32, a first protrusion 43 that extends in the y-axis direction and a second protrusion 47 that extends in the x-axis direction are formed on the surface of the semiconductor substrate 41. The upper surface of the first protrusion 43 is formed by two inclined surfaces 43a and 43b as in the second embodiment, and the ridge line 43c extends in the y-axis direction at the top. The second projecting portion 47 has a flat portion 47 f formed on the upper portion thereof, and a constricted portion cut inwardly is formed on a side portion of the second projecting portion 47.

  As shown in FIG. 32, the diffusion region 42 is formed from the flat portion 47f above the second protrusion 47 to the constricted portion. The cross section at the center position in the width direction of the diffusion region 42 (the line JJ ′ in FIG. 26) is the same as that in FIG. 25, and the diffusion region 42 is formed in a straight line. Here, the semiconductor substrate 41 corresponds to the semiconductor substrate 31 of FIG. 25, the diffusion region 42 corresponds to the diffusion region 32 of FIG. 25, the gate insulating film 44 corresponds to the gate insulating film 34 of FIG. Corresponds to the gate electrode 35 of FIG. As shown in FIG. 32, the gate insulating film 44 is formed to uniformly cover the surface of the semiconductor substrate 41 including the constricted portion of the second protrusion 47. Similarly to the first embodiment, the gate insulating film 44 is formed as a laminate of an oxide film, a nitride film, and an oxide film in order from the substrate side above the semiconductor substrate 41, and the material and film thickness thereof are also the first. This is the same as the gate insulating film 24 of the embodiment.

  As shown in FIG. 32, the gate electrode 45 is formed to extend in the y-axis direction above the inclined surface near the ridge line 43 c of the first protrusion 43. Adjacent gate electrodes are separated by a valley portion formed by an inclined surface as in the second embodiment.

  Next, the manufacturing process of the semiconductor device 40 according to this embodiment will be described. First, steps required until a structure shown in FIG. 27 is formed will be described. A p-type well is formed on the upper surface of the silicon substrate with the silicon (100) surface exposed on the upper surface, and this is used as a semiconductor substrate 41. Thereafter, for example, a silicon oxide film or a silicon nitride film is formed on the surface of the semiconductor substrate 41, and subsequently extends in the <011> direction (x-axis direction in the drawing) by photolithography, anisotropic ion etching, or the like. A striped first mask 48a is formed. Next, for example, a silicon oxide film, a silicon nitride film, or a resist film is uniformly formed on the semiconductor substrate 41 on which the first mask 48a is formed, followed by photolithography and anisotropic ion etching. A stripe-shaped second mask (not shown) extending in the <0-11> direction (y-axis direction in the drawing) is formed by a method or the like. Then, the semiconductor substrate 41 is etched in the vertical direction by anisotropic ion etching using the first mask 48a and the second mask as a mask. Thereafter, the structure shown in FIG. 27 is obtained by selectively removing the second mask.

  Next, steps required until a structure shown in FIG. 27, anisotropic etching is performed on the semiconductor substrate 41 using an anisotropic etching agent such as a KOH aqueous solution or TMAH using the first mask 48a as a mask. Thereby, as shown in FIG. 28, the surface structure which consists of a silicon | silicone (111) surface is formed. Since no mask is formed on the first convex portion 46a, the (100) surface of the upper surface of the first convex portion 46a disappears by etching, and no constriction is formed on the first projecting portion 43. . On the other hand, since the upper surface of the second convex portion 46 b is covered with the mask 48, the etching of the (100) surface does not proceed and remains as the flat portion 47 f of the second protrusion 47. On the side of the second protrusion 47, two (111) planes appear as the etching progresses, and a constricted portion is formed as shown in FIG. By the above processing, a structure as shown in FIG. 28 is formed.

  Next, steps required until a structure shown in FIGS. 29 and 30 is formed will be described. A third mask 48b is uniformly formed on the structure shown in FIG. 28 to obtain the structure shown in FIG. For the third mask 48b, for example, a silicon oxide film or a silicon nitride film by a CVD method can be used. Next, the upper portion of the third mask 48 b is removed by an etch back method or a CMP method, and the first mask 48 a is exposed above the semiconductor substrate 41. Thereafter, the first mask 48a is selectively removed to expose the flat portion 47f of the second protrusion 47. An impurity region is implanted into the flat portion 47f by ion implantation to form an n-type semiconductor diffusion region 42. The structure shown in FIG. 30 is completed through the above steps.

  Next, steps required until a structure shown in FIGS. 31 and 32 is formed will be described. The third mask 48b is removed from the semiconductor substrate 41 on which the diffusion region 42 is formed. After that, an oxide film (for example, a tunnel film made of silicon oxide), a nitride film (for example, a trap film made of silicon nitride film), an oxide film (for example, a silicon oxide film) is formed by a thermal oxidation method or a CVD method. 31 is formed, and the structure shown in FIG. 31 is completed.

  Next, a silicon polycrystalline film is uniformly formed over the semiconductor substrate 41, and impurities are implanted by ion implantation to form n-type polycrystalline silicon. This n-type polycrystalline silicon is etched by a photolithographic method and an anisotropic ion etching method, and is removed leaving the upper surfaces of the inclined surfaces 43 a and 43 b in the vicinity of the ridge line 43 c of the first protrusion 43. Thereby, the gate electrode 45 is formed, and the structure shown in FIG. 32 is completed. Thereafter, although not particularly shown, an interlayer insulating film, a contact, a wiring layer, and the like are formed to complete the semiconductor device 40 according to the present embodiment.

  The equivalent circuit and operation of the semiconductor device 40 of this embodiment are the same as those of the semiconductor device according to the first embodiment.

  As described above, according to the semiconductor device 40 of the third embodiment, the first protrusion 43 having the inclined surfaces 43a and 43b is formed, and the gate electrode 45 is formed above the inclined surface in the vicinity of the ridge line 43c. Therefore, the channel width is widened and current driving capability can be improved as compared with the conventional planar type transistor. Moreover, since the channels of the inclined surfaces are controlled by the gate electrodes not only from above but also from the sides, the short channel effect is suppressed.

  Furthermore, the flat part 47f is formed in the upper part of the semiconductor substrate 41, and the 2nd protrusion part 47 arrange | positioned in the direction orthogonal to the 1st protrusion part 43 is provided while extending linearly. Since the diffusion region 42 is formed in the upper part of the second protrusion 47 near the flat portion 47f, the diffusion region 42 is formed in a straight line. In the semiconductor device 40, since the diffusion region 42 serves as the source and drain wirings, the length in the current transport direction is shorter than the diffusion region 22 of the first embodiment bent in the vertical direction shown in FIG. Therefore, in the semiconductor device 40 of this embodiment, an increase in electrical resistance in the source and drain wirings is suppressed as compared with the semiconductor device according to the first embodiment.

  Further, in the semiconductor device 40 of the present embodiment, a flat portion is formed on the upper portion of the second protrusion 47 and a constricted portion is formed on the side thereof. As a result, the effective channel length is increased, and the short channel effect is suppressed.

(Fourth embodiment)
Hereinafter, the fourth embodiment of the present invention will be described with reference to FIGS. 33 to 38. 34 to 37 are perspective views showing a state during the manufacture of the semiconductor device according to this embodiment. FIG. 38 is a perspective view showing a part of the semiconductor device of this embodiment. The cross section taken along the line KK ′ of FIG. 33 is the same as that of FIG.

  As shown in FIGS. 33 and 38, the semiconductor device 50 according to the fourth embodiment of the present invention is substantially the same as the semiconductor device 40 according to the third embodiment, but an insulating film is formed on a part of the surface of the semiconductor substrate 41. However, the difference is that a gate insulating film 44 and a gate electrode 45 are formed thereon. Hereinafter, the same components as those of the third embodiment are denoted by the same reference numerals, and description thereof is omitted.

On the upper surface of the semiconductor substrate 41 of the present embodiment, as in the third embodiment, a first protrusion 43 extending in the y-axis direction, and a second protrusion 47 extending in the x-axis direction and having a constricted portion Is provided.
In the illustrated example, the height of the ridge line 43 c of the first projecting portion 43 and the height of the flat portion 47 f on the upper portion of the second projecting portion 47 are formed substantially the same. In the present embodiment, the height relationship between the first protrusion 43 and the upper flat portion 47f of the second protrusion 47 is not limited to this, and the conditions for anisotropic etching using an aqueous KOH solution (for example, The etching amount in the silicon <111> direction is changed by adjusting the etching time), and the third mask 48b is used as an anisotropy for the semiconductor substrate 41 where the flat portion 47f above the second protrusion 47 is exposed. It can adjust suitably by methods, such as performing ion etching. A third mask 48 b is embedded in the constricted portion of the second protrusion 47. Further, a part of the valley formed by the inclined surfaces 43a, 43b, 47a, 47b constituting the upper surfaces of the first and second protrusions is also filled with the third mask 48b. As described above, in this embodiment, the surface of the semiconductor substrate 41 is formed except for a part near the ridge line 43c of the inclined surfaces 43a and 43b where the gate electrode 45 is formed and the flat portion 47f above the second protrusion 47. Covered by the third mask 48b, a gate insulating film 44 is formed on the third mask 48b.

  The gate insulating film 44 is formed so as to cover the top of the semiconductor substrate 41 and the third mask 48b. The gate insulating film 44 has a laminated structure in which an oxide film, a nitride film, and an oxide film are sequentially formed from below, and the material and manufacturing method thereof are the same as those of the gate insulating film 24 of the first embodiment (see FIG. 14). ). The gate electrode 45 is formed above the inclined surfaces 43a and 43b in the vicinity of the ridge line 43c of the first protrusion 43, that is, above the portion of the first protrusion 43 that is not covered with the third mask 48b. The

  Next, the manufacturing process of the semiconductor device 50 according to this embodiment will be described. The manufacturing process of the semiconductor device 50 is the same as in the third embodiment up to the point where the silicon substrate is ion-implanted to form the structure in which the diffusion region 42 shown in FIG. 30 is formed. Description of the process is omitted. First, steps required until a structure shown in FIG. 35 is formed will be described. The structure shown in FIG. 30 is formed by the same process as that of the third embodiment, and the fourth mask 48c is uniformly formed above the structure (FIG. 34). For the fourth mask 48c, for example, a silicon oxide film or a silicon nitride film by a CVD method can be used. Thereafter, the surface of the fourth mask 48c is processed by an etch-back method or a CMP method to remove the upper portion of the fourth mask 48c, and the third mask 48b is formed on the surface of the semiconductor substrate 41 as shown in FIG. Expose.

  Next, steps required until a structure shown in FIGS. 36 and 37 is formed will be described. The semiconductor substrate 41 from which the third mask 48b is exposed is subjected to anisotropic ion etching using the fourth mask 48c as a mask, and part of the inclined surfaces 43a and 43b in the vicinity of the ridge line 43c to be the channel of the transistor is formed. The structure shown in FIG. 36 is completed by exposing. Next, only the fourth mask 48c is selectively removed to expose the flat portion 47f of the second protrusion 47 on the surface. Subsequently, a gate insulating film 44 is formed by stacking a tunnel film, a trap film, and a top film on the upper surface of the semiconductor substrate 41. The structure shown in FIG. 37 is completed through the above steps.

  Next, steps required until a structure shown in FIG. A polycrystalline silicon film (not shown) is formed on the structure shown in FIG. 37 by CVD or the like, and n-type polycrystalline silicon is formed by ion implantation or the like. Thereafter, the n-type polycrystalline silicon film is removed by photolithography, anisotropic ion etching, etc., except for the portion to be the gate electrode 45. Thereby, as shown in FIG. 38, the gate electrode 45 extending in the direction of the first ridge line 43 c is formed above the semiconductor substrate 41. Thereafter, although not particularly illustrated, an interlayer insulating film, a contact, a wiring layer and the like are appropriately formed to complete the semiconductor device 50 according to the present embodiment.

  The equivalent circuit and operation of the semiconductor device 50 are the same as those of the semiconductor device 20 of the first embodiment, and the description thereof is omitted.

  As described above, according to the semiconductor device 50 of the fourth embodiment, the first protrusion 43 having the inclined surfaces 43a and 43b is formed, and the gate electrode 45 is formed above the inclined surface near the ridge line 43c. Therefore, the channel width is widened and current driving capability can be improved as compared with the conventional planar type transistor. Moreover, since the channels of the inclined surfaces are controlled by the gate electrodes not only from above but also from the sides, the short channel effect is suppressed.

  Furthermore, the flat part 47f is formed in the upper part of the semiconductor substrate 41, and the 2nd protrusion part 47 arrange | positioned in the direction orthogonal to the 1st protrusion part 43 is provided while extending linearly. Since the diffusion region 42 is formed in the upper part of the second protrusion 47 near the flat portion 47f, the diffusion region 42 is formed in a straight line. In the semiconductor device 50, since the diffusion region 42 also serves as a source and drain wiring, the length in the current transport direction is shorter than the diffusion region 22 of the first embodiment bent in the vertical direction shown in FIG. Therefore, in the semiconductor device 50 of this embodiment, an increase in electrical resistance in the source and drain wiring is suppressed as compared with the semiconductor device according to the first embodiment.

  Further, in the semiconductor device 50 of the present embodiment, a flat portion is formed on the upper portion of the second protrusion 47 and a constricted portion is formed on the side thereof. As a result, the effective channel length is increased, and the short channel effect is suppressed.

  At the same time, in the semiconductor device 50 of the present embodiment, the third mask 48 b is embedded in the constricted portion of the second protrusion 47. Thereby, there is an effect that the capacitance at the constricted portion between the gate electrode 45 and the diffusion region 42 is reduced.

  Further, in the semiconductor device 50 of the present embodiment, after the first protrusion 43 is filled with the third mask 48b, a part of the inclined surfaces 43a and 43b in the vicinity of the ridge line 43c to be the channel of the transistor is etched. Expose. Here, if the exposure width is made smaller than the gate width, the channel width is not the accuracy of the alignment / exposure width / etching width of the gate electrode 45 and the first protrusion 43, but is embedded in the third mask 48b. This can be realized with the accuracy of the etching depth. Note that the embedding of the protrusion and exposure by etching can be applied as appropriate after the protrusion is formed in the first and second embodiments.

(Other embodiments)
In each of the embodiments described above, the semiconductor substrate has been described based on the example in which the silicon (100) surface constitutes the surface. However, instead of the semiconductor substrate, the semiconductor substrate can be formed of the silicon (011) surface. . In this case, the upper surface of the convex portion and the concave portion before anisotropic etching is a (110) plane, and the side surface is a lattice-shaped convex portion having a (001) plane and a (1-10) plane. A similar structure is obtained. In the semiconductor substrate having this convex portion, the ridgeline of the first protrusion and the channel length direction of the transistor may be formed in the <−110> direction or a <001> direction that is 90 ° different from the <−110> direction.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

  (Supplementary Note 1) A semiconductor substrate and a first cross-section perpendicular to the longitudinal direction, which is formed on the upper surface of the semiconductor substrate, extends in a predetermined direction, and is parallel to each other at a predetermined interval. And an impurity region formed on the upper surface of the semiconductor substrate, extending in a direction perpendicular to the longitudinal direction of the first projecting portion and having a predetermined length in the longitudinal direction of the first projecting portion. A plurality of diffusion regions arranged in parallel to each other at intervals, a gate insulating film formed on the semiconductor substrate, and a ridgeline of the first protrusion on the gate insulating film A semiconductor device comprising: a gate electrode formed to extend above a part of two inclined surfaces and linearly extending in a longitudinal direction of the first projecting portion.

  (Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the diffusion region extends linearly.

  (Additional remark 3) Furthermore, it is formed on the upper surface of the semiconductor substrate, extends in a direction orthogonal to the longitudinal direction of the first protrusion, and is arranged in parallel with each other at a predetermined interval. The semiconductor device according to appendix 1, wherein the diffusion region is formed above the second protrusion.

  (Supplementary note 4) The semiconductor device according to supplementary note 3, wherein the second protrusion has a triangular cross section in a plane perpendicular to the longitudinal direction thereof.

  (Additional remark 5) The said 2nd protrusion part has a flat part in the upper part, and the constriction part is formed in the side part, The semiconductor device of Additional remark 3 characterized by the above-mentioned.

  (Additional remark 6) The semiconductor device of Additional remark 5 characterized by the insulating material being embedded between the constriction part of the said 2nd protrusion part, and the said gate insulating film.

  (Supplementary note 7) The supplementary note 1 is characterized in that the gate insulating film has a three-layer structure of a tunnel film made of oxide, a trap film made of nitride, and a top film made of oxide in order from the semiconductor substrate side. The semiconductor device described.

  (Additional remark 8) The said gate electrode is isolate | separated from the adjacent gate electrode by the trough-shaped part formed of the inclined surface of the adjacent said 1st protrusion part, The semiconductor of Additional remark 1 characterized by the above-mentioned. apparatus.

  (Supplementary note 9) The semiconductor device according to supplementary note 8, wherein an insulating material is embedded in a valley-like portion formed by adjacent inclined surfaces of the adjacent first protrusions.

  (Supplementary note 10) The semiconductor device according to supplementary note 1, wherein the semiconductor substrate is a silicon single crystal substrate.

  (Additional remark 11) The semiconductor device of Additional remark 10 characterized by the upper surface of the said semiconductor substrate being a surface parallel to a silicon | silicone (100) surface.

  (Additional remark 12) The said 1st protrusion part is extended | stretched and formed in either the <0-11> direction or the <011> direction on the said semiconductor substrate, The semiconductor device of Additional remark 11 characterized by the above-mentioned. .

  (Additional remark 13) The semiconductor device of Additional remark 10 characterized by the upper surface of the said semiconductor substrate being a surface parallel to a silicon | silicone (110) surface.

  (Supplementary note 14) The semiconductor device according to supplementary note 13, wherein the first protrusion is formed in a <001> direction or a <1-10> direction on the semiconductor substrate.

  (Supplementary Note 15) The semiconductor device according to any one of Supplementary Notes 10 to 14, wherein an upper surface of the first protrusion is formed of a silicon (111) surface.

  (Supplementary Note 16) Forming a plurality of first convex portions formed on a surface of a semiconductor substrate in parallel with a predetermined direction and having a flat upper surface, and the first convex portions are formed. A plurality of first protrusions formed by anisotropically etching the surface of the semiconductor substrate, extending in the longitudinal direction of the first convex portion, and having an upper surface formed by two inclined surfaces. Forming a gate insulating film on the semiconductor substrate on which the first protrusion is formed; implanting impurities into the semiconductor substrate on which the first protrusion is formed; Forming a plurality of diffusion regions extending in parallel along the surface of the first protrusion in a direction perpendicular to the longitudinal direction of the first protrusion, and straddling the ridgeline of the first protrusion. Extending over part of the two inclined surfaces, and the length of the first protrusion The method of manufacturing a semiconductor device, characterized in that it comprises a step of forming a gate electrode extending linearly in direction.

  (Supplementary note 17) A plurality of first convex portions extending in a predetermined direction on a top surface of a semiconductor substrate and having a flat upper surface, and extending in a direction perpendicular to the first convex portion, the upper portion being flat. Forming a plurality of second convex portions having one surface, and anisotropically etching the upper surface of the semiconductor substrate having the first and second convex portions, A plurality of first protrusions extending in the longitudinal direction of the first convex portion, the upper surface comprising two inclined surfaces, the ridge line of which extends in the longitudinal direction of the first convex portion, and the first A plurality of second protrusions extending in a direction perpendicular to the longitudinal direction of the convex portion, the upper surface being formed of two inclined surfaces, and the ridge line extending in a direction perpendicular to the longitudinal direction of the first convex portion; Forming a gate on the semiconductor substrate on which the first and second protrusions are formed. A step of forming an insulating film, a step of implanting impurities into a part near the ridgeline of the inclined surface forming the upper surface of the second protrusion, and forming a diffusion region; and an upper surface of the first protrusion And a step of forming a gate electrode that extends upward in the vicinity of the ridgeline of the inclined surface to be formed and linearly extends in the longitudinal direction of the first protrusion.

  (Supplementary Note 18) A plurality of first convex portions extending in a predetermined direction on a top surface of a semiconductor substrate and having a flat upper surface, and extending in a direction perpendicular to the first convex portion, and the upper portion is flat. A step of forming a plurality of second convex portions comprising one surface, a step of forming a mask on the upper surface of the second convex portion, and a second in which the first convex portions and the mask are formed. The upper surface of the semiconductor substrate having the convex portion is anisotropically etched to extend intermittently in the longitudinal direction of the first convex portion, the upper surface is composed of two inclined surfaces, and the ridge line is the first edge A plurality of first protrusions extending in the longitudinal direction of the convex portion, and a side portion extending linearly in a direction perpendicular to the first convex portion and having a flat upper portion and extending in the longitudinal direction. Forming a plurality of second projecting portions having a constricted portion; and an upper flat surface of the second projecting portion. A step of implanting impurities into one surface to form a diffusion region, a step of forming a gate insulating film on the semiconductor substrate on which the first and second protrusions are formed, and a step of forming the first protrusions And a step of forming a gate electrode extending above a part of the vicinity of the ridge line of the two inclined surfaces forming the upper surface and extending linearly in the longitudinal direction of the first protrusion. Device manufacturing method.

  (Supplementary Note 19) A plurality of first convex portions extending in a predetermined direction on a top surface of a semiconductor substrate and having a flat upper surface, and extending in a direction perpendicular to the first convex portion, and the upper portion being flat. Forming a plurality of second convex portions comprising one surface, forming a first mask on an upper surface of the second convex portion, the first convex portions, and the first convex portions. The surface of the semiconductor substrate having the second convex portion on which the mask is formed is anisotropically etched to intermittently extend in the longitudinal direction of the first convex portion, and the upper surface is composed of two inclined surfaces. The ridge line extends linearly in a direction perpendicular to the first projecting portion, the first projecting portion extending in the longitudinal direction of the first projecting portion, and the upper portion is formed of a flat flat surface in the longitudinal direction. Forming a plurality of second protrusions having constricted portions on the extending side portions; and A step of embedding an insulator in a valley portion formed by the constricted portion and the inclined surface of the first and second protrusions, and injecting and diffusing impurities into a flat surface on the upper portion of the second protrusion; Forming a region, exposing a portion near the ridgeline of the inclined surface of the first projecting portion and a flat surface on the upper portion of the second projecting portion, and then exposing the gate insulating film above the semiconductor substrate And extending above the portion of the first protrusion protruding from the insulator and extending linearly in the ridge line direction of the first protrusion. And a step of forming a gate electrode.

FIG. 1 is a perspective view showing an example of a nonvolatile semiconductor memory device using a conventional fin-type FET. FIG. 2 is a perspective view showing the structure of a TwinMONOS (registered trademark) type transistor array. FIG. 3 is a top view showing the TwinMONOS type transistor array shown in FIG. FIG. 4 is a perspective view showing the structure of a mirror bit (registered trademark) type transistor array. FIG. 5 is a diagram showing a cross section of the structure of a mirror bit type transistor array. FIG. 6 is a diagram illustrating a problem that occurs when a transistor is a fin type in a mirror bit structure. FIG. 7 is a top view showing the semiconductor device according to the first embodiment of the present invention. FIG. 8 is a perspective view showing a state in the process of manufacturing the semiconductor device according to the first embodiment of the present invention, and is a perspective view showing a state immediately after forming the first convex portion on the upper surface of the semiconductor substrate. FIG. 9 is a view showing a state in the process of manufacturing the semiconductor device according to the first embodiment of the present invention, and is a perspective view showing a state immediately after the anisotropic etching process is finished. FIG. 10 is a view showing a state in the process of manufacturing the semiconductor device according to the first embodiment of the present invention, and is a perspective view showing a state immediately after the gate insulating film is formed. FIG. 11 is a view showing a state in the process of manufacturing the semiconductor device according to the first embodiment of the present invention, and is a perspective view showing a state immediately after the diffusion region is formed. FIG. 12 is a view showing a state in the process of manufacturing the semiconductor device according to the first embodiment of the present invention, and is a perspective view showing a state immediately after the polycrystalline silicon film is formed above the semiconductor substrate. FIG. 13 is a perspective view showing the semiconductor device according to the first embodiment of the present invention. FIG. 14 is a cross-sectional view taken along the line E-E ′ of FIG. 7, showing a cross section of the semiconductor device according to the first embodiment. FIG. 15 is a cross-sectional view taken along the line CC ′ of FIG. 7, showing a cross section of the semiconductor device according to the first embodiment. FIG. 16 is a cross-sectional view taken along the line DD ′ of FIG. 7, showing a cross section of the semiconductor device according to the first embodiment. FIG. 17 is a diagram showing an equivalent circuit of the semiconductor device according to the embodiment of the present invention. FIG. 18A is a diagram showing a cross section of the gate electrode of the semiconductor device according to the embodiment of the present invention cut in the channel width direction, and FIG. 18B is a diagram showing the channel width of the gate electrode of the semiconductor device of the comparative example. It is a figure which shows the cross section cut | disconnected in the direction. FIG. 19 is a top view showing a semiconductor device according to the second embodiment of the present invention. FIG. 20 is a view showing a state during the manufacture of the semiconductor device according to the second embodiment of the present invention, and is a perspective view showing a state immediately after the first and second convex portions are formed on the surface. FIG. 21 is a view showing a state in the process of manufacturing the semiconductor device according to the second embodiment of the present invention, and is a perspective view showing a state immediately after forming an inclined surface on the surface by anisotropic etching. FIG. 22 is a view showing a state in the process of manufacturing the semiconductor device according to the second embodiment of the present invention, and is a perspective view showing a state immediately after forming the diffusion region. FIG. 23 is a perspective view showing a semiconductor device according to the second embodiment of the present invention. FIG. 24 is a cross-sectional view taken along line FF ′ of FIG. 19, showing a cross section of the semiconductor device according to the second embodiment. FIG. 25 is a cross-sectional view taken along the line HH ′ of FIG. 19, showing a cross section of the semiconductor device according to the second embodiment. FIG. 26 is a top view showing a semiconductor device according to the third embodiment of the present invention. FIG. 27 is a view showing a state in the process of manufacturing the semiconductor device according to the third embodiment of the present invention, and is a perspective view showing a state immediately after forming the first mask on the second convex portion. is there. FIG. 28 is a view showing a state in the process of manufacturing the semiconductor device according to the third embodiment of the present invention, and is a perspective view showing a state immediately after the inclined surface is formed by anisotropic etching. FIG. 29 is a view showing a state in the process of manufacturing the semiconductor device according to the third embodiment of the present invention, and is a perspective view showing a state immediately after forming the second mask on the surface. FIG. 30 is a view showing a state in the middle of manufacturing the semiconductor device according to the third embodiment of the present invention, and is a perspective view showing a state immediately after the diffusion region is formed. FIG. 31 is a view showing a state during the manufacture of the semiconductor device according to the third embodiment of the present invention, and is a perspective view showing a state immediately after the gate insulating film is formed. FIG. 32 is a perspective view showing a semiconductor device according to the third embodiment of the present invention. FIG. 33 is a top view showing a semiconductor device according to the fourth embodiment of the present invention. FIG. 34 is a view showing a state in the process of manufacturing the semiconductor device according to the fourth embodiment of the present invention, and is a view showing a state immediately after the first mask is formed after forming the diffusion region. FIG. 35 is a diagram showing a state in the process of manufacturing the semiconductor device according to the fourth embodiment of the present invention, and is a diagram showing a state immediately after the surface of the second mask is exposed by the planarization process. FIG. 36 is a view showing a state in the process of manufacturing the semiconductor device according to the fourth embodiment of the present invention, and is a perspective view showing a state immediately after etching the second mask. FIG. 37 is a view showing a state in the process of manufacturing the semiconductor device according to the fourth embodiment of the present invention, and is a perspective view showing a state immediately after forming the gate insulating film. FIG. 38 is a perspective view showing a semiconductor device according to the fourth embodiment of the present invention.

Explanation of symbols

  21, 31, 41, 101, 201, 301, 311 ... semiconductor substrate, 22, 32, 42, 102, 202, 302 ... diffusion region, 23, 33, 43 ... first protrusion, 37, 47 ... second 23a, 33a, 43a ... first slope, 23b, 33b, 43b ... second slope, 37a, 47a ... third slope, 37b, 47b ... fourth slope, 23c, 33c, 43c ... first ridge line, 37c ... second ridge line, 47f ... flat part, 24, 34, 44, 104, 204, 304 ... gate insulating film, 25, 35, 45, 105, 205, 305 ... gate Electrode, 26a, 36a, 46a ... first convex portion, 36b, 46b ... second convex portion, 28, 38 ... mask, 48a ... first mask, 48b ... third mask, 48c ... fourth mask of.

Claims (5)

A semiconductor substrate;
A first protrusion having a triangular cross section perpendicular to the longitudinal direction, formed on the upper surface of the semiconductor substrate, extending in a predetermined direction and arranged in parallel with each other at a predetermined interval;
An impurity region formed on the upper surface of the semiconductor substrate, extending in a direction perpendicular to the longitudinal direction of the first protrusion, and spaced from each other at a predetermined interval in the longitudinal direction of the first protrusion. A plurality of diffusion regions arranged in parallel with
A gate insulating film formed on the semiconductor substrate;
It is formed on the gate insulating film so as to extend above a part of two inclined surfaces straddling the ridge line of the first protrusion, and linearly extends in the longitudinal direction of the first protrusion. A semiconductor device comprising: a gate electrode formed in the same manner.   The semiconductor device according to claim 1, wherein the diffusion region extends linearly.   Furthermore, a plurality of second protrusions formed on the upper surface of the semiconductor substrate, extending in a direction perpendicular to the longitudinal direction of the first protrusions, and arranged in parallel to each other at a predetermined interval are provided. The semiconductor device according to claim 1, wherein the diffusion region is formed on an upper portion of the second protrusion.   2. The semiconductor according to claim 1, wherein the gate insulating film has a three-layer structure of a tunnel film made of an oxide, a trap film made of a nitride, and a top film made of an oxide in order from the semiconductor substrate side. apparatus.   2. The semiconductor device according to claim 1, wherein the gate electrode is separated from an adjacent gate electrode by a valley-shaped portion formed by an inclined surface of the adjacent first projecting portion.

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