US20130264585A1 - Semiconductor device with stress-providing structure - Google Patents

Semiconductor device with stress-providing structure Download PDF

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Publication number
US20130264585A1
US20130264585A1 US13/907,980 US201313907980A US2013264585A1 US 20130264585 A1 US20130264585 A1 US 20130264585A1 US 201313907980 A US201313907980 A US 201313907980A US 2013264585 A1 US2013264585 A1 US 2013264585A1
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United States
Prior art keywords
recess
stress
semiconductor device
substrate
channel structure
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Abandoned
Application number
US13/907,980
Inventor
Chin-I Liao
Ching-Hong Jiang
Ching-I Li
Shu-Yen Chan
Chin-Cheng Chien
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US13/907,980 priority Critical patent/US20130264585A1/en
Assigned to UNITED MICROELECTRONICS CORPORAITON reassignment UNITED MICROELECTRONICS CORPORAITON ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHAN, SHU-YEN, CHIEN, CHIN-CHENG, LI, CHING-I, LIAO, CHIN-I, JIANG, CHING-HONG
Publication of US20130264585A1 publication Critical patent/US20130264585A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device with a stress-providing structure.
  • CMOS complementary metal-oxide-semiconductor
  • SAE selective area epitaxial
  • the object of the present invention is to provide a semiconductor device.
  • the semiconductor device includes a substrate, a recess and a stress-providing structure.
  • a channel structure is formed in the substrate.
  • the recess is formed in the substrate and arranged beside the channel structure.
  • the recess has a round inner surface.
  • the stress-providing structure is formed within the recess.
  • the stress-providing structure has a round outer surface.
  • the semiconductor device further includes a gate structure, which is formed over the channel structure.
  • the recess has a depth from 550 to 700 angstroms, and preferably from 600 to 650 angstroms.
  • the substrate is a silicon substrate.
  • the channel structure is a p-type channel structure
  • the stress-providing structure is made of silicon germanium (SiGe) or germanium.
  • the channel structure is an n-type channel structure
  • the stress-providing structure is made of silicon carbide (SiC).
  • FIGS. 1A ⁇ 1E schematically illustrate a process for fabricating a stress-providing structure according to an embodiment of the present invention.
  • FIGS. 1A ⁇ 1E schematically illustrate a process for fabricating a stress-providing structure according to an embodiment of the present invention.
  • the process for fabricating the stress-providing structure may be applied to the fabrication of a semiconductor device such as a complementary metal-oxide-semiconductor (CMOS) transistor.
  • CMOS complementary metal-oxide-semiconductor
  • a substrate 1 is provided.
  • An example of the substrate 1 includes but is not limited to a silicon substrate.
  • a channel structure 10 is formed in the substrate 1
  • a gate structure 11 is formed over the channel structure 10 .
  • the gate structure 11 comprises a gate insulator layer 110 and a gate conductor layer 111 .
  • a silicon nitride layer 12 is formed over the substrate 20 by chemical vapor deposition under a halogen-containing environment.
  • the chemical vapor deposition is performed under a chlorine-containing environment.
  • the chlorine-containing environment includes a chlorine-containing species such as hexachlorodisilane (Si 2 Cl 6 , also referred as HCD) or dichlorosilane (SiH 2 Cl 2 , also referred as DCS).
  • the silicon nitride layer 12 is chlorine-rich.
  • a series of photolithography and etching processes are performed to partially remove the silicon nitride layer 12 so as to partially expose the surface of the substrate 1 beside the channel structure 10 .
  • an etching process is performed to remove the exposed surface of the substrate 1 to produce a recess 13 .
  • the depth of the recess 13 is from 550 angstroms to 700 angstroms, and preferably from 600 angstroms to 650 angstroms.
  • the recess has a sigma-shaped inner surface 130 .
  • the profile of the sigma-shaped inner surface 130 is similar to the profile of the sidewall of the conventional embedded source/drain structure.
  • the substrate 1 with the recess 13 is subjected to a thermal treatment process.
  • the thermal treatment process is performed by baking the substrate 1 under a hydrogen gas atmosphere at a temperature between 750° C. and 820° C. for a time period from 10 seconds to 10000 seconds.
  • the halogen-rich atoms e.g. chlorine-rich atoms
  • the elevated temperature of between 750° C. and 820° C.
  • the depth of the recess 20 is from 550 angstroms to 700 angstroms, and preferably from 600 angstroms to 650angstroms.
  • the stress-providing material is filled into the recess 20 to form a stress-providing structure 21 within the recess 20 .
  • the stress-providing structure 21 has a round outer surface.
  • the stress-providing material is silicon germanium (SiGe) or germanium (Ge).
  • the stress-providing material is silicon carbide (SiC).
  • the process for manufacturing a stress-providing structure according to the present invention may be applied to the fabrication of a semiconductor device.
  • the inner surface of the recess 20 has enhanced cleanliness, and is chlorine-free.
  • the round inner surface of the recess 20 is beneficial for providing increased channel stress.
  • the round inner surface of the recess produced by embodiment of present invention may provide better channel mobility than the conventional sigma-shaped inner surface.

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, a recess and a stress-providing structure. A channel structure is formed in the substrate. The recess is formed in the substrate and arranged beside the channel structure. The recess has a round inner surface. The stress-providing structure is formed within the recess. Corresponding to the profile of the round inner surface of the recess, the stress-providing structure has a round outer surface.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • The present application is a divisional application claiming benefit from a parent U.S. patent application bearing a Ser. No. 13/110,294 and filed May 18, 2011, entire contents of which are incorporated herein by reference.
    • FIELD OF THE INVENTION
  • The present invention relates to a semiconductor device, and more particularly to a semiconductor device with a stress-providing structure.
    • BACKGROUND OF THE INVENTION
  • Generally, in the fabrication of a complementary metal-oxide-semiconductor (CMOS) transistor, a selective area epitaxial (SAE) (growth) process is widely used to form source/drain regions. By using the selective area epitaxial process to provide stress, the channel mobility of the transistor is improved and the performance of the transistor is enhanced.
  • However, the efficacy of using the conventional selective area epitaxial process to increase the performance of the transistor is still unsatisfactory.
    • SUMMARY OF THE INVENTION
  • Therefore, the object of the present invention is to provide a semiconductor device. The semiconductor device includes a substrate, a recess and a stress-providing structure. A channel structure is formed in the substrate. The recess is formed in the substrate and arranged beside the channel structure. The recess has a round inner surface. The stress-providing structure is formed within the recess. Corresponding to the round inner surface, the stress-providing structure has a round outer surface.
  • In an embodiment, the semiconductor device further includes a gate structure, which is formed over the channel structure.
  • In an embodiment, the recess has a depth from 550 to 700 angstroms, and preferably from 600 to 650 angstroms.
  • In an embodiment, the substrate is a silicon substrate.
  • In an embodiment, the channel structure is a p-type channel structure, and the stress-providing structure is made of silicon germanium (SiGe) or germanium.
  • In an embodiment, the channel structure is an n-type channel structure, and the stress-providing structure is made of silicon carbide (SiC).
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
  • FIGS. 1A˜1E schematically illustrate a process for fabricating a stress-providing structure according to an embodiment of the present invention.
    •  DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
  • FIGS. 1A˜1E schematically illustrate a process for fabricating a stress-providing structure according to an embodiment of the present invention. The process for fabricating the stress-providing structure may be applied to the fabrication of a semiconductor device such as a complementary metal-oxide-semiconductor (CMOS) transistor.
  • Firstly, as shown in FIG. 1A, a substrate 1 is provided. An example of the substrate 1 includes but is not limited to a silicon substrate. In addition, a channel structure 10 is formed in the substrate 1, and a gate structure 11 is formed over the channel structure 10. In this embodiment, the gate structure 11 comprises a gate insulator layer 110 and a gate conductor layer 111.
  • Then, as shown in FIG. 1B, a silicon nitride layer 12 is formed over the substrate 20 by chemical vapor deposition under a halogen-containing environment. In one embodiment, the chemical vapor deposition is performed under a chlorine-containing environment. The chlorine-containing environment includes a chlorine-containing species such as hexachlorodisilane (Si2Cl6, also referred as HCD) or dichlorosilane (SiH2Cl2, also referred as DCS). In such one embodiment, the silicon nitride layer 12 is chlorine-rich.
  • Then, as shown in FIG. 1C, a series of photolithography and etching processes are performed to partially remove the silicon nitride layer 12 so as to partially expose the surface of the substrate 1 beside the channel structure 10. Then, an etching process is performed to remove the exposed surface of the substrate 1 to produce a recess 13. The depth of the recess 13 is from 550 angstroms to 700 angstroms, and preferably from 600 angstroms to 650 angstroms. As shown in FIG. 1C, the recess has a sigma-shaped inner surface 130. The profile of the sigma-shaped inner surface 130 is similar to the profile of the sidewall of the conventional embedded source/drain structure. By utilizing the lattice property of the silicon substrate and performing dry/wet etching processes, the sigma-shaped inner surface 130 will be produced.
  • Then, the substrate 1 with the recess 13 is subjected to a thermal treatment process. For example, the thermal treatment process is performed by baking the substrate 1 under a hydrogen gas atmosphere at a temperature between 750° C. and 820° C. for a time period from 10 seconds to 10000 seconds. Prior to the thermal treatment process, the halogen-rich atoms (e.g. chlorine-rich atoms) of the silicon nitride layer 12 are released to the inner surface of the recess 13, and the halogen-rich atoms and the silicon atoms interact with each other at the inner surface of the recess 13. Moreover, during the thermal treatment process is performed, the elevated temperature of between 750° C. and 820° C. causes migration and recombination of the silicon atoms at the inner wall of the recess 13. Consequently, a recess 20 with a round inner surface is produced (see FIG. 1D). The depth of the recess 20 is from 550 angstroms to 700 angstroms, and preferably from 600 angstroms to 650angstroms.
  • Then, a stress-providing material is filled into the recess 20 to form a stress-providing structure 21 within the recess 20. Corresponding to the round inner surface of the recess 20, the stress-providing structure 21 has a round outer surface. In a case that the channel structure 10 is a p-type channel structure, the stress-providing material is silicon germanium (SiGe) or germanium (Ge). Whereas, in a case that the channel structure 10 is an n-type channel structure, the stress-providing material is silicon carbide (SiC).
  • From the above description, the process for manufacturing a stress-providing structure according to the present invention may be applied to the fabrication of a semiconductor device. The inner surface of the recess 20 has enhanced cleanliness, and is chlorine-free. Moreover, the round inner surface of the recess 20 is beneficial for providing increased channel stress. Experiments demonstrate that under side-by-side comparison by maintaining the stress-providing material to be unchanged or constant, the round inner surface of the recess produced by embodiment of present invention may provide better channel mobility than the conventional sigma-shaped inner surface.
  • While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.

Claims (6)

What is claimed is:
1. A semiconductor device, comprising:
a substrate with a channel structure; and
a stress-providing structure formed within a recess, wherein the recess was formed in the substrate and arranged beside the channel structure, wherein the recess has a round inner surface, the stress-providing structure is filling the recess and has a round outer surface corresponding to the round inner surface of the recess.
2. The semiconductor device according to claim 1, wherein the semiconductor device further comprises a gate structure, which is formed over the channel structure.
3. The semiconductor device according to claim 1, wherein the recess has a depth from 600 angstroms to 650 angstroms.
4. The semiconductor device according to claim 1, wherein the substrate is a silicon substrate.
5. The semiconductor device according to claim 1, wherein the channel structure is a p-type channel structure, and the stress-providing structure is made of silicon germanium (SiGe) or germanium.
6. The semiconductor device according to claim 1, wherein the channel structure is an n-type channel structure, and the stress-providing structure is made of silicon carbide (SiC).
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