US20130223259A1 - Simultaneous data packet processing - Google Patents
Simultaneous data packet processing Download PDFInfo
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- US20130223259A1 US20130223259A1 US13/856,536 US201313856536A US2013223259A1 US 20130223259 A1 US20130223259 A1 US 20130223259A1 US 201313856536 A US201313856536 A US 201313856536A US 2013223259 A1 US2013223259 A1 US 2013223259A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W24/00—Supervisory, monitoring or testing arrangements
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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Abstract
A packet controller for simultaneous processing of data packets transmitted via a plurality of communication channels includes a plurality of inputs to receive a respective plurality of signals, such that each of the plurality of signals is indicative of a presence of a data packet on a respective one of the plurality of communication channels, a clock source to supply a periodic clock signal, a plurality of independent processing modules coupled to the respective plurality of inputs to simultaneously process the plurality of signals, such that each of the plurality of independent processing modules implements a respective state machine driven by the periodic clock signal to process the respective signal independently of every other one of the plurality of processing modules, and an output to transmit an output signal indicative of a presence of at least one data packet on one or more of the plurality of communication channels.
Description
- This application is a divisional of U.S. patent application Ser. No. 12/490,205, entitled “Simultaneous Data Packet Processing,” filed on Jun. 23, 2009 (Attorney Docket No. 31244/43714), and based on and claiming the benefit of priority to U.S. Provisional Application No. 61/074,954, entitled “Wireless Communication Network Analyzer” filed on Jun. 23, 2008 (Attorney Docket No. 31244/43714P), the entire disclosures of which are hereby expressly incorporated herein by reference.
- The present patent relates generally to wireless communications and, more particularly, to a device for capturing and analyzing data transmitted via multiple wireless communication channels.
- The WirelessHART communication protocol establishes a wireless communication standard for process applications. More particularly, WirelessHART is a secure, wireless mesh networking communication technology operating in the 2.4 GHz ISM radio band. WirelessHART utilizes IEEE STD 802.15.4-2006 2.4 GHz DSSS transceivers with channel hopping on a transaction by transaction basis. WirelessHART communication is arbitrated using time division multiple access (TDMA) to schedule link activity. All communications are performed within a designated slot and one or more sources and one or more destination devices may be scheduled to communicate in a given slot. Thus, a slot may be dedicated to communication from a single source device or a slot may support shared communication access between multiple devices. The message being propagated by the source device on a slot may be addressed to a specific device or may be broadcast to each of the destination devices assigned to the slot.
- To be successful, WirelessHART must support interoperability and allow compliant devices from different manufactures to be mixed in the same network to create an integrated system. The HART Communication Foundation (HCF) has always had a strict definition of interoperability. In particular, HCF defines “interoperability” as the ability for like devices from different manufacturers to work together in a system and be substituted one for another without loss of functionality at the host system level.
- To attain compliance, the HCF has developed a quality assurance program to ensure the compliance of WirelessHART products. The objective of the WirelessHART quality assurance program is to ensure product adherence to the high standards of interoperability and compatibility defined by the HCF.
- Using the network analyzer or radio capture tools available today, an operator may monitor an individual communication channel by tuning a network analyzer to the radio frequency associated with the channel and attempting to capture data packets transmitted via this communication channel. To monitor another communication channel, the operator needs to either adjust the frequency setting of the network analyzer being used, or use another network analyzer. Thus, to monitor multiple channels at the same time, the operator needs to set up and operate several network analyzers. In addition to the inconvenience, high cost, and stringent calibration requirements associated with using multiple network analyzers at the same time, the operator may also generate undesirable interference in the respective antennas of the network analyzers when placing these devices close to each other.
- A wireless communication network analyzer for use in, for example, an IEEE 802.11 or 802.15-compliant communication network, includes an acquisition engine to capture and process data packets or other data units transmitted on multiple wireless communication channels, and a user interface to display information related to the data packets and to support channel configuration and selection commands. In some embodiments, the wireless communication network is a WirelessHART network that operates in a process control environment and communicates on IEEE STD 802.15.4-2006 2.4 GHz channels. The acquisition engine includes a radio frequency (RF) interface that can capture communications on multiple radio channels simultaneously and a packet server to receive data packets and related statistics (e.g., Received Signal Level (RSL_, Link Quality Indicator (LQI), Cyclic Redundancy Check (CRC) status) from the RF interface, provide the data packets and the statistics to the local user interface and/or one or more client applications, and control data capture at the RF interface.
- The packet server and the user interface may run on a computer host that supports a standard operating system such as, for example, Linux, QNX, or Microsoft® Windows 2000, XP, or Vista. The RF interface may be implemented as a hardware component powered by the computer host via a USB connection interface such as USB 2.0. The same USB connection interface may also support communications between the packet server and the RF interface. In this manner, the acquisition engine may be manufactured using commercial, off-the-shelf hardware.
- In some embodiments, the communication network in which the network analyzer operates is compliant with the 2.4 GHz IEEE Standard 802.15.4-2006 (“the Standard”), and the acquisition engine can capture communications on all 16 channels specified by the Standard. The acquisition engine may capture information related to all layers of the protocol stack, i.e., from the preamble and header associated with the lowest physical (“PHY”) layer up to the complete payload of the application layer. In an embodiment, the communication network is a secure mesh WirelessHART network operating in a process control environment. In this embodiment, the network analyzer may perform conformance testing of WirelessHART products in addition to sniffing data packets for the purposes of supervising communications between devices.
- In some embodiments, the RF interface includes a single antenna receives a wireless signal that includes all communication channels on which the network analyzer operates, at least one splitter to generate multiple copies of the received signal, and several radio transceivers to process communications on the respective communication channels using the copies of the received signal. Thus, in one operational mode, each radio transceiver is tuned to the frequency of the corresponding communication channel. In another operational mode, all radio transceivers of the RF interface are tuned to the same communication channel to perform reliable diagnostics of communications on the communication channel. In these embodiments, the radio transceivers are tunable. In an embodiment, a user can tune the radio transceivers by entering appropriate commands via the user interface of the network analyzer.
- To allow the use of a single antenna with a relative large number of radio transceivers, the RF interface may also include a low noise amplifier (LNA) disposed upstream of the splitter to compensate for the loss of power that occurs when the splitter slits the received signal. In some embodiments, the LNA provides sufficient power compensation to enable first-stage splitting using a first-stage splitter, and second-stage splitting using several second-stage splitters, each coupled to a respective output of the first-stage splitter.
- In another embodiment, the RF interface includes a bandpass filter that receives a signal from a single antenna, a first-stage amplifier coupled to the output of the bandpass filter, a first-stage splitter coupled to the output of the first-stage amplifier, several second-stage amplifier coupled to the respective outputs of the first-stage splitter, and several second-stage splitters each coupled to the respective second-stage amplifier. In one such embodiment, the first-stage splitter and each of the second-stage splitter is a four-way splitter to accordingly provide a 16-way split of the received radio signal for use by 16 radio transceivers.
- In some embodiments, the RF interface further includes a central processing unit (CPU) such as a microcontroller, and a packet controller with at least a transceiver interface, a CPU interface, and a packet processing module. The CPU provides data packets captured by the radio transceivers to the packet server, receives configuration commands from user interface to be forwarded to the appropriate radio transceiver, etc. The CPU may receive configuration or control data, and transmit data packets and related statistics, via the USB interface connecting the RF interface to the computer host. In some embodiments, the CPU also provides a clock signal for use by other components of the RF interface, including the packet controller. Accordingly, the CPU interface of the packet controller may include a set of pins to transmit packets from the output queue of the packet controller, a pin to output a signal indicative of a presence of one or more data packets in the output queue of the packet controller, and a set of pins to receive a selection of a radio transceiver for control or configuration. In at least some of the embodiments, the CPU interface of the packet controller also includes a pin to receive a clock signal, a set of pins defining the known serial parallel interface.
- The transceiver interface of the packet controller to the radio transceivers provides a separate connection to each transceiver. In some embodiments, the transceiver interface includes a group of sets of pins, each set in the group defining the SPI interface to the respective transceiver. For each transceiver, the transceiver interface may also include a pin to receive a signal indicative of the beginning of reception of a data packet at the transceiver, a pin to receive a signal indicative of the end of reception of a data packet at the transceiver, and a pin to receive a signal indicative of the end of transfer of data packets from the transceiver to the packet controller. In those embodiments where the packet controller has a SPI interface with the CPU and with each transceiver, the packet controller may be considered a serial packet controller (SPC) that operates as a slave device relative to the CPU and as a master device relative to each transceiver.
- The packet controller may further provide independent first-in-first-out (FIFO) buffering for each communication channel, i.e., for data packets received from a particular transceiver. In some embodiments, the packet controller implements a separate state machine for each communication channel, and drives each state machine in parallel using a common clock signal. The clock signal may also drive a counter which the packet controller may use for time stamping data packets. In this manner, the packet controller can generate a highly accurate time stamp for each packet, so that two packets, A and B, detected simultaneously (i.e., within the same clock cycle) by two transceivers on the respective communication channels, acquire an identical time stamp. Thus, when the packet controller forwards the packets A and B to the CPU and, ultimately, to the packet server, the packet A may be forwarded prior to the packet B or, conversely, the packet B may be forwarded prior to the packet A. In either case, the packets A and B can be properly processed because the packet controller always generates a time stamp that reflects the time the data packet was received at the respective transceiver.
- In an embodiment, the packet controller may be implemented as a field-programmable field array (FPGA). The FPGA may be commercially available off-the-shelf hardware, and the packet controller may be implemented as firmware. In other embodiments, the packet controller may be implemented using standard components such as AND and OR gates, for example, or another type of an application-specific integrated circuit (ASIC). The clock may be a low-drift crystal clock with a resolution and accuracy selected in view of the duration of a transmission period in the communication network in which the network analyzer operates. When the communication network is a WirelessHART network, the resolution and accuracy of the clock is preferably one microsecond to provide reliable analysis of communications within TDMA timeslots used by WirelessHART networks.
- The packet server of the network analyzer may receive a stream of time stamped data packets from the acquisition engine via the USB port. The packet server may then provide the stream of data packets to the user interface as well as to one or multiple clients via a standard network protocol such as TCP/IP or UDP/IP, for example. The data stream may be formatted as ASCII text, hex data, or according to any other format. By supporting multiple clients, the packet server allows multiple users to remotely connect to the network analyzer disposed in a convenient location relative to the corresponding communication network, for example.
- A packet client may be a text-only or a graphical application that displays data packets captured from multiple communication channels in a convenient and intuitive format. At least some packet client applications may include filtering functions. In some embodiments, a packet client is adapted to apply a device-specific filter to display only those data packets that travel toward or from the specified network device. Further, a packet client may communicate with multiple packet servers so that a user may, for example, view network communications in several places within the communication network. In some embodiments, a packet client supports automated or scripted testing and/or filtering.
- In some embodiments, a wireless communication network analyzer adapted to simultaneously capture and process communications on multiple communication channels may include a software component executable on a conventional computer system, and a dedicated external hardware component that implements the RF interface and communicates with the software component via a standard interface such as USB, for example. In an embodiment, the software component includes both a packet server and a user interface. In other embodiments, the software component includes a packet server, and the user interface is provided as a separate component executable locally or remotely from the packet server. In yet other embodiments, the packet server alone or in combination with the user interface may be provided as a dedicated hardware component. In one such embodiment, the RF interface along with the packet server and the user interface are implemented in an embedded system.
- In an embodiment, a packet controller for simultaneous processing of data packets transmitted via a plurality of communication channels includes a plurality of inputs, each to receive a respective data packet signal indicative of a presence of a data packet on a respective one of the plurality of communication channels; a clock source to continuously supply a periodic clock signal associated with a certain clock cycle; a counter communicatively coupled to the clock source to generate a clock cycle count defined as a number of instances of the clock cycle that have occurred since a reference time; and plurality of independent time stamp generators, each coupled to the counter and to a respective one of the plurality of inputs to generate a time stamp in response to receiving the respective data packet signal, such that the time stamp includes a value of the clock cycle count. Optionally, the plurality of inputs of the packet controller is a first plurality of inputs, and the packet controller further includes a second plurality of inputs, each to receive data packers from a respective one of the plurality of communication channels; and an output to output data associated with the plurality of communication channels in a first-in, first-out (FIFO) order.
- In another embodiment, a serial data controller for parallel processing of a plurality of communication channels includes a master interface to exchange data with a master device, the master interface having a master output, slave input (MOSI) to receive data from the master device, a first master input, slave output (MISO) to transmit data to the master device, and a serial clock input (SCLK) to receive a master clock signal from the master device; and the serial data controller further includes a plurality of slave interfaces, each to exchange data with a respective one of a plurality of slave devices, such that each of the plurality of slave devices services a respective one of the plurality of communication channels and each of the plurality of slave interfaces having a MOSI to transmit data to the respective one of the plurality of slave devices, a MISO to receive data from the respective one of the plurality of slave devices, and an SCLK output to forward the master clock signal to the respective one of the plurality of slave devices; each of the plurality of slave interfaces further including a multiplexer having a plurality of inputs coupled to the plurality of slave interfaces, and an output coupled to the master interface, and a processing module to simultaneously process data received from each of the plurality of slave interfaces, and coupled to the multiplexer to provide the data to the master device as a single stream via the master interface. Optionally, the serial data controller further includes a mode selection input to select between at least a first mode and a second mode of operation of the serial data controller, such that the first mode is associated with transferring data from the plurality of slave interfaces to the master interface, and the second mode is associated with transferring data from the master interface to the plurality of slave interfaces. Optionally, the serial data controller receives data packets via the plurality of slave serial interfaces, and the processing module includes a clock source to supply a periodic clock signal, a counter coupled to the clock source to count a number of clock cycles of the periodic clock signal, and a plurality of first-in-first-out (FIFO) buffers, each corresponding to a respective one of the plurality of slave serial interfaces; so that the processing module generates a time stamp for each data packet received via one of the plurality of slave serial interfaces, and places each data packet and the corresponding time stamp into one of the plurality of FIFO buffers, where the one of the plurality of FIFO buffers corresponds to the one of the plurality of slave serial interfaces, and where the time stamp includes the number of clock cycles of the periodic clock signal Optionally, the master interface of the serial data controller further includes a slave device selector to select between the plurality of slave devices. Optionally, a wireless communication network analyzer includes the serial packet controller and is adapted to simultaneously capture data packets on a plurality of radio channels; the network analyzer further including a processor defining the master device, a plurality of radio transceivers defining the plurality of slave devices, each of the plurality of radio transceivers associated with a respective one of the plurality of radio channels, and a packet server stored in a computer-readable memory as a set of instructions and executing on the processor to transmit the data packets captured on the plurality of radio channels to one or more clients.
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FIG. 1 schematically illustrates a wireless network in which a wireless communication network analyzer of the present disclosure may operate, and a fragment of an example schedule according to which devices in the wireless network communicate. -
FIG. 2 is a block diagram of the network analyzer ofFIG. 1 . -
FIG. 3 is a circuit board component diagram for an RF interface of the network analyzer illustrated inFIG. 1 . -
FIG. 4 is a block diagram of a signal peripheral controller of the RF interface ofFIG. 3 . -
FIG. 5 is a signal diagram for the signal peripheral controller ofFIG. 3 . -
FIG. 6A is a block diagram of a state machine interaction of the signal peripheral controller of the RF interface ofFIG. 3 . -
FIG. 6B is a state transition diagram which several independent state machines operating in the signal peripheral controller of the RF interface ofFIG. 3 may execute to service a particular communication channel. -
FIG. 7 is a block diagram of a serial peripheral interface interaction of the signal peripheral controller of the RF interface ofFIG. 3 . -
FIG. 8 is a timing diagram of an example scenario in which the network analyzer ofFIG. 1 captures several data packets on different communication channels. -
FIG. 9 is a block diagram of a receive signal transmission path for an alternative embodiment of the RF interface ofFIG. 3 . -
FIGS. 10-13 illustrate circuit diagrams for various components of the RF interface ofFIG. 3 . -
FIG. 14 is a block diagram of a packet client that operates with multiple packet servers of the network analyzer ofFIG. 1 . -
FIG. 1 illustrates anexemplary wireless network 1 in which a wirelesscommunication network analyzer 2 may be used to capture and process data packets P1-P4 communicated by devices D1-D8. Although thewireless network 1 may be compatible with a variety of wireless protocols, the network protocol used in the embodiment illustratedFIG. 1 is a secure, wireless mesh protocol that operates in the 2.4 GHz ISM radio band, utilizes IEEE Standard 802.15.4-2006 2.4 GHz DSSS transceivers with channel hopping on a transaction-by-transaction basis, and schedules link activity using time division multiple access (TDMA). More specifically, the network protocol operating in thewireless network 1 may be the WirelessHART protocol promulgated by the HART Communication Foundation (HCF). Accordingly, devices D1-D8 in the embodiment ofFIG. 1 communicate digital data using data packets of limited length, e.g., not exceeding 128 bytes, during fixed-length timeslots assigned to multiple communication channels corresponding to carrier frequencies F1-F5. The devices D1-D8 support channel hopping to provide frequency diversity that, in turn, minimizes interference and reduces multi-path fading effects. - For ease of explanation,
FIG. 1 also schematically illustrates afragment 4 of a network schedule according to which the devices D1-D8 transmit and receive the data packets P1-P4. Although the schedule of thewireless network 1 generally may specify only timeslot and frequency assignment for a particular pair of communicating devices, thefragment 4 illustrates an example mapping of particular packets P1-P4 to (timeslot, frequency) tuples for a typical communication scenario in thewireless network 1. It will be also noted that although thefragment 4 illustrates assignment to only five frequencies F1-F5 defining five respective communication channels, thewireless network 1 may operate using fewer or more communication channels. For example, thewireless network 1 may utilize all 16 communication channels specified by 2.4 GHz IEEE Standard 802.15.4-2006. - With continued reference to
FIG. 1 , the packet P1 may travel from the device D1 to the device D2 during the timeslot TS1 on carrier or frequency F4, and from the device D2 to the device D7 during timeslot TS2 on carrier F5. Thus, to trace the propagation of the packet P1 from the device D1 to the device D7, it is desirable to capture communications on both carriers F4 and F5. As another example, the packet P3 may also travel from the device D1 to the device D7, but via an additional intermediate device D3. During timeslot TS2, the packet P3 may travel from the device D1 to the device D3 on carriers F1; the packet P3 may then travel to the device D2 during timeslot TS3 on carrier F2; and finally to the device D7 during timeslot TS4 on carrier F3. It will be noted that during timeslot TS2, both packets P1 and P3 travel between the respective pairs of devices D2, D7 and D1, D3. Therefore, it is also desirable to capture communications simultaneously on multiple carriers. - In addition to the packets P1 and P3 that travel “upstream” relative to the device D7, some of the devices D1-D8 may similarly propagate data packets P2 and P4 “downstream” from the device D7 to the destination devices D5 and D4, respectively. As illustrated in
FIG. 1 , the packet P2 may travel to the device D5 during timeslot TS1 on carrier F3, while the packet P4 may travel may travel between the devices D7 and D5 during timeslot TS3 on carrier F5, between the devices D7 and D5 during timeslot TS4 on carrier F1, and between the devices D7 and D5 during timeslot TS5 on carrier F2. - During operation of the
wireless network 1, thenetwork analyzer 2 continuously and simultaneously captures communications on all channels F1-F5 used by the devices D1-D8. Further, thenetwork analyzer 2 captures and maintains timing information to ensure correct TDMA operation. To this end, thenetwork analyzer 2 may use a common clock source to time stamp communications occurring on any channel. Still further, thenetwork analyzer 2 may record all communications to allow the network traffic to be analyzed for the purpose of assessing compliance with the network protocol used by thewireless network 1. - Users such as engineers, technicians, etc. may operate the
network analyzer 2 locally or remotely via the network interface of thenetwork analyzer 2. If desired, several instances of thenetwork analyzer 2 may placed in several locations in the process control plant, and a user at a remote location may run a single client application that communicates with the two ormore network analyzers 2. Conversely, eachnetwork analyzer 2 may support multiple client applications by assigning separate TCP or UDP ports to each instance of a packet client, for example. -
FIG. 2 schematically illustrates example architecture of thenetwork analyzer 2, as well as the interaction between thenetwork analyzer 2 and one or more client applications (or “packet clients”). Thenetwork analyzer 2 includes anacquisition engine 10 partially residing on ahost computer 12, which may be a laptop, another type of a standard computer system, or an embedded computer system specifically designed to support one or several components of thenetwork analyzer 2. Theacquisition engine 10 operates as a data acquisition front end for thenetwork analyzer 2 and, as illustrated inFIG. 2 , includes anRF interface 14 and apacket server 16. - The
RF interface 14 includes one or more receive antennas 18 (preferably only one) and simultaneously acquires data packets on all communication channels used by thewireless network 1, e.g., on all 16 channels of a 802.15.4-compliant 2.4 GHz network protocol. TheRF interface 14 time stamps the data packets upon reception, and provides the data packets to thepacket server 16 for conveyance to a user interface (UI) 20 of thenetwork analyzer 2 and/or one ormultiple client applications 24 via anetwork interface 26 and anetwork 28. Preferably, the time stamps are synchronized across all communication channels with less than ±8 μS (micro-seconds) error. The time stamps also preferably have a resolution of at least 8 μS and preferably have a resolution of 1 μS. In an embodiment, the time stamp corresponds to the reception of the delimiter byte in the IEEE 802.15.4 PHY PDU. Alternatively, the time stamp may correspond to another event such as the reception of the last octet of the data packet, for example. - The connection between the
RF interface 14 and thepacket server 16, which is executed in thehost computer 12, may be implemented using aUSB connection port 22, which may be a USB 2.0 full speed (12 Mbits/sec) or a high speed (480 Mbits/sec) connection, and may comply with the appropriate USB device type profile. TheRF interface 14 is preferably appropriately packaged for laboratory and non-hazardous plant floor use. The packaging should also be appropriate for accompaniment by a laptop host computer. Further, packaging should ensure that all 16 channels can be received equally well. Thus, for example, there should not be more variance than ±3 dBm in received signal sensitivity between any of the 16 channels. - The
packet server 16 may be a simple console application that connects to and supports theRF interface 14. The basic control of thepacket server 16 may be implemented via command-line options. Once launched, thepacket server 16 connects to the specifiedRF interface 14 via theUSB port 22 and waits for theuser interface 20 to connect to thepacket server 16 via a predefined control port, for example. Thepacket server 16 may also support one or several data ports to which theuser interface 20 and/or theclient applications 24 may connect to retrieve data captured at theRF interface 14. Alternatively, the interaction between thepacket server 16 and the UI may be implemented remote procedure calls (RPCs) or other inter-task communication techniques supported by the operating system executing on thehost 12. Preferably, both thepacket server 16 and theuser interface 20 are compatible with Microsoft® Windows 2000, XP, or Vista, as well as with Linux, QNX, and other operating systems. - As discussed in greater detail below, the
packet server 16 may support a set of commands which the user may enter directly via the command-line interface or via theuser interface 20. Once theuser interface 20 successfully connects to thepacket server 16, the user may transmit the “START” to thepacket server 16 to initiate transfer of data from theRF interface 14 to theuser interface 20. The data transfer may continue until thepacket server 16 receives the “STOP” command, or until theUI application 20 disconnects. - Still referring to
FIG. 2 , at least one of thepacket clients 24 may be a packet analyzer that displays, filters, and analyzes the data packets and the statistics captured and collected at theRF interface 14 and forwarded by thepacket server 16. Preferably, the packet analyzer understands both IEEE 802.15.4 and WirelessHART packet structures. During operation, the packet analyzer may convert the binary fields in the data packets into legible human-readable display. Further, the packet analyzer may parse the captured data packets into the separate fields, and optionally display the text included in or corresponding to the fields to simplify the human analysis and understanding of the communications between the devices D1-D8. - In an embodiment, the
packet analyzer 24 may run on thesame compute host 12, and connect to thepacket server 16 locally. Alternatively, thepacket analyzer 24 may run on another host and connect to thepacket server 16 remotely, as illustrated inFIG. 2 . Thus, theRF interface 14 and thepacket server 16 may be located at a plant site, and thepacket analyzer 24 can conveniently connect to thepacket server 16 from a service center to remotely troubleshoot the operation of thewireless network 1. - As indicated above, the
packet analyzer 24 can also connect tomultiple packet servers 16 simultaneously (seeFIG. 1 in which two instances of thenetwork analyzer 2 are disposed at two different locations within the process plant in which thewireless network 1 operates). Moreover, eachpacket server 16 may support multiple RF interfaces 14. As a result, data from several geographically distributed RF interfaces 14 can be combined on one display to provide a comprehensive view of the entire RF space occupied by thewireless network 1. - Next,
FIGS. 3-8 illustrate various components of theRF interface 14 in several embodiments, as well as the interactions between these components from various perspectives to better explain the operation of theRF interface 14. In particular,FIG. 3 illustrates an example circuit board component diagram of theRF interface 14;FIGS. 4 and 5 provide a high-level diagram and a signal diagram, respectively, of one of the components of theRF interface 14;FIGS. 6A-B and 7 illustrate the same component from the perspectives of state machine execution and serial peripheral interface (SPI) operation, respectively; andFIG. 8 illustrates an example signal transmission path of one of the embodiments of theRF interface 14. - Referring to
FIG. 3 , theRF interface 14 may include anSMA antenna connector 30 coupled to an RF low noise amplifier (LNA) 32, which in turn is connected to a 4-way signal splitter 34. Each of the outputs of thesignal splitter 34 is provided to one of a set of 4-way signal splitters radio transceiver 38, each of which receives and decodes a single radio channel associated with the respective frequency Fn. Thus,multiple radio transceivers 38 may be incorporated into a single circuit on a single circuit board. Further, theradio transceivers 38, which may be implemented using CC2420 chips, provide a decoded output to a serial peripheral controller (SPC) 40 which may include an FPGA module, which may be a Xilinx XC3S1000-FT256 chip. TheSPC 40 stores these data steams in a set of first-in-first-out (FIFO) buffers or memories, which may be implemented within theSPC 40 or in a separate memory chip. TheRF interface 14 also includes a central processing unit (CPU) 42 which is connected to the serialperipheral controller 40 to receive processed data streams and operates to provide these data steams to the packet server 16 (seeFIG. 2 ). A serialboot flash memory 44 may store a boot program used to boot up theCPU 42 upon power up and may provide additional non-volatile memory for theSPC 40. - The
CPU 42 may be connected to the host computer 12 (seeFIG. 2 ) via aUSB connection 46 and may be connected to drive one or more light emitting diodes (LEDs) 48, which may serve as a diagnostic, status or operational interface on theRF interface 14. Anadditional radio transceiver 50, which may also be implemented as a CC2420 chip, is connected to theCPU 42 and to anSMA antenna connector 52 and may be used as a transmit radio. During operation, the receive antenna 18 (seeFIG. 2 ) may be connected to theconnector 30 and a transmit antenna (not shown) may be connected to theconnector 52. These antennas may be, for example, whip antennas. TheCPU 42 may drive theradio transceiver 50 to transmit to the WirelessHART network. However, if desired, theradio transceiver 50 may be connected to the serialperipheral controller 40 via an SPI connection to allow theradio transceiver 50 to be used as an additional receiver. - As illustrated in
FIG. 3 , a DC toDC power supply 54 is coupled to theUSB connection 46 to receive power on theUSB connection 46, and operates to convert the USB power to the power levels needed by theCPU 42, the serialperipheral controller 40, theradio transceivers LNA 32 and other powered components on theRF interface 14. As illustrated inFIG. 2 , thepower supply 54 may provide 3.3 volt, 2.5 volt and 1.2 volt power signals, although other power levels may be provided as well or instead. Still further, theRF interface 14 may include aJTAG connector 58 to allow programming, diagnostics or other access to the serialperipheral controller 40. - In general, the
SPC 40 may perform several functions in theradio interface 14. On the one hand, the purpose of theSPC 40 is to provide separate SPI interfaces to each of the 16 802.15.4radio transceivers 38, as well as to thetransceiver 50. TheSPC 40 may operate as an SPI master device relative to thetransceivers CPU 42. On the other hand, the FPGA of theSPC 40 also provides first-in-first-out (FIFO) buffering, channel selection, start of packet time stamping and a parallel interface to theCPU 42 for capturing packet data. In addition, the FPGA of theSPC 40 includes an interface from theCPU 40 for reading and writing all radio and internal FPGA registers as needed. - Referring to
FIG. 4 , theSPC 40 in one embodiment may include amultiplexer 60 to which severalradio control modules 64 provide respective inputs. Each of theradio control modules 64 may control and maintain a separate FIFO queue to store data packets received at a correspondingtransceiver 38. As explained in more detail with respect toFIG. 7 , theradio control modules 64 implement independent state machines driven by a common clock signal, provided by the CPU or another clock source. As a result,radio control modules 64 are able to generate accurate time stamps in parallel and independently of each other. When theradio control modules 64 provide data packets to theCPU 42 via the multiplexer and aread control module 66, these independently generated time stamps permit accurate subsequent processing irrespective of the order in which data packets, received simultaneously or almost simultaneously on different channels, are supplied to theCPU 42 from themultiplexer 60. Upon receiving one or several data packets, theread control module 66 may notify theCPU 42 via an interrupt, for example, prior to outputting the one or several data packets to theCPU 42. Additionally, each of theradio control modules 64 may interact with an SPI interface andglobal control module 68 to receive control or configuration data to be forwarded to arespective radio transceiver 38. -
FIG. 5 illustrates a signal diagram of theSPC 40. In this embodiment, theSPC 40 includes a transceiver interface and a CPU interface, each of which may be implemented as a set of input and output pins to respectively receive and transmit electronic signals. Some signals in the diagram ofFIG. 5 are named using the physical channel number as a postfix, e.g., SFD_n, where n is the physical channel number from 0 to 15. For the purposes of clarity, these signals are named using the physical channel number rather than the actual 802.15.4 frequency channel numbers of 11 to 26. In the discussion ofFIG. 5 below, the terms “pin” and “signal” are used interchangeably. - On the transceiver interface, signals MOSI_n, MISO_n, and SCLK_n may define a synchronous serial data link consistent with the SPI architecture for each
transceiver 38. Signals SFD_n, FIFO_n and FIFOP_n may be used to drive independent state machines responsible for time stamping data packets, as well for initiating and stopping packet data transfer from the transceivers 38 (state machine implementation is discussed in detail with reference toFIGS. 6 and 11 ). Further, signals XCVR_CLK_n may be used to forward a clock signal to eachtransceiver 38. Still further, the transceiver interface may include CS_n signals to select aparticular transceiver 38 chip, and a single outbound reset signal/NRESET which may be sent to all of thetransceivers 38. - Regarding the CPU interface of the
SPC 40, eight RXDATA pins are used to transfer a byte to theCPU 42 from a FIFO memory or buffer associated with a certain communication channel within theSPC 40, the READ_DATA signal is used to advance the readout to the next byte, and the /RX_INT signal is used to generate an interrupt that notifies theCPU 42 that data is available in one of the FIFO buffers in theSPC 40. The five pins ADDR[5:0] are used to select one of thetransceivers 38 or one of the internal registers of theSPC 40, as discussed in more detail below. Further with respect to the CPU interface, signals MOSI, MISO, and SCLK define an SPI interface in which theCPU 42 operates as a master device and theSPC 40 operates as a slave device. Still further, the /CS_SPC signal provides theCPU 42 with access to any register within theSPC 40; the /LED1 and /LED2 signals are used to control respective light-emitting diodes to indicate network activity or errors, and may be connected to theCPU 42 so that theCPU 42 can read the LED states directly; the /CLK —16 MHZ signal is used to supply a clock signal from theCPU 42 and the SPC_CLK is used for monitoring the internal clock of theSPC 40; and the /RESET_SPC signal from theCPU 42 may reset all or some of the data and/or internal states of theSPC 40. - In general, the
SPC 40 may operate in one of two fundamental modes, a setup mode and a receive mode, selectable via the RX_MODE pin. The setup mode is used to initialize theradio transceivers radio transceiver 38. To enter the setup mode, the RX_MODE pin may be set to 0, for example. - More particularly, the
network analyzer 2 may initially program eachradio transceiver 38 using the setup mode. First, one of the 16 channels is selected using a set of ADDR[3:0] pins and setting an ADDR4 pin low. These five pins are some of the inputs to theSPC 40 when theSPC 40 is in the setup mode. Next, a normal SPI cycle is performed using the SPI engine run on theCPU 42. A set of /CS_SPC, MOSI, MISO and SCLK signals are automatically routed through theSPC 40 to theradio transceiver 38 associated with the addressed channel. Thus, in the setup mode, theSPC 40 can forward signals associated with standard SPI communications between theCPU 42 and the selected one of thetransceivers 38. For maximum flexibility, the /CS_SPC signal timing is generated by software via a GPIO port in output mode. - In the setup mode, all of the registers of the selected
radio transceiver 38 are programmed, and eachtransceiver 38 is set to a different one of the 16 frequency channels defined by the 802.15.4 specification. As the last step performed in the setup mode, thenetwork analyzer 2 may write the 16-bit channel enable register within theSPC 40 to indicate which ones of the 16 channels are actually enabled in the receive mode. Once this step is completed, the RX_MODE pin is set to 1 to enter the receive mode. - In addition to selecting one of the
radio transceivers 38 via the ADDR[3:0] pins and transmitting control or configuration data to the selectedtransceiver 38, theCPU 42 may directly access the internal registers of theSPC 40 via the /CS_SPC signal by setting ADDR4 signal high, for example. In this scenario, the ADDR[3:0] pins may be used to select one of the 16 internal registers of theSPC 40. In some embodiments, the internal registers are all 16-bits wide. The exact functions of the registers of theSPC 40 in one embodiment are defined in the table below. -
Register # Name Function Format 0 Channel Enable Selects which channels Bit 15 (MSB) = 1, channel 16 is(Read/Write) are in receive mode enabled after RX_MODE is set . . . to 1 Bit 0 (LSB) = 1, channel 0 isenabled 1 Status (Read Reports internal FIFO Bit 0 = Radio RX FIFO Overflow Only) overflows and/or Radio Bit 1 = SPC RX FIFO Overflow FIFO overflows 4 Packet Counte Set to select Counter to Bit 0 to 3 - counter # to be readChannel Address be read back in register 5Bit 4 - Read Packet Counter or (Write Only) Discarded Packet Counter 5 Read Counter Read back Packet 16-bit Packet Counter (Read Only) Counter addressed by register 46 Debug register 6Read back Debug Info Variable (read only) 7 Debug register 7Read back Debug Info Variable (read only) 15 FPGA Firmware Read back SPC Read 0x0100 means Version 1.00 Version Firmware Version
In an embodiment, the register data is clocked in on the positive-edge of the SCLK signal and is saved in the appropriate register when /CS_SPC goes high. - In the receive mode, an independent state machine within the
SPC 40 processes data packets from arespective transceiver 38, and generates time stamps for each received data packet. Thetransceiver 38 may forward all layers of the captured data packet to theSPC 40, including the PHY header and possibly the preamble. When the RX_MODE pin is set to 1, theSPC 40 automatically sends a command (SRX-ON) to each enabled radio transceiver 38 (identifiable using the channel enableregister 0 as described in the table above) to start reception. The operation of theSPC 40 in the receive mode, as well as the components used in the receive mode, are discussed next with reference toFIGS. 6A and 6B and continued reference to the signal diagram ofFIG. 5 . - Normally, each
radio transceiver 38 is set to a different one of the set of communication channels used to transmit data packets in thenetwork 1. As indicated above, thenetwork analyzer 2 may thus capture communications occurring on all communication channels of thenetwork 1. However, thenetwork analyzer 2 preferably permits the user to program any of theradio transceivers 38 via theuser interface 20 to operate on any 802.15.4 channel. As one example, the user may configure allradio transceivers 38 of theRF interface 14 to receive communications on the same channel in order to determine the RSSI signal strength variance between communication channels. This mode of operation is referred to below as the calibration mode. - As indicated above, the
CPU 42 and theSPC 40 use the signals RXDATA[7:0], READ_DATA and /RX-INT to transfer data packets to theCPU 42 and, in particular, the RXDATA pins are used to read a byte from a corresponding FIFO buffer. When transitioning from the receive mode back to the setup mode (i.e., RX-MODE pin goes low), theSPC 40 may automatically clear all of the internal states related to the receive mode, and flushes all FIFO buffers. -
FIG. 6A schematically illustrates signaling related toindependent state machines 70 that operate in the receive mode of theSPC 40. Each of thestate machines 70 is connected to and services arespective radio transceiver 38. Referring back toFIG. 4 , theindependent state machines 70 may be a component of a respective independentradio control module 54. In particular, eachindependent state machine 70 may be responsible for generating a time stamp in response to detecting the beginning of a data packet, initiating the transfer of a data packet from thecorresponding radio transceiver 38 in response to detecting the end of the data packet, and stopping data transfer in response to detecting that the entire data packet has been transferred to the channel-specific internal buffer of theSPC 40 from theradio transceiver 38. A state transition diagram of thestate machine 70 in accordance with one embodiment is illustrated in, and discussed in more detail with reference toFIG. 6B . - Still referring to
FIG. 6A , aclock source 72 provides a periodic clock signal to acounter 74, which may be a 40-bit integer counter, for example. Theclock source 72 may be an accurate, low drift crystal with a resolution and accuracy of 1 microsecond over an interval of greater than 12.7 days. If desired, theclock source 72 may be provided separately from theSPC 40 to provide a clock signal to theSPC 40 via a dedicated pin, for example. Eachstate machine 70 is communicatively coupled to thecounter 74 so that a time stamp for a data packet received from any of thetransceivers 38 may be generated immediately upon detecting the beginning of the data packet at the correspondingtransceiver 38, and irrespective of the number of packets detected on other communication channels. Eachstate machine 70 may operate a respective packet formatter 76 (which may be another component of theradio control module 54 illustrated inFIG. 4 ). Thepacket formatter 76 may append, prepend, or otherwise attach the current value of the counter 74 (defining the time stamp) to the data packet prior to adding the data packet to the corresponding FIFO queue or buffer. Alternatively, theSPC 40 may include only one packet formatter, and thestate machine 70 may cause the current value of thecounter 74 to be stored in a register or buffer for subsequent use by the packet formatter. It will be noted that in general, only some of the processing of data packets needs to proceed in parallel on all communication channels. As yet another alternative, theSPC 40 may includemultiple counters 74 driven by a common clock signal. - Each of the
state machines 70 may operate according to a state transition diagram 90 illustrated inFIG. 6B . In this embodiment, the state transition diagram 90 includes an idle state during which theSPC 40 is neither transferring data packets from the correspondingtransceiver 38, nor is registering the reception of a new data packet at thetransceiver 38. Thestate machine 70 may transition tostate 94, in which a new data packet is being received at thetransceiver 38, when the corresponding SFD_n signal goes from 0 to 1. For example, thetransceiver 38 tuned to the frequency F3 (seeFIG. 1 ) associated withcommunication channel 3 may detect a preamble of a packet on the physical layer of the 802.15.4 protocol stack, followed by a start frame delimiter (SFD) field indicating the start of the data packet. Upon detecting the frame delimiter, thetransceiver 38 may immediately output a 1 on the outbound SFD pin of thetransceiver 38. Because thetransceiver 38 in this example is associated withcommunication channel 3, theSPC 40 receives a 1 on SFD_3 coupled to astate machine 70 that services thecommunication channel 3. - In the notation used in
FIG. 6B , the event that triggers the transaction indicated by an arrow is listed to the left of the forward slash, and the action performed in response to the event prior to entering the new state is listed to the right of the forward slash. Thus, as illustrated inFIG. 6B , thestate machine 70 may generate the time stamp in response to detecting that the corresponding SFD_n signal is now 1. In a sense, the SFD_n signal is used to “freeze” the packet time stamp for the corresponding communication channel. Once the last byte of the packet is received, thetransceiver 38 changes the FIFOP_n signal to high. This signal causes thestate machine 70 to generate a packet header, initiate an SPI transfer in order to read the data packet bytes from the radio FIFO buffer, and transition tostate 96. In an embodiment, each channel-specific FIFO buffer may be 2 Kb deep. - Prior to retrieving a data packet in the
state 96, theSPC 40 may generate a header identifying the channel on which the data packet was received and a 5-byte long time stamp. TheSPC 40 may insert the generated header into the corresponding FIFO buffer ahead of the data packet to be retrieved from thetransceiver 38 instate 96. In some embodiments, the packet header data format may be defined as follows: -
0 1 2 3 4 5 Channel TS Byte 4 TS Byte 3TS Byte 2TS Byte 1TS Byte 0MSB LSB - According to this example format, the lower nibble of the channel byte is in the
range 0 to 15 to indicate the physical channel of the packet. The software of thenetwork analyzer 2 may map this physical channel to the 802.15.4 channel in the setup mode. The upper nibble of the channel byte carries a copy of the status bits fromSPC Register # 1 defined above. The time stamp is preferably a 40-bit value with a resolution of 1 microsecond per bit. This resolution allows a packet capture period of more than 12.7 days without wrapping. The time stamp counter is set to 0 when theSPC 40 is reset at power-up. - In
state 96, thestate machine 70 may retrieve the data packet available at thetransceiver 38. In other embodiments, thestate machine 70 may read multiple data packets instate 96 without transitioning back tostate 92 after each reception. However, time stamp generation and insertion may need to be adjusted accordingly. In general, the transfer instate 96 may occur via the corresponding SPI interface (i.e., MISO_n, MOSI_n, and SCLK_n pins). - In the
example network 1 that implements WirelessHART, the packet data is up to 128 bytes in length. The first byte indicates the length in bytes of the rest of the packet. The SPC state machine first reads the length byte and uses it to read the remaining bytes of the packet. Alternatively, theSPC 40 can just read the bytes from theradio transceiver 38 until the FIFO_n pin goes low indicating that there are no more bytes to read. - If desired, the
SPC 40 may also append a length check byte at the end of a data packet stored in the corresponding FIFO. This additional byte is used for synchronization purposes and validation of packet boundaries. Any packets with a length byte greater than 127 may be considered invalid and can be discarded. When a discard occurs, a packet discard counter may be incremented. Packets with valid lengths but with cyclical redundancy check (CRC) errors also may be captured. The last byte of the packet may include a bit that indicates whether the packet had a CRC error. - Once the packet has been received, time stamped and stored in the appropriate channel-specific FIFO memory, the
SPC 40 may proceed to notify theCPU 42 that new data is available for retrieval and subsequent processing bypacket server 16 and, ultimately by one of the packet clients 24 (seeFIG. 1 ). To this end, theSPC 40 may generate an interrupt by asserting the /RX-INT pin. TheCPU 42 may respond by reading a byte of the packet via the RXDATA[7:0] pins, toggling the READ_DATA pin to advance the FIFO readout to the next byte, checking to see whether the /RX_INT pin is still asserted (i.e., checking whether the entire data packet has been transferred), and continuing to retrieve individual bytes of the data packet until the /RX_INT pin is de-asserted. - In some embodiments, to ensure that the
CPU 42 can detect the de-asserted /RX-INT pin before the next interrupt comes in, theSPC 40 waits to issue any pending interrupts until after the READ_DATA signal is toggled one additional time by theCPU 42. - Further, the
SPC 40 may be adapted to efficiently and safely handle overflows. Although theSPC 40 is preferably fast enough to avoid an overflow under normal conditions, an overflow may still occur if, for example, one of thetransceivers 38 receives a data packet longer than the maximum length of 128 bytes. In this case, an overflow may be indicated by the FIFO_n signal going low after FIFOP_n goes high at the end of the data packet. In an embodiment, theSPC 40 detects this condition and issues a command to the correspondingtransceiver 38 to flush the associated FIFO memory and to resume operation. In this case, some data in the FIFO buffer is lost and the corresponding time stamp is not used. This condition could be reported using, for example, one of theLEDs 48 on a pin from theSPC 40, if desired. - Further with respect to clock signals used to drive the
state machines 70, the clock source 72 (see FIG. 6A0) may be the CLK-16 MHz input pin. This signal may be highly accurate clock (+−1.5 ppm), and may be also used to drive thetime stamp counter 74 and the XCVR_CLK—[16:0] signals. In this case, theSPC 40 may be simply used as a distribution buffer for the XCVR_CLK_n outputs. Theextra XCVR_CLK —16 signal may go to theradio transceiver 50, if desired. - Further, the SPC_CLK output pin may be the internal clock used by the
state machines 70. This signal is preferably a 40 MHz clock generated by an internal phase locked loop (PLL) of theSPC 40, and this clock signal may be output at pin for SPC_CLK testing purposes. - As indicated above, the
CPU 42 may also completely reset theSCP 40 by issuing a low pulse on the /RESET_SPC input. In this case, theSPC 40 may set the one ormore counters 70, the internal registers, and all of the internal FIFO buffers to zero. TheSPC 40 may also reset all of the state machines to the idle state. TheSPC 40 may also send a single /NRESET signal to all of thetransceivers 38. Preferably, this signal is pulsed low when theSPC 40 is reset via the /RESET_SPC signal. - When operating in the calibration mode, the
network analyzer 2 may tune alltransceivers 38 to the same carrier frequency. TheRF interface 14 may then receive the same control signal on every communication channel, measure the RSL on each communication channel, and use the obtained RSL measurements to compensate for variations in channel-specific signal attenuation in subsequent processing. In other words, thenetwork analyzer 2 may operate thetransceivers 38 on the same frequency in order to reduce or completely cancel out channel-to-channel variations in receiver sensitivity, and thus efficiently and accurately calibrate theRF interface 14. The control signal may include actual data packets transmitted by the devices D1-D7 in thenetwork 1, or a signal from a control transmitter. In one embodiment, thenetwork analyzer 2 may use thetransceiver 50 to generate the control signal having a controlled strength and/or other parameters. It will be appreciated that accurate calibration of theRF interface 14 across multiple communication channels allows thenetwork analyzer 2 to estimate the strength of the signal emitted by a device under test (e.g., one of the devices D1-D7 illustrated inFIG. 1 ). - Next,
FIG. 7 illustrates the interaction between theCPU 42, theSPC 40, and thetransceivers FIG. 7 illustrates only those pins or signals that are related to serial interface signaling, and omits other pins or signals for clarity of illustration. It will be appreciated that theCPU 42 inFIG. 7 operates as a master device relative to theSPC 40 which, in turn, operates as a master device relative totransceivers CPU 42 operates with a single slave device (SPC 40), the CPU interface of theSPC 40 includes ADDR pins (seeFIG. 5 ) that operate as slave selection signals. As discussed above, the configuration illustrated inFIG. 7 advantageously permits theSPC 40 to provide buffering, parallel processing, time stamping, independent management of FIFO queues dedicated to individual channels, etc. - From the foregoing, it will be appreciated that the
radio interface 14 in general, and theSPC 40 in particular, permit the client applications 24 (seeFIG. 1 ) to receive accurate information regarding the timing of data packets transmitted in thenetwork 1. Whereas a conventional processor can only service multiple data streams in a pseudo-parallel manner, i.e., by slicing the CPU time, theSPC 40 registers critical information such as time stamps on multiple communication channels in a genuinely parallel manner. As is known, parallel processing on a conventional processor typically involves slicing the available CPU time into multiple periods for use by parallel task, and switching between the tasks (i.e., “context switching”) according to some algorithm or selection principle. In this sense, parallel processing is only quasi-parallel, in that the CPU only performs one task at a given point in time. - To better illustrate some of the advantages associated with this approach,
FIG. 8 illustrates a timing diagram in which a data packet is received at the time T1 oncommunication channel 0, as indicated by theSFD —0 signal going high at the time T1, and another two data packets are simultaneously received at the time T2 oncommunication channels SPC 40 is used, the arrival of data packets oncommunication channels - In general, the time stamp accuracy may be limited to the resolution of the CLK signal. The data packet detected on communication channel N at the time T4 may accordingly acquire a time stamp associated with the time T5 different from the time T3, while the data packets detected on
communication channels - Further, it will be noted that the
SPC 40 need not trigger time stamping at the beginning of the delimiter field. If, for example, all packets are known to use the same format of the PHY preamble and/or header, theSPC 40 may trigger using other signals, or different transitions of the same signals, received from thetransceivers 38. For example, the relative accuracy of time stamps can be the same if theSPC 40 were to trigger on the transition of SFD_n from high to low at the times T6, T7, or T9. - Next,
FIG. 9 illustrates another embodiment of the RF signaling path which may be used in thenetwork analyzer 2. Although different from the embodiment ofFIG. 3 , the configuration illustrated inFIG. 9 also allows thenetwork analyzer 2 to use of a single antenna. WhileFIG. 3 illustrates a configuration in which a single band pass filter andhigh gain amplifier 32 is used to process the RF signals received across the 802.15.4 spectrum,FIG. 9 illustrates an alternativeRF signal path 98 in which asingle bandpass filter 100 is disposed between the RF input and afirst stage amplifier 102 which drives the first 4-way splitter 34.Second stage amplifiers 104 are then provided between thesplitter 34 and the 4-way splitters 36 a-36 d. However, it appears to be easier to drive thesingle amplifier 32 ofFIG. 3 using the USB power than the five separate amplifiers illustrated inFIG. 9 . Furthermore, it is desirable to use a balun for coupling theradios 38 to the antenna coupler itself with a low part count. One possible balun requires only two components instead of seven. - In an embodiment, the
SPC 40 may include a Xilinx XC3S1000-FT256 FPGA in which the serial slave mode configuration is implemented. In this mode, theCPU 42 controls loading the FPGA code via the CCLK, DIN, DONE, INIT_B & PROG_B pins on the FPGA. The code itself is stored in theserial flash 44 connected to theCPU 42. TheCPU 42 is required to download the FPCA code at power-up time. More details may be found in the Xilinx Application Note (XAPP502) on using a microprocessor to configure a Xilinx FPGA. Further, theradio transceivers 38 may be TI/Chipcon CC2420 chips and the FPCA may be customized to use the signal interface of this transceiver.FIGS. 10-13 illustrate circuit diagrams for various components of theRF interface 14, at least some of which include the CC2420 chips. - From the foregoing, it will be appreciated that the
radio interface 14 discussed with reference toFIGS. 3-9 provides a number of important advantages including, for example, simultaneous capture of communications on multiple communication channels, parallel processing of captured streams (and, in particular, accurate-time stamping), ability to capture all layers of a data packet including the physical layer, etc. Because multiple data streams are processed using the same clock signal, time synchronization across all 16 channels is assured and accurate time stamps are generated upon PHY delimiter reception. Moreover, theRF interface 14 may operate using a single antenna to simultaneously capture data packets on 16 communication channels or more, if desired. In general, it is also possible to use multiple antennas and, at least in theory, a separate antenna such as a chip antenna may be provided for each communication channel. However, testing has revealed that placing relatively many antennas proximately to each produces significant interference, sometimes enough to cause thenetwork analyzer 2 to occasionally drop packets. - Referring back to
FIG. 2 , the architecture of thenetwork analyzer 2 efficiently separates tasks into those that are optimally performed by hardware or firmware, and those that are best performed by software. Thus, the packet analyzer or asimilar packet client 24 performs the “heavy lifting” of decoding data packets, processing user commands, displaying data packets textually and/or graphically, etc. Further, thepacket server 16 ofFIG. 1 is designed so that data packets are conveyed from theRF interface 14 to theuser interface application 20 and are formatted accordingly. The command line arguments for thepacket server 16 may be as follows: - -p port
- Server port used to establish a bi-directional configuration and control connection to a
packet client 24 and/or the user interface 20 (default: 1024) - -l descriptor
- ISO 639 specified language descriptor string (default: “en”).
- -d
- Run in debug mode taking input from stdin and sending the capture packets to stdout. The capture is stopped by sending a AC via stdin. If this option is not specified, the message server will wait for control commands on the control port before starting the capture
- -O stdout
-
- file name with optional path (default: “analysaeout.txt”)
- -G stdlog
- file name with optional path (default: “analysaelog.txt”)
- -E stderr
- file name with optional path (default: “analysaeerr.txt”)
- The
user interface 20 and thepacket server 16 may use a TCP data port and a TCP control port to communicate with each other. In operation, theuser interface 20 may first assess the connection port for the application configuration and control. In one embodiment, the control port at “localhost” is the TCP port “ANALYS_WH_UI_CONNECT” (localhost refers to thehost computer 12 on which theacquisition engine 10 is executing, and ANALYS_WH_UI_CONNECT is a compile-time constant for the default port number). - After the
user interface 20 connects to thepacket server 16 of theacquisition engine 10 via the ANALYS_WH_UI_CONNECT port, the other uni-directional data port number may be provided as a decimal number in ASCII text form. A negative number may indicate a stream allocation error or some other error condition. Theuser interface 20 may also display a list of USB devices attached to thepacket server 16. - The
user interface 20 can send configuration and control commands to thepacket server 16 using the configuration and control ports. If themessage server 16 accepts the command, it preferably responds with an acknowledgement. If the command contains an error or if thepacket server 16 is unable to complete the command for some reason, thepacket server 16 preferably responds with a negative acknowledgement along with a string of text specifying the reason. The table below provides an example set of control port commands thepacket server 16 may recognize: -
Command Description LIST_DEVICES Get a list of devices connected to the message server. Response is the device number (dd) and the serial number/id of device (dd) START dd Start the data stream through the data port for device dd STOP dd Stop the data stream through the data port for device dd FILTER Filter parameters - During operation of the
network analyzer 2, theacquisition engine 10 may provide a data stream to theuser interface 20 and/or thepacket clients 24 that includes data packets captured on several wireless channels as well as additional information useful in device and network diagnostics. For example, the data stream may include some or all of the fields Description (e.g., “802.15.4-DATA”), Packet Number (e.g., a continuously increasing 32-bit number to keep track of each captured packet), Date and Time, Timestamp, RSL, Packet Status, Channel, Byte Stream, USB Device Number. Additionally, the data stream may include a field USB Device Number to specify the USB device on which the packet was captured. - In some embodiments, the Date and Time field includes the ISO 8601 date string, a space character, and the ISO 8601 time string. The second field is immediately followed by a decimal point and the number of milliseconds. This configuration is similar to the output of the standard ANSI C library function strftime invoked with the format string of “% Y-% m-% d % H:% M:% S” with the addition of the milliseconds. Meanwhile, the field Elapsed Time may contain the number of milliseconds since the acquisition system was last reset. The elapsed time is reported every 8 μS and may have an accuracy of at least 8 μS. The time is preferably represented as a floating point number with three digits to the right of the decimal point. The value should not overflow for at least 48 hours.
- The RSL field may indicate the receive signal level for each packet, included to provide an estimate of a power level (in dB) of the signal for the received packet. This value may be represented and stored as a signed integer between −128 and +127.
- Further, the Packet Status may be an unsigned, 16-bit enumerated status of the packet. The status may indicate the following values, for example:
bit 0—Packet FCS Error;Bit 1—Bad receive byte count;Bit 2—Receiver overflow. Bits 3-15 are reserved. - Still further, the field Channel contains the decimal channel number as per the IEEE 802.15.4-2006 specifications. The field byte Stream preferably contains all of the bytes received in the data packet. Each byte may be separated by a space character and includes 2 hexadecimal characters.
- In general, all fields may be ASCII text separated by a comma, and the packet is preferably terminated by a line feed. An example of the resulting stream is:
- 1, 802.15.4-DATA, 10523, Jul. 16, 2007 14:04:31.261, 6581973.929 , −14, 0x0000, 23,
5B 41 882C 11 00 . . . equivalent). -
FIG. 14 provides another example of an advantageous configuration of components of thenetwork analyzer 2. In this embodiment, apacket client 24 connects to multiple instances of thepacket server 16. Eachpacket server 16 transmits a stream of data packets to thepacket client 24 so that thepacket client 24 can conveniently display information from multiple physical locations. Moreover, somepacket servers 16 may connect to multiple RF interfaces, as also illustrated inFIG. 14 . Thus, asingle packet client 24 can collect a relatively large amount of information related to multiple communication channels and physical locations. - Because the
packet client 24 illustrated inFIG. 14 may collect a relatively large amount of data, filtering functions may be further provided to select data packets based on various criteria such as transmission from or reception at a particular device. Referring back toFIG. 1 , for example, an operator may wish to see all data packets traveling through the device D2. He or she may accordingly select the appropriate filter and apply the selected filter to block all packets unrelated to D2. It is contemplated that this function may be particularly useful when verifying compliance of a particular device to the protocol (e.g., WirelessHART) of thenetwork 1. - It is also contemplated that the
network analyzer 2 may be used for automated test execution as well as test annotation. In particular, thepacket server 16 may be provisioned to execute predefined test scenarios in response to corresponding commands from apacket client 24. In other words, thenetwork analyzer 2 can process data packets addressed to thenetwork analyzer 2 itself. For example, packets can be used to instruct thenetwork analyzer 2 to start and stop recording data; to specify the name of the file to record the data; to provide cryptographic keys in use during the test may be used, etc. Thenetwork analyzer 2 may create a specific directory (e.g., on a memory disk of the host 12) to which thepacket server 16 may direct data packets collected in the course of executing the particular test scenario. In this manner, the amount of information which a human operator has to analyze manually may be significantly reduced. - Although the forgoing text sets forth a detailed description of numerous different embodiments, it should be understood that the scope of the patent is defined by the words of the claims set forth at the end of this patent. The detailed description is to be construed as exemplary only and does not describe every possible embodiment because describing every possible embodiment would be impractical, if not impossible. Numerous alternative embodiments could be implemented, using either current technology or technology developed after the filing date of this patent, which would still fall within the scope of the claims.
Claims (20)
1. A radio interface circuit for use in a wireless communication network analyzer that simultaneously captures communications on a plurality of radio frequency (RF) carriers, the radio interface circuit comprising:
an RF input to receive a signal associated with the plurality of RF carriers from an antenna;
a splitting module communicatively coupled to the RF input to split the received signal into a plurality of signals; wherein the splitting module includes a plurality of outputs at which the splitting module outputs the respective plurality of signals;
a plurality of radio transceivers, each coupled to a respective one of the plurality of outputs to process the plurality of signals in parallel and generate a respective plurality of data streams; and
a processing unit communicatively coupled to the plurality of radio transceivers to process data associated with the plurality of data streams.
2. The radio interface circuit of claim 1 , further comprising an amplifier disposed downstream of the RF input and upstream of the splitting module to amplify the received signal prior to splitting the received signal at the splitter.
3. The radio interface circuit of claim 1 , wherein the splitting module includes:
a first-stage splitter having an input coupled to the RF input, and a multiplicity of outputs; and
a multiplicity of second-stage splitters, each having an input coupled to a respective one of the multiplicity of outputs of the first-stage splitter, and a plurality of outputs; wherein the pluralities of outputs of the multiplicity of second-stage splitters define the plurality of outputs of the splitting module.
4. The radio interface circuit of claim 3 , wherein the splitting module further includes a multiplicity of second-stage amplifiers, each disposed between a respective one of the multiplicity of outputs and a respective one of the multiplicity of second-stage splitters.
5. The radio interface circuit of claim 1 , further comprising a packet controller coupled to the plurality of radio transceivers and to the processing unit, the packet controller configured to simultaneously process data packets included in the plurality of data streams to generate an output data stream, and to provide the output data stream to the processing unit.
6. The radio interface circuit of claim 1 , further comprising a clock source to generate a clock signal and provide the clock signal to each of the plurality of radio transceivers.
7. The radio interface circuit of claim 1 , further comprising a packet controller including:
a plurality of inputs, each coupled to a respective one of the plurality of radio transceivers;
a clock source to supply a periodic clock signal;
a plurality of independent state machines, each driven by the periodic clock signal and coupled to a respective one of the plurality of inputs to simultaneously process a respective one of the plurality of data streams; and
a multiplexer coupled to the plurality of independent state machines to provide an output data stream that includes data packets from the plurality of data streams; wherein the output data stream is provided to the processing unit.
8. The radio interface circuit of claim 1 , further comprising a packet controller including:
a plurality of inputs to receive a respective plurality of data packet start signals from the plurality of radio transceivers, each of the plurality of data packet start signals being indicative of a start of reception of a data packet by a respective one of the plurality of radio transceivers;
a plurality of independent processing modules coupled to the respective plurality of inputs to simultaneously process the plurality of data packet start signals, wherein each of the plurality of independent processing modules implements a respective state machine driven by a periodic clock signal to process a respective data packet start signal independently of every other one of the plurality of processing modules; and
an output to transmit an output signal indicative of a presence of at least one data packet on one or more of the plurality of RF carriers.
9. The radio interface circuit of claim 8 , wherein the packet controller further comprises a mode selection input to receive a selection signal from the processing unit to select between at least a receive mode and a control mode of operation of the packet controller, wherein:
the receive mode corresponds to receiving data packets from the plurality of radio transceivers and forwarding the received data packets to the processing unit, and
the control mode corresponds to receiving control data from the processing unit and forwarding the received control data to a specified one of the plurality of radio transceivers.
10. The radio interface circuit of claim 8 , wherein the plurality of inputs is a first plurality of inputs and the output is a first output, and wherein the packet controller further-comprises:
a second plurality of inputs to receive a respective plurality of data packet signals from the respective plurality of radio transceivers, each of the plurality of data packet signals conveying the data packet received by the respective one of the plurality of radio transceivers on the respective one of the plurality of RF carriers;
a multiplexer coupled to the plurality of independent processing modules; and
a second output coupled to the multiplexer to transmit the data packets received on the plurality of RF carriers.
11. The radio interface circuit of claim 8 , wherein:
the periodic clock signal is a first periodic clock signal provided by a first clock source having a first clock cycle duration;
the packet controller is further configured to receive a second periodic clock signal provided by a second clock source having a second clock cycle duration shorter than the first clock cycle duration;
the first periodic clock signal drives state transitions of each of the plurality of independent processing modules, and
the second periodic clock signal is used to execute instructions in each of the plurality of independent processing modules.
12. The radio interface circuit of claim 8 , wherein the plurality of inputs is a first plurality of inputs, and the packet controller further comprises a second plurality of inputs to receive a respective plurality of data packet end signals from the plurality of radio transceivers, each of the plurality of data packet end signals being indicative of an end of reception of the data packet by the respective one of the plurality of radio transceivers.
13. A method for a wireless communication network analyzer to simultaneously capture communications on a plurality of radio frequency (RF) carriers, the method comprising:
receiving, at the wireless communication network analyzer, an RF input associated with the plurality of RF carriers;
splitting, by the wireless communication network analyzer, the received RF input into a plurality of signals;
providing the plurality of signals to a plurality of radio transceivers of the wireless communication network analyzer;
generating, in parallel by the plurality of radio transceivers, a respective plurality of data streams from the plurality of signals; and
processing, by the wireless communication network analyzer, the respective plurality of data streams to generate process data.
14. The method of claim 13 , wherein receiving the RF input comprises receiving the RF input using a single antenna of the wireless communication network analyzer.
15. The method of claim 13 , wherein at least one of:
splitting the received RF input comprises splitting the received RF input into a plurality of copies of the received RF input;
splitting the received RF input comprises splitting the received RF input using multiple stages of splitting; or
the method further comprises amplifying the received RF input prior to splitting the received RF input.
16. The method of claim 13 , further comprising generating, by each of the plurality of radio transceivers at least one of: (i) a respective packet start signal indicative of a beginning of a data packet included in a respective data stream, or (ii) a packet end signal indicative of an end of the data packet.
17. The method of claim 13 , wherein processing the respective plurality of data streams to generate the process data comprises processing the respective plurality of data streams in parallel.
18. The method of claim 17 , wherein processing the respective plurality of data streams in parallel comprises simultaneously driving a plurality of state machines using a periodic clock signal to retrieve data packets corresponding to a respective plurality of data packet start signals corresponding to respective data packets included in the plurality of data streams.
19. The method of claim 18 , wherein each of the plurality of state machines corresponds to a respective one of the plurality of RF carriers and uses a respective one of the plurality of data streams.
20. The method of claim 13 , wherein processing the respective plurality of data streams to generate the process data comprises multiplexing the plurality of data streams into a single data stream including the process data.
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130122946A1 (en) * | 2011-11-11 | 2013-05-16 | Fujitsu Limited | System and method for selecting transceivers to provide wireless communication service for a wireless user endpoint |
US20160132440A1 (en) * | 2014-11-11 | 2016-05-12 | Microchip Technology Incorporated | Multi-channel i2s transmit control system and method |
RU2762040C1 (en) * | 2020-11-06 | 2021-12-15 | СВИ Коммуникатионс-унд Компутер ГмбХ | System for combining digital streams and method for combining digital streams (variants) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9730078B2 (en) * | 2007-08-31 | 2017-08-08 | Fisher-Rosemount Systems, Inc. | Configuring and optimizing a wireless mesh network |
US8121826B1 (en) * | 2009-07-17 | 2012-02-21 | Xilinx, Inc. | Graphical user interface for system design |
JP5573053B2 (en) * | 2009-09-04 | 2014-08-20 | ソニー株式会社 | Wireless communication apparatus and wireless communication method |
US8351404B2 (en) * | 2009-09-25 | 2013-01-08 | Nigel Iain Stuart Macrae | Method and apparatus for multiple accesses to a communications channel |
US8363693B2 (en) * | 2010-04-16 | 2013-01-29 | Hitachi, Ltd. | Adaptive frequency hopping in time-slotted based wireless network |
US9176919B2 (en) * | 2012-06-06 | 2015-11-03 | Honeywell International Inc. | Process controller having multi-channel serial communications link |
US9418037B2 (en) * | 2012-07-11 | 2016-08-16 | Infineon Technologies Ag | SPI interface and method for serial communication via an SPI interface having an SPI protocol handler for evaluating signal transitions of SPI signals |
WO2014070883A2 (en) | 2012-10-30 | 2014-05-08 | Jds Uniphase Corporation | Method and system for identifying matching packets |
JP6094562B2 (en) | 2014-11-06 | 2017-03-15 | 横河電機株式会社 | Recorder |
WO2017026249A1 (en) * | 2015-08-07 | 2017-02-16 | ソニー株式会社 | Reception device and data processing method |
MX2018001345A (en) * | 2015-08-07 | 2018-06-15 | Sony Corp | Receiving device and data processing method. |
JPWO2017138620A1 (en) * | 2016-02-09 | 2018-11-29 | 株式会社東芝 | Memory device, edge device for handling storable data, and data management method |
US10277384B2 (en) * | 2017-04-04 | 2019-04-30 | Cisco Technology, Inc. | Intermediate distribution frame for distributed radio heads |
US9734099B1 (en) * | 2017-04-27 | 2017-08-15 | Micro Lambda Wireless, Inc. | QSPI based methods of simultaneously controlling multiple SPI peripherals |
CN107144751B (en) * | 2017-06-09 | 2020-06-09 | 中国电子科技集团公司第四十一研究所 | Multi-channel vector network parameter analysis system and method |
FR3068797B1 (en) * | 2017-07-04 | 2019-07-19 | STMicroelectronics (Grand Ouest) SAS | METHOD OF COMMUNICATION BETWEEN A MASTER DEVICE AND N SLAVES CONNECTED ON A SYNCHRONOUS DATA BUS OF THE SPI TYPE AND CORRESPONDING DEVICE |
US10484109B2 (en) * | 2018-02-22 | 2019-11-19 | Rohde & Schwarz Gmbh & Co. Kg | Test arrangement and test method |
CN111630504A (en) * | 2018-12-19 | 2020-09-04 | 美光科技公司 | Memory devices having different physical sizes, memory formats, and operational capabilities, modules, and systems having memory devices |
EP3709177B1 (en) * | 2019-03-13 | 2021-03-03 | Axis AB | Serial peripheral interface master |
JP7242389B2 (en) * | 2019-04-11 | 2023-03-20 | 株式会社東芝 | Packet generator and method |
US11418969B2 (en) | 2021-01-15 | 2022-08-16 | Fisher-Rosemount Systems, Inc. | Suggestive device connectivity planning |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8072983B2 (en) * | 2006-11-01 | 2011-12-06 | Huawei Technologies Co., Ltd. | Method and apparatus for dispatching signals in an optical transport network |
Family Cites Families (154)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0771097B2 (en) | 1985-12-20 | 1995-07-31 | 株式会社日立製作所 | Time division multiplex communication system |
US5159592A (en) | 1990-10-29 | 1992-10-27 | International Business Machines Corporation | Network address management for a wired network supporting wireless communication to a plurality of mobile users |
US5459855A (en) * | 1992-08-10 | 1995-10-17 | Hewlett-Packard Company | Frequency ratio detector for determining fixed frequency ratios in a computer system |
ATE187824T1 (en) * | 1994-10-24 | 2000-01-15 | Fisher Rosemount Systems Inc | DEVICE THAT ALLOWS ACCESS TO FIELD DEVICES IN A DISTRIBUTED CONTROL SYSTEM |
US5535193A (en) * | 1995-02-09 | 1996-07-09 | Wandel & Goltermann Technologies, Inc. | Multiport analyzing with time stamp synchronizing |
US5719859A (en) * | 1995-09-19 | 1998-02-17 | Matsushita Electric Industrial Co., Ltd. | Time division multiple access radio communication system |
US5781549A (en) * | 1996-02-23 | 1998-07-14 | Allied Telesyn International Corp. | Method and apparatus for switching data packets in a data network |
US6901299B1 (en) * | 1996-04-03 | 2005-05-31 | Don Whitehead | Man machine interface for power management control systems |
US6701361B1 (en) * | 1996-08-22 | 2004-03-02 | Intermec Ip Corp. | Enhanced mobility and address resolution in a wireless premises based network |
US6424872B1 (en) * | 1996-08-23 | 2002-07-23 | Fieldbus Foundation | Block oriented control system |
US6233327B1 (en) * | 1997-02-14 | 2001-05-15 | Statsignal Systems, Inc. | Multi-function general purpose transceiver |
US7137550B1 (en) | 1997-02-14 | 2006-11-21 | Statsignal Ipc, Llc | Transmitter for accessing automated financial transaction machines |
US6628764B1 (en) | 1997-02-14 | 2003-09-30 | Statsignal Systems, Inc. | System for requesting service of a vending machine |
US7079810B2 (en) * | 1997-02-14 | 2006-07-18 | Statsignal Ipc, Llc | System and method for communicating with a remote communication unit via the public switched telephone network (PSTN) |
US6618578B1 (en) | 1997-02-14 | 2003-09-09 | Statsignal Systems, Inc | System and method for communicating with a remote communication unit via the public switched telephone network (PSTN) |
US5926531A (en) * | 1997-02-14 | 1999-07-20 | Statsignal Systems, Inc. | Transmitter for accessing pay-type telephones |
US6430268B1 (en) * | 1997-09-20 | 2002-08-06 | Statsignal Systems, Inc. | Systems for requesting service of a vending machine |
US6198751B1 (en) * | 1997-11-19 | 2001-03-06 | Cabletron Systems, Inc. | Multi-protocol packet translator |
US6457038B1 (en) | 1998-03-19 | 2002-09-24 | Isochron Data Corporation | Wide area network operation's center that sends and receives data from vending machines |
FI114745B (en) | 1998-06-01 | 2004-12-15 | Metso Automation Oy | Control systems for field devices |
US6218953B1 (en) * | 1998-10-14 | 2001-04-17 | Statsignal Systems, Inc. | System and method for monitoring the light level around an ATM |
US6891838B1 (en) | 1998-06-22 | 2005-05-10 | Statsignal Ipc, Llc | System and method for monitoring and controlling residential devices |
US6028522A (en) * | 1998-10-14 | 2000-02-22 | Statsignal Systems, Inc. | System for monitoring the light level around an ATM |
US6522974B2 (en) * | 2000-03-01 | 2003-02-18 | Westerngeco, L.L.C. | Method for vibrator sweep analysis and synthesis |
US6914893B2 (en) | 1998-06-22 | 2005-07-05 | Statsignal Ipc, Llc | System and method for monitoring and controlling remote devices |
US6437692B1 (en) * | 1998-06-22 | 2002-08-20 | Statsignal Systems, Inc. | System and method for monitoring and controlling remote devices |
US6914533B2 (en) | 1998-06-22 | 2005-07-05 | Statsignal Ipc Llc | System and method for accessing residential monitoring devices |
US20060062250A1 (en) * | 1998-06-26 | 2006-03-23 | Payne William A Iii | Method for wireless access system supporting multiple frame types |
US7103511B2 (en) | 1998-10-14 | 2006-09-05 | Statsignal Ipc, Llc | Wireless communication networks for providing remote monitoring of devices |
US20020013679A1 (en) | 1998-10-14 | 2002-01-31 | Petite Thomas D. | System and method for monitoring the light level in a lighted area |
US7640007B2 (en) * | 1999-02-12 | 2009-12-29 | Fisher-Rosemount Systems, Inc. | Wireless handheld communicator in a process control environment |
US6747557B1 (en) * | 1999-03-18 | 2004-06-08 | Statsignal Systems, Inc. | System and method for signaling a weather alert condition to a residential environment |
US20040183687A1 (en) | 1999-03-18 | 2004-09-23 | Petite Thomas D. | System and method for signaling a weather alert condition to a residential environment |
EP1169690A2 (en) | 1999-03-18 | 2002-01-09 | Statsignal Systems, Inc. | System for monitoring conditions in a residential living community |
US7650425B2 (en) | 1999-03-18 | 2010-01-19 | Sipco, Llc | System and method for controlling communication between a host computer and communication devices associated with remote devices in an automated monitoring system |
JP2000339345A (en) * | 1999-03-25 | 2000-12-08 | Sony Corp | Retrieval system, retrieval device, retrieval method, input device and input method |
US6532507B1 (en) * | 1999-05-28 | 2003-03-11 | National Semiconductor Corporation | Digital signal processor and method for prioritized access by multiple core processors to shared device |
US6487403B2 (en) | 1999-08-19 | 2002-11-26 | Verizon Laboratories Inc. | Wireless universal provisioning device |
US7002958B1 (en) * | 1999-09-10 | 2006-02-21 | Pluris, Inc. | Method for load-balancing with FIFO guarantees in multipath networks |
US6836477B1 (en) | 1999-12-23 | 2004-12-28 | Tekelec | Methods and systems for routing messages in a communications network |
US6996100B1 (en) * | 2000-02-03 | 2006-02-07 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and system for medium access on a radio channel |
JP2001313672A (en) * | 2000-04-28 | 2001-11-09 | Toshiba Corp | Network system, packet repeater, wireless terminal and packet processing method |
US6996065B2 (en) * | 2000-07-06 | 2006-02-07 | Lucent Technologies Inc. | Dynamic backup routing of network tunnel paths for local restoration in a packet network |
US6721779B1 (en) * | 2000-07-07 | 2004-04-13 | Softwired Ag | Messaging proxy system |
FI114507B (en) | 2000-07-07 | 2004-10-29 | Metso Automation Oy | System for diagnostics of a device |
US6643504B1 (en) * | 2000-07-10 | 2003-11-04 | At&T Corp. | Automatic wireless service activation in a private local wireless system |
US6836737B2 (en) | 2000-08-09 | 2004-12-28 | Statsignal Systems, Inc. | Systems and methods for providing remote monitoring of consumption for a utility meter |
DE10042165C1 (en) * | 2000-08-17 | 2002-04-18 | Butzke Werke Aqua | System for controlling and monitoring sanitary fittings |
GB0021440D0 (en) * | 2000-08-31 | 2000-11-01 | Cit Alcatel | An optical signal processor |
US7519011B2 (en) | 2000-09-29 | 2009-04-14 | Intel Corporation | Frame structure for radio communications system |
US20020031101A1 (en) * | 2000-11-01 | 2002-03-14 | Petite Thomas D. | System and methods for interconnecting remote devices in an automated monitoring system |
US7870196B2 (en) * | 2000-11-08 | 2011-01-11 | Nokia Corporation | System and methods for using an application layer control protocol transporting spatial location information pertaining to devices connected to wired and wireless internet protocol networks |
US20030026268A1 (en) * | 2000-11-28 | 2003-02-06 | Siemens Technology-To-Business Center, Llc | Characteristic routing |
US6920171B2 (en) * | 2000-12-14 | 2005-07-19 | Motorola, Inc. | Multiple access frequency hopping network with interference anticipation |
WO2002063806A2 (en) | 2001-02-07 | 2002-08-15 | Xtremespectrum, Inc. | System, method, and computer program product for sharing bandwidth in a wireless personal area network or a wireless local area network |
US6937861B2 (en) * | 2001-02-13 | 2005-08-30 | Telefonaktiebolaget Lm Ericsson (Publ) | Connection management for dual mode access terminals in a radio network |
DE10109196B4 (en) * | 2001-02-26 | 2005-04-28 | Viessmann Werke Kg | Apparatus and method for remote monitoring and parameterization of equipment, in particular of heating systems |
US7075536B1 (en) | 2001-07-13 | 2006-07-11 | Cisco Technology, Inc. | Incremental plotting of network topologies and other graphs through use of markup language |
US20030014535A1 (en) * | 2001-07-16 | 2003-01-16 | Oscar Mora | Collision avoidance method for home automation devices using an ethernet hub |
US6959356B2 (en) | 2001-07-30 | 2005-10-25 | Fisher-Rosemount Systems, Inc. | Multi-protocol field device and communication method |
US7346463B2 (en) * | 2001-08-09 | 2008-03-18 | Hunt Technologies, Llc | System for controlling electrically-powered devices in an electrical network |
US7542867B2 (en) * | 2001-08-14 | 2009-06-02 | National Instruments Corporation | Measurement system with modular measurement modules that convey interface information |
EP1293853A1 (en) | 2001-09-12 | 2003-03-19 | ENDRESS + HAUSER WETZER GmbH + Co. KG | Transceiver module for a field device |
ES2292847T3 (en) * | 2001-09-27 | 2008-03-16 | Telefonaktiebolaget Lm Ericsson (Publ) | RUNNING METHOD FOR MULTIPLE JUMPS FOR DISTRIBUTED WLAN NETWORKS. |
US6970909B2 (en) | 2001-10-11 | 2005-11-29 | The Trustees Of Columbia University In The City Of New York | Multi-protocol data communication system supporting wireless telephony and content delivery |
US6801777B2 (en) | 2001-11-27 | 2004-10-05 | Intel Corporation | Device and method for intelligent wireless communication selection |
DE50303574D1 (en) * | 2002-03-08 | 2006-07-06 | Epcos Ag | METHOD AND DEVICE FOR INFLUENCING VOLATILE LIQUIDS IN HOUSINGS OF ELECTRICAL COMPONENTS AND FOR CLOSING THE HOUSINGS |
US7920897B2 (en) * | 2002-03-14 | 2011-04-05 | Intel Corporation | Interference suppression in computer radio modems |
US7079856B2 (en) | 2002-04-05 | 2006-07-18 | Lucent Technologies Inc. | Data flow control between a base station and a mobile station |
US6765905B2 (en) | 2002-04-18 | 2004-07-20 | Motorola, Inc. | Method for reducing packet data delay variation in an internet protocol network |
CN1653755A (en) * | 2002-04-18 | 2005-08-10 | 沙诺夫股份有限公司 | Method and apparatus for providing ad-hoc networked sensors and protocols |
US7764617B2 (en) | 2002-04-29 | 2010-07-27 | Harris Corporation | Mobile ad-hoc network and methods for performing functions therein based upon weighted quality of service metrics |
JP4133001B2 (en) * | 2002-06-12 | 2008-08-13 | シャープ株式会社 | Wireless communication system |
DE50211013D1 (en) * | 2002-09-11 | 2007-11-15 | Tektronix Int Sales Gmbh | Method and device for monitoring a data transmission |
KR100511295B1 (en) * | 2002-10-30 | 2005-08-31 | 엘지전자 주식회사 | A filter structure and a operating method there of for multi channel poly phase interpolation psf fir |
KR100561393B1 (en) * | 2002-11-30 | 2006-03-16 | 삼성전자주식회사 | Media access control method in the wireless network and apparatus thereof |
FR2850250B1 (en) | 2003-01-27 | 2005-03-25 | Lee Sara Corp | METHOD OF ASSEMBLING EDGE ON BOARD OF TWO TEXTILE PIECES |
US6904327B2 (en) * | 2003-01-29 | 2005-06-07 | Honeywell International Inc. | Integrated control system to control addressable remote devices |
JP2006520137A (en) * | 2003-02-18 | 2006-08-31 | エクストリコム リミティド | Multiplexing between access point and hub |
KR100948383B1 (en) | 2003-03-04 | 2010-03-22 | 삼성전자주식회사 | Method of allocatng ip address and detecting duplication of ip address in ad hoc netwok |
WO2004107673A1 (en) * | 2003-05-27 | 2004-12-09 | International Business Machines Corporation | System for defining an alternate channel routing mechanism in a messaging middleware environment |
US20040242249A1 (en) * | 2003-05-30 | 2004-12-02 | Neilson Paul Christian | Non-interfering multipath communications systems |
US7436797B2 (en) | 2003-06-18 | 2008-10-14 | Fisher-Rosemount Systems, Inc. | Wireless architecture and support for process control systems |
US7460865B2 (en) | 2003-06-18 | 2008-12-02 | Fisher-Rosemount Systems, Inc. | Self-configuring communication networks for use with process control systems |
US7295519B2 (en) | 2003-06-20 | 2007-11-13 | Motorola, Inc. | Method of quality of service based flow control within a distributed switch fabric network |
US7336642B2 (en) * | 2003-08-07 | 2008-02-26 | Skypilot Networks, Inc. | Communication protocol for a wireless mesh architecture |
US7225037B2 (en) * | 2003-09-03 | 2007-05-29 | Unitronics (1989) (R″G) Ltd. | System and method for implementing logic control in programmable controllers in distributed control systems |
US7436789B2 (en) * | 2003-10-09 | 2008-10-14 | Sarnoff Corporation | Ad Hoc wireless node and network |
US7680033B1 (en) * | 2003-10-20 | 2010-03-16 | Ciena Corporation | Network manager circuit rediscovery and repair |
JP4290529B2 (en) * | 2003-11-07 | 2009-07-08 | 株式会社バッファロー | Access point, terminal, encryption key setting system, encryption key setting method, and program |
JP4193678B2 (en) | 2003-11-10 | 2008-12-10 | 沖電気工業株式会社 | Communication terminal and communication network |
US7191021B2 (en) * | 2003-12-04 | 2007-03-13 | Honeywell International | Remote management of field devices in a manufacturing plant |
US7818018B2 (en) | 2004-01-29 | 2010-10-19 | Qualcomm Incorporated | Distributed hierarchical scheduling in an AD hoc network |
EP1714446A1 (en) | 2004-02-09 | 2006-10-25 | Packethop, Inc. | Reliable message distribution with enhanced emfc for ad hoc mesh networks |
US7216365B2 (en) * | 2004-02-11 | 2007-05-08 | Airtight Networks, Inc. | Automated sniffer apparatus and method for wireless local area network security |
KR101010774B1 (en) | 2004-02-11 | 2011-01-25 | 엘지전자 주식회사 | Method for discontinuously transmitting and receiving point-to-multipoint service data in mobile communication system |
CA2558323A1 (en) | 2004-03-25 | 2005-10-06 | Research In Motion Limited | Wireless access point methods and apparatus for reduced power consumption and cost |
US7881239B2 (en) | 2004-03-27 | 2011-02-01 | Dust Networks, Inc. | Low-powered autonomous radio node with temperature sensor and crystal oscillator |
US8194655B2 (en) * | 2004-08-05 | 2012-06-05 | Dust Networks, Inc. | Digraph based mesh communication network |
US7529217B2 (en) * | 2004-03-27 | 2009-05-05 | Dust Networks, Inc. | Low-power autonomous node for mesh communication network |
WO2005096722A2 (en) | 2004-03-27 | 2005-10-20 | Dust Networks | Digraph based mesh communication network |
US7420980B1 (en) | 2004-03-27 | 2008-09-02 | Dust Networks, Inc. | Digraph network superframes |
US20050228509A1 (en) | 2004-04-07 | 2005-10-13 | Robert James | System, device, and method for adaptively providing a fieldbus link |
KR100595984B1 (en) * | 2004-04-12 | 2006-07-03 | 한국전력공사 | Transceiver Frame Structure for Control Communication Network of Distributed Control System |
US7454173B2 (en) | 2004-04-23 | 2008-11-18 | Telefonaktiebolaget L M Ericsson (Publ) | Load control in shared medium many-to-one communication systems |
US7697893B2 (en) | 2004-06-18 | 2010-04-13 | Nokia Corporation | Techniques for ad-hoc mesh networking |
JP2006013612A (en) * | 2004-06-22 | 2006-01-12 | Traffic Shimu:Kk | Data monitoring system and program, recording medium, display operating method |
US8441935B2 (en) * | 2004-08-09 | 2013-05-14 | Jds Uniphase Corporation | Method and apparatus to distribute signaling data for parallel analysis |
US7606213B2 (en) * | 2004-08-12 | 2009-10-20 | Qualcomm Incorporated | Wireless MAC layer throughput improvements |
US8098676B2 (en) * | 2004-08-12 | 2012-01-17 | Intel Corporation | Techniques to utilize queues for network interface devices |
US20060045016A1 (en) * | 2004-08-31 | 2006-03-02 | Dawdy Jay J | Method and apparatus for managing packet data network loading |
US20060067280A1 (en) * | 2004-09-29 | 2006-03-30 | Howard John S | Wireless medium access control protocol with micro-scheduling |
US20060077917A1 (en) * | 2004-10-07 | 2006-04-13 | Honeywell International Inc. | Architecture and method for enabling use of wireless devices in industrial control |
US7853221B2 (en) | 2004-11-12 | 2010-12-14 | Homerun Holdings Corp. | Network bridge device and methods for programming and using the same |
US20060120384A1 (en) * | 2004-12-08 | 2006-06-08 | International Business Machines Corporation | Method and system for information gathering and aggregation in dynamic distributed environments |
ATE364291T1 (en) * | 2005-01-28 | 2007-06-15 | Research In Motion Ltd | AUTOMATIC INTEGRATION OF CONTENT FROM MULTIPLE STORES USING A MOBILE COMMUNICATIONS DEVICE |
US7586888B2 (en) * | 2005-02-17 | 2009-09-08 | Mobitrum Corporation | Method and system for mesh network embedded devices |
DE102005008488B4 (en) * | 2005-02-24 | 2011-08-18 | VEGA Grieshaber KG, 77709 | Data transmission system for wireless communication |
US7899027B2 (en) | 2005-03-23 | 2011-03-01 | Cisco Technology, Inc. | Automatic route configuration in hierarchical wireless mesh networks |
US7975300B2 (en) * | 2005-04-15 | 2011-07-05 | Toshiba America Research, Inc. | Secure isolation and recovery in wireless networks |
JP4763334B2 (en) | 2005-04-28 | 2011-08-31 | ルネサスエレクトロニクス株式会社 | Wireless ad hoc communication system and communication terminal synchronization method in wireless ad hoc communication system |
US20060253584A1 (en) | 2005-05-03 | 2006-11-09 | Dixon Christopher J | Reputation of an entity associated with a content item |
JP2006318148A (en) | 2005-05-12 | 2006-11-24 | Yokogawa Electric Corp | Field equipment control system |
US8473673B2 (en) * | 2005-06-24 | 2013-06-25 | Hewlett-Packard Development Company, L.P. | Memory controller based (DE)compression |
US7375594B1 (en) * | 2005-07-12 | 2008-05-20 | Dust Networks, Inc. | Radio oscillator tuning |
KR101199752B1 (en) * | 2005-09-08 | 2012-11-08 | 더 유니버시티 코트 오브 더 유니버시티 오브 에딘버그 | Hybrid wireless communication system and communicating method thereof |
US7869378B2 (en) * | 2005-09-26 | 2011-01-11 | Interdigital Technology Corporation | Method and apparatus for sharing slot allocation schedule information amongst nodes of a wireless mesh network |
US8014404B2 (en) * | 2005-09-30 | 2011-09-06 | Motorola Solutions, Inc. | Method and system for priority based routing |
US8065680B2 (en) * | 2005-11-15 | 2011-11-22 | Yahoo! Inc. | Data gateway for jobs management based on a persistent job table and a server table |
US8270413B2 (en) * | 2005-11-28 | 2012-09-18 | Cisco Technology, Inc. | Method and apparatus for self-learning of VPNS from combination of unidirectional tunnels in MPLS/VPN networks |
US7730385B2 (en) * | 2005-11-30 | 2010-06-01 | Motorola, Inc. | Method for decoding a received control channel message with a priori information |
US7827545B2 (en) * | 2005-12-15 | 2010-11-02 | Microsoft Corporation | Dynamic remediation of a client computer seeking access to a network with a quarantine enforcement policy |
US8306026B2 (en) | 2005-12-15 | 2012-11-06 | Toshiba America Research, Inc. | Last hop topology sensitive multicasting key management |
WO2007082015A2 (en) * | 2006-01-11 | 2007-07-19 | Fisher-Rosemount Systems, Inc. | Control of low power wireless networks for power conservation |
JP4697431B2 (en) * | 2006-01-26 | 2011-06-08 | 日本電気株式会社 | Radio wave monitoring apparatus and method, radio wave monitoring program |
US7848827B2 (en) | 2006-03-31 | 2010-12-07 | Honeywell International Inc. | Apparatus, system, and method for wireless diagnostics |
US7492739B2 (en) | 2006-04-05 | 2009-02-17 | Motorola, Inc. | Method for enhancing the communication capability in a wireless telecommunication system |
US8170572B2 (en) | 2006-04-14 | 2012-05-01 | Qualcomm Incorporated | Methods and apparatus for supporting quality of service in communication systems |
US8266602B2 (en) | 2006-05-31 | 2012-09-11 | Honeywell International Inc. | Apparatus and method for converting between device description languages in a process control system |
US7889747B2 (en) | 2006-05-31 | 2011-02-15 | Honeywell International Inc. | Apparatus, system, and method for integrating a wireless network with wired field devices in a process control system |
US7675935B2 (en) * | 2006-05-31 | 2010-03-09 | Honeywell International Inc. | Apparatus and method for integrating wireless or other field devices in a process control system |
US7965664B2 (en) | 2006-05-31 | 2011-06-21 | Honeywell International Inc. | Apparatus and method for integrating wireless field devices with a wired protocol in a process control system |
US7747416B2 (en) | 2006-06-06 | 2010-06-29 | Siemens Industry, Inc. | System and method for batch process control with diverse distributed control system protocols |
US7706283B2 (en) * | 2006-09-25 | 2010-04-27 | Mitsubishi Electric Research Laboratories, Inc. | Decentralized and dynamic route selection in cooperative relay networks |
US8005020B2 (en) * | 2006-09-29 | 2011-08-23 | Rosemount Inc. | Wireless mesh network with multisized timeslots for TDMA communication |
US8505036B2 (en) * | 2006-09-29 | 2013-08-06 | Fisher-Rosemount Systems, Inc. | Unified application programming interface for a process control system network |
US8028045B2 (en) * | 2006-09-29 | 2011-09-27 | Rockwell Automation Technologies, Inc. | Web-based configuration server for automation systems |
JP2008103988A (en) * | 2006-10-19 | 2008-05-01 | Fujitsu Ltd | Encryption communication system, device, method and program |
US7924793B2 (en) * | 2006-11-20 | 2011-04-12 | At&T Intellectual Property I, L.P. | Methods and apparatus to manage bandwidth in a wireless network |
US20080120676A1 (en) * | 2006-11-22 | 2008-05-22 | Horizon Semiconductors Ltd. | Integrated circuit, an encoder/decoder architecture, and a method for processing a media stream |
BRPI0721002A2 (en) | 2006-12-22 | 2014-07-29 | Qualcomm Inc | ENHANCED WIRELESS USB PROTOCOL AND HUB |
US20080192812A1 (en) * | 2007-02-09 | 2008-08-14 | Marco Naeve | Wireless communication adapter for a programmable logic controller and programmable logic controller system including the same |
US20080198860A1 (en) | 2007-02-15 | 2008-08-21 | Microsoft Corporation | Enabling routing of data on a network based on a portion of data accessed from a non-network enabled device |
US8351369B2 (en) * | 2007-12-12 | 2013-01-08 | Synapsense Corporation | Apparatus and method for adaptive data packet scheduling in mesh networks |
-
2009
- 2009-06-23 JP JP2011516549A patent/JP2011527146A/en active Pending
- 2009-06-23 CN CN2009801307989A patent/CN102113367B/en not_active Expired - Fee Related
- 2009-06-23 EP EP09798505.5A patent/EP2294858A4/en not_active Withdrawn
- 2009-06-23 WO PCT/US2009/048342 patent/WO2010008867A2/en active Application Filing
- 2009-06-23 US US12/490,205 patent/US8441947B2/en active Active
-
2013
- 2013-04-04 US US13/856,536 patent/US20130223259A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8072983B2 (en) * | 2006-11-01 | 2011-12-06 | Huawei Technologies Co., Ltd. | Method and apparatus for dispatching signals in an optical transport network |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130122946A1 (en) * | 2011-11-11 | 2013-05-16 | Fujitsu Limited | System and method for selecting transceivers to provide wireless communication service for a wireless user endpoint |
US8914053B2 (en) * | 2011-11-11 | 2014-12-16 | Fujitsu Limited | System and method for selecting transceivers to provide wireless communication service for a wireless user endpoint |
US20160132440A1 (en) * | 2014-11-11 | 2016-05-12 | Microchip Technology Incorporated | Multi-channel i2s transmit control system and method |
US9842071B2 (en) * | 2014-11-11 | 2017-12-12 | Microchip Technology Incorporated | Multi-channel I2S transmit control system and method |
RU2762040C1 (en) * | 2020-11-06 | 2021-12-15 | СВИ Коммуникатионс-унд Компутер ГмбХ | System for combining digital streams and method for combining digital streams (variants) |
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EP2294858A4 (en) | 2014-07-02 |
WO2010008867A2 (en) | 2010-01-21 |
JP2011527146A (en) | 2011-10-20 |
EP2294858A2 (en) | 2011-03-16 |
WO2010008867A3 (en) | 2010-04-15 |
US8441947B2 (en) | 2013-05-14 |
CN102113367B (en) | 2013-11-20 |
CN102113367A (en) | 2011-06-29 |
US20100110916A1 (en) | 2010-05-06 |
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