CN115801637A - Data packet receiving and transmitting time delay measuring method and system - Google Patents

Abstract

The invention discloses a method and a system for measuring the time delay of data packet receiving and sending, wherein the method comprises the following steps: configuring a timestamp value and a value of a transmitting circuit and a receiving circuit to a register; the transmitting circuit transmits the real-time data packet to a WRS; the WRS sends a real-time data packet to a receiving circuit; the PC machine obtains a measurement result by monitoring data packets of the transmitting circuit and the receiving circuit through the WRS. The invention records the time stamp based on the FPGA hardware scheme on the basis of the PTP protocol, and records the time from sending to receiving of the real-time data packet, so that the PTP protocol can get rid of the limitation, can run in a background in a non-real-time operating system, and occupies less resources. The invention realizes the process of transmitting and receiving the real-time data packet based on the LXI standard, gives consideration to real-time triggering and real-time measurement, designs two real-time protocol types of triggering and event, ensures the ultrahigh real-time property required by triggering, and reduces the background noise.

Description

Data packet receiving and transmitting time delay measuring method and system

Technical Field

The invention relates to the technical field of internet communication, in particular to a method and a system for measuring the time delay of data packet receiving and transmitting.

Background

The LXI standard is based on LAN, is established on the IEEE802.3 and IEEE1588 protocols, and is an extension of mature Ethernet technology in the test field. LXI has two communication modes, one is point-to-point, and data packets are continuously transmitted through TCP; the other is a one-to-many broadcast form, and the data packets are transmitted in a UDP broadcast form. The LXI standard provides five triggering synchronization modes, wherein IEEE1588 time-based synchronization is the main characteristic of the LXI standard, but at present, LXI instruments are few in types and poor in universality, and functions of the LXI instruments cannot be modularly customized. Meanwhile, the difference between real-time triggering and real-time measurement is large, and the method is not suitable for constructing a distributed large-scale test system.

Disclosure of Invention

The embodiment of the invention provides a method and a system for measuring the receiving and sending time delay of a data packet, which are used for solving the problems that the universality of LXI (local X-ray inspection) is poor, the real-time triggering and real-time measurement are not accurate enough, and a distributed large-scale test system is not suitable to be constructed in the prior art.

In one aspect, an embodiment of the present invention provides a method for measuring a time delay between receiving and transmitting a data packet, including:

configuring a time stamp value and a value of a transmitting circuit and a time stamp value and a value of a receiving circuit to registers;

the transmitting circuit transmits a real-time data packet to a WRS (write driver switching system);

the WRS sends a real-time data packet to the receiving circuit;

and the PC machine obtains a measurement result by monitoring the data packets of the transmitting circuit and the receiving circuit through the WRS at the same time.

In one possible implementation, the timestamp is based on the PTP protocol, and the timestamp is recorded using FPGA hardware.

In a possible implementation manner, the sending circuit is provided with a data sending module, and a real-time data packet sent by the data sending module is transmitted by using a UDP protocol.

In a possible implementation manner, the receiving circuit is provided with a data receiving module, and a real-time data packet sent by the data receiving module is transmitted by using a UDP protocol.

In a possible implementation manner, the real-time data packet includes the timestamp, and the data packet is sent and received through the data sending module and the data receiving module according to a set time sequence.

In a possible implementation, the switch WRS is connected to the PC through a network cable.

In a possible implementation manner, the switch WRS implements the transfer of the real-time data packet through a MAC layer.

In another aspect, an embodiment of the present invention provides a system for measuring a time delay between receiving and transmitting a data packet, including:

a data transmission module for configuring the time stamp value and the value of the transmission circuit and the time stamp value and the value of the reception circuit to the register; transmitting the real-time data packet transmitted by the transmitting circuit to a WRS (switch WRS); sending the real-time data packet sent by the WRS to the receiving circuit;

and the data monitoring module is used for obtaining a measurement result by using a PC (personal computer) to simultaneously monitor the data packets of the transmitting circuit and the receiving circuit passing through the WRS.

The method for measuring the time delay of the data packet receiving and transmitting has the following advantages:

(1) The method can run in a background in a non-real-time operating system, and occupies less resources;

(2) The method has the advantages of considering real-time triggering and real-time measurement, designing two real-time protocol types of triggering and event, ensuring ultrahigh real-time performance required by triggering, considering repetition and processing time required by measurement and reducing background noise.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic diagram of a method for measuring a time delay of data packet transceiving according to an embodiment of the present invention;

fig. 2 is a schematic diagram of data transceiving according to an embodiment of the present invention;

fig. 3 is a schematic diagram of an LXI data frame format according to an embodiment of the present invention;

fig. 4 is a schematic diagram illustrating a real-time data packet output method according to an embodiment of the present invention;

fig. 5 is a schematic diagram illustrating a state transition of a data sending program according to an embodiment of the present invention;

fig. 6 is a timing diagram of a data sending module according to an embodiment of the present invention;

fig. 7 is a Wireshark monitoring diagram for transmitting LXI data in real time according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating a state transition of a program receiving data according to an embodiment of the present invention;

FIG. 9 is a timing diagram of a receive data module according to an embodiment of the present invention;

fig. 10 is a diagram of Wireshark monitoring for receiving LXI data in real time according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a schematic diagram of a method for measuring a packet transmit-receive time delay according to an embodiment of the present invention. The embodiment of the invention provides a data packet receiving and transmitting time delay measuring method, which comprises the following steps:

configuring a time stamp value and a value of a transmitting circuit and a time stamp value and a value of a receiving circuit to registers;

the transmitting circuit transmits a real-time data packet to a WRS (write driver switching system);

the WRS sends a real-time data packet to the receiving circuit;

and the PC machine obtains a measurement result by monitoring the data packets of the transmitting circuit and the receiving circuit through the WRS at the same time.

Illustratively, the transmitting circuit and the receiving circuit are two self-developed circuit boards, a system for testing delay of a data packet is formed by the transmitting circuit and the circuit boards and a switch WRS (high precision time synchronization switch), the transmitting circuit is used for transmitting data, the receiving circuit is used for receiving data, the switch WRS is connected between the transmitting circuit and the circuit boards and used for transmitting a timestamp, the switch WRS is connected with a PC (computer) through a network cable in a broadcasting mode to observe the data receiving and transmitting conditions, and the switch WRS transmits the data packet through an MAC (media access control) layer, so that the precision of time synchronization is improved to a great extent. As shown in fig. 2, an FPGA (field programmable gate array) of the transmitting circuit first transmits a data packet to an FIFO (first-in first-out data buffer), the FIFO then sequentially transmits each received frame data to a txstream (data receiving module) module in sequence, and finally the txstream module sequentially transmits the data frames to an MAC layer of an Ethernet according to a sequential logic control FIFO, and finally transmits the data to a WRS of the switch through an optical fiber. As shown in fig. 1, the transmitting circuit transmits data to the switch WRS through the optical fiber according to an LXI (modular test platform standard based on local area network) data packet format, the receiving circuit is responsible for receiving data of the switch WRS, and the data is transmitted bidirectionally, and the PC can observe data of the transmitting circuit and the receiving circuit passing through the switch WRS simultaneously by using Wireshark software.

The real-time data packet is shown in fig. 3, where the ethernet header is a header of the network data packet; payload is an LXI Data packet needing to be transmitted, comprises hardware information HW _ Data, a counting source ID, a Timestamp and 3 Value values defined according to requirements, and can transmit Data of a sensor; the CRC is the check portion. Fig. 4 is a schematic diagram of a real-time packet output mode, in which an ID of a transmitting circuit and values of second and up are respectively assigned to three value values of a receiving circuit, data of two circuit boards can be seen by using network packet analysis software Wireshark, a time delay at a certain time can be calculated by using a difference between the values of the receiving circuit and the transmitting circuit in second and up, the values of the timestamp in second and down and the value values defined as required exist in defined registers, and the register configuration is shown in table 1.

Table 1 (register configuration table)

The data frame format of the LXI network data packet is combined with the time sequence of sending and receiving the data packet, and the real-time data packet is transmitted by a UDP (user datagram protocol) protocol. The state machine of the txstream of the transmitting circuit operates as shown in fig. 5, and divides the DATA transmission process into 4 states, namely SEND _ IDLE (IDLE state), SEND _ PORT (transmit PORT start), SEND _ LEN _ CHECK (DATA word length CHECK), and SEND _ DATA (transmit DATA state). In the SEND _ IDLE state, all signals are in a reset state, and according to the time sequence of a sending module, when a trigger signal t0_ edge is detected, starting a data sending port; when detecting that the transmission interruption signal tx _ dreq is high, starting to transmit LXI DATA and entering a state of SEND _ DATA; when data is transmitted, when the data counter move _ cnt counts to "10'h19", that is, 25 data are already transmitted ", wherein 10 represents a 16-system number defining a byte length of 10 bits at most, the' h19 represents that 19 is a 16-system number, the 16-system 19 is converted into 10-system number of 16+9=25, the data count is 25, and the state returns to the SEND _ IDLE IDLE state again. A timing chart of a SEND _ DATA sending DATA module is shown in fig. 6, wherein tx _ DATA is DATA to be sent; tx _ valid is a mark for effectively transmitting data, and the high level is effective; tx _ last is a mark for ending data transmission, and the high level is effective; tx _ dreq is a flag for interrupting transmission, and high level is active.

After the logic program is designed, the generated bitstream file is downloaded to a hardware sending circuit through a JTAG (joint test group) downloader after the ISE14.7 software is compiled, and an LXI data packet sent in real time can be checked through network data packet analysis software Wireshark, as shown in fig. 7, which is a diagram for monitoring the LXI data Wireshark sent in real time.

Illustratively, the logic of the rx data module rxstream of the receiving circuit is similar to that of the TX data module TX stream, and fig. 8 is a diagram illustrating the state transition of the rx data program. The process of DATA transmission is divided into 3 states, RECV _ IDLE (IDLE state), CHECK _ FIRST (leading DATA detection), and RECV _ DATA (received DATA state), respectively. In the RECV _ IDLE state, all signals are in the reset state, and enter the CHECK _ FIRST state when rx _ FIRST signal pulling Gao Lagao is detected according to the time sequence of a receiving module; entering a DATA receiving state RECV _ DATA when detecting that the receiving valid signal rx _ valid and the DATA request signal rx _ dreq are both high level; when receiving data, whether the data is successfully received is judged by checking the transmitted data each time, and each data is judged by adopting a data counter. FIG. 9 is a timing diagram of a receive data module, wherein rx _ data is the data to be received; rx _ valid is a flag that data reception is valid, and high level is valid; rx _ first is a mark for receiving first data, and the high level is effective; rx _ last is a mark for ending data receiving, and the high level is effective; rx _ dreq is a flag for interrupting transmission, and high level is active.

After the design and compilation of the receiving program is completed by using ISE14.7, the generated bitstream is downloaded to the receiving circuit through JTAG, and the LXI packet received in real time can be observed in the Wireshark tool as well. Fig. 10 shows a diagram of real-time reception of LXI data Wireshark monitoring.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

The embodiment of the invention also provides a data packet receiving and transmitting time delay measuring system, which comprises:

a data transmission module for configuring the time stamp value and the value of the transmission circuit and the time stamp value and the value of the reception circuit to the register; transmitting the real-time data packet transmitted by the transmitting circuit to a WRS (write driver switching system); sending the real-time data packet sent by the WRS to the receiving circuit;

and the data monitoring module is used for obtaining a measurement result by using a PC (personal computer) to simultaneously monitor the data packets of the transmitting circuit and the receiving circuit passing through the WRS.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (8)

1. A method for measuring time delay of data packet receiving and transmitting is characterized by comprising the following steps:

configuring a time stamp value and a value of a transmitting circuit and a time stamp value and a value of a receiving circuit to registers;

the transmitting circuit transmits the real-time data packet to a WRS;

the WRS sends a real-time data packet to the receiving circuit;

and the PC machine obtains a measurement result by monitoring the data packets of the transmitting circuit and the receiving circuit through the WRS at the same time.

2. The method according to claim 1, wherein the timestamp is based on a PTP protocol and is recorded by FPGA hardware.

3. The method for measuring delay of data packet transceiving according to claim 1,

the sending circuit is provided with a data sending module, and real-time data packets sent by the data sending module are transmitted by a UDP protocol.

4. The method of claim 3, wherein the data packet transceiving time delay measurement method,

the receiving circuit is provided with a data receiving module, and the real-time data packet sent by the data receiving module is transmitted by a UDP protocol.

5. The method as claimed in claim 4, wherein the real-time data packet includes the timestamp, and the data packet is transmitted and received through the data transmitting module and the data receiving module according to a predetermined time sequence.

6. The method as claimed in claim 1, wherein the WRS is connected to the PC through a network cable.

7. The method as claimed in claim 1, wherein the WRS of the switch implements the transmission of the real-time data packet through the MAC layer.

8. A system for measuring packet transmit-receive time delay, comprising:

a data transmission module for configuring the time stamp value and the value of the transmission circuit and the time stamp value and the value of the reception circuit to the register; transmitting the real-time data packet transmitted by the transmitting circuit to a WRS (write driver switching system); sending the real-time data packet sent by the WRS to the receiving circuit;

and the data monitoring module is used for obtaining a measurement result by using a PC (personal computer) through monitoring the data packets of the transmitting circuit and the receiving circuit passing through the WRS of the switch at the same time.

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