US20120181542A1 - Thin Film Transistor Array Substrate - Google Patents
Thin Film Transistor Array Substrate Download PDFInfo
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- US20120181542A1 US20120181542A1 US13/433,720 US201213433720A US2012181542A1 US 20120181542 A1 US20120181542 A1 US 20120181542A1 US 201213433720 A US201213433720 A US 201213433720A US 2012181542 A1 US2012181542 A1 US 2012181542A1
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- insulation layer
- array substrate
- tft array
- drain electrode
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- 239000010409 thin film Substances 0.000 title abstract description 4
- 238000009413 insulation Methods 0.000 claims description 47
- 239000004065 semiconductor Substances 0.000 claims description 29
- 239000011368 organic material Substances 0.000 claims description 7
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Definitions
- the present invention relates to a display apparatus. More particularly, the present invention relates to a liquid crystal display (LCD).
- LCD liquid crystal display
- a pixel aperture ratio directly affects the utilization rate of a backlight source, and also affects the display brightness of the LCD.
- One of the major factors affecting the pixel aperture ratio is the area of a contact hole disposed on a thin film transistor (TFT) array substrate.
- TFT thin film transistor
- the contact hole in general cannot pass through an insulation layer smoothly.
- COA Color Filter On Array
- UHA Ultra High Aperture
- An aspect of the present invention is to provide a TFT array substrate in which a stack structure is used to raise an extended electrode of a drain electrode of a TFT, and thus a contact hole does not need to be very deep for exposing the extended electrode of the drain electrode to contact a pixel electrode.
- a TFT array substrate includes a substrate, a first patterned conductive layer, a first insulation layer, a semiconductor layer, a second patterned conductive layer, a second insulation layer, a contact hole, and a pixel electrode.
- the first patterned conductive layer is disposed on the substrate, and includes a scan line, a gate electrode, and a float electrode, wherein the gate electrode is electrically connected to the scan line.
- the first insulation layer is disposed on the first patterned conductive layer.
- the semiconductor layer is disposed on the first insulation layer, and includes a channel area.
- the second patterned conductive layer is disposed on the first insulation layer, and includes a source electrode, a drain electrode, a data line crossing the scan line, and an extended electrode of the drain electrode.
- the gate electrode, the source electrode, the drain electrode, and the channel area constructs a TFT, wherein the source electrode is electrically connected to the data line, and the extended electrode of the drain electrode is partially overlapped with the float electrode.
- the second insulation layer is disposed on the second patterned conductive layer.
- the contact hole passes through the second insulation layer and exposes a portion of the extended electrode of the drain electrode.
- the pixel electrode is electrically connected to the extended electrode of the drain electrode through the contact hole.
- a TFT array substrate includes a substrate, a first patterned conductive layer, a first insulation layer, a semiconductor layer, a second patterned conductive layer, a second insulation layer, a contact hole, and a pixel electrode.
- the first patterned conductive layer is disposed on the substrate, and includes a scan line and a gate electrode, wherein the gate electrode is electrically connected to the scan line.
- the first insulation layer is disposed on the first patterned conductive layer.
- the semiconductor layer is disposed on the first insulation layer, and includes a channel area and a first semiconductor area.
- the second patterned conductive layer is disposed on the first insulation layer, and includes a source electrode, a drain electrode, a data line crossing the scan line, and an extended electrode of the drain electrode.
- the gate electrode, the source electrode, the drain electrode, and the channel area constructs a TFT, wherein the source electrode is electrically connected to the data line, and the extended electrode of the drain electrode is partially overlapped with the first semiconductor area.
- the second insulation layer is disposed on the second patterned conductive layer.
- the contact hole passes through the second insulation layer and exposes a portion of the extended electrode of the drain electrode.
- the pixel electrode is electrically connected to the extended electrode of the drain electrode through the contact hole.
- FIG. 1 is a schematic top view showing a TFT array substrate according to an embodiment of the present invention
- FIG. 2 is a schematic cross-sectional diagram viewed along line 2 - 2 in FIG. 1 ;
- FIG. 3 is a schematic cross-sectional diagram showing a TFT array substrate according to another embodiment of the present invention, wherein the cutting position thereof is similar to that of FIG. 2 ;
- FIG. 4 is a schematic cross-sectional diagram showing a TFT array substrate according to another embodiment of the present invention, wherein the cutting position thereof is similar to that of FIG. 2 ;
- FIG. 5 is a schematic cross-sectional diagram showing a TFT array substrate according to another embodiment of the present invention, wherein the cutting position thereof is similar to that of FIG. 2 ;
- FIG. 6 is a schematic cross-sectional diagram showing a TFT array substrate according to another embodiment of the present invention, wherein the cutting position thereof is similar to that of FIG. 2 ;
- FIG. 7 is a schematic top view showing a TFT array substrate according to another embodiment of the present invention.
- FIG. 8 is a schematic top view showing a TFT array substrate according to another embodiment of the present invention.
- FIG. 9 is a schematic top view showing a TFT array substrate according to another embodiment of the present invention.
- FIG. 1 is a schematic top view showing a TFT array substrate according to an embodiment of the present invention
- FIG. 2 is a schematic cross-sectional diagram viewed along line 2 - 2 in FIG. 1
- the TFT array substrate includes a substrate 110 , a first patterned conductive layer 120 , a first insulation layer 130 , a semiconductor layer 140 , a second patterned conductive layer 150 , a second insulation layer 160 , a contact hole 170 , and a pixel electrode 180 .
- the first patterned conductive layer 120 is disposed on the substrate 110 , and includes a scan line 122 (as shown in FIG. 1 ), a gate electrode 124 , and a float electrode 126 , wherein the gate electrode 124 is electrically connected to the scan line 122 (as shown in FIG. 1 ).
- the material forming the substrate 110 can be such as glass or plastic.
- the material forming the first patterned conductive layer 120 can be metal such as aluminum, copper, silver, gold, or any combination thereof, or alloy thereof.
- the first insulation layer 130 is disposed on the first patterned conductive layer 120 .
- the first insulation layer 130 can at least cover the gate electrode 124 as a gate dielectric layer of a TFT 200 .
- the material forming the first insulation layer 130 can be one of various dielectric materials such as silicon dioxide, silicon nitride, and silicon oxynitride, or any combination thereof.
- the semiconductor layer 140 is disposed on the first insulation layer 130 , and includes a channel area 142 .
- the channel 142 can be disposed above the gate electrode 124 , and opposite to the gate electrode 124 with the first insulation layer 130 sandwiched therebetween.
- the second patterned conductive layer 150 is disposed on the first insulation layer 130 , and includes a source electrode 152 , a drain electrode 154 , a data line 156 crossing the scan line 122 (as shown in FIG. 1 ), and an extended electrode 158 of the drain electrode 154 .
- the gate electrode 124 , the source electrode 152 , the drain electrode 154 , and the channel area 142 constructs the TFT 200 , wherein the source electrode 152 is electrically connected to the data line 156 (as shown in FIG. 1 ), and the extended electrode 158 of the drain electrode 154 is partially overlapped with the float electrode 126 .
- the extended electrode 158 of the drain electrode 154 is stacked above the float electrode 126 , i.e. a portion of the extended electrode 158 of the drain electrode 154 overlaps the float electrode 126 with the first insulation 130 sandwiched between the extended electrode 158 and the float electrode 126 , so that when viewed from the top, the extended electrode 158 of the drain electrode 154 is at least partially overlapped with the float electrode 126 .
- the material forming the second patterned conductive layer 150 can be metal such as aluminum, copper, silver, gold, or any combination thereof, or alloy thereof.
- the second insulation layer 160 is disposed on the second patterned conductive layer 150 , and can be formed from an organic or inorganic material. Further, when the TFT array substrate has a COA or UHA structure, a third insulation layer (not shown) also can be optionally formed on the second insulation layer 160 , and can be formed from an organic material layer 205 such as a color resist or a color filter layer; or formed from an inorganic material.
- the second insulation layer 160 and the third insulation layer (not shown) can be used to planarize the TFT array substrate, and in another embodiment, also can provide the required filtering function, wherein the second insulation 160 and the third insulation layer (not shown) can be formed from the same material, such as a color filter layer.
- the contact hole 170 is generally formed on the second insulation layer 160 and the organic material layer 205 , and passes through the second insulation layer 160 and the organic material layer 205 to expose a portion of the extended electrode 158 of the drain electrode 154 , so that the pixel electrode 180 can be electrically connected to the extended electrode 158 of the drain electrode 154 through the contact hole 170 .
- the pixel electrode 180 is formed on the portion of the organic material layer 205 and is electrically connected to the extended electrode 158 of the drain electrode 154 through the contact hole 170 .
- the extended electrode 158 of the drain electrode 154 has the float electrode 126 formed thereunder, and thus the extended electrode 158 can be effectively raised. That is, the contact hole 170 does not need to be very deep to expose the extended electrode 158 of the drain electrode 154 . Consequently, even though the current etching technique fails to fabricate the contact hole 170 having a high aspect ratio on the color resist, yet since the contract hole 170 does not require a deep depth, the area of the contact hole 170 still can be relatively small, thereby promoting the pixel aperture ratio.
- the float electrode 126 is an electrode which is not electrically connected to any elements. Since the float electrode 126 is not electrically connected to any elements (directly or indirectly), the potential of the float electrode 126 is generally equal or close to the ground potential. Also, since the potential of the float electrode 126 is equal or close to the ground potential, no noticeable capacitance effect between the float electrode 126 and there will be the extended electrode 158 of the drain electrode 154 and the operation of the TFT array substrate will not be affected.
- the aforementioned semiconductor layer 140 can further include a first semiconductor area 144 disposed between the first insulation layer 130 and the extended electrode 158 of the drain electrode 154 , i.e. the extended electrode 158 of the drain electrode 154 can be partially overlapped with the first semiconductor area 144 . In other words, at least one portion of the extended electrode 158 of the drain electrode 154 is stacked on the first semiconductor area 144 .
- a portion of the extended electrode 158 of the drain electrode 154 overlaps the float electrode 126 with the first insulation 130 and the first semiconductor area 144 sandwiched between the extended electrode 158 and the float electrode 126 , so that when viewed from the top, the extended electrode 158 of the drain electrode 154 at least partially cover the first semiconductor area 144 and the float electrode 126 , thereby further raising the extended electrode 158 of the drain electrode 154 .
- a height HT between a surface of the substrate 110 and a top surface of the extended electrode 158 exposed through the contact hole 170 is ranged between about 3700 ⁇ and about 14000 ⁇
- a height HP between the surface of the substrate 110 and a bottom surface of the extended electrode 158 contacting the first semiconductor area 144 is ranged between about 1500 ⁇ and about 10000 ⁇ .
- FIG. 3 is a schematic cross-sectional diagram showing a TFT array substrate according to another embodiment of the present invention, wherein the cutting position thereof is similar to that of FIG. 2 .
- the difference between this embodiment and the previous embodiment is that: in the previous embodiment, the channel 142 is separated from the first semiconductor area 144 ; but in this embodiment, the channel 142 and the first semiconductor area 144 are connected to each other.
- One of ordinary skill in the art may flexibly choose the method for implementing the channel 142 and the first semiconductor area 144 in accordance with actual needs.
- an edge of the extended electrode 158 of the drain electrode 154 is substantially aligned with an edge of the float electrode 126 .
- the present invention is not limited thereto.
- One of ordinary skill in the art may flexibly choose the relative position between the float electrode 126 and the extended electrode 158 of the drain electrode 154 in accordance with actual needs.
- a projection position of an edge of the extended electrode 158 located away from the drain electrode 154 protrudes a distance R from an edge of the float electrode 126 located away from the gate electrode 124 , wherein the distance R is ranged between about 0 ⁇ m and about 10 ⁇ m, as shown in FIG. 4 .
- a projection position of an edge of the extended electrode 158 located away from the drain electrode 154 shrinks a distance P from an edge of the float electrode 126 located away from the gate electrode 124 , and the distance P is ranged between about 0 ⁇ m and about 10 ⁇ m, as shown in FIG. 5 .
- FIG. 6 is used as an example to concretely explaining the aforementioned technical contents.
- FIG. 6 is a schematic cross-sectional diagram showing a TFT array substrate according to another embodiment of the present invention, wherein the cutting position thereof is similar to that of FIG. 2 .
- the difference between this embodiment and the previous embodiments is that: this embodiment does not dispose the float electrode on the substrate, but merely disposes the first semiconductor area 144 between the first insulation layer 130 and the extended electrode 158 of the drain electrode 154 .
- a height HT between a surface of the substrate 110 and a top surface of the extended electrode 158 exposed through the contact hole 170 is ranged between about 3200 ⁇ and about 13500 ⁇
- a height HP between a surface of the substrate 110 and a bottom surface of the extended electrode 158 contacting the first semiconductor area 144 is ranged between about 1000 ⁇ and about 9500 ⁇ .
- one of ordinary skill in the art should flexibly choose the structure stacked under the extended electrode 158 of the drain electrode 154 in accordance with actual needs, and it is not necessary to choose the float electrode 126 .
- one of ordinary skill in the art may choose only using the float electrode 126 ; only using the first semiconductor area 144 ; or simultaneously using both of the float electrode 126 and the first semiconductor area 144 to raise the extended electrode 158 of the drain electrode 154 .
- the shape of the float 126 depicted in FIG. 1 substantially is a square, yet the embodiments of the present invention are not limited thereto.
- the shape of the float electrode 126 also can be a polygon as shown in FIG. 7 ; an ellipse as shown in FIG. 8 ; or a circle.
- One of ordinary skill in the art may flexibly choose the appropriate shape in accordance with actual needs.
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
A thin film transistor (TFT) array substrate includes a stack structure disposed to raise an extended electrode of a drain electrode of a thin film transistor. Therefore, a contact hole does need to be very deep to expose the extended electrode of the drain electrode.
Description
- The present application is a divisional of U.S. application Ser. No. 12/683,842, filed on Jan. 7, 2010, which was based on, and claims priority from, Taiwan Patent Application Serial Number 98108983, filed Mar. 19, 2009, the disclosure of which is hereby incorporated by reference herein in its entirely.
- 1. Field of Invention
- The present invention relates to a display apparatus. More particularly, the present invention relates to a liquid crystal display (LCD).
- 2. Description of Related Art
- With respect to a LCD, a pixel aperture ratio directly affects the utilization rate of a backlight source, and also affects the display brightness of the LCD. One of the major factors affecting the pixel aperture ratio is the area of a contact hole disposed on a thin film transistor (TFT) array substrate. Generally speaking, if the area of the contact hole is smaller, the area of a pixel region will be larger, and also the pixel aspect ratio will be larger.
- However, due to the limitation of the current etching technique, if the area of the contact hole is too small, the contact hole in general cannot pass through an insulation layer smoothly. Particularly, with respect to a COA (Color Filter On Array) structure or an UHA (Ultra High Aperture) structure, since it is very difficult for the current etching technique to fabricate a contact hole having a high aspect ratio on a color resist, the contact hole has to be designed to have a sufficiently large area so as to ensure a certain yield level. However, this design will definitely affect the pixel aperture ratio. Hence, a designer is usually trapped in this dilemma and cannot have a breakthrough.
- An aspect of the present invention is to provide a TFT array substrate in which a stack structure is used to raise an extended electrode of a drain electrode of a TFT, and thus a contact hole does not need to be very deep for exposing the extended electrode of the drain electrode to contact a pixel electrode.
- According to an embodiment of the present invention, a TFT array substrate includes a substrate, a first patterned conductive layer, a first insulation layer, a semiconductor layer, a second patterned conductive layer, a second insulation layer, a contact hole, and a pixel electrode. The first patterned conductive layer is disposed on the substrate, and includes a scan line, a gate electrode, and a float electrode, wherein the gate electrode is electrically connected to the scan line. The first insulation layer is disposed on the first patterned conductive layer. The semiconductor layer is disposed on the first insulation layer, and includes a channel area. The second patterned conductive layer is disposed on the first insulation layer, and includes a source electrode, a drain electrode, a data line crossing the scan line, and an extended electrode of the drain electrode. The gate electrode, the source electrode, the drain electrode, and the channel area constructs a TFT, wherein the source electrode is electrically connected to the data line, and the extended electrode of the drain electrode is partially overlapped with the float electrode. The second insulation layer is disposed on the second patterned conductive layer. The contact hole passes through the second insulation layer and exposes a portion of the extended electrode of the drain electrode. The pixel electrode is electrically connected to the extended electrode of the drain electrode through the contact hole.
- According to another embodiment of the present invention, a TFT array substrate includes a substrate, a first patterned conductive layer, a first insulation layer, a semiconductor layer, a second patterned conductive layer, a second insulation layer, a contact hole, and a pixel electrode. The first patterned conductive layer is disposed on the substrate, and includes a scan line and a gate electrode, wherein the gate electrode is electrically connected to the scan line. The first insulation layer is disposed on the first patterned conductive layer. The semiconductor layer is disposed on the first insulation layer, and includes a channel area and a first semiconductor area. The second patterned conductive layer is disposed on the first insulation layer, and includes a source electrode, a drain electrode, a data line crossing the scan line, and an extended electrode of the drain electrode. The gate electrode, the source electrode, the drain electrode, and the channel area constructs a TFT, wherein the source electrode is electrically connected to the data line, and the extended electrode of the drain electrode is partially overlapped with the first semiconductor area. The second insulation layer is disposed on the second patterned conductive layer. The contact hole passes through the second insulation layer and exposes a portion of the extended electrode of the drain electrode. The pixel electrode is electrically connected to the extended electrode of the drain electrode through the contact hole.
- It is to be understood that both the foregoing general description and the following detailed description are examples, and are intended to provide further explanation of the invention as claimed.
- These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:
-
FIG. 1 is a schematic top view showing a TFT array substrate according to an embodiment of the present invention; -
FIG. 2 is a schematic cross-sectional diagram viewed along line 2-2 inFIG. 1 ; -
FIG. 3 is a schematic cross-sectional diagram showing a TFT array substrate according to another embodiment of the present invention, wherein the cutting position thereof is similar to that ofFIG. 2 ; -
FIG. 4 is a schematic cross-sectional diagram showing a TFT array substrate according to another embodiment of the present invention, wherein the cutting position thereof is similar to that ofFIG. 2 ; -
FIG. 5 is a schematic cross-sectional diagram showing a TFT array substrate according to another embodiment of the present invention, wherein the cutting position thereof is similar to that ofFIG. 2 ; -
FIG. 6 is a schematic cross-sectional diagram showing a TFT array substrate according to another embodiment of the present invention, wherein the cutting position thereof is similar to that ofFIG. 2 ; -
FIG. 7 is a schematic top view showing a TFT array substrate according to another embodiment of the present invention; -
FIG. 8 is a schematic top view showing a TFT array substrate according to another embodiment of the present invention; and -
FIG. 9 is a schematic top view showing a TFT array substrate according to another embodiment of the present invention; - Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
-
FIG. 1 is a schematic top view showing a TFT array substrate according to an embodiment of the present invention, andFIG. 2 is a schematic cross-sectional diagram viewed along line 2-2 inFIG. 1 . As shown inFIG. 1 andFIG. 2 , the TFT array substrate includes asubstrate 110, a first patternedconductive layer 120, afirst insulation layer 130, asemiconductor layer 140, a second patternedconductive layer 150, asecond insulation layer 160, acontact hole 170, and apixel electrode 180. - The first patterned
conductive layer 120 is disposed on thesubstrate 110, and includes a scan line 122 (as shown inFIG. 1 ), agate electrode 124, and afloat electrode 126, wherein thegate electrode 124 is electrically connected to the scan line 122 (as shown inFIG. 1 ). The material forming thesubstrate 110 can be such as glass or plastic. The material forming the first patternedconductive layer 120 can be metal such as aluminum, copper, silver, gold, or any combination thereof, or alloy thereof. - The
first insulation layer 130 is disposed on the first patternedconductive layer 120. Concretely speaking, thefirst insulation layer 130 can at least cover thegate electrode 124 as a gate dielectric layer of aTFT 200. The material forming thefirst insulation layer 130 can be one of various dielectric materials such as silicon dioxide, silicon nitride, and silicon oxynitride, or any combination thereof. - The
semiconductor layer 140 is disposed on thefirst insulation layer 130, and includes achannel area 142. Concretely speaking, thechannel 142 can be disposed above thegate electrode 124, and opposite to thegate electrode 124 with thefirst insulation layer 130 sandwiched therebetween. - The second patterned
conductive layer 150 is disposed on thefirst insulation layer 130, and includes asource electrode 152, adrain electrode 154, adata line 156 crossing the scan line 122 (as shown inFIG. 1 ), and an extendedelectrode 158 of thedrain electrode 154. Thegate electrode 124, thesource electrode 152, thedrain electrode 154, and thechannel area 142 constructs theTFT 200, wherein thesource electrode 152 is electrically connected to the data line 156 (as shown inFIG. 1 ), and the extendedelectrode 158 of thedrain electrode 154 is partially overlapped with thefloat electrode 126. Detailedly speaking, at least one portion of the extendedelectrode 158 of thedrain electrode 154 is stacked above thefloat electrode 126, i.e. a portion of the extendedelectrode 158 of thedrain electrode 154 overlaps thefloat electrode 126 with thefirst insulation 130 sandwiched between the extendedelectrode 158 and thefloat electrode 126, so that when viewed from the top, the extendedelectrode 158 of thedrain electrode 154 is at least partially overlapped with thefloat electrode 126. The material forming the second patternedconductive layer 150 can be metal such as aluminum, copper, silver, gold, or any combination thereof, or alloy thereof. - The
second insulation layer 160 is disposed on the second patternedconductive layer 150, and can be formed from an organic or inorganic material. Further, when the TFT array substrate has a COA or UHA structure, a third insulation layer (not shown) also can be optionally formed on thesecond insulation layer 160, and can be formed from anorganic material layer 205 such as a color resist or a color filter layer; or formed from an inorganic material. Thesecond insulation layer 160 and the third insulation layer (not shown) can be used to planarize the TFT array substrate, and in another embodiment, also can provide the required filtering function, wherein thesecond insulation 160 and the third insulation layer (not shown) can be formed from the same material, such as a color filter layer. - In order to electrically contact the
extended electrode 158 of thedrain electrode 154, thecontact hole 170 is generally formed on thesecond insulation layer 160 and theorganic material layer 205, and passes through thesecond insulation layer 160 and theorganic material layer 205 to expose a portion of theextended electrode 158 of thedrain electrode 154, so that thepixel electrode 180 can be electrically connected to theextended electrode 158 of thedrain electrode 154 through thecontact hole 170. For example, thepixel electrode 180 is formed on the portion of theorganic material layer 205 and is electrically connected to theextended electrode 158 of thedrain electrode 154 through thecontact hole 170. - In this embodiment, since the
extended electrode 158 of thedrain electrode 154 has thefloat electrode 126 formed thereunder, and thus theextended electrode 158 can be effectively raised. That is, thecontact hole 170 does not need to be very deep to expose theextended electrode 158 of thedrain electrode 154. Consequently, even though the current etching technique fails to fabricate thecontact hole 170 having a high aspect ratio on the color resist, yet since thecontract hole 170 does not require a deep depth, the area of thecontact hole 170 still can be relatively small, thereby promoting the pixel aperture ratio. - In detail, the
float electrode 126 is an electrode which is not electrically connected to any elements. Since thefloat electrode 126 is not electrically connected to any elements (directly or indirectly), the potential of thefloat electrode 126 is generally equal or close to the ground potential. Also, since the potential of thefloat electrode 126 is equal or close to the ground potential, no noticeable capacitance effect between thefloat electrode 126 and there will be theextended electrode 158 of thedrain electrode 154 and the operation of the TFT array substrate will not be affected. - Further, the
aforementioned semiconductor layer 140 can further include afirst semiconductor area 144 disposed between thefirst insulation layer 130 and theextended electrode 158 of thedrain electrode 154, i.e. theextended electrode 158 of thedrain electrode 154 can be partially overlapped with thefirst semiconductor area 144. In other words, at least one portion of theextended electrode 158 of thedrain electrode 154 is stacked on thefirst semiconductor area 144. Detailedly speaking, a portion of theextended electrode 158 of thedrain electrode 154 overlaps thefloat electrode 126 with thefirst insulation 130 and thefirst semiconductor area 144 sandwiched between theextended electrode 158 and thefloat electrode 126, so that when viewed from the top, theextended electrode 158 of thedrain electrode 154 at least partially cover thefirst semiconductor area 144 and thefloat electrode 126, thereby further raising theextended electrode 158 of thedrain electrode 154. - Concretely speaking, in this embodiment, a height HT between a surface of the
substrate 110 and a top surface of theextended electrode 158 exposed through thecontact hole 170 is ranged between about 3700 Å and about 14000 Å, a height HP between the surface of thesubstrate 110 and a bottom surface of theextended electrode 158 contacting thefirst semiconductor area 144 is ranged between about 1500 Å and about 10000 Å. It should be understood that the aforementioned size is merely stated as an example for explanation, and is not used to limit the embodiments of the present invention. One of ordinary skill in the art may flexibly adjust the height of theextended electrode 158 of thedrain electrode 154 in accordance with actual needs. -
FIG. 3 is a schematic cross-sectional diagram showing a TFT array substrate according to another embodiment of the present invention, wherein the cutting position thereof is similar to that ofFIG. 2 . The difference between this embodiment and the previous embodiment is that: in the previous embodiment, thechannel 142 is separated from thefirst semiconductor area 144; but in this embodiment, thechannel 142 and thefirst semiconductor area 144 are connected to each other. One of ordinary skill in the art may flexibly choose the method for implementing thechannel 142 and thefirst semiconductor area 144 in accordance with actual needs. - Also, in the embodiment shown in
FIG. 3 , an edge of theextended electrode 158 of thedrain electrode 154 is substantially aligned with an edge of thefloat electrode 126. However, the present invention is not limited thereto. One of ordinary skill in the art may flexibly choose the relative position between thefloat electrode 126 and theextended electrode 158 of thedrain electrode 154 in accordance with actual needs. - For example, in another embodiment, a projection position of an edge of the
extended electrode 158 located away from thedrain electrode 154 protrudes a distance R from an edge of thefloat electrode 126 located away from thegate electrode 124, wherein the distance R is ranged between about 0 μm and about 10 μm, as shown inFIG. 4 . Alternatively, a projection position of an edge of theextended electrode 158 located away from thedrain electrode 154 shrinks a distance P from an edge of thefloat electrode 126 located away from thegate electrode 124, and the distance P is ranged between about 0 μm and about 10 μm, as shown inFIG. 5 . - Besides using the
float electrode 126 to raise theextended electrode 158 of thedrain electrode 154, one of ordinary skill in the art may optionally omit thefloat electrode 126, and merely use thefirst semiconductor area 144 to raise theextended electrode 158 of thedrain electrode 154. In the below,FIG. 6 is used as an example to concretely explaining the aforementioned technical contents. -
FIG. 6 is a schematic cross-sectional diagram showing a TFT array substrate according to another embodiment of the present invention, wherein the cutting position thereof is similar to that ofFIG. 2 . The difference between this embodiment and the previous embodiments is that: this embodiment does not dispose the float electrode on the substrate, but merely disposes thefirst semiconductor area 144 between thefirst insulation layer 130 and theextended electrode 158 of thedrain electrode 154. Detailedly speaking, a height HT between a surface of thesubstrate 110 and a top surface of theextended electrode 158 exposed through thecontact hole 170 is ranged between about 3200 Å and about 13500 Å, and a height HP between a surface of thesubstrate 110 and a bottom surface of theextended electrode 158 contacting thefirst semiconductor area 144 is ranged between about 1000 Å and about 9500 Å. - In other words, one of ordinary skill in the art should flexibly choose the structure stacked under the
extended electrode 158 of thedrain electrode 154 in accordance with actual needs, and it is not necessary to choose thefloat electrode 126. Concretely speaking, one of ordinary skill in the art may choose only using thefloat electrode 126; only using thefirst semiconductor area 144; or simultaneously using both of thefloat electrode 126 and thefirst semiconductor area 144 to raise theextended electrode 158 of thedrain electrode 154. - Further, although the shape of the
float 126 depicted inFIG. 1 substantially is a square, yet the embodiments of the present invention are not limited thereto. The shape of thefloat electrode 126 also can be a polygon as shown inFIG. 7 ; an ellipse as shown inFIG. 8 ; or a circle. One of ordinary skill in the art may flexibly choose the appropriate shape in accordance with actual needs. - It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. For example, one of ordinary skill in the art also can integrate a
common electrode 210 into the TFT array substrate as shown inFIG. 9 without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (9)
1. A TFT array substrate, comprising:
a substrate;
a first patterned conductive layer disposed on the substrate, wherein the first patterned conductive layer comprises a scan line and a gate electrode, and the gate electrode is electrically connected to the scan line;
a first insulation layer disposed on the first patterned conductive layer;
a semiconductor layer disposed on the first insulation layer, wherein the semiconductor layer comprises a channel area and a first semiconductor area;
a second patterned conductive layer disposed on the first insulation layer, the second patterned conductive layer comprising a source electrode, a drain electrode, a data line crossing the scan line, and an extended electrode of the drain electrode, wherein the gate electrode, the source electrode, the drain electrode, and the channel area constructing a TFT, wherein the source electrode is electrically connected to the data line, and the extended electrode of the drain electrode is partially overlapped with the first semiconductor area;
a second insulation layer disposed on the second patterned conductive layer;
a contact hole passing through the second insulation layer and exposing a portion of the extended electrode of the drain electrode; and
a pixel electrode electrically connected to the extended electrode of the drain electrode through the contact hole.
2. The TFT array substrate of claim 1 , wherein the first semiconductor area is separated from the channel area.
3. The TFT array substrate of claim 1 , wherein a height between a surface of the substrate and a top surface of the extended electrode exposed through the contact hole is ranged between about 3200 Å and about 13500 Å.
4. The TFT array substrate of claim 1 , wherein a height between a surface of the substrate and a bottom surface of the extended electrode contacting the first semiconductor area is ranged between about 1000 Å and about 9500 Å.
5. The TFT array substrate of claim 1 , wherein the second insulation layer is formed from an organic or inorganic material.
6. The TFT array substrate of claim 1 , further comprising a third insulation layer disposed above the second insulation layer.
7. The TFT array substrate of claim 6 , wherein the third insulation layer is formed from an organic or inorganic material.
8. The TFT array substrate of claim 6 , wherein the third insulation layer is a color filter layer.
9. The TFT array substrate of claim 1 , wherein the second insulation layer is a color filter layer.
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US13/433,720 US20120181542A1 (en) | 2009-03-19 | 2012-03-29 | Thin Film Transistor Array Substrate |
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TW98108983 | 2009-03-19 | ||
TW098108983A TWI383232B (en) | 2009-03-19 | 2009-03-19 | Thin film transistor array substrate |
US12/683,842 US20100237348A1 (en) | 2009-03-19 | 2010-01-07 | Thin Film Transistor Array Substrate |
US13/433,720 US20120181542A1 (en) | 2009-03-19 | 2012-03-29 | Thin Film Transistor Array Substrate |
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US12/683,842 Division US20100237348A1 (en) | 2009-03-19 | 2010-01-07 | Thin Film Transistor Array Substrate |
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US12/683,842 Abandoned US20100237348A1 (en) | 2009-03-19 | 2010-01-07 | Thin Film Transistor Array Substrate |
US13/433,720 Abandoned US20120181542A1 (en) | 2009-03-19 | 2012-03-29 | Thin Film Transistor Array Substrate |
US13/433,660 Active US8455877B2 (en) | 2009-03-19 | 2012-03-29 | Thin film transistor array substrate |
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CN104867939A (en) | 2015-04-13 | 2015-08-26 | 合肥京东方光电科技有限公司 | Pixel unit, preparation method thereof, array substrate and display device |
TWI622972B (en) * | 2016-12-30 | 2018-05-01 | 友達光電股份有限公司 | Pixel structure |
CN111092092A (en) * | 2018-10-08 | 2020-05-01 | Tcl集团股份有限公司 | active backlight LED light source plate driven by a-Si TFT device and backlight module |
CN109270751B (en) * | 2018-10-23 | 2020-10-30 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display panel |
TWI789748B (en) * | 2021-04-26 | 2023-01-11 | 友達光電股份有限公司 | Electronic device and manufacturing method thereof |
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US8455877B2 (en) | 2013-06-04 |
TW201035653A (en) | 2010-10-01 |
US20120181541A1 (en) | 2012-07-19 |
US20100237348A1 (en) | 2010-09-23 |
TWI383232B (en) | 2013-01-21 |
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