US20120168826A1

US20120168826A1 - One-transistor pixel array

Info

Publication number: US20120168826A1
Application number: US13/421,692
Authority: US
Inventors: Keith FIFE
Original assignee: Life Technologies Corp
Current assignee: Life Technologies Corp
Priority date: 2010-06-30
Filing date: 2012-03-15
Publication date: 2012-07-05
Anticipated expiration: 2031-06-30
Also published as: US8415176B2; EP2598804B1; US20180224393A1; US20120001236A1; JP2018109647A; CN106449632B; CN105806917B; US20120022795A1; US8772698B2; US20240201127A1; EP3964829A1; US20120001056A1; US8432150B2; EP2589084A2; US20150241387A1; US20120001779A1; US8432149B2; WO2012003368A2; CN109449171A; JP2013540259A

Abstract

To reduce the pixel size to the smallest dimensions and simplest form of operation, a pixel may be formed by using only one ion sensitive field-effect transistor (ISFET). This one-transistor, or 1T, pixel can provide gain by converting the drain current to voltage in the column. Configurable pixels can be created to allow both common source read out as well as source follower read out. A plurality of the 1T pixels may form an array, having a number of rows and a number of columns and a column readout circuit in each column.

Description

RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 13/174,207 filed Jun. 30, 2011, which claims the benefit of priority to previously filed U.S. provisional patent application Ser. No. 61/360,493 filed Jun. 30, 2010, U.S. provisional application Ser. No. 61/360,495 filed Jul. 1, 2010, U.S. provisional application Ser. No. 61/361,403 filed Jul. 3, 2010, and U.S. provisional application Ser. No. 61/365,327 filed Jul. 17, 2010, the disclosures of all of which are incorporated herein by reference in their entireties.

BACKGROUND

Electronic devices and components have found numerous applications in chemistry and biology (more generally, “life sciences”), especially for detection and measurement of various chemical and biological reactions and identification, detection and measurement of various compounds. One such electronic device is referred to as an ion-sensitive field effect transistor, often denoted in the relevant literature as an “ISFET” (or pHFET). ISFETs conventionally have been explored, primarily in the academic and research community, to facilitate measurement of the hydrogen ion concentration of a solution (commonly denoted as “pH”).
More specifically, an ISFET is an impedance transformation device that operates in a manner similar to that of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and is particularly configured to selectively measure ion activity in a solution (e.g., hydrogen ions in the solution are the “analytes”). A detailed theory of operation of an ISFET is given in “Thirty years of ISFETOLOGY: what happened in the past 30 years and what may happen in the next 30 years,” P. Bergveld, Sens. Actuators, 88 (2003), pp. 1-20 (“Bergveld”), which publication is hereby incorporated herein by reference in its entirety.
Details of fabricating an ISFET using a conventional CMOS (Complementary Metal Oxide Semiconductor) process may be found in Rothberg, et al., U.S. Patent Publication No. 2010/0301398, Rothberg, et al., U.S. Patent Publication No. 2010/0282617, and Rothberg et al, U.S. Patent Publication 2009/0026082; these patent publications are collectively referred to as “Rothberg”, and are all incorporated herein by reference in their entirety. In addition to CMOS, however, biCMOS (i.e., bipolar and CMOS) processing may also be used, such as a process that would include a PMOS FET array with bipolar structures on the periphery. Alternatively, other technologies may be employed wherein a sensing element can be made with a three-terminal devices in which a sensed ion leads to the development of a signal that controls one of the three terminals; such technologies may also include, for example, GaAs and carbon nanotube technologies.
Taking a CMOS example, a P-type ISFET fabrication is based on a P-type silicon substrate, in which an N-type well forming a transistor “body” is formed. Highly doped P-type (P+) regions S and D, constituting a source and a drain of the ISFET, are formed within the N-type well. A highly doped N-type (N+) region B may also be formed within the N-type well to provide a conductive body (or “bulk”) connection to the N-type well. An oxide layer may be disposed above the source, drain and body connection regions, through which openings are made to provide electrical connections (via electrical conductors) to these regions. A polysilicon gate may be formed above the oxide layer at a location above a region of the N-type well, between the source and the drain. Because it is disposed between the polysilicon gate and the transistor body (i.e., the N-type well), the oxide layer often is referred to as the “gate oxide.”
Like a MOSFET, the operation of an ISFET is based on the modulation of charge concentration (and thus channel conductance) caused by a MOS (Metal-Oxide-Semiconductor) capacitance. This capacitance is constituted by a polysilicon gate, a gate oxide and a region of the well (e.g., N-type well) between the source and the drain. When a negative voltage is applied across the gate and source regions, a channel is created at the interface of the region and the gate oxide by depleting this area of electrons. For an N-well, the channel would be a P-channel (and vice-versa). In the case of an N-well, the P-channel would extend between the source and the drain, and electric current is conducted through the P-channel when the gate-source potential is negative enough to attract holes from the source into the channel. The gate-source potential at which the channel begins to conduct current is referred to as the transistor's threshold voltage VTH (the transistor conducts when VGS has an absolute value greater than the threshold voltage VTH). The source is so named because it is the source of the charge carriers (holes for a P-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.
As described in Rothberg, an ISFET may be fabricated with a floating gate structure, formed by coupling a polysilicon gate to multiple metal layers disposed within one or more additional oxide layers disposed above the gate oxide. The floating gate structure is so named because it is electrically isolated from other conductors associated with the ISFET; namely, it is sandwiched between the gate oxide and a passivation layer that is disposed over a metal layer (e.g., top metal layer) of the floating gage.
As further described in Rothberg, the ISFET passivation layer constitutes an ion-sensitive membrane that gives rise to the ion-sensitivity of the device. The presence of analytes such as ions in an analyte solution (i.e., a solution containing analytes (including ions) of interest or being tested for the presence of analytes of interest), in contact with the passivation layer, particularly in a sensitive area that may lie above the floating gate structure, alters the electrical characteristics of the ISFET so as to modulate a current flowing through the channel between the source and the drain of the ISFET. The passivation layer may comprise any one of a variety of different materials to facilitate sensitivity to particular ions; for example, passivation layers comprising silicon nitride or silicon oxynitride, as well as metal oxides such as silicon, aluminum or tantalum oxides, generally provide sensitivity to hydrogen ion concentration (pH) in an analyte solution, whereas passivation layers comprising polyvinyl chloride containing valinomycin provide sensitivity to potassium ion concentration in an analyte solution. Materials suitable for passivation layers and sensitive to other ions such as sodium, silver, iron, bromine, iodine, calcium, and nitrate, for example, are known, and passivation layers may comprise various materials (e.g., metal oxides, metal nitrides, metal oxynitrides). Regarding the chemical reactions at the analyte solution/passivation layer interface, the surface of a given material employed for the passivation layer of the ISFET may include chemical groups that may donate protons to or accept protons from the analyte solution, leaving at any given time negatively charged, positively charged, and neutral sites on the surface of the passivation layer at the interface with the analyte solution.
With respect to ion sensitivity, an electric potential difference, commonly referred to as a “surface potential,” arises at the solid/liquid interface of the passivation layer and the analyte solution as a function of the ion concentration in the sensitive area due to a chemical reaction (e.g., usually involving the dissociation of oxide surface groups by the ions in the analyte solution in proximity to the sensitive area). This surface potential in turn affects the threshold voltage of the ISFET; thus, it is the threshold voltage of the ISFET that varies with changes in ion concentration in the analyte solution in proximity to the sensitive area. As described in Rothberg, since the threshold voltage VTH of the ISFET is sensitive to ion concentration, the source voltage VS provides a signal that is directly related to the ion concentration in the analyte solution in proximity to the sensitive area of the ISFET.
Arrays of chemically-sensitive FETs (“chemFETs”), or more specifically ISFETs, may be used for monitoring reactions—including, for example, nucleic acid (e.g., DNA) sequencing reactions, based on monitoring analytes present, generated or used during a reaction. More generally, arrays including large arrays of chemFETs may be employed to detect and measure static and/or dynamic amounts or concentrations of a variety of analytes (e.g., hydrogen ions, other ions, non-ionic molecules or compounds, etc.) in a variety of chemical and/or biological processes (e.g., biological or chemical reactions, cell or tissue cultures or monitoring, neural activity, nucleic acid sequencing, etc.) in which valuable information may be obtained based on such analyte measurements. Such chemFET arrays may be employed in methods that detect analytes and/or methods that monitor biological or chemical processes via changes in charge at the chemFET surface. Such use of ChemFET (or ISFET) arrays involves detection of analytes in solution and/or detection of change in charge bound to the chemFET surface (e.g. ISFET passivation layer).
Research concerning ISFET array fabrication is reported in the publications “A large transistor-based sensor array chip for direct extracellular imaging,” M. J. Milgrew, M. O. Riehle, and D. R. S. Cumming, Sensors and Actuators, B: Chemical, 111-112, (2005), pp. 347-353, and “The development of scalable sensor arrays using standard CMOS technology,” M. J. Milgrew, P. A. Hammond, and D. R. S. Cumming, Sensors and Actuators, B: Chemical, 103, (2004), pp. 37-42, which publications are incorporated herein by reference and collectively referred to hereafter as “Milgrew et al.” Descriptions of fabricating and using ChemFET or ISFET arrays for chemical detection, including detection of ions in connection with DNA sequencing, are contained in Rothberg. More specifically, Rothberg describes using a chemFET array (in particular ISFETs) for sequencing a nucleic acid involving incorporating known nucleotides into a plurality of identical nucleic acids in a reaction chamber in contact with or capacitively coupled to chemFET, wherein the nucleic acids are bound to a single bead in the reaction chamber, and detecting a signal at the chemFET, wherein detection of the signal indicates release of one or more hydrogen ions resulting from incorporation of the known nucleotide triphosphate into the synthesized nucleic acid.
However, traditionally, ion concentration in the analyte solution is measured by measuring an instantaneous voltage at an output of the ISFET. The signal-to-noise ratio provided by the instantaneous voltage may not be as high as desired in a lot of situations. Further, with the scaling of ISFET sensor array designs, more ISFET sensors are packed on a chip. Thus, there is a need in the art to provide a better SNR than the instantaneous voltage measurement and also a need for on-chip data compression.
Moreover, with the scaling of ISFET sensor array designs, more and more ISFET sensors are packed on a chip. Thus, there is a need in the art to provide a readout scheme to output measured data from a chip at a high speed.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

FIG. 1 illustrates a 1T ion sensitive pixel according to an embodiment of the present invention.

FIG. 2 illustrates the cross section of a 1T pixel according to an embodiment of the present invention.

FIG. 3 shows the schematic of an array of pixels with column readout switches according to an embodiment of the present invention.

FIG. 4 shows the source follower configuration of the 1T pixel according to an embodiment of the present invention.

FIG. 5A shows a 1T common source ion sensitive pixel according to an embodiment of the present invention.

FIG. 5B shows the pixel in a common source readout configuration according to an embodiment of the present invention.

FIG. 5C shows a common source equivalent circuit according to an embodiment of the present invention.

FIG. 6 shows a schematic of an array of pixels with column readout switches according to an embodiment of the present invention.

FIG. 7A shows a cross section of a 1T common source pixel according to an embodiment of the present invention.

FIG. 7B shows a cross section of a 1T common source pixel according to an embodiment of the present invention.

FIG. 8 shows a common source pixel with a cascoded row selection device according to an embodiment of the present invention.

FIG. 9 shows a one-transistor pixel array with cascoded column circuit according to an embodiment of the present invention.

FIGS. 10A and 10B show a one-transistor pixel array according to an embodiment of the present invention.

FIG. 11 shows a two-transistor (2T) pixel according to an embodiment of the present invention.

FIG. 12A to 12H illustrate 2T pixel configurations according to embodiments of the present invention.

FIG. 13A to 13D illustrate common source 2T cell configurations according to embodiments of the present invention.

FIG. 14A shows a 2T pixel array according to an embodiment of the present invention.

FIGS. 14B and 14C show a layout for a 2×2 2T pixel array according to an embodiment of the present invention.

FIG. 15 shows a capacitive charge pump according to an embodiment of the present invention.

FIG. 16 shows a charge pump according to an embodiment of the present invention.

FIG. 17 shows a charge pump according to an embodiment of the present invention.

FIG. 18 shows a charge pump according to an embodiment of the present invention.

FIG. 19 shows a basic IS accumulation pixel according to an embodiment of the present invention.

FIG. 20A-P show surface potential diagrams for basic charge accumulation according to an embodiment of the present invention.

FIGS. 21 and 22 show an IS accumulation pixel with 2 transistors according to an embodiment of the present invention.

FIG. 23 shows surface potential diagrams for the pixel of FIG. 22 according to an embodiment of the present invention.

FIG. 24 shows an IS accumulation pixel with 2 transistors and 4 electrodes according to an embodiment of the present invention.

FIG. 25 shows the surface potential diagrams for the pixel of FIG. 24 according to an embodiment of the present invention.

FIG. 26 shows an IS accumulation pixel with 1 transistor and 3 electrodes according to an embodiment of the present invention.

FIG. 27 shows a three transistor (3T) active pixel sensor according to an embodiment of the present invention.

FIG. 28 shows an alternate embodiment of a 3T active pixel sensor.

FIG. 29 shows a 3T active pixel sensor with a sample and hold circuit according to an embodiment of the present invention.

FIG. 30 shows a 3T active pixel sensor with a correlated double sampling circuit according to an embodiment of the present invention.

FIG. 31 shows a 2.5T active pixel sensor array according to an embodiment of the present invention.

FIG. 32 shows a 1.75T active pixel sensor array according to an embodiment of the present invention.

DETAILED DESCRIPTION

One-Transistor Pixel Array

A floating gate (FG) transistor may be used to detect ions in close proximity to the gate electrode. The transistor may be configured with other transistors to form a pixel that can be placed into an array for addressable readout. In the simplest form, the ancillary transistors are used solely to isolate and select the floating gate transistor for readout in an array. The floating gate transistor may be a chemically-sensitive transistor, and more specifically, a chemically-sensitive field effect transistor (ChemFET). The ChemFET may be designed with a metal-oxide-semiconductor field-effect transistor (MOSFET) containing self-aligned source and drain implants fabricated using standard complementary metal-oxide-semiconductor (CMOS) processing. The ChemFET may be an ion sensitive FET (ISFET), and may be a PMOS or an NMOS device.
To reduce the pixel size to the smallest dimensions and simplest form of operation, the ancillary transistors may be eliminated to form an ion sensitive field-effect transistor (ISFET) using one transistor. This one-transistor, or 1T, pixel can provide gain by converting the drain current to voltage in the column. Parasitic overlap capacitance between terminals of the transistor limits the gain. The capacitance ratios also allow consistent pixel-to-pixel gain matching and relatively constant current operation which justifies the use of a row selection line which can sink the necessary current without causing unacceptable variation. Derivatives of this allow for increased programmable gain through a cascoded transistor enabled during readout. Configurable pixels can be created to allow both common source read out as well as source follower read out.
FIG. 1 illustrates a 1T ion sensitive pixel according to one embodiment of the present invention. As shown, the pixel 100 may have one and only one transistor 101, one and only one row line R and one and only one column line C. The transistor 101 is shown as an n-channel MOSFET (NMOS) transistor in a p-type epitaxial substrate available using standard CMOS processes in this embodiment. It should be understood that NMOS is only used as an example in the present invention, and the transistor 101 may be a PMOS as well. The selection of NMOS or PMOS as a preferred device depends on which device does not require a top-side bulk contact for a given process. Typically NMOS is preferred when using a P+ wafer with P-epitaxy layer (called an epi-wafer) because the underlying P+ substrate biases the bulk on an array of pixels without the need to wire in a bulk contact at each pixel location. Therefore, a global bulk contact is an attractive combination for use with a 1T pixel where a small pixel pitch is required. The floating gate G of the transistor 101 may contain trapped charge, which may be properly discharged such that the electrode is at approximately the same potential as the substrate when all other terminals are also biased to the substrate potential. The row line R may be capacitively coupled to the drain D of the transistor 101, and the column line may be coupled to the source S of the transistor 101. A gate to drain overlap capacitance Cgd may form between the gate G and the drain D. The pixel 100 may be addressable from the row line R, which supplies the column current (i.e., drain-to-source current of the transistor 101) and boosts the potential at the floating gate.
In a one-transistor pixel array, such as the one shown in FIG. 3, row selection may be facilitated by boosting the FG nodes for a particular row. In one embodiment, the readout of the pixel is a winner-take-all circuit, which will be described below.
FIG. 2 illustrates the cross section of a 1T pixel according to one embodiment of the present invention. The transistor in the 1T pixel may be formed using an n-channel FET device by having a drain D and a source S formed using n-type implants within a p-type semiconductor. As shown, the transistor may have a floating gate G, the drain D and the source S. The source S may be coupled to the column line C and the drain D may be coupled to the row line R. Lightly doped drain (LDD) regions may create a gate to drain overlap capacitance Cgd and/or a gate to source overlap capacitance Cgs.
In one embodiment, the 1 T ion pixel 100 may work by boot-strapping the row selection line R to the floating gate G while at the same time providing a source of current for the column line bias. In the simplest form, this bootstrapping occurs without adding any extra capacitors. The gate to drain overlap capacitance Cgd, as shown in FIGS. 1 and 2, may naturally form the necessary capacitive coupling. To increase capacitive coupling, if desired, the row selection metal line can form an extra metal capacitor to the floating metal electrode or more significant source and drain extensions can be made with ion implantation.
FIG. 3 shows the schematic of an array of pixels with column readout switches according to one embodiment of the present invention. For illustrative purposes, four 1 T pixels 301, 302, 303 and 304 of an array 300 are shown arranged into two rows and two columns, though the array 300 could extend to an array of any size of 1T pixels. The 1T pixel may be similar to the one shown in FIG. 1. The drains of pixels 301 and 302 are coupled to a row line RO, and the sources of pixels 301 and 302 are coupled to column lines C0 and C1 respectively. The drains of pixels 303 and 304 are coupled to a row line R1, and the sources of pixels 303 and 304 are coupled to column lines C0 and C1 respectively. The pixel array can be loaded with a current source but the simplest implementation makes use of just a single switch that precharges the column line to a low potential such as the substrate potential. A column readout switch 305 is coupled to the column line CO and a column readout switch 306 is coupled to the column line C1. The column readout switch 305 comprises a switch Sa, a switch Sb, a current source Isource and a capacitor Cw. The switch Sa is used for precharging the column line and to initialize the column line quickly between samples. The switch Sb is used to sample and hold the analog value that is read on the column line. In some cases, neither a sampling capacitor nor a switch Sb are required if the pixel is converted to digital through and analog to digital converter while the pixel is held under bias. The switch Sa is used to ground the column line CO. After the column line switch Sb is open the sample is held in the capacitor, the final value on the column line, as sampled by the capacitor, will be determined almost entirely by the active row because the circuit operates according to “a winner take-all” mode (i.e., the resulting voltage represents the largest voltage of the ISFETs coupled to the readout circuit). The column readout circuit 306 functions similarly.
The operation of this pixel depends on the fact that the signal range of any given pixel is small compared to the supply voltage or read range of the source follower. For example, the useful signal range may be only 100 mV and the supply voltage may be 3.3V. When a row is selected, the R line is driven to an active high voltage VH, while all other row lines are held at an active low voltage VL. The voltage VL is selected to be approximately equal to the nominal voltage on the column line C during the readout of any given pixel. Because the signal range is small, this voltage is known to within 100 mV in this example. Therefore, the drain to source voltage of all inactive pixels is always held to small values. This point is only critical if the gate to source voltage of inactive pixels is near the threshold of the device. For the row driven to VH, the FG voltages for that row are significantly higher than the other rows because of the bootstrapping that occurs when the row line transitions to VH. After the column line switch Sb is open, the final value on the column line will be determined almost entirely by the active row because the circuit operates according to the winner take-all mode.
There are two sources of current from other rows that can distort the signal value (one that adds current and one that takes away current) and there must be enough bootstrapping available to successfully read pixels without significant interaction from the other rows that produce these sources. The analysis to determine how much bootstrapping is needed is as follows. By the time the pixel is sampled, the device has entered the subthreshold region of operation which has a transconductance slope, for example, of approximately 100 mV/decade. This means that for every 100 mV of change in gate voltage, the current changes by 10 times. In order to effectively read a single pixel, a criteria is set so that 99% of the current on the column line is attributable to the active row and only 1% is attributable to the inactive rows (distortion current). From here it can be determined how much bootstrapping is necessary. With only 2 rows in the pixel array, a 200 mV difference in the floating gate voltages is needed according to the subthreshold slope. Since a signal range of about 100 mV is also needed to be accounted for, the total requirement is about 300 mV. If there are 10 rows, there may be 10 times more contribution from inactive rows. Therefore an extra 100 mV is needed. If the array is increased to 100 rows, another 100 mV is needed. If the array is increased to 10̂n rows, 300+100*n mV is needed. As an example, a 10000 (10̂4) row pixel array only requires a total of 700 mV (300+100*4) of bootstrapping. This amount of bootstrapping can be achieved from the overlap capacitance of the gate and drain. If more capacitance is needed, extra coupling can be facilitated in the mask layout. The above analysis only applies to pixels contributing to the readout current.
Pixels can also take current away from the column line and sink it through the deactivated row lines. Since the deactivated row line is set to approximately the level of the column line, this current draw will be minimal but it must still be quantified and controlled. To accomplish this, the final current on the column line should not be allowed to diminish beyond a certain level. This is ensured by loading the column with a small current sink such as 1 uA. For a W/L (width to length) ratio of 1, a transistor biased at its threshold will have a saturation current of about 0.1 uA. This current decreases by a factor of 10 for every 100 mV of reduction in gate to source voltage. If less than 1% contribution of current is required, the VGS of inactive pixels needs to be kept to 100+100*n mV below the threshold voltage where 10̂n is the number of pixels in the row. Thus, for a 10000 row pixel array, VGS needs to be kept to 500 mV below threshold. A typical 3.3V NMOS transistor has a VT of 600 mV. Therefore, VGS should be less than 100 mV for inactive pixels. Assuming that the FG has a nominal voltage of 0V when the row (R) and column (C) lines are at 0V, this condition is met even as R and C couple to the FG. If the FG has a larger nominal voltage than 0V (for example, due to the trapped charge), more bootstrapping is necessary to cause the column line to reach a level within 100 mV of the FG. As long as the nominal FG voltage is sufficiently low, the second criteria for minimizing distortion current is not a limiting factor. Finally, enough bootstrapping is needed to produce a current on the column line that matches the bleeding current so that the pixel can produce a measurable voltage on the column line. If VG is nominally 0v, then 700 mV is needed for bootstrapping. Therefore, for an NMOS with VT as large as 600 mV, the amount of bootstrapping required is simply limited by the VT. In order to readout the pixel with margin, a good target for bootstrapping is 1V. This leaves 300 mV of range for variation. Achieving 1V of bootstrapping is practical within a 3.3V supply.
All the current from the column readout is distributed through the row line. This causes significant droop in the voltage of the row line if the column current is also significant. The voltage droop affects the bootstrapping level but is not detrimental to the readout of the source follower because variation in drain voltage has only a second order effect. Since pixels are read out with multiple samples, offsets are canceled such that the droop does not affect the sensitivity of the pixels.
It should be noted that the same layout can be used for both source follower readout and common source readout as long as optimizations are not made for either. Only accommodations that need to be made are in the column circuits. This makes for a flexible readout architecture and either readout method may be used depending on the necessary signal range. If the signal needs a high gain, the common source mode should be used. Otherwise, the source follower mode may be used.
FIG. 4 shows the source follower configuration of the 1T pixel according to one embodiment of the present invention. The source follower mode has a buffered readout and operates in a voltage mode, and has a gain less than 1. As shown, the sole transistor 401 may be coupled to an input voltage Vi at its gate G and to a fixed voltage at its drain D. The source S of the transistor 401 may be grounded via a current source Isource. The output voltage Vo may be taken from the source of the transistor 401. A coupling capacitance Cc may exist between the input and the gate of the transistor 401, a parasitic capacitor Cgd may exist between the gate G and the drain D of the transistor 401, and a parasitic capacitor Cgs may exist between the gate and the source S of the transistor 401.
The following analysis is given for the gain of the source follower readout. Referring to FIG. 4, the gain of the circuit (G) may be defined as Vo/Vi. Using reference pixels the electrode of the system may be swept to measure the gain such that Vo/Vi=G. Using the measured value of a parameter G, which is 0.65 in this example, the ratio of Cc to Cgd may be determined. As will be discussed later, it is this ratio that will determine the gain in the common source mode. The input capacitance of the source follower is Ci=Cgd+Cgs(I-Asf), wherein Asf is the gain of source follower. Due to the body effect, Asf is approximately 0.85. The capacitive divider relating to the input voltage on the FET is Cc/(Ci+Cc) and therefore, Cc/(Ci+Cc)=G/Asf. Since Cgs is about 3-5 times larger than Cgd and Asf is about 0.85, Ci is approximately 2 Cgd. Therefore, Cc=2 Cgd(G/(Asf-G)). In this example, the ratio of Cc to Cgd is about 6.5.
In one embodiment, the present invention obtains voltage gain by reading out with the common source configuration. It is desirable to achieve both a reduction in pixel size as well as an increase in signal level. The present invention eliminates the ancillary transistors in other pixel designs (e.g., 2T and 3T discussed below) and uses the source of the ISFET as the selection line to achieve both of these goals. The common source mode is a gain mode and a current mode.
FIG. 5A shows a 1T common source ion sensitive pixel according to one embodiment of the present invention. As shown, the pixel 500 may have one and only one transistor 501, one and only one row line R and one and only one column line C. The transistor 501 is shown as an n-channel MOSFET (NMOS) transistor in a p-type epitaxial substrate available using standard CMOS processes in this embodiment, although it may be a p-channel MOSFET as well. An NMOS device is typically preferred in use with a P+ epi wafer that requires no front side bulk contacts. Technically a PMOS could be use with a N+ epi wafer, but this configuration is not as commonly produced in standard CMOS processes. The row line R may be coupled to the source S of the transistor 501, and the column line may be coupled to the drain D of the transistor 501. The row selection is facilitated by switching on a path for the source voltage, and the readout of the pixel is through the drain.
The schematic of an array of pixels with column readout switches according to one embodiment of the present invention is shown in FIG. 6. The array 600 has four 1T common source pixels 601, 602, 603 and 604. The 1T pixel may be similar to the one shown in FIG. 5A. In this example, pixels are arranged into two rows and two columns. The drains of pixels 601 and 602 are coupled to a column line C0, and the sources of pixels 601 and 602 are coupled to row lines R0 and R1 respectively. The drains of pixels 603 and 604 are coupled to a column line C1, and the sources of pixels 603 and 604 are coupled to row lines R0 and R1 respectively. A column readout switch 605 is coupled to the column line C0 and a column readout switch 606 is coupled to the column line C1. The column readout switch 605 comprises a switch Sa, a switch Sb, a resistor R and a capacitor C_w0. The column readout switch 606 comprises a switch Sa, a switch Sb, a resistor R and a capacitor C_w1. The switch Sa may pull the voltage on the column line to a fixed voltage, for example, to a 3.3V supply. When the column line switch Sb is open, the final value on the column line will be determined by the active row since the switch Sb, along with the capacitor C_w0, acts as a sample and hold circuit.
The pixel array can be loaded with a current source with finite output resistance or another load device such as a resistor. Normally the row selection lines will be held at an active high voltage VH. When a row is selected for readout, its row selection line is pulled low to VL. The value of VL is set such that the nominal current level is about 1 uA. If the FG has a value of 100 mV higher than the norm, 10 times this current will result on the column line. If the value of FG is 100 mV lower than the norm, the current will be 10 times lower. The settling time of the signal on the column line will be signal dependent. The voltage gain is achieved with the selection of the value of R and it can be configurable to achieve programmable gain. For example, if R is 100 k ohms, then the 100 mV, translates to 1V at the output.
The actual circuit is more complicated than just a simple common source amplifier because of the parasitic capacitance involved. Since the FG node is not driven, but rather capacitively coupled to the output, there is a feedback mechanism that limits the gain. This limit is roughly equal to the total capacitance at the FG node to the gate to drain capacitance. This ratio may be about 3. It could be designed to achieve higher gain such as 10 times with careful mask operations to reduce source and drain extensions.
FIG. 7A shows the cross section of a 1T common source pixel according to one embodiment of the present invention. The transistor in the 1T pixel may be formed using an n-channel FET device by having a drain D and source S be formed using n-type implants within a p-type semiconductor. As shown, the transistor may have a floating gate G, the drain D and the source S. The source S may be coupled to the row line R and the drain D may be coupled to the column line C. Lightly doped drain (LDD) regions may create a gate to source overlap capacitance Cgs and a gate to drain overlap capacitance Cgd.
The overlap capacitance created by the LDD regions can be reduced by skipping the LDD implants at the drain for the device. FIG. 7B shows the cross section of a 1T common source pixel according to one embodiment of the present invention. FIG. 7B shows a drain node with a missing LDD region. This missing region reduces the capacitance and increases gain. This can be achieved through masking out the LDD implants and can be implemented in standard CMOS processing.
In the 1T pixel shown in FIG. 5A, since the source current must be supplied from the row selection line, variations in current due to variations in signal will create variations in voltage. These variations can distort the measurements. Therefore the row selection line should be low resistance and the driver for that line should also supply a steady source voltage independent of the current load. Where this is not possible, the current can be supplied from the column line and a second selection transistor can be added to form a 2T pixel for common source read out, as shown in FIG. 10A described below. Since the gain is limited by the parasitic overlap capacitance, it is expected that the best load to use is a current source implemented with transistors of high output resistance. In this case, relatively constant current will be maintained in all devices since the gain is achieved through capacitor ratios. This makes the 1T configuration feasible since voltage variation at the source is minimal, even with a single row selection line that carries all the current.
The pixel in common source readout configuration is shown in FIG. 5B. The transistor forms an amplifier with negative voltage gain. This negative voltage gain forms a natural feedback loop with the parasitic capacitors in order to control the gain. The open loop gain of the amplifier is A=gm(ro), wherein gm is a transconductance. The value A is typically larger than 100 for a given bias condition and process technology. As shown in FIG. 5C, the common source equivalent circuit has a feedback capacitance Cgd, a coupling capacitance Cc, and Cgs.
Since A is large compared to the loop gain, the negative input terminal may be considered as a virtual ground node and the gain of the circuit may be determined as Vo/Vi=−Cc/Cgd. Since this ratio is known from the analysis or measured values of the source follower configuration, the gain may be determined to be about 6.5. However compared to the source follower, the gain is Vo/Vi=2/(Asf-G). In this example, a gain of 10 is realized over the source follower configuration. A lower bound on this gain is given by assuming that the input capacitance of the source follower is solely due to Cgd and that the Asf is equal to 1. In this case the gain is about 3. Since neither of these conditions is realistic, the gain is expected to always exceed this number. Thus, if the gain of the source follower configuration of a pixel is known, the gain of the common source configuration of this pixel is also known. In addition, the higher the gain, the more sensitive the pixel is. This makes the common source configuration preferable.
Flicker noise can be reduced by using a channel doping of the same type as the minority carrier. For example, an NMOS with a n-type implant produces a buried channel transistor. To shift the workfunction of the device, a P+ gate electrode can be used.

One-Transistor Pixel Array with Cascoded Column Circuit

One derivative of the one-transistor pixel allows for increased programmable gain through a cascoded transistor enabled during readout.
Since the gain of the common source readout is limited by the Cgd capacitance, as shown in FIG. 5B, lowering this capacitance can increase the gain. FIG. 8 shows a common source pixel with a cascoded row selection device. As shown, a transistor 801 may be added to a common source pixel, e.g., the circuit shown in FIG. 5B. The gate of the transistor 801 may be coupled to a voltage Vb, and the source of the transistor 801 may be coupled to the drain of the transistor 501. The output voltage Vo may be taken from the drain of the transistor 801. The cascode effectively removes the Cgd capacitance from the feedback loop and replaces it with Cds which is much smaller. Gain on the order of the loop gain is then achievable, which may exceed 100.
Higher gain and variable gain may be produced in the 1T configuration by bringing the cascode device outside the pixel to the column line. FIG. 9 shows a one-transistor pixel array with cascoded column circuit. This allows high gain and yet still allows the pixel pitch to be minimized with only 1 transistor per pixel. The shown pixel array is a column having a number of one-transistor pixels (e.g., 500) connected in series, and has a cascode device at the base of the array. The cascode device may comprise a transistor 901. The gate of the transistor 901 may be coupled to a bias voltage Vb, the source of the transistor 901 may be coupled to the drain of the transistor 501, and the drain of the transistor 901 may be coupled to a fixed voltage via a current source. The output voltage Vo may be taken from the drain of the transistor 901. It should be understood that the array may have a number of columns.
In this case, the cascode forces the drain of the pixel to remain at a fairly steady voltage over the range of inputs. This causes the pixel to push nearly all of the change in current through the cascode device at the base of the array and into the current load. This reduces the negative feedback from Cds, which would otherwise limit the gain. Given that the current load has infinite output resistance and there is effectively no coupling capacitor to the FG node, the gain of the pixel is now −(gmlrO1+1)gm2rO2, wherein gml is the transconductance of the cascode device at the base of the column line and gm2 is the transconductance of the pixel and rO1 and rO2 are the small signal output resistances as seen at the drain. The value of the output resistance is determined by channel length modulation. Longer gate lengths produce higher output resistance because the effect of channel length modulation is minimized. Since this gain is so large, it can be limited and configured by variation of the current source output resistance, which is shown as Radj in FIG. 9. This allows for programmable gain at the column level while maintaining a simple 1 transistor pixel. The gain of the pixel is then set by −gm2RL, assuming that the load resistance RL is much smaller than the output resistance of the cascode configuration, where R_Lis the adjusted value of Radj. The gain is now configurable and programmable within the range of 1 to 100 or larger. For example, if the bias current is about 5 uA, the transconductance of the pixel is about 50 uA/V, and a load resistance of 20K ohms is needed for gain of 1. A gain of 10 is achieved with a 200K ohm load and gain of 100 with a 2M ohm load. There are many was to implement the effect of the cascode device at the column line. The main purpose of the cascode, as shown in FIG. 901 as an NMOS transistor, is that the column line is held to a potential that is largely independent of the the current level in the pixel. A differential amplifier with high gain can be applied to maintain this condition more precisely. This approach would be called gain-enhanced cascoding.
Various layout choices can be made to implement a 1T and 2T transistor. In order to reduce the size of the pixel the source and drains of adjacent pixels can be shared. In this way a single row selection line enables 2 rows at a time. This reduces the row wiring: two columns are then read out at once for a given column pitch. Such a scheme is shown in FIGS. 10A and 10B. As shown, a pixel array 1000 comprises transistors 1001, 1002, 1003 and 1004 in a column. The source of 1001 is coupled to a row line R2, and the source of 1004 is coupled to a row line R0. Transistors 1001 and 1002 may form a mirror Ml, and transistors 1003 and 1004 may form a mirror M2. The drain of 1001 and 1002 are coupled to a column line CA, and the drain of 1003 and 1004 are coupled to a column line CB.
In one embodiment, the cascoded device is gain-enhanced with a differential amplifier in feedback to control a transistor that maintains a constant voltage on the column line.

Two-Transistor Pixel Array

In a pixel array, a row selection device may be used for selection and isolation.
When a row selection line is activated, the row selection device (a MOSFET) forms a channel due to the gate voltage exceeding a threshold voltage and acts like a switch. When the row selection is deactivated, the channel is diminished. It is important to note that a row selection device never really completely turns “on” or “off”. It only approximates a switch. When the gate is substantially lower than the source of the row selection transistor, good isolation is achieved and the pixel with the active row selection can be read effectively without input from deactivated pixels. With many rows in an array of pixels, it is necessary to achieve a given level of isolation for each row selection device. That is, the requirements for the row selection device depend on the number of rows.
FIG. 11 shows a two-transistor (2T) pixel according to one embodiment of the present invention. As shown, the 2 T pixel 1100 comprises an ISFET 1101 and a row selection device 1102. In the pixel 1100, the source of the ISFET 1101 is coupled to a column line Cb, the drain of the row selection device 1102 is coupled to a column line Ct, and the drain of the ISFET 1101 is coupled to the source of the row selection device 1102. The gate of the row selection device 1102 is coupled to a row line R.
Both ISFET 1101 and the row selection device 1102 are shown as NMOS, but other types of transistors may be used as well. The 2 T pixel 1100 is configured as the source follower readout mode, although 2T pixels may be configured as the common source readout mode.
FIG. 12A to 12H illustrate more 2T pixel configurations according to embodiments of the present invention. In these Figures, “BE” stands for “with body effect”, i.e. the ISFET is body-effected because the body terminal is connected to the analog supply voltage or analog ground voltage (depending on whether the ISFET transistor type is p-channel or n-channel MOS). The body effect is eliminated if the body terminal is connected to the source terminal of the transistor. “PR” stands for “PMOS devices in reversed positions”, i.e. the positions of the p-channel ISFET and row selection device in the pixel circuit topology have been reversed (or switched around). “PNR” stands for “PMOS/NMOS devices in reversed positions”, i.e. the positions of the p-channel ISFET and n-channel row selection device in the pixel circuit topology have been reversed (or switched around).
FIG. 12A illustrates a 2T pixel, according to one embodiment of the present invention. As shown, both the ISFET and the row selection device SEL are p-channel MOS transistors, with the source terminal of the ISFET coupled to the drain terminal of the row selection device. The drain terminal of the ISFET is connected to the analog ground voltage and the source terminal of the row selection device is connected to a current source, which provides a bias current to the pixel. The output voltage Vout is read out from the source terminal of the row selection device.
FIG. 12B illustrates a 2T pixel, according to one embodiment of the present invention. As shown, both the ISFET and the row selection device SEL are p-channel MOS transistors, with the source terminal of the ISFET connected to the body terminal to eliminate the body effect, and also connected to the drain terminal of the row selection device. The drain terminal of the ISFET is connected to the analog ground voltage and the source terminal of the row selection device is connected to a current source, which provides a bias current to the pixel. The output voltage Vout is read out from the source terminal of the row selection device.
FIG. 12C illustrates a 2T pixel, according to one embodiment of the present invention. As shown, both the ISFET and the row selection device SEL are p-channel MOS transistors, with the drain terminal of the ISFET connected to the source terminal of the row selection device. The drain terminal of the row selection device is connected to the analog ground voltage and the source terminal of the ISFET is connected to a current source. The output voltage Vout is read out from the source terminal of the ISFET.
FIG. 12D illustrates a 2T pixel, according to one embodiment of the present invention. As shown, both the ISFET and the row selection device SEL are p-channel MOS transistors, with the drain terminal of the ISFET connected to the source terminal of the row selection device. The drain of the row selection terminal is connected to the analog ground voltage and the source terminal of the ISFET is connected to a current source, which provides a bias current to the pixel. The output voltage Vout is read out from the source terminal of the ISFET. The source terminal of the ISFET is connected to the body terminal to eliminate the body effect.
FIG. 12E illustrates a 2T pixel, according to one embodiment of the present invention. As shown, the ISFET and the row selection device SEL are p-channel and n-channel MOS transistors respectively, with their source terminals connected together. The drain terminal of the ISFET is connected to the analog ground voltage and the drain of the row selection device is connected to a current source, which provides a bias current to the pixel. The output voltage Vout is read out from the drain terminal of the row selection device.
FIG. 12F illustrates a 2T pixel, according to one embodiment of the present invention. As shown, the ISFET and the row selection device SEL are p-channel and n-channel MOS transistors respectively, with their source terminals connected together. The drain terminal of the ISFET is connected to the analog ground voltage and the drain of the row selection device is connected to a current source, which provides a bias current to the pixel. The output voltage Vout is read out from the drain terminal of the row selection device. The source terminal of the ISFET is connected to the body terminal to eliminate the body effect.
FIG. 12G illustrates a 2T pixel, according to one embodiment of the present invention. As shown, the ISFET and the row selection device SEL are p-channel and n-channel MOS transistors respectively, with their drain terminals coupled together. The source terminal of the row selection device is connected to the analog ground voltage and the source terminal of the ISFET is connected to a current source, which provides a bias current to the pixel. The output voltage Vout is read out from the source terminal of the ISFET.
FIG. 12H illustrates a 2T pixel, according to one embodiment of the present invention. As shown, the ISFET and the row selection device SEL are p-channel and n-channel MOS transistors respectively, with their drain terminals coupled together. The source terminal of the row selection device is connected to the analog ground voltage and the source terminal of the ISFET is connected to a current source, which provides a bias current to the pixel. The output voltage Vout is read out from the source terminal of the ISFET. The source terminal of the ISFET is connected to the body terminal to eliminate the body effect.
FIGS. 13A to 13D illustrate common source 2T cell configurations according to embodiments of the present invention. In FIGS. 13A and 13B, both the ISFET and the row selection device are n-channel MOS transistors, and in FIGS. 13C and 13D, both the ISFET and the row selection device are p-channel MOS transistors.
In FIG. 13A, the source terminal of the ISFET is connected to the analog ground supply and the drain terminal of the row selection device is connected to a current source, which provides a bias current to the pixel. The source terminal of the row selection device and the drain terminal of the ISFET are connected together. The output voltage Vout is read out from the drain terminal of the row selection device.
In FIG. 13B, the source terminal of the row selection device is connected to the analog ground supply and the drain terminal of the ISFET is connected to a current source, which provides a bias current to the pixel. The drain terminal of the row selection device and the source terminal of the ISFET are connected together. The output voltage Vout is read out from the drain terminal of the ISFET.
In FIG. 13C, the source terminal of the ISFET is connected to the analog supply voltage, and the drain terminal of the row selection device is connected to a current source, which provides a bias current to the pixel. The source terminal of the row selection device and the drain terminal of the ISFET are connected together. The output voltage Vout is read out from the drain terminal of the row selection device.
In FIG. 13D, the source terminal of the row selection device is connected to the analog supply voltage, and the drain terminal of the ISFET is connected to a current source, which provides a bias current to the pixel. The source terminal of the ISFET and the drain terminal of the row selection terminal are connected together. The output voltage Vout is read out from the drain terminal of the ISFET.
FIG. 14A shows a 2T pixel array according to one embodiment of the present invention. For illustrative purposes, eight 2T pixels are shown arranged into two columns, though the 2 T pixel array 1400 could extend to an array of any size of 2T pixels. Each column pitch contains three column lines cb[0], ct[0] and cb[1], The row lines rs[0], rs[1], rs[2] and rs[3], connect to all columns in parallel.. A row selection device 1401RS and an ISFET 1401IS may form one 2T pixel, with the source of 1401IS connected to the drain of 1401RS. The source of 1401RS is connected to the column line cb[0], and the drain of 1401IS is connected to the column line ct[0]. The gate of 1401RS is connected to the row line rs[0]. This pixel is mirrored in a pixel comprising 1402IS and 1402RS, with drains of 1401IS and 1402IS connected to the column line ct[0], and the gate of 1402RS connected to the row line rs[1]. The pixel comprising 1402IS and 1402RS is mirrored in a pixel comprising 1403IS and 1403RS, with the source of 1402RS and 1403RS connected to the row line cb[1], and the gate of 1403RS coupled to the row line rs[2]. The pixel comprising 1403IS and 1403RS is mirrored in a pixel comprising 1404IS and 1404RS, with the drains of 1403IS and 1404IS connected to the row line ct[0], the gate of 1404RS coupled to the row line rs[3], and the source of 1404RS coupled to the column line cb[0]. In the embodiment shown in FIG. 14, each of the IS devices is an ISFET and each of the RS devices is a row select device.
The right column, including a pixel consisting of 1405RS and 1405IS, a pixel consisting of 1406RS and 1406IS, a pixel consisting of 1407RS and 1407IS, and a pixel consisting of 1408RS and 1408IS, is coupled to column traces cb[2], ct[1], and cb[3] in substantially the same manner as described above.
FIGS. 14B and 14C show a layout for a 2×2 2T pixel array according to an embodiment of the present invention. The 2×2 2T pixel array may be part of the pixel array 1400. FIG. 14B shows that polysilicon gates for 1401RS, 1401IS, 1402RS and 1402IS may be placed on top of a continuous diffusion layer 1410 and polysilicon gates for 1405RS, 1405IS, 1406RS and 1406IS may be placed on top of a continuous diffusion layer 1412. In one embodiment, the continuous diffusion layers 1410 and 1412 may run from the top of the pixel array to the bottom of the pixel array. That is, the diffusion layer may have no discontinuities in the pixel array.
FIG. 14C shows where microwells for ISFETs 1401IS, 1402IS, 1405IS and 1406IS may be placed. The microwells may be used to hold analyte solutions that may be analyzed by the ISFETs. As shown in FIG. 14C, in one embodiment, the microwells may each have a hexagonal shape and stacked like a honeycomb. Further, in one embodiment, the contact may be placed directly on top of the gate structure. That is, the ISFETs may have a contact landed on polysilicon gate over thin oxide.
The pixel array 1400 has high density because of continuous diffusion, shared contacts, mirrored pixels, and one ct (column top) line and 2 cb (column bottom) line per physical column. A global bulk contact may be implemented by using a P+ wafer with P− epitaxy region.
The arrangement of pixel array 1400 provides for high speed operation. Row lines rs[0] and rs[1] are selected together and readout through cb[0] and cb[1]. This leads to a 4 times faster readout due to twice the number of pixels enabled for a single readout and half the parasitic load of a continuous array, allowing each column to settle twice as fast. In an embodiment, the full array is separated into a top half and a bottom half. This leads to another 4 times faster readout time due to twice the number of pixels readout at a time (both out the top and the bottom) and half the parasitic load of a continuous array. Thus, the total increase in speed over a single row selected continuous array is 16 times.
In an embodiment, both top and bottom halves of the pixel array may be enabled at the same time during readout. This can allow a multiplexing of readout between the top half and the bottom half. For example, one half can be doing a “wash” (e.g., flushing out reactants from the wells over the pixel devices) and the other half can be performing the readout. Once the other half is read, the readout for the two halves is switched.
In an embodiment, a 2T pixel design can incorporate two chemically-sensitive transistors (e.g., ISFETs) rather than one chemically-sensitive transistor and one row select device as described with respect to FIGS. 11-14. Both chemically-sensitive transistors, or ISFETs, can be NMOS or PMOS device and configured in a source follower or common source readout mode. Possible uses of such a 2T pixel may be where the first chemically-sensitive transistor has a different sensitivity to a particular analyte to that of the second chemically-sensitive transistor, allowing a local and in-pixel differential measurement to be made. Alternatively, both chemically-sensitive transistors may have the same sensitivity to a particular analyte, allowing a local and in-pixel average measurement to be made. These are among two examples of potential uses for this embodiment, and based on the description herein, a person of ordinary skill in the art will recognize other uses for the 2T pixel design that incorporate two chemically-sensitive transistors (e.g., ISFETs).
In one embodiment, a column circuit allows column lines to be swapped to a sampling circuit such that either source-side or drain-side row selection can be made in either source follower mode or common source mode.

Capacitive Charge Pump

One or more charge pumps may be used to amplify the output voltage from a chemically-sensitive pixel that comprises one or more transistors, such as those described above.
FIG. 15 shows a capacitive charge pump with a two times voltage gain according to one embodiment of the present invention. A charge pump 1500 may comprise Φ1 switches 1501, 1502, 1503 and 1504, φ2 switches 1505 and 1506, and capacitors 1507 and 1508. Vref1 and Vref2 are set to obtain the desired DC offset of the output signal, and both are chosen to avoid saturation of the output during the boost phase. The operation of the charge pump may be controlled by timing signals, which may be provided by a timing circuit.
At time t0, all switches are off.
At time t1, φ1 switches 1501, 1502, 1503 and 1504 are turned on. The track phase may start. An input voltage Vin, which may be from an ion sensitive pixel, may start to charge capacitors 1507 and 1508.
At time t2, φ1 switches 1501, 1502, 1503 and 1504 are turned off, and capacitors 1507 and 1508 are charged to Vin-Vref1.
At time t3, φ2 switches 1505 and 1506 are turned on, while φ1 switches 1501, 1502, 1503 and 1504 remain off. The boost phase may start. The capacitor 1507 may start to discharge through the capacitor 1508. Since the capacitors are in parallel during the track phase and in series during the boost phase, and the total capacitance is halved during the boost phase while the total charge remains fixed, the voltage over the total capacitance must double, making Vout approximately two times Vin.
A source follower SF may be used to decouple the gain circuit from the following stage.
The charge pump 1500 may provide a two times gain without a noisy amplifier to provide a virtual ground.
FIG. 16 shows a charge pump according to an embodiment of the present invention.
At time t0, all switches are off.
At time t1, φ1 switches 1501, 1502, 1503, 1504, 1601 and 1602 are turned on. The track phase may start. An input voltage Vin, which may be from an ion sensitive pixel, may start to charge capacitors 1507, 1508 and 1604.
At time t2, φ1 switches 1501, 1502, 1503, 1504, 1601 and 1602 are turned off, and capacitors 1507, 1508 and 1604 are charged to Vin-Vref1.
At time t3, φ2 switches 1505 and 1603 are turned on, while φ1 switches 1501, 1502, 1503, 1504, 1601 and 1602 remain off. The boost phase may start. The capacitor 1507 may start to discharge through the capacitors 1508 and 1604, and the capacitor 1508 may start to discharge through the capacitor 1604. Since the capacitors are in parallel during the track phase and in series during the boost phase, and the total capacitance is divided by three during the boost phase while the total charge remains fixed, the voltage over the total capacitance must triple, making Vout approximately three times Vin.
FIG. 17 shows an embodiment of a charge pump according to an embodiment of the present invention. Two charge pumps 1500 shown in FIG. 15 are connected in series, enabling gain pipelining and amplifying input voltage Vin by a factor of four.
Additional series charge pumps can be added to increase the gain further. In a multi-stage charge pump, the capacitor values do not have to be the same size from stage to stage. It can be observed that the total area consumed by capacitors increases with the square of the gain. Although this feature may, in some cases, be undesirable with respect to area usage, power consumption, and throughput, the charge pump can be used without these penalties when the total noise produced by the ion sensitive pixel and associated fluidic noise is larger than the charge pump KT/C noise when a reasonable capacitor size is used.
FIG. 18 shows an embodiment of a charge pump according to an embodiment of the present invention. A feedback path including a source follower SFP and a switch φfb is added to the charge pump 1500, feeding the output Vout back to the input of the charge pump.
At time tO, all switches are off.
At time t1, a switch φsp is on, providing an input voltage Vin to the input of the charge pump 1500.
From time t2 to time t5, the charge pump 1500 operates to push the output voltage Vout to 2(Vin-Vref1), as described before with reference to FIG. 15.
From time t6 to t7, the switch φfb is on, feeding the output voltage 2(Vin-Vref1). back to the input of the charge pump 1500, and the first cycle ends.
During the second cycle, the charge pump 1500 amplifies the output voltage by 2(2(Vin-Vref1)). The process repeats, with the output being amplified during each cycle.

CCD-Based Multi-Transistor Active Pixel Sensor Array

An ion sensitive MOS electrode is charge coupled to adjacent electrodes to facilitate both confinement and isolation of carriers. Measurements of ion concentration are made by discrete charge packets produced at each pixel and confined by potential barriers and wells. The ion sensitive electrode can act as either a barrier level or as a potential well. Working in the charge domain provides several benefits, including but not limited to: 1) increased signal level and improved signal to noise through the accumulation of multiple charge packets within each pixel, 2) better threshold matching of the MOS sensing and reference structures, 3) reduction in flicker noise, and 4) global-snap shot operation.
A floating electrode is used to detect ions in close proximity to the electrode. The electrode is charge coupled to other electrodes and to other transistors to form a pixel that can be placed into an array for addressable readout. It is possible to obtain gain by accumulating charge into another electrode or onto a floating diffusion (FD) node or directly onto the column line. It is desirable to achieve both a reduction in pixel size as well as increase in signal level. To reduce pixel size, ancillary transistors may be eliminated and a charge storage node with certain activation and deactivation sequences may be used.
The ion sensitive (IS) accumulation pixel contains some of the following concepts:

- 1. Electrodes are charge coupled to the IS electrode;
- 2. A source of carriers (electrons or holes) for charge packets;
- 3. A reference electrode to act as a barrier or a well for the charge packets;
- 4. A floating diffusion node for charge to voltage conversion;
- 5. Ancillary transistors to provide buffering and isolation for addressable readout; and
- 6. Sequences to eliminate some or all ancillary transistors depending on the application.

The basic IS accumulation pixel is shown in FIG. 19. Charge accumulation can occur either locally at the time of readout or globally during a separate integration time. The embodiment shown in FIG. 19 is a three transistor three electrode (3T3E) pixel. The three transistors include a reset transistor RT, a source follower 1901 and a row selection transistor RS, and the three electrodes include an electrode VS, an electrode VR, and an ion sensitive electrode 1902. The pixel also includes a transfer gate TX. It is also possible to configure the IS accumulation pixel with additional elements to allow simultaneous accumulation and readout. This can be done, for example, by adding 2 more electrodes to pipeline the process. In the basic configuration, charge is accumulated onto the floating diffusion node that is connected to the source of the reset (RT) control gate. In a rolling shutter operation, the floating diffusion (FD) is reset to CD=VDD. The row is then selected and readout through the source follower enabled by row selection (RS). Next, charge is accumulated onto the FD node which discharged the parasitic capacitor. A second sample is then taken. The difference between the samples represents the ion concentration. The samples are correlated and taken relatively quickly in time. Therefore, the thermal noise of the readout circuit is eliminated and the 1/f noise is reduced. To operate in a global shutter mode, all FD nodes are simultaneously reset to VDD. Then charge is accumulated on each isolated FD node. After accumulation, each row is selected by enabling the RS gate. The signal value is readout on the column line with a load on the source follower. Next the pixel is reset and sampled again. The difference between the samples represents the ion concentration. The 1/f noise is reduced through the double sampling. However, the thermal reset noise is not eliminated because the reset value is uncorrelated in time. The thermal noise can be reduced by half the power by following the reset operation with a subthreshold reset before sampling. In general, the thermal noise is low compared to the signal due to the charge accumulation. A correlated reset scheme with global shutter is available in other configurations.
The basic charge accumulation scheme is shown in FIG. 20 using the surface potential diagrams. Only the electrodes are shown since the transistors are only used for readout. In each of these sequences, increasing potential is pointing down as is conventional to show potential wells containing electrons. Four cycles of charge accumulation are shown in FIG. 20 A-P. First, all charge is removed from the channel under the IS electrode and the channels are fully depleted using a high potential on FD (A). Next, the TX gate transitions to a low potential which creates the confinement barrier (B). A fill and spill operation is used to produce a charge packet proportional to the ion concentration at the IS electrode (C-D). In the next cycle, this charge packet is transferred to the FD node which discharges due to the electrons. The diagram shows electrons accumulating on the FD node, but the voltage is actually decreasing. After many cycles, as shown in FIG. 20 E-P, the signal to noise ratio is improved and the signal can be read out with gain. Hundreds to millions of cycles can be used to amplify the signal.
In alternative embodiments, the order of electrodes may be switched, and/or the IS electrode may be used as the barrier rather than the well. Transistors may be added to this accumulation line to enable a large array of pixels. The ancillary transistors are used to increase speed. However, it should be noted that no transistors are necessary to enable a full pixel array of the accumulation line. Instead, an array can be partitioned such that no transistors are needed. In an embodiment, the FD nodes are connected to the column line. Before a pixel is read out, the column line is reset to VDD. Then a row is selected by accumulating charge for that row directly onto the column line. After many cycles, the column discharges to a value directly proportional to the ion concentration. Since the capacitance of the column line depends on the total number of rows, the amount of accumulation required, depends on the number of rows. The array can be partitioned into sub arrays to make timing scalable. For example, every 100 rows can contain a local source follower buffer that is then connected to a global array. This hierarchical approach can be used in general with all readout schemes to make massive arrays of pixels with fast readout.
Due to the thermal activity of carriers, charge packets cannot be generated without noise. Each fill and spill operation produces charge error proportional to KTC (thermal noise in the floating diffusion capacitor), where C is equal to Cox times the area of the ion sensitive electrode. During the fill operation charge can flow freely between the source of electrons and the confinement well. However, during the spill operation, the device enters the subthreshold mode and carriers move by diffusion, mainly in only one direction, which results in half of the thermal noise of a resistive channel. The total noise in electrons for each charge packet is therefore sqrt(KTC/2)/q where q represents the charge of one electron in coulombs (1.6×10e−19). The signal in electrons is equal to VC/q. The signal to noise ratio after n cycles is equal to V*sqrt(2nC/KT). Note that the signal to noise ratio improves by the square root of the number of cycles of accumulation. For small signal levels, the amount of accumulation will be limited to the threshold mismatch between the VR reference electrode and the ion sensitive electrode. Since there is a reference electrode in every pixel and the electrodes are charge coupled, the relative threshold mismatch between each pair of electrodes is small. Assuming, this difference is about 1 mV, over 1000 accumulation cycles should be feasible, thereby improving the signal to noise by more than 30 times. By way of example, if the signal is 1 mV and the electrode area is 1 square micron with Cox=5fF/um̂2, the signal to noise ratio after 1000 cycles is 50 to 1. Since the signal level then reaches 1V, it is expected that no other noise source is relevant. For clarity, the dominant noise is simply the charge packet thermal noise which is well known.
FIGS. 21 and 22 show the IS accumulation pixel with only 2 transistors. The selection transistor is eliminated by using a deactivation sequence after a row is read out. To deactivate, the FD node is discharged, which reduces the potential of the FD node and disables the source follower for that row. The surface potential diagrams for the pixel of FIG. 22 are shown in FIG. 23.
FIG. 24 shows the IS accumulation pixel with 2 transistors and 4 electrodes. This pixel produces the fill and spill charge packets and readout all at the same FD node. The 4th electrode allows global shutter operation and correlated double sampling. For faster readout, single sampling can be used if charge accumulation sufficiently reduces the 1/f noise contribution. FIG. 25 shows the surface potential diagrams for the basic operation of the pixel of FIG. 24.
FIG. 26 shows an IS accumulation pixel with 1 transistor and 3 electrodes. The channel can be depleted and supplied from the same node. This pixel depends on charge coupling, and signal range is lower than signal range for the other pixels.
Several design permutations are available depending on the desired mode of operation. The CCD channels are surface mode and are built in standard CMOS technology preferably below 0.13 um. Extra implants can be added to avoid surface trapping and other defects. A channel stop and channel can be formed from donor and acceptor impurity implants. The channel can be made of multiple implants to produce a potential profile optimal for the mode of operation.
FIG. 27 shows an embodiment of a three transistor (3T) active pixel sensor. The three transistors are a reset transistor 2701, a source follower 2702 and a row selection switch 2703. The reset transistor 2701 has a gate controlled by a reset signal RST, a source coupled to the floating diffusion (FD) of a pixel, and a drain connected to a fixed voltage. The source follower 2702 has its gate connected to the source of the reset transistor 2701, and its drain connected to a fixed voltage. A row selection transistor 2703 has its gate connected to a row line, its drain connected to a fixed voltage and its source connected to a column. Other electrodes interacting with the pixel includes a transfer gate TG, an ion selective electrode ISE, an input control gate ICG, and an input diffusion ID. These three elements form charge coupled electrodes that are operated in an identical way to VS, VR, and TX in FIG. 19.
FIG. 28 shows an alternate embodiment of a 3T active pixel sensor. The difference between the sensor in FIG. 28 and the sensor shown in FIG. 27 is that the sensor 2800 has a second input control gate ICG2, which allows more control over the potential barrier near the ion-sensitive electrode.
FIG. 29 shows an embodiment of a 3T active pixel sensor with a sample and hold circuit, which may be used to eliminate signal variations. As shown, the gate of the row selection transistor 2703 is controlled by a RowSelm signal provided by a row selection shift register. The source of the row selection transistor 2703 is coupled to a current sink ISink 2902 and a column buffer 2903. The current sink ISink 2902 may be biased by a voltage VB1 and the column buffer, which may be an amplifier, may be biased by a voltage VB2.
The sample and hold circuit 2901 may include a switch SH, a switch CAL, a capacitor Csh, and an amplifier Amp. The switch SH's input is coupled to the output of the column buffer 2903, and its output is coupled to a voltage VREF through the switch CAL, the upper part of the capacitor Csh, and the input of the amplifier Amp. The amplifier is biased by a voltage VB2. The output of the amplifier is coupled to a switch 2904 controlled by a signal ColSeln from a column selection shift register. The output of the switch 2904 is buffered by an output buffer 2905 before reaching the output terminal Vout. The output buffer is biased by a voltage VB3.
FIG. 30 shows an embodiment of a 3T active pixel sensor with a correlated double sampling circuit. The most significant difference between the sensor in FIG. 30 and that in FIG. 29 is that the former uses a correlated double sampling circuit 3001 to measure the signal from the column buffer 2903. An amplifier in the correlated double sampling circuit 3001 receives at its first input the output of the column buffer 2903 via a switch SH, and a capacitor Cin. The amplifier receives a reference voltage VREF at its second input, and is biased by the voltage VB2. A reset switch RST and a capacitor Cf are coupled in parallel with the amplifier.
FIG. 31 shows an embodiment of a 2.5T active pixel sensor used for a four pixel array. Each of the pixels has its own transfer transistor TX1, TX2, TX3 and TX4 and its own reset transistor. The drain of each transfer transistor is coupled to the source of the reset transistor in the same pixel, and the source of each transfer transistor is coupled to the gate of the source follower.
FIG. 32 shows an embodiment of a 1.75T active pixel sensor for a four pixel array. Each of the pixels has its own transfer transistor. The source of each transfer transistor is coupled to the floating diffusion of the same pixel, and the drain of each transfer transistor is coupled to the drain of the reset transistor RST of the sensor.
Several embodiments of the present invention are specifically illustrated and described herein. However, it will be appreciated that modifications and variations of the present invention are covered by the above teachings. In other instances, well-known operations, components and circuits have not been described in detail so as not to obscure the embodiments. It can be appreciated that the specific structural and functional details disclosed herein may be representative and do not necessarily limit the scope of the embodiments. For example, some embodiments are described with an NMOS. A skilled artisan would appreciate that a PMOS may be used as well.
Those skilled in the art may appreciate from the foregoing description that the present invention may be implemented in a variety of forms, and that the various embodiments may be implemented alone or in combination. Therefore, while the embodiments of the present invention have been described in connection with particular examples thereof, the true scope of the embodiments and/or methods of the present invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.
Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate array (FPGA), logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an embodiment is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints.
Some embodiments may be implemented, for example, using a computer-readable medium or article which may store an instruction or a set of instructions that, if executed by a machine, may cause the machine to perform a method and/or operations in accordance with the embodiments. Such a machine may include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, processor, or the like, and may be implemented using any suitable combination of hardware and/or software. The computer-readable medium or article may include, for example, any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium and/or storage unit, for example, memory, removable or non-removable media, erasable or non-erasable media, writeable or re-writeable media, digital or analog media, hard disk, floppy disk, Compact Disc Read Only Memory (CD-ROM), Compact Disc Recordable (CD-R), Compact Disc Rewriteable (CD-RW), optical disk, magnetic media, magneto-optical media, removable memory cards or disks, various types of Digital Versatile Disc (DVD), a tape, a cassette, or the like. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, and the like, implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.

Claims

1. A device comprising:

an array of chemically-sensitive field-effect transistors (chemFETs), at least some chemFETs in the array of chemFETs comprising:

a first source/drain terminal and a second source/drain terminal; and

a floating gate coupled to a passivation layer;

a plurality of first conductive lines coupled to chemFETs in the array, wherein each first conductive line in the plurality of first conductive lines is directly connected to the first source/drain terminals of chemFETs in a column in the array; and

a plurality of second conductive lines coupled to chemFETs in the array, wherein each second conductive line is directly connected to the second source/drain terminals of chemFETs in a row in the array;

bias circuitry coupled to the array to apply a read bias to selected chemFETs via the first conductive lines and second conductive lines; and

sense circuitry coupled to the array to sense charge coupled to the floating gates of selected chemFETs.

2. The device of claim 1, wherein the sensed charge indicates an ion-concentration of an analyte solution coupled to the floating gate of a selected chemFET via the passivation layer.

3. The device of claim 1, wherein:

the bias circuitry applies a read voltage to a selected first conductive line in the plurality of first conductive lines during a read interval; and

the sense circuitry includes a sample circuit to read a selected chemFET connected to the selected first conductive line and a selected second conductive line during the read interval.

4. The device of claim 3, wherein the sample circuit includes a sample and hold circuit to hold an analog value of a voltage on the selected second conductive line during the read interval, and an analog to digital converter to convert the analog value to a digital value.

5. The device of claim 3, wherein the sample circuit includes an analog to digital converter to directly convert a voltage on the selected second conductive line to a digital value during the read interval.

6. The device of claim 3, including a pre-charge circuit to pre-charge the selected second line to a pre-charge voltage level prior to the read interval.

7. The device of claim 1, wherein:

the read bias includes a read voltage on a selected first conductive line applied to boost by capacitive coupling the floating gate of a selected chemFET to a boosted voltage level, thereby inducing current flow through the selected chemFET to establish a voltage level on a selected second conductive line; and

the read bias further includes a voltage on first conductive lines connected to unselected chemFETs connected to the selected second conductive line, applied to bias by capacitive coupling the floating gates of the unselected chemFETs to an inhibit voltage level.

8. The device of claim 7, including a current sink coupled to the selected second conductive line to compensate for leakage current through unselected chemFETs connected to the selected second conductive line during the read interval.

9. A device comprising:

a first source/drain terminal and a second source/drain terminal; and

a floating gate coupled to a passivation layer;

a plurality of first conductive lines coupled to chemFETs in the array, wherein each first conductive line in the plurality of first conductive lines is directly connected to the first source/drain terminals of a corresponding first plurality of chemFETs in the array; and

a plurality of second conductive lines coupled to chemFETs in the array, wherein each second conductive line in the plurality of second conductive lines is coupled to the second source/drain terminals of a corresponding second plurality of chemFETs in the array.

10. The device of claim 9, wherein each second conductive line in the plurality of second conductive lines is directly connected to the second source/drain terminals of the corresponding second plurality of chemFETs in the array.

11. The device of claim 9, wherein the chemFETs in the array are arranged in rows and columns, each first conductive line is directly connected to the first source/drain terminals of chemFETs arranged in a corresponding column in the plurality of columns, and each second conductive line is directly connected to the second source/drain terminals of chemFETs arranged in a corresponding row in the plurality of rows.

12. The device of claim 9, further comprising circuitry coupled to the plurality of first conductive lines and the plurality of second conductive lines for reading a selected chemFET directly connected to a selected first conductive line and directly connected a selected second conductive line by:

inducing current flow between the selected second conductive line and the selected first conductive line through the selected chemFET during a read interval, thereby establishing an output voltage level on the selected second conductive line;

compensating for leakage current through unselected chemFETs connected to the selected second conductive line during the read interval; and

reading the selected chemFET based on the output voltage level on the selected second conductive line.

13. The device of claim 12, wherein the circuitry for reading induces current flow between the selected second conductive line and the selected first conductive line through the selected chemFET by:

pre-charging the selected second conductive line to a pre-charge voltage level prior to the read interval;

applying a read voltage to the selected first conductive line during the read interval to boost by capacitive coupling the floating gate of the selected chemFET to a boosted voltage level, thereby inducing the current flow to establish the output voltage level on the selected second conductive line.

14. The device of claim 13, including circuitry to apply a voltage to corresponding first conductive lines connected to unselected chemFETs connected to the selected second conductive line, thereby biasing by capacitive coupling the floating gates of the unselected chemFETs to an inhibit voltage level.

15. The device of claim 14, wherein a magnitude voltage difference between the boosted voltage level and the inhibit voltage level is at least 200 mV.

16. The device of claim 13, including a switch coupled between the selected second conductive line and a reference voltage, and wherein the circuitry turns on the switch prior to the read interval to bias the selected second conductive line to the pre-charge voltage level, and turns off the switch during the read interval.

17. The device of claim 13, including a current sink coupled to the selected second conductive line to compensate for the leakage current through the remaining chemFETs during the read interval.

18. A device comprising:

an array of chemically-sensitive field-effect transistors (chemFETs) arranged in a plurality of rows and a plurality of columns, chemFETs in the array of chemFETs comprising:

a first source/drain terminal and a second source/drain terminal; and

a floating gate coupled to a passivation layer;

a plurality of column lines coupled to chemFETs in the array, wherein each column line in the plurality of column lines is directly connected to the first source/drain terminals of chemFETs arranged in a corresponding column in the plurality of columns;

a plurality of row lines coupled to chemFETs in the array, wherein each row line in the plurality of row lines is directly connected to the second source/drain terminals of chemFETs arranged in a corresponding row in the plurality of rows;

circuitry coupled to the plurality of column lines and row lines for reading a selected chemFET connected to a selected column line and a selected row line, the circuitry comprising:

bias circuitry coupled to the row lines to apply a read voltage to the selected row line in the plurality of row lines during a read interval, and to apply voltages to corresponding row lines and corresponding column lines connected to unselected chemFETs connected to the selected column line; and

sense circuitry to sense an ion-concentration of an analyte solution coupled to the floating gate via the passivation layer in the selected chemFET based on a sampled voltage level on the selected column line, wherein the sampled voltage level is established based on the current flowing on the selected column line.

19. The device of claim 18, wherein the sense circuitry includes a current sink coupled to the selected column line to compensate for leakage current through the remaining chemFETs connected to the selected column line.

20. The device of claim 18, wherein the sense circuitry includes:

a pre-charge circuit to pre-charge a selected column line to a pre-charge voltage level prior to a read interval; and

a sample circuit to read the selected chemFET based on the sampled voltage level on the selected column line during the read interval.