US20110273598A1 - Solid-state image sensor and camera - Google Patents

Solid-state image sensor and camera Download PDF

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Publication number
US20110273598A1
US20110273598A1 US13/090,380 US201113090380A US2011273598A1 US 20110273598 A1 US20110273598 A1 US 20110273598A1 US 201113090380 A US201113090380 A US 201113090380A US 2011273598 A1 US2011273598 A1 US 2011273598A1
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Prior art keywords
signal processing
column signal
processing circuits
pixels
well
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US13/090,380
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English (en)
Inventor
Masaya Ogino
Yuichiro Yamashita
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Canon Inc
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Canon Inc
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Assigned to CANON KABUSHIKI KAISHA reassignment CANON KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OGINO, MASAYA, YAMASHITA, YUICHIRO
Publication of US20110273598A1 publication Critical patent/US20110273598A1/en
Priority to US14/996,651 priority Critical patent/US9621832B2/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/10—Circuitry of solid-state image sensors [SSIS]; Control thereof for transforming different wavelengths into image signals
    • H04N25/11—Arrangement of colour filter arrays [CFA]; Filter mosaics
    • H04N25/13—Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements
    • H04N25/134—Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements based on three different wavelength filter elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
    • H04N25/625—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of smear
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
    • H04N25/628—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for reducing horizontal stripes caused by saturated regions of CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/709—Circuitry for control of the power supply
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/745—Circuitry for generating timing or clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/767—Horizontal readout lines, multiplexers or registers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/7795—Circuitry for generating timing or clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present invention relates to a solid-state image sensor and a camera including the same.
  • a potential change of a column signal line often influences other column signal lines via a power supply line used to drive a column signal processing circuit or a signal line used to control the column signal processing circuit.
  • a potential change of a column signal line often influences other column signal lines via a power supply line used to drive a column signal processing circuit or a signal line used to control the column signal processing circuit.
  • mixture of colors may occur since the pixel signals of the plurality of colors influence each other.
  • the present invention provides a technique which is effective to reduce mixture of colors in the arrangement in which pixel signals of a plurality of colors are read out during a single period.
  • the first aspect of the present invention provides a solid-state image sensor comprising a pixel array in which a plurality of pixels are two-dimensionally arranged, and a plurality of column signal processing circuits which read out signals from the pixel array via a plurality of column signal lines arranged in correspondence with respective columns of the pixel array, wherein signals of the pixels of different colors in the pixel array are read out by the plurality of column signal processing circuits during a single period, and wherein at least the column signal processing circuits which process signals of the pixels of different colors, of the plurality of column signal processing circuits, are driven via conductive lines which are separated from each other in a region where at least the column signal processing circuits which process signals of the pixels of different colors are arranged.
  • the second aspect of the present invention provides a camera comprising the above solid-state image sensor, and a processing section which processes signals output from the solid-state image sensor.
  • FIG. 1 is a block diagram showing an example of the arrangement of a solid-state image sensor
  • FIG. 2 is a diagram for explaining the reason why mixture of colors occurs via a power supply line
  • FIG. 3 is a diagram for explaining the reason why mixture of colors occurs via a control line
  • FIG. 4 is a block diagram showing the arrangement of a solid-state image sensor according to the first embodiment of the present invention.
  • FIG. 5 is a block diagram showing the arrangement of a solid-state image sensor according to the second embodiment of the present invention.
  • FIG. 6 is a block diagram showing the arrangement of a solid-state image sensor according to the third embodiment of the present invention.
  • FIG. 7 is a view for explaining an example of a chip layout of the solid-state image sensor of each of the first to third embodiments;
  • FIG. 8 is a view for explaining a modification of the solid-state image sensor of each of the first to third embodiments.
  • FIG. 9 is a circuit diagram for explaining an example of the practical circuit arrangement and operation of the solid-state image sensor of each of the first to third embodiments.
  • FIG. 10 is a timing chart for explaining an example of the practical circuit arrangement and operation of the solid-state image sensor of each of the first to third embodiments;
  • FIG. 11 a sectional view for explaining an example of the sectional structure of the solid-state image sensor.
  • FIG. 12 a sectional view for explaining an example of the sectional structure of the solid-state image sensor.
  • FIG. 1 is a block diagram showing an example of the arrangement of a solid-state image sensor.
  • a pixel array 102 is configured by arranging a plurality of pixel sections 101 in two-dimension.
  • Each pixel can include, for example, a photoelectric conversion element, a floating diffusion (to be abbreviated as FD hereinafter), a transfer switch which transfers a charge generated and accumulated by the photoelectric conversion element to the FD, and an amplifier section which outputs a signal according to the charge transferred to the FD to a column signal line 122 or 123 .
  • Each pixel can further include a reset section which resets a potential of the FD, and a selection section. A method of omitting the selection section, and selecting a row by controlling the FD potential is also available.
  • any of R, G 1 , G 2 , and B color filters are arranged according to an arrangement such as a Bayer arrangement. Pixels on which the R, G 1 , G 2 , and B color filters are arranged can be respectively called an R pixel, G 1 pixel, G 2 pixel, and B pixel.
  • the R pixel is a red pixel
  • the G 1 and G 2 pixels are green pixels
  • the B pixel is a blue pixel.
  • the G 1 and G 2 pixels are those having the same color (both pixels may be called G pixels), and the R, G, and B pixels are those having different colors.
  • a row of the pixel array 102 is selected by a row selecting circuit (vertical scanning circuit) 120 , and columns of the pixel array 102 are selected by column selecting circuits (horizontal scanning circuits) 106 and 107 .
  • the row selecting circuit 120 and the column selecting circuits 106 and 107 operate according to timing signals which are generated by a timing control circuit 104 based on clocks 103 .
  • Signals of pixels of a column selected by the column selecting circuit 107 are read out by a column signal processing circuit of that column, and are output via a switch 151 , horizontal signal lines 131 and 132 , and output amplifiers 141 and 142 .
  • Signals of pixels of a column selected by the column selecting circuit 106 are read out by a column signal processing circuit of that column, and are output via a switch 152 , horizontal signal lines 133 and 134 , and output amplifiers 143 and 144 .
  • a plurality of column signal lines 122 and 123 are connected, so that two column signal lines 122 and 123 are connected to each column.
  • the plurality of column signal lines 122 are connected to column signal processing circuits 108 to 111 arranged on one side of the pixel array 102 .
  • the plurality of column signal lines 123 are connected to column signal processing circuits 114 to 117 arranged on the other side of the pixel array 102 .
  • the column signal processing circuits 108 to 111 read out signals from the G 2 and B pixels via the plurality of column signal lines 122 during a single period.
  • the column signal processing circuits 114 to 117 read out signals from the R and G 1 pixels via the plurality of column signal lines 123 during a single period.
  • the column signal processing circuits 108 to 111 arranged on one side of the pixel array 102 read out signals from the pixels of the two different colors during a single period.
  • the column signal processing circuits 114 to 117 arranged on the other side of the pixel array 102 read out signals from the pixels of the two different colors during a single period.
  • the column signal processing circuits 108 to 111 and 114 to 117 are controlled to read out signals from the pixels during a single period, and the signals can be read out from the pixels of all the colors during the single period.
  • a signal output from the amplifier circuit 306 is influenced by the potential variation of the control signal 119 L. That is, signals of a plurality of colors are read out by the column signal processing circuits using the common control line during a single period, thus causing mixture of colors. As a result, the resolution and color reproducibility deteriorate.
  • signals of a plurality of colors are read out by the column signal processing circuits using a common conductive line (for example, the power supply line or control line) during a single period, thus causing mixture of colors.
  • a common conductive line for example, the power supply line or control line
  • FIG. 4 is a block diagram showing the arrangement of a solid-state image sensor according to the first embodiment of the present invention.
  • the same reference numerals in FIG. 4 denote the same parts as in FIG. 1 .
  • pixel sections 101 are arranged in 4 rows ⁇ 4 columns in a pixel array 102 in FIG. 4 .
  • this arrangement is for the purpose of descriptive convenience, and in general more pixel sections 101 are arranged.
  • at least column signal processing circuits which process signals of pixels of different colors of a plurality of column signal processing circuits are driven via separated conductive lines.
  • At least the column signal processing circuits which process signals of pixels of different colors of the plurality of column signal processing circuits are supplied with power supply voltages via separated conductive lines (power supply lines), and are supplied with control signals of the same logic level via separated conductive lines (control lines).
  • at least the column signal processing circuits which process signals of pixels of the same color of the plurality of column signal processing circuits may also be supplied with power supply voltages via separated power supply lines, and may also be supplied with control signals of the same logic level via separated control lines.
  • a power supply line 519 as one conductive line connected to a power supply section 112 is branched into power supply lines 519 a and 519 b as conductive lines outside a region where column signal processing circuits 506 to 509 as supply destinations (or driving targets) of a power supply voltage are arranged. Therefore, the power supply line 519 is separated into the power supply lines 519 a and 519 b within the region where the column signal processing circuits 506 to 509 as the supply destinations of a power supply voltage are arranged.
  • a power supply line 520 as one conductive line connected to a power supply section 118 is branched into power supply lines 520 a and 520 b as conductive lines outside a region where column signal processing circuits 510 to 513 as supply destinations (or driving targets) of a power supply voltage are arranged.
  • the power supply line 520 is separated into the power supply lines 520 a and 520 b within the region where the column signal processing circuits 510 to 513 as the supply destinations of a power supply voltage are arranged.
  • a control line 516 as one conductive line connected to a timing control circuit 104 is branched into control lines 516 a and 516 b as conductive lines outside a region where the column signal processing circuits 506 to 509 as supply destinations (or driving targets) of a control signal are arranged.
  • the control line 516 is separated into the control lines 516 a and 516 b within the region where the column signal processing circuits 506 to 509 as the supply destinations of a control signal are arranged.
  • a control line 517 as one conductive line connected to a timing control circuit 104 is branched into control lines 517 a and 517 b as conductive lines outside a region where the column signal processing circuits 510 to 513 as supply destinations (or driving targets) of a control signal are arranged.
  • the control line 517 is separated into the control lines 517 a and 517 b within the region where the column signal processing circuits 510 to 513 as the supply destinations of a control signal are arranged.
  • the power supply sections 112 and 118 may be interface circuits (power supply circuits) such as voltage conversion circuits which convert an externally supplied voltage, or may be a power supply pad of the solid-state image sensor configured as a chip.
  • the power supply pad is an example of a pad which is driven by the solid-state image sensor or an external circuit of the chip (external power supply circuit).
  • the column signal processing circuits 506 and 508 which process signals of G 2 pixels are supplied with a power supply voltage via the power supply line 519 a, and are supplied with column signal processing pulses as an example of a control signal via the control line 516 a.
  • the column signal processing circuits 507 and 509 which process signals of B pixels are supplied with a power supply voltage via the power supply line 519 b, and are supplied with column signal processing pulses as an example of a control signal via the control line 516 b .
  • the column signal processing circuits 510 and 512 which process signals of R pixels are supplied with a power supply voltage via the power supply line 520 a, and are supplied with column signal processing pulses as an example of a control signal via the control line 517 a .
  • the power supply line 520 b and control line 517 b connected to the column signal processing circuits 511 and 513 which process signals of the G 1 pixels are different from the power supply line 519 a and control line 516 a connected to the column signal processing circuits 506 and 508 which process signals of the G 2 pixels.
  • At least the signal processing circuits which process signals of pixels of different colors of the plurality of signal processing circuits are supplied with power supply voltages via the separated power supply lines, and are supplied with control signals of the same logic level via the separated control lines.
  • the problem of mixture of colors is reduced.
  • the signal processing circuits which process signals of pixels of different colors of the plurality of signal processing circuits are supplied with only control signals of the same logic level via the separated control lines, the problem of mixture of colors is reduced.
  • FIG. 5 is a block diagram showing the arrangement of a solid-state image sensor according to the second embodiment of the present invention.
  • signals of G 1 and G 2 pixels are read out by column signal processing circuits 606 to 609 which are arranged in the same direction when viewed from a pixel array 102 .
  • the column signal processing circuits 606 to 609 which read out signals of the G 1 and G 2 pixels may be driven via conductive lines which are separated from each other. That is, separated power supply lines and/or separated control lines may be provided to the column signal processing circuits 606 to 609 which read out signals of the G 1 and G 2 pixels.
  • the G 1 and G 2 pixels have the same color, mutual influences between the G 1 and G 2 pixels are smaller than mixture of colors between different colors.
  • FIG. 6 is a block diagram showing the arrangement of a solid-state image sensor according to the third embodiment of the present invention.
  • all column signal processing circuits 906 to 913 are arranged in the same direction when viewed from a pixel array 102 .
  • at least signal processing circuits which process signals of pixels of different colors of a plurality of signal processing circuits are driven via conductive lines which are separated from each other. That is, in the third embodiment as well, at least the signal processing circuits which process signals of pixels of different colors of the plurality of signal processing circuits are supplied with power supply voltages via separated power supply lines, and are supplied with control signals of the same logic level via separated control lines.
  • At least the signal processing circuits which process signals of pixels of different colors of the plurality of signal processing circuits need only be supplied with power supply voltages via the separated power supply lines.
  • at least the signal processing circuits which process signals of pixels of different colors of the plurality of signal processing circuits need only be supplied with control signals (column signal processing pulses) of the same logic level via the separated control lines.
  • a power supply line 520 connected to a power supply section 118 is separated into power supply lines 520 a to 520 d outside a region where the column signal processing circuits 906 to 913 as supply destinations of a power supply voltage are arranged.
  • a control line 517 connected to a timing control circuit 104 is separated into control lines 517 a to 517 d outside the region where the column signal processing circuits 906 to 913 as supply destinations of a control signal are arranged.
  • the arrangement design of the column signal processing circuits is facilitated even when the arrangement pitch of the pixel sections 101 is reduced.
  • the column signal processing block 710 is configured by a plurality of column signal processing circuits (the column signal processing circuits 506 to 509 in the first embodiment). Also, the column signal processing block 710 includes first and second regions 710 A and 710 B. The first region 710 A is closer to the pixel array 102 than the second region 710 B. In other words, the first region 710 A is arranged between the pixel array 102 and second region 710 B. In the first region 710 A, first column signal processing circuits which read out signals of pixels of the same color (the column signal processing circuits 506 and 508 in the first embodiment) are arranged.
  • second column signal processing circuits which read out signals of pixels of the same color (the column signal processing circuits 507 and 509 in the first embodiment) are arranged.
  • the first column signal processing circuits arranged in the first region 710 A and the second column signal processing circuits arranged in the second region 710 B read out signals of pixels of different colors.
  • the column signal processing block 720 is configured by a plurality of column signal processing circuits (the column signal processing circuits 510 to 513 in the first embodiment).
  • the column signal processing block 720 includes first and second regions 720 A and 720 B.
  • the first region 720 A is closer to the pixel array 102 than the second region 720 B.
  • the first region 720 A is arranged between the pixel array 102 and second region 720 B.
  • first column signal processing circuits which read out signals of pixels of the same color are arranged.
  • the control line 516 connected to the timing control circuit 104 is branched (separated) into the control lines 516 a and 516 b outside the region where the column signal processing block 710 as a supply destination of a control signal is arranged.
  • the control line 517 connected to the timing control circuit 104 is branched (separated) into the control lines 517 a and 517 b outside the region where the column signal processing block 720 as a supply destination of a control signal is arranged.
  • a circuit corresponding to the timing control circuit 104 is arranged as an external circuit outside the solid-state image sensor configured as the chip 700 .
  • the chip 700 has input pads 810 and 820 , and control signals are supplied from the external circuit to the input pads 810 and 820 .
  • the input pad is an example of a pad which is driven by the solid-state image sensor or an external circuit of the chip.
  • the control line 516 is connected to the input pad 810 via an interface circuit such as an input circuit or directly.
  • the control line 516 is branched (separated) into the control lines 516 a and 516 b outside the region where the column signal processing block 710 as the supply destination of a control signal is arranged.
  • the control line 517 is connected to the input pad 820 via an interface circuit such as an input circuit or directly.
  • the control line 517 is branched (separated) into the control lines 517 a and 517 b outside the region where the column signal processing block 720 as the supply destination of a control signal is arranged.
  • a column signal processing circuit 220 corresponds to the column signal processing circuits 506 to 509 and the like (the first embodiment).
  • a column signal line 230 corresponds to the column signal lines 122 and 123 .
  • a switch section 240 corresponds to the switches 151 and 152 .
  • An output amplifier 250 corresponds to the output amplifiers 141 to 144 .
  • the pixel section 101 includes, for example, a photoelectric conversion element 201 , transfer transistor 202 , floating diffusion (to be abbreviated as FD hereinafter) 217 , reset transistor 204 , source-follower transistor 203 , and selecting transistor 205 .
  • the photoelectric conversion element 201 can be, for example, a photodiode.
  • the transfer transistor 202 transfers a charge generated by photoelectric conversion in the photoelectric conversion element 201 to the FD 217 when a transfer pulse PTX goes to active level.
  • the FD 217 converts the charge into a potential.
  • the reset transistor 204 resets the potential of the FD 217 when a reset pulse PRES goes to active level.
  • the source-follower transistor 203 amplifies the potential of the FD 217 .
  • the selecting transistor 205 sets the pixel section 101 including that selecting transistor 205 in a selected state when a selecting pulse PSEL goes to active level. In the selected state, a signal of the pixel section 101 is output
  • the column signal line 230 is connected to a current source 210 which configures a source-follower circuit together with the source-follower transistor 203 , and a clamp capacitor 206 of the column signal processing circuit 220 .
  • the column signal processing circuit 220 is a circuit which processes a signal output from the pixel section 101 via the column signal line 230 and, more specifically, a circuit which reads out a signal from the pixel section 101 via the column signal line 230 .
  • the column signal processing circuit 220 includes a column amplifier circuit configured by the clamp capacitor 206 , a differential amplifier 207 , feedback capacitor 208 , and switch 219 .
  • the differential amplifier 207 is supplied with a power supply voltage via a power supply line (for example, one of the aforementioned power supply lines 519 a, 519 b , 520 a, and 520 b ).
  • An output terminal 209 and one input terminal of the differential amplifier 207 are connected via the switch 219 .
  • the other input terminal of the differential amplifier 207 is connected to a reference voltage VCOR.
  • the output terminal 209 of the differential amplifier 207 (column amplifier circuit) is connected to holding capacitors 213 and 214 via switches 211 and 212 .
  • a gate electrode of a constant current transistor 218 which controls a consumption current of the differential amplifier 207 is connected to a current control section 260 .
  • Control signals supplied to the column signal processing circuit via the aforementioned control lines 516 and 517 can be, for example, pulse signals such as a clamp pulse PCOR, PTN pulse, and PTS pulse which respectively control the switches 219 , 211 , and 212 .
  • the selecting pulse PSEL goes to high level (active level), and the source-follower transistor 203 is set in an active state.
  • the reset pulse PRES is at high level (active level)
  • the FD 217 is reset to a reset voltage by the reset transistor 204 .
  • the clamp pulse PCOR goes to high level, and the differential amplifier 207 is set in a buffer state, that is, a state in which it outputs the reference voltage VCOR.
  • the reset transistor 204 is disabled. In this state, the potential of the column signal line 230 is a reference potential VN corresponding to the potential of the reset FD 217 .
  • the clamp pulse PCOR goes to low level, and the reference potential VN on the column signal line 230 is clamped.
  • the transfer pulse PTX goes to high level (active level) to enable the transfer transistor 202 , and a charge accumulated on the photoelectric conversion element 201 is transferred to the FD 217 . Then, the potential of the column signal line 230 changes to a voltage VS according to the charge transferred to the FD 217 .
  • the PTS pulse goes to high level to enable the switch 212 , and an output voltage of the column amplifier circuit including the differential amplifier 207 is written in the holding capacitor 214 . In this case, when a signal charge of the pixel section 101 is given by electrons, VS ⁇ VN.
  • the output voltage of the column amplifier circuit amounts to a sum of a voltage which is obtained by inversely amplifying a voltage change amount (VS ⁇ VN) by a gain determined by C 0 /Cf, and a voltage which is obtained by adding the offset voltage of the differential amplifier 207 to the reference voltage VCOR.
  • CO is the capacitance of the clamp capacitor 206
  • Cf is that of the feedback capacitor 208 .
  • the signals held in the holding capacitors 213 and 214 are supplied to the output amplifier 250 via the switches 215 and 216 of the switch section 240 according to the column selecting pulse driven by the column selecting circuits 106 and 107 , and are differentially amplified.
  • FIG. 11 is a sectional view illustrating an example of the sectional structure taken along A-A′ in FIG. 7 .
  • P-wells 1005 , 1006 , 1007 , and 1008 are arranged in an N-type semiconductor substrate 1011 .
  • the pixel array 102 is arranged in the P-well 1005 .
  • MOS transistors of the column signal processing circuits in the first region 720 A are formed, and the P-well 1006 is grounded via a ground line 1003 .
  • MOS transistors of the column signal processing circuits in the second region 720 B are formed, and the P-well 1007 is grounded via a ground line 1004 .
  • the P-wells 1006 and 1007 are isolated from each other.
  • the column selecting circuit 106 is arranged.
  • the column signal processing circuits in the first region 720 A are supplied with a power supply voltage via the power supply line 520 b.
  • the power supply line 520 b is arranged on an N + -region 1009 arranged between the P-wells 1005 and 1006 , and is connected to the N + -region 1009 .
  • the column signal processing circuits in the second region 720 B are supplied with a power supply voltage via the power supply line 520 a.
  • the power supply line 520 a is arranged on an N + -region 1010 arranged between the P-wells 1006 and 1007 , and is connected to the N + -region 1010 .
  • the N-type semiconductor substrate 1011 As exemplified in FIG. 11 , upon adopting a structure in which the P-wells 1006 and 1007 where the column signal processing circuits that process signals of pixels of different colors are formed are isolated, electron mobility between the P-wells 1006 and 1007 is suppressed by the N-type semiconductor substrate 1011 . This is advantageous in reduction of mixture of colors. Furthermore, the N + -regions 1009 and 1010 and the power supply lines 520 b and 520 a, which are arranged between the P-wells 1005 , 1006 , and 1007 , have an effect of ejecting neighboring electrons outside the N-type semiconductor substrate 1011 . They are also advantageous in reduction of mixture of colors.
  • FIG. 12 is a sectional view illustrating another example of the sectional structure taken along A-A′ in FIG. 7 .
  • the example shown in FIG. 12 adopts a so-called “triple-well structure”.
  • P-wells 1105 , 1106 , 1107 , and 1108 are arranged in the N-type semiconductor substrate 1011 .
  • the pixel array 102 is arranged in the P-well 1105 .
  • the MOS transistors of the column signal processing circuits in the first region 720 A are formed.
  • the P-well (second P-well) 1107 the MOS transistors of the column signal processing circuits in the second region 720 B are formed.
  • the P-well 1108 the column selecting circuit 106 is arranged.
  • the P-wells 1106 and 1107 are isolated from each other.
  • a P + -region 1113 which is connected to a ground line 1103 , is arranged, and the P-well 1106 is grounded by this region.
  • An N-well 1109 is further arranged in the P-well 1106 , and an N + -region 1111 , which is connected to the power supply line 520 b, is arranged in the N-well 1109 .
  • a P + -region 1114 which is connected to a ground line 1104 , is arranged, and the P-well 1107 is grounded by this region.
  • An N-well 1110 is further arranged in the P-well 1107 , and an N + -region 1112 , which is connected to the power supply line 520 a, is arranged in the N-well 1110 .
  • the present invention When the present invention is applied to a CMOS image sensor, the same effects can be obtained not only for an obverse surface incidence type image sensor, which is popularly used, but also for a reverse surface incidence type image sensor.
  • the reverse surface irradiation type since a semiconductor substrate is generally as thin as several microns, generated electrons are not diffused in a deep region of the substrate, but they float near the surface, thus readily causing mixture of colors. Therefore, a reduction of the mixture of colors can be obtained more notably.
  • a camera which incorporates the solid-state image sensor will be exemplified below.
  • the concept of a camera includes not only an apparatus which mainly aims at image capturing but also an apparatus which accessorily includes an image capturing function (for example, a personal computer and mobile phone).
  • the camera includes the solid-state image sensor according to the present invention exemplified as the aforementioned embodiments, and a processing section which processes signals output from the solid-state image sensor.
  • the processing section can include, for example, an A/D converter, and a processor which processes digital data output from the A/D converter.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Color Television Image Signal Generators (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
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US9621832B2 (en) 2017-04-11
JP5631050B2 (ja) 2014-11-26

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