US20110163452A1 - Semiconductor device, method of manufacturing semiconductor device, and substrate processing apparatus - Google Patents

Semiconductor device, method of manufacturing semiconductor device, and substrate processing apparatus Download PDF

Info

Publication number
US20110163452A1
US20110163452A1 US12/984,018 US98401811A US2011163452A1 US 20110163452 A1 US20110163452 A1 US 20110163452A1 US 98401811 A US98401811 A US 98401811A US 2011163452 A1 US2011163452 A1 US 2011163452A1
Authority
US
United States
Prior art keywords
film
metal film
metal
chamber
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/984,018
Other languages
English (en)
Inventor
Sadayoshi Horii
Arito Ogawa
Hideharu Itatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Kokusai Electric Inc
Original Assignee
Hitachi Kokusai Electric Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Kokusai Electric Inc filed Critical Hitachi Kokusai Electric Inc
Assigned to HITACHI KOKUSAI ELECTRIC INC. reassignment HITACHI KOKUSAI ELECTRIC INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HORII, SADAYOSHI, ITATANI, HIDEHARU, OGAWA, ARITO
Publication of US20110163452A1 publication Critical patent/US20110163452A1/en
Priority to US14/629,345 priority Critical patent/US9437704B2/en
Priority to US14/629,338 priority patent/US9472637B2/en
Priority to US15/228,840 priority patent/US9653301B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
    • C23C16/45529—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations specially adapted for making a layer stack of alternating different compositions or gradient compositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device, a method of manufacturing a semiconductor device, and a substrate processing apparatus.
  • a high-k/metal gate structure which is constituted by a gate insulating film made of a high permittivity insulating material (high-k material) and a gate electrode made of a metal.
  • a gate electrode is made of a metal having a high work function of about 4.8 eV to 5.1 eV, and for example, it is considered that a gate electrode is made of a noble metal such as platinum (Pt).
  • a capacitor insulating film is made of a high permittivity insulating material such as a hafnium dioxide (HfO 2 ), a zirconium dioxide (ZrO 2 ), a titanium dioxide (TiO 2 ), a tantalum pentoxide (Ta 2 O 5 ), and a niobium pentoxide (Nb 2 O 5 ).
  • a leak current of a capacitor part can be effectively reduced by forming a capacitor electrode using a metal having a high work function.
  • a capacitor electrode is made of a material such as a titanium nitride (TiN) having a work function of about 4.6 eV.
  • a capacitor electrode is made of a noble metal such as Pt having a high work function of about 5.1 eV.
  • a metal film for example, a gate electrode, a capacitor electrode, etc.
  • an expensive noble metal such as Pt
  • another metal having a high work function such as nickel (Ni) or cobalt (Co) is used instead of a noble metal such as Pt.
  • Ni nickel
  • Co cobalt
  • such a metal is easily oxidized, and if a metal film (a gate electrode or a capacitor electrode) is oxidized, the equivalent oxide thickness (EOT) of the metal film may be increased.
  • a semiconductor device including: an insulating film disposed on a substrate; and a metal film disposed adjacent to the insulating film, wherein the metal film includes a stacked structure of a first metal film and a second metal film, an oxidation resistance of the first metal film is greater than that of the second metal film, the second metal film has a work function greater than 4.8 eV and is different from the first metal film in material, and the first metal film is disposed between the second metal film and the insulating film.
  • a method of manufacturing a semiconductor device including: forming an insulating film on a substrate; and forming a metal film including a stacked structure of a first metal film and a second metal film adjacent to the insulating film, the first metal film being formed between the second metal film and the insulating film, wherein an oxidation resistance of the first metal film is greater than that of the second metal film, and the second metal film has a work function greater than 4.8 eV and is different from the first metal film in material.
  • a substrate processing apparatus including: a process chamber configured to process a substrate; a first process gas supply system configured to supply a first process gas into the process chamber to form a first metal film; a second process gas supply system configured to supply a second process gas into the process chamber to form a second metal film; and a controller configured to control the first process gas supply system and the second process gas supply system, wherein an oxidation resistance of the first metal film is greater than that of the second metal film, the second metal film has a work function greater than 4.8 eV and is different from the first metal film in material, and the controller controls the first process gas supply system and the second process gas supply system to form a metal film having a stacked structure of the first metal film and the second metal film adjacent to an insulating film disposed on the substrate by supplying the first process gas and the second process gas into the process chamber where the substrate is accommodated such that the first metal film is formed between the second metal film and the insulating film.
  • FIG. 1 is a flowchart for explaining substrate processing processes according to an embodiment of the present invention.
  • FIG. 2 is a view illustrating a gas supply system of a substrate processing apparatus relevant to the embodiment of the present invention.
  • FIG. 3 is a sectional view illustrating the substrate processing apparatus when a wafer is processed according to the embodiment of the present invention.
  • FIG. 4 is a sectional view illustrating the substrate processing apparatus when a wafer is carried according to the embodiment of the present invention.
  • FIG. 5A is a sectional view illustrating a gate electrode formed by performing a TiN film-forming process and a Ni film-forming process once
  • FIG. 5B is sectional view illustrating a gate electrode formed by performing the TiN film-forming process and the Ni film-forming process a plurality of times.
  • FIG. 6A is a sectional view illustrating a capacitor electrode formed by performing a TiN film-forming process and a Ni film-forming process once
  • FIG. 6B is sectional view illustrating a capacitor electrode formed by performing the TiN film-forming process and the Ni film-forming process a plurality of times.
  • FIG. 7 is a schematic view illustrating the energy level of a conventional capacitor electrode constituted by a single layer of TiN film.
  • FIG. 8 is a schematic view illustrating the energy levels of a metal film formed by performing a TiN film-forming process and a Ni film-forming process once.
  • FIG. 9 is a schematic view illustrating the energy levels of a metal film formed by setting a TiN film-forming process and a Ni film-forming process as one cycle and performing the cycle a plurality of times.
  • FIG. 10 is a table illustrating a group of metals having work functions higher than 4.8 eV which can be used for forming a second metal film.
  • FIG. 11 is a flowchart for explaining processes of forming an example 1 (sample B) and a comparative example (sample C) illustrated in FIG. 12 .
  • FIG. 12 is a schematic view for explaining the stacked structure of the example 1 (sample B) of the present invention together with the stacked structure of a conventional example (sample A) and the stacked structure of the comparative example (sample C).
  • FIG. 13 is a graph illustrating the equivalent oxide thicknesses (EOTs) of the samples A, B, and C illustrated in FIG. 12 .
  • FIG. 14 is a graph illustrating relationships between leak current densities and EOTs of the respective samples A, B, and C illustrated in FIG. 12 .
  • FIG. 15 is a graph illustrating relationships between leak current densities and applied voltages of the respective samples A, B, and C illustrated in FIG. 12 .
  • FIG. 16A is a schematic view illustrating the stacked structure of an example 2 (sample D) of the present invention
  • FIG. 16B is a graph illustrating a relationship between work function and TiN film thickness of the sample D together with those of the sample B and sample C.
  • FIG. 17A and FIG. 17B are schematic views illustrating a vertical process furnace of a vertical apparatus according to another embodiment of the present invention, in which FIG. 17A is a vertical sectional view illustrating the vertical process furnace and FIG. 17B is a sectional view of the vertical process furnace taken along line A-A of FIG. 17A .
  • FIG. 18 is a schematic view illustrating a cluster apparatus according to another embodiment of the present invention.
  • FIG. 3 is a sectional view illustrating the substrate processing apparatus when a wafer is processed according to an embodiment of the present invention
  • FIG. 4 is a sectional view illustrating the substrate processing apparatus when the wafer is carried according to the embodiment of the present invention.
  • the substrate processing apparatus relevant to the current embodiments includes a process vessel 202 .
  • the process vessel 202 is a flat airtight vessel having a circular cross sectional shape.
  • the process vessel 202 is made of a metal material such as aluminum or stainless steel (e.g., SUS described in the Japanese industrial standard).
  • a process chamber 201 is formed to process a substrate such as a wafer 200 (e.g., a silicon wafer).
  • a support stage 203 is installed to support a wafer 200 .
  • a susceptor 217 made of a material such as quartz (SiO 2 ), carbon, a ceramic material, silicon carbide (SiC), aluminum oxide (Al 2 O 3 ), or aluminum nitride (AlN) is installed as a support plate.
  • a heater 206 is built as a heating unit (heating source) configured to heat the wafer 200 .
  • the lower end part of the support stage 203 penetrates the bottom side of the process vessel 202 .
  • an elevating mechanism 207 b is installed to raise and lower the support stage 203 .
  • the elevating mechanism 207 b By operating the elevating mechanism 207 b to raise and lower the support stage 203 , the wafer 200 supported on the susceptor 217 can be raised and lowered.
  • the support stage 203 When the wafer 200 is carried, the support stage 203 is lowered to a position (wafer carrying position) shown in FIG. 4 , and when the wafer 200 is processed, the support stage 203 is raised to a position (wafer processing position) shown in FIG. 3 .
  • the lower end part of the support stage 203 is surrounded by a bellows 203 a so that the inside of the process chamber 201 can be hermetically maintained.
  • three lift pins 208 b are installed in a manner such that the lift pins 208 b are vertically erected. Furthermore, in the support stage 203 (including the susceptor 217 ), penetration holes 208 a are respectively formed at positions corresponding to the lift pins 208 b so that the lift pins 208 b can be inserted through the penetration holes 208 a . Therefore, when the support stage 203 is lowered to the wafer carrying position, as shown in FIG. 4 , upper parts of the lift pins 208 b protrude from the top surface of the susceptor 217 so that the lift pins 208 b can support the wafer 200 from the bottom side of the wafer 200 .
  • the lift pins 208 b are retracted from the top surface of the susceptor 217 so that the susceptor 217 can support the wafer 200 from the bottom side of the wafer 2 . Since the lift pins 208 b make direct contact with the wafer 200 , it is preferable that the lift pins 208 b are made of a material such as quartz or alumina.
  • a wafer carrying entrance 250 is installed so that a wafer 200 can be carried into and out of the process chamber 201 through wafer carrying entrance 250 .
  • a gate valve 251 is installed so that the inside of the process chamber 201 can communicate with the inside of a carrying chamber (preliminary chamber) 271 by opening the gate valve 251 .
  • the carrying chamber 271 is formed in a carrying vessel (airtight vessel) 272 .
  • a carrying robot 273 is installed to carry a wafer 200 .
  • the carrying robot 273 includes a carrying arm 273 a to support a wafer 200 when the wafer 200 is carried.
  • a wafer 200 can be carried between the inside of the process chamber 201 and the inside of the carrying chamber 271 by using the carrying robot 273 .
  • a wafer 200 carried into the process chamber 201 is temporarily placed on the lift pins 208 b as described above.
  • a loadlock chamber (not shown) is installed, and a wafer 200 can be carried between the inside of the loadlock chamber and the inside of the carrying chamber 271 by using the carrying robot 273 .
  • the loadlock chamber is used as a preliminary chamber to temporarily accommodate a non-processed or processed wafer 200 .
  • an exhaust outlet 260 is installed for exhausting the inside atmosphere of the process chamber 201 .
  • An exhaust pipe 261 is connected to the exhaust outlet 260 through an exhaust chamber 260 a , and at the exhaust pipe 261 , a pressure regulator 262 such as an auto pressure controller (APC) configured to control the inside pressure of the process chamber 201 , a source collection trap 263 , and a vacuum pump 264 are sequentially connected in series.
  • An exhaust system (exhaust line) is constituted mainly by the exhaust outlet 260 , the exhaust chamber 260 a , the exhaust pipe 261 , the pressure regulator 262 , the source collection trap 263 , and the vacuum pump 264 .
  • a gas inlet 210 is installed at the top surface (the ceiling wall) of a shower head 240 (described later) installed at an upper part of the process chamber 201 .
  • a gas supply system connected to the gas inlet 210 will be described later.
  • the shower head 240 is installed as a gas distributing mechanism.
  • the shower head 240 includes a distributing plate 240 a configured to distribute a gas introduced through the gas inlet 210 , and a shower plate 240 b configured to distribute the gas passing through the distributing plate 240 a more uniformly and supply the gas to the surface of the wafer 200 placed on the support stage 203 .
  • a plurality of ventilation holes are formed in the distributing plate 240 a and the shower plate 240 b .
  • the distributing plate 240 a is disposed to face the top surface of the shower head 240 and the shower plate 240 b
  • the shower plate 240 b is disposed to face the wafer 200 placed on the support stage 203 .
  • spaces are provided which function as a first buffer space (distributing chamber) 240 c through which gas supplied through the gas inlet 210 is distributed and a second buffer space 240 d through which gas passing through the distributing plate 240 a is diffused.
  • a stopper 201 a is installed in the side surface of the inner wall of the process chamber 201 (process vessel 202 ).
  • the stopper 201 a is configured to hold a conductance plate 204 at a position adjacent to the wafer processing position.
  • the conductance plate 204 is configured as a doughnut-shaped (ring-shaped) circular disk having an opening to accommodate the wafer 200 in its inner circumferential part.
  • a plurality of discharge outlets 204 a are formed in the outer circumferential part of the conductance plate 204 in a manner such that the discharge outlets 204 a are arranged at predetermined intervals in the circumferential direction of the conductance plate 204 .
  • the discharge outlets 204 a are discontinuously formed so that the outer circumferential part of the conductance plate 204 can support the inner circumferential part of the conductance plate 204 .
  • a lower plate 205 latches onto the outer circumferential part of the support stage 203 .
  • the lower plate 205 includes a ring-shaped concave part 205 b and a flange part 205 a formed in one piece with the inner upper side of the concave part 205 b .
  • the concave part 205 b is installed to close a gap between the outer circumferential part of the support stage 203 and the side surface of the inner wall of the process chamber 201 .
  • a plate exhaust outlet 205 c is formed to discharge (distribute) gas from the inside of the concave part 205 b toward the exhaust outlet 260 .
  • the flange part 205 a functions as a latching part that latches onto the upper outer circumferential part of the support stage 203 . Since the flange part 205 a latches onto the upper outer circumferential part of the support stage 203 , the lower plate 205 can be lifted together with the support stage 203 when the support stage 203 is lifted.
  • the lower plate 205 When the support stage 203 is raised to the wafer processing position, the lower plate 205 is also raised to the wafer processing position. As a result, the top surface of the concave part 205 b of the lower plate 205 is blocked by the conductance plate 204 held at a position adjacent to the wafer processing position, and thus a gas flow passage region is formed in the concave part 205 b as an exhaust duct 259 . At this time, by the exhaust duct 259 (the conductance plate 204 and the lower plate 205 ) and the support stage 203 , the inside of the process chamber 201 is divided into an upper process chamber higher than the exhaust duct 259 and a lower process chamber lower than the exhaust duct 259 .
  • the conductance plate 204 and the lower plate 205 may be formed of a material that is durable at a high temperature, for example, high temperature resistant and high load resistant quartz, for the case where reaction products deposited on the inner wall of the exhaust duct 259 are etched away (for the case of self cleaning).
  • gas supplied from the gas inlet 210 to the upper side of the shower head 240 flows from the first buffer space (distributing chamber) 240 c to the second buffer space 240 d through the plurality of holes of the distributing plate 240 a , and is then supplied to the inside of the process chamber 201 through the plurality of holes of the shower plate 240 b , so that the gas can be uniformly supplied to the wafer 200 .
  • the gas supplied to the wafer 200 flows outward in the radial directions of the wafer 200 .
  • the gas After the gas makes contact with the wafer 200 , remaining gas is discharged to the exhaust duct 259 disposed at the outer circumference of the wafer 200 : that is, the remaining gas flows outward on the conductance plate 204 in the radial directions of the wafer 200 and is discharged to the gas flow passage region (the inside of the concave part 205 b ) of the exhaust duct 259 through the discharge outlets 204 a formed in the conductance plate 204 . Thereafter, the gas flows in the exhaust duct 259 and is exhaust through the plate exhaust outlet 205 c and the exhaust outlet 260 . Since gas is guided to flow in this manner, the gas may be prevented from flowing to the lower part of the process chamber 201 . That is, the gas may be prevented from flowing to the rear side of the support stage 203 or the bottom side of the process chamber 201 .
  • FIG. 2 illustrates the configuration of the gas supply system (gas supply lines) of the substrate processing apparatus relevant to the embodiment of the present invention.
  • the gas supply system of the substrate processing apparatus of the current embodiment includes: a bubbler as a vaporizing unit configured to vaporize a liquid source which is liquid at room temperature; a source gas supply system configured to supply a source gas, which is obtained by vaporizing the liquid source using the bubbler, into the process chamber 201 ; and a reaction gas supply system configured to supply a reaction gas different from the source gas into the process chamber 201 .
  • the substrate processing apparatus of the current embodiment includes a purge gas supply system configured to supply a purge gas into the process chamber 201 , and a vent (bypass) system so as not to supply a source gas generated from the bubbler into the process chamber 201 but to exhaust the source gas through a passage bypassing the process chamber 201 .
  • a first source container (first bubbler) 220 a is installed which contains a first source (source A) which is a liquid source
  • a second source container (second bubbler) 220 b is installed which contains a second source (source B) which is a liquid source.
  • Each of the first and second bubblers 220 a and 220 b is configured as a tank (airtight container) in which a liquid source can be stored (filled).
  • the first and second the bubblers 220 a and 220 b are configured as vaporizing units capable of generating a first source gas and a second source gas by vaporizing a first source and a second source through bubbling.
  • sub-heaters 206 a are installed around the first bubbler 220 a and the second bubbler 220 b to heat the first and second bubblers 220 a and 220 b and liquid sources filled in the first and second bubblers 220 a and 220 b .
  • a metal liquid source containing titanium (Ti) such as titanium tetrachloride (TiCl 4 ) may be used as the first source
  • a metal liquid source containing nickel (Ni) such as tetrakis(trifluorophosphine)nickel (Ni(PF 3 ) 4 ) may be used as the second source.
  • a first carrier gas supply pipe 237 a and a second carrier gas supply pipe 237 b are connected to the first bubbler 220 a and the second bubbler 220 b , respectively.
  • Carrier gas supply sources (not shown) are connected to the upstream end parts of the first carrier gas supply pipe 237 a and the second carrier gas supply pipe 237 b .
  • the downstream end parts of the first carrier gas supply pipe 237 a and the second carrier gas supply pipe 237 b are placed in the liquid sources filled in the first bubbler 220 a and the second bubbler 220 b , respectively.
  • a mass flow controller (MFC) 222 a which is a flow rate controller configured to control the supply flow rate of a carrier gas, and valves va 1 and va 2 configured to control supply of the carrier gas are installed at the first carrier gas supply pipe 237 a .
  • a mass flow controller (MFC) 222 b which is a flow rate controller configured to control the supply flow rate of a carrier gas, and valves vb 1 and vb 2 configured to control supply of the carrier gas are installed at the second carrier gas supply pipe 237 b .
  • a gas that does not react with the liquid sources may be used as the carrier gas.
  • inert gas such as N 2 gas and Ar gas may be used as the carrier gas.
  • a first carrier gas supply system (first carrier gas supply line) is constituted mainly by the first carrier gas supply pipe 237 a , the MFC 222 a , and the valves va 1 and va 2
  • a second carrier gas supply system (second carrier gas supply line) is constituted mainly by the second carrier gas supply pipe 237 b , the MFC 222 b , and the valves vb 1 and vb 2 .
  • valves va 1 , va 2 , vb 1 , and vb 2 are opened, and a carrier gas the flow rates of which are controlled by the MFC 222 a and the MFC 222 b is supplied from the first carrier gas supply pipe 237 a and the second carrier gas supply pipe 237 b into the first bubbler 220 a and the second bubbler 220 b .
  • the liquid sources filled in the first and second bubblers 220 a and 220 b are vaporized by bubbling, and thus source gases are generated.
  • the supply flow rates of the first source gas and the second source gas may be calculated from the supply flow rates of the carrier gas. That is, the supply flow rates of the first source gas and the second source gas may be controlled by adjusting the supply flow rates of the carrier gas.
  • a first source gas supply pipe 213 a and a second source gas supply pipe 213 b are respectively connected to the first bubbler 220 a and the second bubbler 220 b to supply the first source gas and the second source gas generated in the first bubbler 220 a and the second bubbler 220 b into the process chamber 201 .
  • the upstream end parts of the first and second source gas supply pipes 213 a and 213 b communicate with inner upper spaces of the first and second bubblers 220 a and 220 b .
  • the downstream end parts of the first and second source gas supply pipes 213 a and 213 b are joined together and then connected to the gas inlet 210 .
  • valves va 5 and va 3 are sequentially installed from the upstream side of the first source gas supply pipe 213 a .
  • the valve va 5 is configured to control supply of the first source gas from the first bubbler 220 a to the first source gas supply pipe 213 a , and the valve va 5 is installed at a position adjacent to the first bubbler 220 a .
  • the valve va 3 is configured to control supply of the first source gas from the first source gas supply pipe 213 a to the process chamber 201 , and the valve va 3 is installed at a position adjacent to the gas inlet 210 .
  • valves vb 5 and vb 3 are sequentially installed from the upstream side of the second source gas supply pipe 213 b .
  • the valve vb 5 is configured to control supply of the second source gas from the second bubbler 220 b to the second source gas supply pipe 213 b , and the valve vb 5 is installed at a position adjacent to the second bubbler 220 b .
  • the valve vb 3 is configured to control supply of the second source gas from the second source gas supply pipe 213 b to the process chamber 201 , and the valve vb 3 is installed at a position adjacent to the gas inlet 210 .
  • the valves va 3 and vb 3 , and a valve ve 3 are highly-durable, high-speed valves. Highly-durable, high-speed valves are integrated valves configured to rapidly switch supply of gas, interruption of gas supply, and exhaustion of gas.
  • the valve ve 3 controls introduction of a purge gas so as to rapidly purge a space of the first source gas supply pipe 213 a between the valve va 3 and the gas inlet 210 and a space of the second source gas supply pipe 213 b between the valve vb 3 and the gas inlet 210 , and then to purge the inside of the process chamber 201 .
  • the liquid sources are vaporized in the first and second bubblers 220 a and 220 b to generate the first and second source gases, and along with this, the valves va 5 , va 3 , vb 5 , and vb 3 are opened, so that the first and second source gases can be supplied into the process chamber 201 from the first and second source gas supply pipes 213 a and 213 b .
  • a first source gas supply system (first source gas supply line) is constituted mainly by the first source gas supply pipe 213 a and the valve va 5 and va 3
  • a second source gas supply system (second source gas supply line) is constituted mainly by the second source gas supply pipe 213 b and the valves vb 5 and vb 3 .
  • a first source supply system (first source supply line) is constituted mainly by the first carrier gas supply system, the first bubbler 220 a , and the first source gas supply system; and a second source supply system (second source supply line) is constituted mainly by the second carrier gas supply system, the second bubbler 220 b , and the second source gas supply system.
  • a first process gas supply system is constituted by the first source supply system and a reaction gas supply system (described later), and a second process gas supply system is constituted by the second source gas supply system.
  • a reaction gas supply source 220 c is installed to supply a reaction gas.
  • the upstream end part of a reaction gas supply pipe 213 c is connected to the reaction gas supply source 220 c .
  • the downstream end part of the reaction gas supply pipe 213 c is connected to the gas inlet 210 through a valve vc 3 .
  • An MFC 222 c which is a flow rate controller configured to control the supply flow rate of a reaction gas, and valves vc 1 and vc 2 configured to control supply of the reaction gas are installed at the reaction gas supply pipe 213 c .
  • ammonia (NH 3 ) gas may be used as the reaction gas.
  • a reaction gas supply system (reaction gas supply line) is constituted mainly by the reaction gas supply source 220 c , the reaction gas supply pipe 213 c , the MFC 222 c , and the valves vc 1 , vc 2 , and vc 3 .
  • purge gas supply sources 220 d and 220 e are installed to supply a purge gas.
  • the upstream end parts of purge gas supply pipes 213 d and 213 e are connected to the purge gas supply sources 220 d and 220 e , respectively.
  • the downstream end part of the purge gas supply pipe 213 d is joined to the reaction gas supply pipe 213 c and is connected to the gas inlet 210 through the valve vc 3 .
  • the downstream end part of the purge gas supply pipe 213 e is joined to the first source gas supply pipe 213 a and the second source gas supply pipe 213 b and is connected to the gas inlet 210 through the valve ve 3 .
  • MFCs 222 d and 222 e are respectively installed as flow rate controllers configured to control the supply flow rates of purge gas, and valves vd 1 , vd 2 , ve 1 , and ve 2 , are respectively installed to control supplies of purge gas.
  • inert gas such as N 2 gas and Ar gas may be used as a purge gas.
  • a purge gas supply system (purge gas supply line) is constituted mainly by the purge gas supply sources 220 d and 220 e , the purge gas supply pipes 213 d and 213 e , the MFCs 222 d and 222 e , the valves vd 1 , vd 2 , vc 3 , ve 1 , ve 2 , and ve 3 .
  • first vent pipe 215 a and a second vent pipe 215 b are respectively connected to the upstream sides of the valves va 3 and vb 3 of the first and second source gas supply pipes 213 a and 213 b .
  • downstream end parts of the first and second vent pipes 215 a and 215 b are joined together and connected between the downstream side of the pressure regulator 262 and the upstream side of the source collection trap 263 of the exhaust pipe 261 .
  • valves va 4 and vb 4 are respectively installed to control flows of gases.
  • a first vent system is constituted mainly by the first vent pipe 215 a , the valve va 4 , and a second vent system is constituted mainly by the second vent pipe 215 b and the valve vb 4 .
  • the sub-heaters 206 a are also installed around the first and second vent pipes 215 a and 215 b .
  • the sub-heaters 206 a are also installed around other members such as the first carrier gas supply pipe 237 a , the second carrier gas supply pipe 237 b , the first source gas supply pipe 213 a , the second source gas supply pipe 213 b , the exhaust pipe 261 , the process vessel 202 , and the shower head 240 .
  • the sub-heater 206 a is configured to heat such members to, for example, 100° C. or lower, so as to prevent the first and second source gases from changing back to liquid in the members.
  • the substrate processing apparatus relevant to the current embodiment includes a controller 280 configured to control each part of the substrate processing apparatus.
  • the controller 280 controls operations of parts such as the gate valve 251 , the elevating mechanism 207 b , the carrying robot 273 , the heater 206 , the sub-heater 206 a , the pressure regulator (APC) 262 , the vacuum pump 264 , the valves va 1 to va 5 , vb 1 to vb 5 , vc 1 to vc 3 , vd 1 and vd 2 , and ve 1 to ve 3 , and the MFCs 222 a , 222 b , 222 c , 222 d , and 222 e.
  • APC pressure regulator
  • FIG. 1 is a flowchart for explaining substrate processing processes according to the embodiment of the present invention. In the following description, operations of parts constituting the substrate processing apparatus are controlled by the controller 280 .
  • a metal film having a stacked structure constituted by a TiN film being a first metal film and a Ni film being a second metal film is formed on a TiO 2 film which is previously formed on a substrate such as a wafer 200 as an insulating film (gate insulating film or capacitor insulating film).
  • the TiN film which is a first metal film is formed according to an ALD method by alternately supplying a first source gas (Ti source), which is generated by vaporizing a first source (TiCl 4 ), and a reaction gas (NH 3 gas) into the process chamber 201 in which the wafer 200 is accommodated.
  • the Ni film which is a second metal film is formed according to a CVD method by supplying a second source gas (Ni source) generated by vaporizing a second source (Ni(PF 3 ) 4 ) into the process chamber 201 in which the wafer 200 is accommodated.
  • the first source gas and the reaction gas constitute a first process gas
  • the second source gas constitutes a second process gas.
  • metal film is used to denote a film formed of a conductive material containing metal atoms.
  • examples thereof include a conductive elemental metal film formed of an elemental metal, a conductive metal nitride film, a conductive metal oxide film, a conductive metal oxynitride film, a conductive metal composite film, a conductive metal alloy film, and a conductive metal silicide film.
  • the TiN film is a conductive metal nitride film
  • the Ni film is a conductive elemental metal film.
  • the elevating mechanism 207 b is operated to lower the support stage 203 to the wafer carrying position as shown in FIG. 4 .
  • the gate valve 251 is opened so that the process chamber 201 can communicate with the carrying chamber 271 .
  • a wafer 200 to be processed is carried from the carrying chamber 271 to the process chamber 201 by using the carrying robot 273 in a state where the wafer 200 is supported on the carrying arm 273 a (S 1 ).
  • a TiO 2 film is previously formed as an insulating film (gate insulating film or capacitor insulating film) on the wafer 200 to be processed.
  • the wafer 200 loaded in the process chamber 201 is temporarily placed on the lift pins 208 b which protrude upward from the top surface of the support stage 203 .
  • the carrying arm 273 a of the carrying robot 273 is moved from the inside of the process chamber 201 back to the carrying chamber 271 , and the gate valve 251 is closed.
  • the elevating mechanism 207 b is operated to raise the support stage 203 to the wafer processing position as shown in FIG. 3 .
  • the lift pins 208 b are retracted from the top surface of the support stage 203 , and the wafer 200 is placed on the susceptor 217 disposed at the top surface of the support stage 203 (S 2 ).
  • the inside pressure of the process chamber 201 is adjusted to a predetermined process pressure (S 3 ).
  • power supplied to the heater 206 is controlled to increase the surface temperature of the wafer 200 to a predetermined process temperature (S 4 ).
  • the temperature adjusting process S 4 may be performed in parallel with or prior to the pressure adjusting process S 3 .
  • the predetermined process temperature and process pressure are set in a manner such that a TiN film can be formed in a TiN film-forming process S 5 (described later) by an ALD method.
  • the process temperature and the process pressure are set in a manner such that a first source gas supplied in a Ti source supply process S 5 a does not decompose by itself
  • the vacuum pump 264 is operated in a state where the valves va 3 and vb 3 are closed and the valves vd 1 , vd 2 , vc 3 , ve 1 , ve 2 , and ve 3 are opened, so as to create a flow of N 2 gas in the process chamber 201 .
  • adhesion of particles to the wafer 200 can be suppressed.
  • a first source (TiCl 4 ) is vaporized to generate a first source gas (Ti source). That is TiCl 4 gas is generated (preliminary vaporization). That is, the valves va 1 , va 2 , and va 5 are opened, and a carrier gas the flow rate of which is controlled by the MFC 222 a is supplied from the first carrier gas supply pipe 237 a into the first bubbler 220 a so as to vaporize a first source filled in the first bubbler 220 a by bubbling to generate a first source gas (preliminary vaporization process).
  • the valve va 4 is opened in a state where the valve va 3 is closed, so that the first source gas is not supplied into to the process chamber 201 but is exhausted through a route bypassing the process chamber 201 .
  • a predetermined time is necessary for the first bubbler 220 a to stably generate the first source gas.
  • the first source gas is preliminary generated, and the flow passage of the first source gas is changed by selectively opening and closing the valves va 3 and va 4 . That is, by selectively opening and closing the valves va 3 and va 4 , stable supply of the first source gas into the process chamber 201 can be quickly started and stopped. This operation is preferable.
  • the valve va 4 is closed and the valve va 3 is opened to start supply of the first source gas (Ti source) into the process chamber 201 .
  • the first source gas is distributed by the shower head 240 so that the first source gas can be uniformly supplied to the wafer 200 disposed in the process chamber 201 .
  • Surplus first source gas flows in the exhaust duct 259 and is exhausted to the exhaust outlet 260 and the exhaust pipe 261 .
  • the process temperature and process pressure are set in a manner such that the first source gas does not decompose by itself. Therefore, molecules of the first source gas are adsorbed on the TiO 2 film which is previously formed on the wafer 200 as an insulating film (gate insulating film or capacitor insulating film).
  • valves ve 1 , vc 2 , and vc 3 are kept in an opened state to continuously supply N 2 gas into the process chamber 201 .
  • valve va 3 After a predetermined time from the start of supply of the first source gas by opening the valve va 3 , the valve va 3 is closed, and the valves va 4 is opened to stop supply of the first source gas into the process chamber 201 .
  • the valves vd 1 , vd 2 , vc 3 , ve 1 , ve 2 , and ve 3 are opened to supply N 2 gas into the process chamber 201 .
  • the N 2 gas is dispersed by the shower head 240 and uniformly supplied to the wafer 200 disposed in the process chamber 201 , and then the N 2 gas flows in the exhaust duct 259 and is exhausted to the exhaust outlet 260 and the exhaust pipe 261 . In this way, the first source gas remaining in the process chamber 201 is removed, and the inside of the process chamber 201 is purged with N 2 gas.
  • a reaction gas (NH 3 gas)
  • the reaction gas is dispersed by the shower head 240 and uniformly supplied to the wafer 200 disposed in the process chamber 201 so that the reaction gas reacts with the molecules of the first source gas adsorbed on the TiO 2 film previously formed on the wafer 200 .
  • a TiN film constituted by about less than one atomic layer (less than 1 ⁇ ) is formed on the TiO 2 film.
  • Surplus reaction gas or reaction byproducts are allowed to flow in the exhaust duct 259 and are exhausted to the exhaust outlet 260 and the exhaust pipe 261 .
  • the supply of the reducing gas into the process chamber 201 is interrupted by closing the valves vc 1 and vc 2 .
  • valves ve 1 , ve 2 , and ve 3 are kept opened to continue supply of N 2 gas into the process chamber 201 .
  • the valves vd 1 , vd 2 , vc 3 , ve 1 , ve 2 , and ve 3 are opened to supply N 2 gas into the process chamber 201 .
  • the N 2 gas is dispersed by the shower head 240 and uniformly supplied to the wafer 200 disposed in the process chamber 201 , and then the N 2 gas flows in the exhaust duct 259 and is exhausted to the exhaust outlet 260 and the exhaust pipe 261 .
  • reaction gas and reaction byproducts remaining in the process chamber 201 are removed, and the inside of the process chamber 201 is purged with the N 2 gas.
  • the Ti source supply process S 5 a , the purge process S 5 b , the reaction gas supply process S 5 c , and the purge process S 5 d are set as one cycle, and the cycle (ALD cycle) is performed predetermined times (n1 cycles) so that a titanium nitride (TiN) film having a predetermined thickness can be formed as a first metal film on the TiO 2 film previously formed on the wafer 200 .
  • the TiN film which is a first metal film has an oxidation resistance greater than that of a Ni film that will be formed as a second metal film (described later).
  • the inside pressure of the process chamber 201 is adjusted to a predetermined process pressure (S 6 ).
  • power supplied to the heater 206 is controlled to increase the surface temperature of the wafer 200 to a predetermined process temperature (S 7 ).
  • the temperature adjusting process S 7 may be performed in parallel with or prior to the pressure adjusting process S 6 .
  • the predetermined process temperature and process pressure are set in a manner such that a Ni film can be formed in a Ni film-forming process S 8 (described later) by a CVD method. That is, the process temperature and the process pressure are set in a manner such that a second source gas supplied in a Ni source supply process S 8 a can decompose by itself.
  • a second source (Ni(PF 3 ) 4 ) is vaporized to previously generate a second source gas (Ni source), that is, Ni(PF 3 ) 4 gas for the next Ni film-forming process S 8 (preliminary vaporization). That is, the valves vb 1 , vb 2 , and vb 5 are opened, and a carrier gas, the flow rate of which is controlled by the MFC 222 b , is supplied from the second carrier gas supply pipe 237 b into the second bubbler 220 b so as to vaporize a second source filled in the second bubbler 220 b by bubbling to generate a second source gas (preliminary vaporization process).
  • the valve vb 4 is opened in a state where the vb 3 is closed so as not to supply the second source gas into the process chamber 201 but exhaust the second source gas through a route bypassing the process chamber 201 .
  • a predetermined time is necessary for the second bubbler 220 b to stably generate the second source gas.
  • the second source gas is preliminary generated, and the flow passage of the second source gas is changed by selectively opening and closing the valves vb 3 and vb 4 . That is, by selectively opening and closing the valves vb 3 and vb 4 , stable supply of the second source gas into the process chamber 201 can be quickly started and stopped. This operation is preferable.
  • the valve va 4 is closed and the valve va 3 is opened to supply the second source gas (Ni source) into the process chamber 201 .
  • the second source gas is distributed by the shower head 240 so that the second source gas can be uniformly supplied to the wafer 200 disposed in the process chamber 201 .
  • Surplus second source gas flows in the exhaust duct 259 and is exhausted to the exhaust outlet 260 and the exhaust pipe 261 .
  • the process temperature and process pressure are set in a manner such that the second source gas can decompose. Therefore, the second source gas supplied to the wafer 200 thermally decomposes and participates in a CVD reaction, and accordingly a Ni film is formed on the wafer 200 .
  • valves vd 1 , vd 2 , and vd 3 are kept in an opened state to continuously supply N 2 gas into the process chamber 201 .
  • valve vb 3 After a predetermined time from the start of supply of the second source gas by opening the valve vb 3 , the valve vb 3 is closed and the valves vb 4 is opened to stop supply of the second source gas into the process chamber 201 .
  • the valves vd 1 , vd 2 , vc 3 , ve 1 , ve 2 , and ve 3 are opened to supply N 2 gas into the process chamber 201 .
  • the N 2 gas is dispersed by the shower head 240 and supplied into the process chamber 201 , and then the N 2 gas flows in the exhaust duct 259 and is exhausted to the exhaust outlet 260 and the exhaust pipe 261 . In this way, the second source gas remaining in the process chamber 201 is removed, and the inside of the process chamber 201 is purged with N 2 gas.
  • the Ni source supply process S 8 a and the purge process S 8 b are set as one cycle, and the cycle is performed predetermined times (n2 cycles) so that a nickel film (Ni film) having a predetermined thickness can be formed as a second metal film on the TiN film which is formed as a first metal film over the wafer 200 .
  • the Ni film which is a second metal film is made of a material having a work function greater than 4.8 eV and different from a material used to form the first metal film.
  • the pressure adjusting process S 3 to the TiN film-forming process S 5 and the pressure adjusting process S 6 to the Ni film-forming process S 8 are set as one cycle, and the cycle is performed predetermined times (n3 cycles) so that a metal film having a stacked structure constituted by the TiN film being the first metal film and the Ni film being the second metal film can be formed on the TiO 2 film previously formed on the wafer 200 .
  • the TiN film which is the first metal film has an oxidation resistance greater than the oxidation resistance of the Ni film which is the second metal film.
  • the Ni film which is the second metal film is made of a material having a work function greater than 4.8 eV and being different from the first metal film.
  • the TiN film which is the first metal film is formed between the Ni film (second metal film) and the TiO 2 film.
  • the inside pressure of the process chamber 201 is adjusted to a predetermined process pressure (S 10 ), and the surface temperature of the wafer 200 is adjusted to a predetermined process temperature (S 11 ).
  • the first source gas (Ti source) is supplied into the process chamber 201 for a predetermined time, and then the supply of the first source gas into the process chamber 201 is stopped.
  • the inside of the process chamber 201 is purged with N 2 gas like in the purge process S 5 b.
  • reaction gas (NH 3 gas) is supplied into the process chamber 201 for a predetermined time, and then the supply of the reaction gas into the process chamber 201 is stopped.
  • the inside of the process chamber 201 is purged with N 2 gas like in the purge process S 5 d.
  • the Ti source supply process S 12 a , the purge process S 12 b , the reaction gas supply process S 12 c , and the purge process S 12 d are set as one cycle, and the cycle is performed predetermined times (n4 cycles) so that a TiN film (TiN cap film) having a predetermined thickness can be formed as a first metal film on the metal film (having a stacked structure constituted by TiN film and Ni film) formed through the predetermined-time executing process S 9 .
  • the metal film can be formed adjacent to the TiO 2 film which is previously formed on the wafer 200 as an insulating film (gate insulating film or capacitor insulating film).
  • the metal film has a stacked structure constituted by the TiN film which is the first metal film and the Ni film which is the second metal film.
  • the first metal film is made of a material (TiN) having an oxidation resistance greater than the oxidation resistance of the second metal film
  • the second metal film is made of a material (Ni) having a work function greater than 4.8 eV and being different from the material used to make the first metal film.
  • the TiN film is formed between the Ni film and the TiO 2 film.
  • TiN cap film is formed on the outermost surface of the metal film. If the execution number (n3 cycles) of the predetermined-time executing process S 9 is set to one (one cycle), a metal film can be formed as a gate electrode as shown in FIG. 5A or a top capacitor electrode as shown in FIG. 6A . If the execution number (n3 cycles) of the predetermined-time executing process S 9 is set to two or more (two or more cycles), a metal film can be formed as a gate electrode as shown in FIG. 5B or a top capacitor electrode as shown in FIG. 6B . A bottom capacitor electrode as shown in FIG. 6B may also be formed through a process similar to the process of forming the top capacitor electrode.
  • the inside of the process chamber 201 is vacuum-evacuated, and the valves vd 1 , vd 2 , vc 3 , ve 1 , ve 2 , and ve 3 are opened to supply N 2 gas into the process chamber 201 .
  • the N 2 gas is dispersed by the shower head 240 and supplied into the process chamber 201 , and then the N 2 is exhausted to the exhaust pipe 261 . In this way, gas and reaction byproducts remaining in the process chamber 201 are removed, and the inside of the process chamber 201 is purged with the N 2 gas.
  • the wafer 200 is carried out from the process chamber 201 to the carrying chamber 271 , thereby completing the substrate processing process of the current embodiment.
  • the TiN film-forming process S 5 may be performed to a wafer 200 under the following exemplary conditions.
  • Process temperature 250° C. to 550° C., preferably, 350° C. to 550° C.,
  • the Ni film-forming process S 8 may be performed to a wafer 200 under the following exemplary conditions.
  • Process temperature 150° C. to 250° C., preferably, 150° C. to 200° C.,
  • Film thickness 0.5 nm to 10 nm, preferably, 4 nm to 5 nm.
  • total film thickness in the predetermined-time executing process S 9 that is, the thickness of a metal film having a stacked structure constituted by TiN film being first metal film and Ni film being second metal film may be, for example, 10 nm to 30 nm.
  • the TiN cap film-forming process S 12 may be performed to a wafer 200 under the following exemplary conditions.
  • Process temperature 250° C. to 550° C., preferably, 350° C. to 550° C.,
  • the TiN film may not be constituted by one or more continuous layers between a Ni film and a TiO 2 film. That is, the TiN film may be constituted by a discontinuous layer, and thus the Ni film and the TiO 2 may make contact with each other. Therefore, an oxygen component included in the TiO 2 film may permeate into the Ni film through a contact part, and thus the Ni film may be oxidized.
  • a TiN film is formed to have a thickness greater than 4 nm in the TiN film-forming process S 5 , the effective work function of an entire metal film may not be the work function of a Ni film (about 5.15 eV) but may be close to the work function of the TiN film (about 4.6 eV). Thereafter, it is preferable that a TiN film is formed to have a thickness of 0.2 nm to 4 nm in the TiN film-forming process S 5 .
  • the process temperature of the Ni film-forming process S 8 is lower than 150° C., in the Ni film-forming process S 8 a , the second source (Ni(PF 3 ) 4 ) may not decompose by itself, and thus, a CVD film-forming reaction may not occur.
  • the process temperature is higher than 250° C. in a state where the process pressure is kept in the above-mentioned range, the film-forming rate may increase excessively, and thus it may be difficult to control a film thickness. Therefore, in the Ni film-forming process S 8 , it is necessary to keep the process temperature in the range from 150° C. to 250° C. for inducing a CVD film-forming reaction and controlling a film thickness.
  • the TiN film-forming process S 5 and the Ni film-forming process S 8 are performed at the same process temperature and/or the same process pressure. That is, in the current embodiment, it is preferable that the TiN film-forming process S 5 and the Ni film-forming process S 8 are performed at a constant process temperature and/or a constant process pressure. If the process temperature and the process pressure are set to predetermined values in the above-mentioned ranges, ALD film formation and CVD film formation can be performed under the same conditions.
  • the TiN film having an oxidation resistance greater than that of the Ni film is formed as the lowermost layer of the metal film, that is, the layer (interfacial surface) between the Ni film and the TiO 2 film. Since the TiN film has an oxidation resistance greater than that of the Ni film, for example, when the Ni film is formed by a CVD method or the wafer 200 on which the metal film is formed is heated to about 400° C. to perform an annealing treatment, it can be prevented that the Ni film is oxidized by an oxygen component permeated from the TiO 2 film into the Ni film through an interfacial surface therebetween.
  • the TiN film is formed to have a thickness of 0.2 nm or greater in the TiN film-forming process S 5 .
  • the TiN film formed between the Ni film and the TiO 2 film can be surely constituted by one or more continuous layers, and thus the Ni film and the TiO 2 film can be prevented from directly making contact with each other and oxidation of the Ni film can be effectively suppressed.
  • oxidation of the metal film can be suppressed, and an increase of equivalent oxide thickness (EOT) can be prevented.
  • the TiN film (TiN cap layer) having an oxidation resistance greater than that of the Ni film is formed as the uppermost layer of the metal film, that is, the exposed surface layer of the metal film.
  • the TiN film (TiN cap layer) having an oxidation resistance greater than that of the Ni film is formed as the uppermost layer of the metal film, that is, the exposed surface layer of the metal film.
  • the TiN film in the TiN cap forming process S 12 , is formed to have a thickness of 0.2 nm to 50 nm, preferably, 1 nm to 10 nm, and thus the TiN film covering the surface of the Ni film can be surely constituted by one or more continuously layers. Therefore, the Ni film can be prevented from making direct contact with the atmosphere, and thus oxidation of the Ni film can be effectively suppressed. Hence, oxidation of the metal film can be suppressed, and an increase of EOT can be prevented.
  • the second metal film is formed of Ni (different from the first metal film in material) having a work function greater than 4.8 eV.
  • the work function of TiN used to form the first metal film is estimated to be 4.6 eV
  • the work function of Ni is 5.15 eV as shown in FIG. 10 .
  • the effective work function of the entire metal film having a stacked structure constituted by the TiN film and the Ni film can be close to the work function of the Ni film (about 5.15 eV).
  • the thickness of the Ni film formed in the Ni film-forming process S 8 is greater than the thickness of the TiN film formed in the TiN film-forming process S 5 .
  • the effect of the work function of the thicker Ni film is increased, and thus the effective work function of the entire work function of the metal film having a stacked structure constituted by the TiN film and the Ni film can be closer to the work function of the Ni film (about 5.15 eV). Therefore, when the metal film is used as a capacitor electrode, a leak current of a capacitor part can be reduced.
  • a metal film as shown in FIG. 5A or FIG. 6A is formed by performing the TiN film-forming process S 5 and the Ni film-forming process S 8 once in a manner such that a TiN film is formed to have a thickness ranging from 0.2 nm to 4 nm in the TiN film-forming process S 5 and a thicker Ni film is formed to have a thickness ranging from 0.5 nm to 10 nm, preferably, 4 nm to 5 nm in the Ni film-forming process S 8 , the effect of the work function of the thicker Ni film is high so that the effective work function of the entire metal film can approach about 5.0 eV.
  • the effective work function of the entire metal film can be adjusted to a desired value. That is, in this case, since the work functions of TiN films and Ni films are affected by each other, the effective work function of the entire metal film can be adjusted to a desired value between 4.6 eV and 5.0 eV by adjusting a thickness ratio of the TiN films and the Ni films. In either case, if the thickness of the TiN film formed in the TiN film-forming process S 5 is greater than 4 nm, the effective work function of the entire metal film may be decreased to be close to the work function (4.6 eV) of the TiN film.
  • FIG. 7 is a schematic view illustrating the energy level of a conventional capacitor electrode constituted by a single layer of TiN film.
  • the leak current of a capacitor structure metal-insulator-metal (MIM) structure, in which a capacitor insulating film (for example, a TiO 2 film) is disposed between TiN films, is determined mainly by the work function of capacitor electrodes and the band offset (conduction band offset) of the conduction band side of the capacitor insulating film. Since a voltage of ⁇ 1 V is generally applied between capacitor electrodes, it is preferable that a conduction band offset is greater than 1.0 eV.
  • MIM metal-insulator-metal
  • FIG. 8 is a schematic view illustrating the energy levels of a metal film formed by performing the TiN film-forming process S 5 and the Ni film-forming process S 8 once.
  • the work function of the metal film having a structure in which a TiN film and a Ni film are stacked can approach almost the same level (for example, 5. 0 eV) as the work function of the Ni film (about 5.15 eV). Therefore, if a TiO 2 film is used as an insulating film, a conduction band offset of about 1.4 eV can be ensured, and thus leak current can be largely reduced.
  • FIG. 9 is a schematic view illustrating the energy levels of a metal film formed by setting the TiN film-forming process S 5 and the Ni film-forming process S 8 as one cycle and performing the cycle a plurality of times.
  • the work function of the metal film having a structure in which TiN films and Ni films are stacked can be adjusted to a desired value (for example, 4.8 eV) in the range of, for example, 4.6 eV to 5.0 eV. Therefore, if a TiO 2 film is used as an insulating film, a conduction band offset can be set to a desired value (for example, 1.2 eV) in the range of 1.0 eV to 1.4 eV, and thus leak current can be effectively reduced.
  • a second metal film having a work function greater than 4.8 eV is formed by using a Ni film which is a metal film (non-noble metal film), instead of using an expensive noble metal film such as an Au, Ag, Pt, Pd, Rh, Ir, Ru, or Os film. In this way, manufacturing costs of semiconductor devices can be reduced.
  • the Ni film is formed by a CVD method. Therefore, the total film-forming rate of the metal film can be increased as compared with the case of using only an ALD method, and the throughput can be improved.
  • a liquid source filled in the bubbler is vaporized by bubbling.
  • the present invention is not limited thereto.
  • the liquid source may be vaporized by using a vaporizer instead of using the bubbler.
  • TiCl 4 is used as a Ti source in the TiN film-forming process S 5 .
  • the present invention is not limited thereto.
  • a Ti source such as TDMAT (tetrakis(dimethylamino)titanium: Ti[N(CH 3 ) 2 ] 4 ) may be used instead of TiCl 4 .
  • a TiO 2 film having a high permittivity is used as an insulating film.
  • the present invention is not limited thereto.
  • the present invention can be applied to the case of using another insulating film or a high permittivity insulating film such as a hafnium oxide (HfO 2 ) film, a zirconium oxide (ZrO 2 ) film, a niobium oxide (Nb 2 O 5 ) film, a tantalum oxide (Ta 2 O 5 ) film, a hafnium oxide film doped with aluminum (HfAlO film), a zirconium oxide film doped with aluminum (ZrAlO film), a strontium titanate (SrTiO) film, a barium strontium titanate (BaSrTiO) film, and a lead zirconate titanate (PZT) film.
  • HfO 2 hafnium oxide
  • ZrO 2 zirconium oxide
  • Nb 2 O 5 n
  • a TiN film is used as a first metal film.
  • the present invention is not limited thereto.
  • the present invention can be properly applied to the case where another film, such as a tantalum nitride (TaN) film, a titanium aluminum nitride (TiAlN) film, or tantalum aluminum nitride (TaAlN) film, is used as a first metal film. All the TaN film, the TiAlN film, and the TaAlN film have an oxidation resistance greater than that of a second metal film (Ni film).
  • the TaN film is a conductive metal nitride film
  • the TiAlN film is a conductive composite metal film
  • the TaAlN film is a conductive composite metal film.
  • a Ni film is used as a second metal film.
  • the present invention is not limited thereto.
  • the present invention can be properly applied to the case where a non-noble metal film having a work function greater than 4.8 eV, such as a beryllium (Be) film, a carbon (C) film, a cobalt (Co), a selenium (Se) film, a tellurium (Te) film, or a rhenium (Re) film, is used as a second metal film. All the listed films are conductive elemental metal films.
  • FIG. 10 is a table illustrating a group of metals having work functions higher than 4.8 eV which can be used for forming a second metal film.
  • examples 1 and 2 of the present invention will be described together with a conventional example and a comparative example with reference to FIG. 12 to FIG. 16 .
  • FIG. 12 is a schematic view for explaining a stacked structure of the example 1 (sample B) of the present invention together with a stacked structure of the conventional example (sample A) and a stacked structure of the comparative example (sample C).
  • FIG. 11 is a flowchart for explaining processes of forming the sample A (conventional example), the sample B (example 1), and the sample C (comparative example) that are illustrated in FIG. 12 .
  • a surface treatment cleaning
  • HF hydrogen fluoride
  • TiN film was formed on the silicon substrate as a bottom electrode (bottom metal deposition).
  • HfO 2 film doped with Al HfAlO film
  • the ratio of Hf and Al included in the capacitor insulating film was set to be 19:1.
  • a post deposition annealing was performed at 700° C., and then a process similar to the predetermined-time executing process S 9 of the above-described embodiment was performed by using the substrate processing apparatus of the above-described embodiment so as to form a stacked structure (Ni/TiN-laminate structure) in which a plurality of TiN films and a plurality of Ni films were alternately stacked (top metal deposition).
  • the TiN film was first formed when forming the stacked structure (TiN start), and the stacked structure was formed in a manner such that the TiN film was formed between the Ni film and the HfAlO film.
  • the thicknesses of the TiN film and the Ni film were set to 1 nm, respectively, and the execution number of the predetermined-time executing process S 9 was set to five so that the thickness of the stacked structure can be 10 nm.
  • a process similar to the TiN cap film-forming process S 12 of the above-described embodiment was performed to form a TiN film (TiN cap film) having a thickness of 50 nm on the stacked structure of the TiN films and the Ni films (TiN deposition).
  • a metal film (a stacked film constituted by the stacked structure of the TiN films and the Ni films, and the TiN cap film formed on the stacked structure) was formed as a top electrode.
  • a gate structure was patterned by photolithography (gate patterning), and after a forming gas annealing (FGA) treatment was performed at 400° C., an Al film was formed on the backside of the silicon substrate (backside Al deposition).
  • the sample C (comparative example) was prepared by forming a stacked structure (Ni/TiN-laminate structure) in which Ni films and TiN films were alternately stacked on a capacitor insulating film (top metal deposition).
  • the Ni film was first formed when forming the stacked structure (Ni start), and the stacked structure was formed in a manner such that the Ni film made direct contact with a HfAlO film.
  • Other film-forming flows and conditions were set to be equal to those of the sample B.
  • the sample A (conventional example) was prepared by forming a one-layer TiN film on a capacitor insulating film as a top electrode (TiN), instead of forming a stacked structure (Ni/TiN-laminate structure) in which Ni films and TiN films were alternately stacked on the capacitor insulating film. Furthermore, in the sample A, a TiN cap film having a thickness of 50 nm was not formed. Other film-forming flows and conditions were set to be equal to those of the sample B.
  • FIG. 13 is a graph illustrating the equivalent oxide thicknesses (EOTs) of the sample A (conventional example), the sample B (example 1), and the sample C (comparative example) illustrated in FIG. 12 .
  • EOT equivalent oxide thicknesses
  • the vertical axis denotes EOT (nm)
  • the horizontal axis denotes the samples.
  • the EOT of the sample B (example 1) is 0.80 nm or less, which is almost not increased as compared with the EOT of the sample A (conventional example) in which a single layer of TiN having a high oxidation resistance is formed.
  • the EOT of the sample C in which the stacked structure is formed in a manner such that a Ni film makes direct contact with the HfAlO film, is increased to 1.40 nm.
  • the Ni film is oxidized by an oxygen component included in the HfAlO film. That is, like in the case of the sample B, if formation of a stacked structure is started from formation of a TiN film (TiN start) to dispose the TiN film between a Ni film and a HfAlO film, oxidation of the Ni film can be effectively suppressed.
  • FIG. 14 is a graph illustrating relationships between leak current densities (Jg) and EOTs of the sample A (conventional example), the sample B (example 1), and the sample C (comparative example) illustrated in FIG. 12 .
  • the vertical axis denotes leak current density (Jg, A/cm 2 ) when a voltage of ⁇ 1 V is applied between top and bottom electrodes
  • the horizontal axis denotes EOT (nm).
  • the symbol ⁇ denotes the sample A (conventional example)
  • the symbol ⁇ denotes the sample B (example 1)
  • the symbol ⁇ denotes the sample C (comparative example).
  • the EOT of the sample B is almost not increased and the leak current density (Jg) of the sample B is decreased by one digit.
  • the leak current density (Jg) of the sample C is decreased by one digit, but the EOT of the sample C (symbol ⁇ ) is largely increased. That is, like in the case of the sample B, if a TiN film is disposed between a Ni film and a HfAlO film, an increase of EOT can be suppressed, and along with this, leak current can be decreased.
  • FIG. 15 is a graph illustrating relationships between leak current densities (Jg) and applied voltages of the sample A (conventional example), the sample B (example 1), and the sample C (comparative example) illustrated in FIG. 12 .
  • the vertical axis denotes leak current density (Jg, A/cm 2 )
  • the horizontal axis denotes voltage applied between top and bottom electrodes.
  • the dashed-dotted line denotes the sample A (conventional example)
  • the solid line denotes the sample B (example 1)
  • the dashed line denotes the sample C (comparative example).
  • the leak current densities (Jg) of the sample B (solid line) and the sample C (dashed line) are smaller than the leak current density (Jg) of the sample A (convention example). That is, like in the case of the sample B, if a stacked structure of TiN films and Ni films is formed, leak current can be decreased.
  • FIG. 16A is a schematic view illustrating the stacked structure of an example 2 (sample D) of the present invention.
  • a metal film was formed as a gate electrode by stacking a one-layer TiN film and a one-layer Ni film on a SiO 2 film functioning as a gate insulating film.
  • the TiN film was formed to be disposed between the Ni film and the SiO 2 film.
  • a plurality of samples having different thickness TiN films were prepared.
  • the thickness of the Ni film was set to 20 nm.
  • FIG. 16B is a graph illustrating a relationship between the work function of the metal film and the thickness of the TiN film of the sample D together with those of the sample B and sample C.
  • the vertical axis denotes the work function (eV) of metal films
  • the horizontal axis denotes the thickness (nm) of the TiN film of the sample D (example 2).
  • the symbol ⁇ denotes the work function of the metal film of the sample D
  • the solid line denotes the work function of the metal film of the sample C
  • the dashed line denotes the work function of the metal film of the sample B.
  • the effective work function of the entire metal film having a stacked structure of the TiN film and the Ni film can approach the work function of the Ni film (about 5.15 eV).
  • the thickness of the TiN film is 4.0 nm or less.
  • a batch type vertical apparatus configured to process a plurality of substrates at a time may be used as a substrate processing apparatus to perform a substrate processing process.
  • FIG. 17A and FIG. 17B are schematic views illustrating a vertical process furnace 302 of a vertical apparatus that can be suitably used according to an embodiment of the present invention, in which FIG. 17A is a vertical sectional view of the process furnace 302 , and FIG. 17B is a sectional view of the process furnace 302 taken along line A-A of FIG. 17A .
  • the process furnace 302 includes a heater 307 as a heating unit (heating mechanism).
  • the heater 307 has a cylindrical shape and is supported on a holding plate such as a heater base so that the heater 307 can be vertically fixed.
  • a process tube 303 is installed concentrically with the heater 307 as a reaction tube.
  • the process tube 303 is made of a heat-resistant material such as quartz (SiO 2 ) and silicon carbide (SiC) and has a cylindrical shape with a closed top side and an opened bottom side.
  • a process chamber 301 is formed, which is configured to accommodate substrates such as wafers 200 in a state where the wafers 200 are horizontally positioned and vertically arranged in multiple stages in a boat 317 (described later).
  • a manifold 309 is installed concentrically with the process tube 303 .
  • the manifold 309 is made of a material such as stainless steel and has a cylindrical shape with opened top and bottom sides.
  • the manifold 309 is engaged with the process tube 303 and installed to support the process tube 303 .
  • an O-ring 320 a is installed as a seal member.
  • the manifold 309 is supported by the heater base such that the process tube 303 can be vertically fixed.
  • the process tube 303 and the manifold 309 constitute a reaction vessel.
  • a first nozzle 333 a as a first gas introducing part, and a second nozzle 333 b as a second gas introducing part are connected to the manifold 309 in a manner such that the first and second nozzles 333 a and 333 b penetrate the sidewall of the manifold 309 .
  • Each of the first and second nozzles 333 a and 333 b has an L-shape with a horizontal part and a vertical part. The horizontal part is connected to the manifold 309 , and the vertical part is erected in an arc-shaped space between the inner wall of the process tube 303 and the wafers 200 along the inner wall of the process tube 303 from the lower side to the upper side in the arranged direction of the wafers 200 .
  • first gas supply holes 348 a and second gas supply holes 348 b are formed, respectively.
  • the first and second gas supply holes 348 a and 348 b have the same size and are arranged at the same pitch from the lower side to the upper side.
  • the same gas supply systems as those explained in the previous embodiment are connected to the first and second nozzles 333 a and 333 b .
  • the current embodiment is different from the previous embodiment, in that the first source gas supply system and the second source gas supply system are connected to the first nozzle 333 a , and the reaction gas supply system is connected to the second nozzle 333 b . That is, in the current embodiment, source gases (the first source gas and the second source gas) are supplied through a nozzle different from a nozzle used to supply a reaction gas. Alternatively, the first source gas and the source gas may be supplied through different nozzles.
  • an exhaust pipe 331 is installed to exhaust the inside atmosphere of the process chamber 301 .
  • a vacuum exhaust device such as a vacuum pump 346 is connected to the exhaust pipe 331 through a pressure detector such a pressure sensor 345 and a pressure regulator such as an auto pressure controller (APC) valve 342 , and based on pressure information detected by the pressure sensor 345 , the APC valve 342 is controlled so that the inside of the process chamber 301 can be vacuum-evacuated to a predetermined pressure (vacuum degree).
  • the APC valve 342 is an on-off valve configured to be opened and closed to start and stop vacuum evacuation of the inside of the process chamber 301 , and configured to be adjusted in valve opening degree for adjusting the inside pressure of the process chamber 301 .
  • a seal cap 319 is installed as a furnace port cover capable of hermetically closing the opened bottom side of the manifold 309 .
  • the seal cap 319 is configured to be brought into contact with the manifold 309 in a vertical direction from the bottom side of the manifold 309 .
  • the seal cap 319 is made of a metal such as stainless steel and has a circular disk shape.
  • an O-ring 320 b is installed as a seal member configured to make contact with the bottom side of the manifold 309 .
  • a rotary mechanism 367 is installed to rotate the boat 317 (described later).
  • a rotation shaft 355 of the rotary mechanism 367 is inserted through the seal cap 319 and is connected to the boat 317 , so as to rotate the wafers 200 by rotating the boat 317 .
  • the seal cap 319 is configured to be vertically moved by a boat elevator 315 which is disposed at the outside of the process tube 303 as an elevating mechanism, and by this, the boat 317 can be loaded into and out of the process chamber 301 .
  • the boat 317 which is a substrate holding tool is made of a heat-resistant material such as quartz or silicon carbide and is configured to hold a plurality of wafers 200 in a state where the wafers 200 are horizontally positioned and arranged in multiple stages with the centers of the wafers 200 being aligned.
  • an insulating member 318 made of a heat-resistant material such as quartz or silicon carbide is installed to prevent heat transfer from the heater 307 to the seal cap 319 .
  • a temperature sensor 363 is installed as a temperature detector, and based on temperature information detected by the temperature sensor 363 , power supplied to the heater 307 is controlled to obtain a desired temperature distribution in the process chamber 301 .
  • the temperature sensor 363 is installed along the inner wall of the process tube 303 .
  • a controller 380 which is a controller (control part) is configured to control operations of parts such as the APC valve 342 , the heater 307 , the temperature sensor 363 , the vacuum pump 346 , the rotary mechanism 367 , the boat elevator 315 , the valves va 1 to va 5 , vb 1 to vb 5 , vc 1 to vc 3 , vd 1 and vd 2 , and ve 1 to ve 3 , and the MFCs 222 a , 222 b , 222 c , 222 d , and 222 e.
  • each part of the vertical apparatus is controlled by the controller 380 .
  • a plurality of wafers 200 are charged into the boat 317 (wafer charging). Then, as shown in FIG. 17A , the boat 317 in which the plurality of wafers 200 are held is lifted and loaded into the process chamber 301 by the boat elevator 315 (boat loading). In this state, the bottom side of the manifold 309 is sealed by the seal cap 319 with the O-ring 320 b being disposed therebetween.
  • the inside of the process chamber 301 is vacuum-evacuated to a desired pressure (vacuum degree) by the vacuum pump 346 .
  • the inside pressure of the process chamber 301 is measured by the pressure sensor 345 , and based on the measured pressure, the APC valve 342 is feedback-controlled.
  • the inside of the process chamber 301 is heated to a desired temperature by the heater 307 .
  • power to the heater 307 is feedback-controlled based on temperature information detected by the temperature sensor 363 .
  • the rotary mechanism 367 rotates the boat 317 to rotate the wafers 200 .
  • metal films having a stacked structure constituted by a TiN film and a Ni film are formed on TiO 2 films previously formed on the wafers 200 , and then TiN films (TiN cap films) having a predetermined thickness are formed on the metal films. Thereafter, according to a sequence similar to the remaining gas removing process S 13 , a remaining gas removing process is performed.
  • the boat elevator 315 lowers the seal cap 319 to open the bottom side of the manifold 309 and unload the boat 317 from the process tube 303 through the opened bottom side of the manifold 309 in a state where the wafers 200 on which the metal films and the TiN cap films having predetermined thicknesses are formed are held in the boat 317 (boat unloading). Thereafter, the processed wafers 200 are discharged from the boat 317 (wafer discharging).
  • a TiN film and a Ni film are formed in the same process chamber.
  • the present invention is not limited thereto.
  • a TiN film and a Ni film may be formed in different process chambers.
  • a substrate processing apparatus such as a multi-chamber type substrate processing system including a plurality of process chambers, may be used.
  • an explanation will be given on an exemplary case where a TiN film and a Ni film are formed in different process chambers of the cluster apparatus.
  • Front Opening Unified Pods (FOUPs, hereinafter referred to as pods) 1 are used as wafer carrying carriers (substrate containers) configured to carry wafers 200 .
  • FOUPs Front Opening Unified Pods
  • the cluster apparatus 10 includes a first wafer transfer chamber 11 (hereinafter referred to as a negative pressure transfer chamber 11 ) as a transfer module (carrying chamber) configured to endure a pressure (negative pressure) lower than atmospheric pressure, and when viewed from the top, a case 12 (hereinafter referred to as a negative pressure transfer chamber case 12 ) of the negative pressure transfer chamber 11 has a heptagonal box shape with closed top and bottom sides.
  • the negative pressure transfer chamber case 12 is configured as a carrying vessel (airtight vessel).
  • a wafer transfer machine 13 (hereinafter referred to as a negative pressure transfer machine 13 ) is installed as a carrying robot configured to transfer a wafer 200 under a negative pressure condition.
  • a carrying-in preliminary chamber 14 (hereinafter referred to as a carrying-in chamber 14 ) and a carrying-out preliminary chamber 15 (hereinafter referred as a carrying-out chamber 15 ) are closely disposed and connected to the biggest sidewall (front wall) of the seven sidewalls of the negative pressure transfer chamber case 12 .
  • each of a case of the carrying-in chamber 14 and a case of the carrying-out chamber 15 is formed in an approximately rhombic shape with closed top and bottom sides and is configured as a loadlock chamber capable of enduring a negative pressure condition.
  • a second wafer transfer chamber 16 (hereinafter referred to as a positive pressure transfer chamber 16 ), which is a front end module configured to be kept at atmospheric pressure or higher (hereinafter referred to as a positive pressure), is connected to sides of the carrying-in chamber 14 and the carrying-out chamber 15 opposite to the negative pressure transfer chamber 11 , and when viewed from the top, a case of the positive pressure transfer chamber 16 has a horizontally elongated rectangular shape with closed top and bottom sides.
  • a gate valve 17 A is installed between the carrying-in chamber 14 and the positive pressure transfer chamber 16
  • a gate valve 17 B is installed between the carrying-in chamber 14 and the negative pressure transfer chamber 11 .
  • a gate valve 18 A is installed between the carrying-out chamber 15 and the positive pressure transfer chamber 16 , and between the carrying-out chamber 15 and the negative pressure transfer chamber 11 , a gate valve 18 B is installed.
  • a second wafer transfer machine 19 (hereinafter referred to as a positive pressure transfer machine 19 ) is installed as a carrying robot configured to transfer a wafer 200 under a positive pressure condition.
  • the positive pressure transfer machine 19 is configured to be moved upward and downward by an elevator installed at the positive pressure transfer chamber 16 , and is also configured to reciprocate left and right by a linear actuator.
  • a notch aligning device 20 is installed at the left end part of the positive pressure transfer chamber 16 .
  • Pod openers 24 are installed at the wafer carrying entrances 21 , 22 , and 23 , respectively.
  • Each of the pod openers 24 includes a stage 25 on which a pod 1 can be placed, and a cap attachment/detachment mechanism 26 configured to attach/detach a cap to/from a pod 1 placed on the stage 25 .
  • Pods 1 are supplied to the stages 25 of the pod openers 24 and taken away from the stages 25 of the pod openers 24 by an in-process carrying device (rail guided vehicle, RGV).
  • RGV rail guided vehicle
  • a first process unit 31 TiN film-forming unit 31
  • a second process unit 32 Ni film-forming unit 32
  • the first process unit 31 and the second process unit 32 have a structure similar to the substrate processing apparatus of the above-described embodiment.
  • a first source supply system and a reaction gas supply system are installed at the first process unit 31 but a second source supply system is not installed at the first process unit 31 , and a second source supply system is installed at the second process unit 32 but a first source supply system and a reaction gas supply system are not installed at the second process unit 32 .
  • a gate valve 44 is installed between the first process unit 31 and the negative pressure transfer chamber 11 .
  • a gate valve 118 is installed between the second process unit 32 and the negative pressure transfer chamber 11 .
  • a first cooling unit 35 and a second cooling unit 36 are respectively connected to two sidewalls of the seven sidewalls of the negative pressure transfer chamber case 12 that face the positive pressure transfer chamber 16 , and each of the first and second cooling units 35 and 36 functions as a cooling chamber for cooling a processed wafer 200 .
  • the cluster apparatus 10 includes a main controller 37 for overall controlling of substrate processing flows.
  • the main controller 37 controls each part of the cluster apparatus 10 .
  • each part of the cluster apparatus 10 is controlled by the main controller 37 .
  • a cap of a pod 1 placed on the stage 25 of the cluster apparatus 10 is detached by the cap attachment/detachment mechanism 26 , and thus a wafer taking in/out entrance of the pod 1 is opened.
  • the positive pressure transfer machine 19 installed at the positive pressure transfer chamber 16 picks up wafers 200 one by one from the pod 1 through the wafer carrying entrance and carries the wafers 200 to the carrying-in chamber 14 where the wafers 200 are placed on a carrying-in chamber temporary stage.
  • the gate valve 17 A disposed at a side of the carrying-in chamber 14 facing the positive pressure transfer chamber 16 is in an opened state; the gate valve 17 B disposed at the other side of the carrying-in chamber 14 facing the negative pressure transfer chamber 11 is in a closed state; and the inside of the negative pressure transfer chamber 11 is kept at, for example, 100 Pa.
  • the side of the carrying-in chamber 14 facing the positive pressure transfer chamber 16 is closed by the gate valve 17 A, and the carrying-in chamber 14 is exhausted to a negative pressure by an exhaust device.
  • the gate valve 17 B disposed at the other side of the carrying-in chamber 14 facing the negative pressure transfer chamber 11 is opened.
  • the negative pressure transfer machine 13 of the negative pressure transfer chamber 11 picks up the wafers 200 one by one from the carrying-in chamber temporary stage and carries the wafers 200 into the negative pressure transfer chamber 11 .
  • the gate valve 17 B disposed at the other side of the carrying-in chamber 14 facing the negative pressure transfer chamber 11 is closed.
  • the gate valve 44 of the first process unit 31 is opened, and the negative pressure transfer machine 13 loads the wafer 200 into a process chamber of the first process unit 31 (wafer loading).
  • the wafer 200 is loaded into the process chamber of the first process unit 31 , since the carrying-in chamber 14 and the negative pressure transfer chamber 11 are previously vacuum-evacuated, permeation of oxygen or moisture into the process chamber of the first process unit 31 can be surely prevented.
  • a TiN film is formed on a TiO 2 film previously formed on the wafer 200 .
  • the wafer 200 on which the TiN film is formed to have a predetermined thickness is unloaded from the process chamber of the first process unit 31 to the negative pressure transfer chamber 11 .
  • the gate valve 118 of the second process unit 32 is opened, and the negative pressure transfer machine 13 loads the wafer 200 into a process chamber of the second process unit 32 (wafer loading).
  • wafer loading When the wafer 200 is loaded into the process chamber of the second process unit 32 , since the carrying-in chamber 14 and the negative pressure chamber 11 are previously vacuum-evacuated, permeation of oxygen or moisture into the process chamber of the second process unit 32 can be surely prevented.
  • a Ni film is formed on the TiN film formed over the wafer 200 in the first process unit 31 .
  • the wafer 200 over which the Ni film is formed to have a predetermined thickness is unloaded from the process chamber of the second process unit 32 to the negative pressure transfer chamber 11 .
  • the TiN film-forming process using the first process unit 31 and the Ni film-forming process using the second process unit 32 are set as one cycle, and the cycle is performed predetermined times so as to form a metal film having a stacked structure of TiN film and Ni film on the TiO 2 film previously formed on the wafer 200 .
  • the gate valve 44 of the first process unit 31 is opened, and the negative pressure transfer machine 13 loads the wafer 200 into the process chamber of the first process unit 31 (wafer loading). Then, according to a sequence similar to the sequence of the pressure adjusting process S 10 to the TiN cap film-forming process S 12 , a TiN film (TiN cap film) having a predetermined thickness is formed on the metal film having a stacked structure of TiN film and Ni film. After that, in the reverse sequence to the above-described sequence, the wafer 200 over which the TiN film is formed to have a predetermined thickness is unloaded from the process chamber of the first process unit 31 to the negative pressure transfer chamber 11 .
  • TiN cap film TiN cap film
  • the side of the carrying-out chamber 15 facing the negative pressure chamber 11 is opened by the gate valve 18 B, and the negative pressure transfer machine 13 carries the wafer 200 from the negative pressure chamber 11 to the carrying-out chamber 15 , and the wafer 200 is transferred to a carrying-out chamber temporary stage.
  • the side of the carrying-out chamber 15 facing the positive pressure transfer chamber 16 is previously closed by the gate valve 18 A, and the carrying-out chamber 15 is exhausted to a negative pressure by an exhaust device.
  • the side of the carrying-out chamber 15 facing the negative pressure chamber 11 is opened by the gate valve 18 B, and the wafer 200 is unloaded. After the wafer 200 is unloaded, the gate valve 18 B is closed.
  • twenty five wafers 200 batch-loaded in the chamber 14 can be sequentially processed through the above-described processes. After the twenty five wafers 200 are sequentially processed, the processed wafers 200 are collected on the temporary stage of the carrying-out chamber 15 .
  • the carrying-out chamber 15 which is kept at a negative pressure so as to adjust the inside pressure of the carrying-out chamber 15 to atmospheric pressure, and then the side of the carrying-out chamber 15 facing the positive pressure transfer chamber 16 is opened by the gate valve 18 A.
  • a cap of an empty pod 1 placed on the stage 25 is opened by the cap attachment/detachment mechanism 26 of the pod opener 24 .
  • the positive pressure transfer machine 19 of the positive pressure transfer chamber 16 picks up the wafers 200 from the carrying-out chamber 15 to the positive pressure transfer chamber 16 and carries the wafers 200 into the pod 1 through the wafer carrying entrance 23 of the positive pressure transfer chamber 16 .
  • the cap of the pod 1 is attached to the wafer taking in/out entrance of the pod 1 by the cap attachment/detachment mechanism 26 of the pod opener 24 so that the pod 1 is closed.
  • a process similar to the substrate processing process of the above-described embodiment can be performed by using the cluster apparatus 10 of the current embodiment, and effects similar to those of the above-described embodiment can be obtained.
  • process conditions (particularly, a process temperature) for forming a first metal film are different from process conditions (particularly, a process temperature) for forming a second metal film
  • the first and second metal films may be formed in different process chambers like in the current embodiment.
  • examples of a gate electrode forming process include: a gate first process in which a source/drain diffusion layer is formed by performing about 1000° C. annealing, that is, activation annealing (spike annealing) after a gate electrode is formed; and a gate last process in which such a source/drain diffusion layer is formed before a gate electrode is formed.
  • a gate first process a gate electrode is heated to about 1,000° C. during activation annealing, and thus the present invention may be unsuitable for a gate first process because a TiN film does not have oxidation resistance in a temperature region of about 1,000° C.
  • a gate electrode is not heated to a temperature about 1,000° C., and a TiN film has oxidation resistance in temperature regions of processes that are performed after the gate electrode is formed.
  • the present invention may be suitable for a gate last process. That is, the present invention can be suitably applied to the case where a gate electrode is formed through a gate last process.
  • annealing is performed at about 400° C. under a H 2 -gas atmosphere after a capacitor electrode is formed.
  • a capacitor electrode is heated to about 400° C. at most, and in such a temperature condition, TiN has high oxidation resistance as compared with Ni. That is, the present invention can be suitably applied to the case where a capacitor electrode of a DRAM is manufactured.
  • the present invention provides a semiconductor device including a metal film which can be formed with lower costs but have a necessary work function and oxidation resistance.
  • a method of manufacturing a semiconductor device and a substrate processing apparatus which are designed to form a metal film having a necessary work function and oxidation resistance with lower costs.
  • the present invention also includes the following preferred embodiments.
  • a semiconductor device including: an insulating film disposed on a substrate; and a metal film disposed adjacent to the insulating film, wherein the metal film includes a stacked structure of a first metal film and a second metal film, an oxidation resistance of the first metal film is greater than that of the second metal film, the second metal film has a work function greater than 4.8 eV and is different from the first metal film in material, and the first metal film is disposed between the second metal film and the insulating film.
  • the metal film is disposed on the insulating film, and further includes the first metal film disposed on an outermost surface thereof.
  • the stacked structure is repeatedly stacked in the metal film.
  • a thickness of the first metal film ranges from 0.2 nm to 4 nm.
  • a thickness of the second metal film ranges from 0.5 nm to 10 nm.
  • a thickness of the second metal film ranges from 4 nm to 5 nm.
  • the second metal film is thicker than the first metal film.
  • the first metal film includes one of a titanium nitride film, a tantalum nitride film, a titanium aluminum nitride film, and a tantalum aluminum nitride film.
  • the second metal film includes a non-noble metal.
  • the second metal film includes at least one of a nickel film, a cobalt film, a beryllium film, a carbon film, a selenium film, a tellurium film and a rhenium film.
  • the insulating film includes a high permittivity film.
  • the insulating film includes at least one of a hafnium oxide film, a zirconium oxide film, a hafnium oxide film doped with an aluminum, a zirconium oxide film doped with the aluminum, a titanium oxide film, a niobium oxide film, a tantalum oxide film, a strontium titanate film, a barium strontium titanate film and a lead zirconate titanate film.
  • a method of manufacturing a semiconductor device including: forming an insulating film on a substrate; and forming a metal film including a stacked structure of a first metal film and a second metal film adjacent to the insulating film, the first metal film being formed between the second metal film and the insulating film, wherein an oxidation resistance of the first metal film is greater than that of the second metal film, and the second metal film has a work function greater than 4.8 eV and is different from the first metal film in material.
  • a substrate processing apparatus including: a process chamber configured to process a substrate; a first process gas supply system configured to supply a first process gas into the process chamber to form a first metal film; a second process gas supply system configured to supply a second process gas into the process chamber to form a second metal film; and a controller configured to control the first process gas supply system and the second process gas supply system, wherein an oxidation resistance of the first metal film is greater than that of the second metal film, the second metal film has a work function greater than 4.8 eV and is different from the first metal film in material, and the controller controls the first process gas supply system and the second process gas supply system to form a metal film having a stacked structure of the first metal film and the second metal film adjacent to an insulating film disposed on the substrate by supplying the first process gas and the second process gas into the process chamber where the substrate is accommodated such that the first metal film is formed between the second metal film and the insulating film.
  • a substrate processing apparatus including: a first process chamber configured to process a substrate; a first process gas supply system configured to supply a first process gas into the first process chamber to form a first metal film; a second process chamber configured to process the substrate; a second process gas supply system configured to supply a second process gas into the second process chamber to form a second metal film; a carrying chamber disposed between the first process chamber and the second process chamber for carrying the substrate; a carrying robot installed in the carrying chamber to carry the substrate between the first process chamber and the second process chamber; and a controller configured to control the first process gas supply system, the second process gas supply system and the carrying robot, wherein an oxidation resistance of the first metal film is greater than that of the second metal film, the second metal film has a work function greater than 4.8 eV and is different from the first metal film in material, and the controller controls the first process gas supply system, the second process gas supply system and the carrying robot to form a metal film having a stacked structure of the first metal film
US12/984,018 2010-01-07 2011-01-04 Semiconductor device, method of manufacturing semiconductor device, and substrate processing apparatus Abandoned US20110163452A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US14/629,345 US9437704B2 (en) 2010-01-07 2015-02-23 Semiconductor device having electrode made of high work function material, method and apparatus for manufacturing the same
US14/629,338 US9472637B2 (en) 2010-01-07 2015-02-23 Semiconductor device having electrode made of high work function material and method of manufacturing the same
US15/228,840 US9653301B2 (en) 2010-01-07 2016-08-04 Semiconductor device having electrode made of high work function material, method and apparatus for manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-002256 2010-01-07
JP2010002256A JP5721952B2 (ja) 2010-01-07 2010-01-07 半導体装置、半導体装置の製造方法および基板処理装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US14/629,345 Continuation US9437704B2 (en) 2010-01-07 2015-02-23 Semiconductor device having electrode made of high work function material, method and apparatus for manufacturing the same
US14/629,338 Continuation-In-Part US9472637B2 (en) 2010-01-07 2015-02-23 Semiconductor device having electrode made of high work function material and method of manufacturing the same

Publications (1)

Publication Number Publication Date
US20110163452A1 true US20110163452A1 (en) 2011-07-07

Family

ID=44224230

Family Applications (3)

Application Number Title Priority Date Filing Date
US12/984,018 Abandoned US20110163452A1 (en) 2010-01-07 2011-01-04 Semiconductor device, method of manufacturing semiconductor device, and substrate processing apparatus
US14/629,345 Active US9437704B2 (en) 2010-01-07 2015-02-23 Semiconductor device having electrode made of high work function material, method and apparatus for manufacturing the same
US15/228,840 Active US9653301B2 (en) 2010-01-07 2016-08-04 Semiconductor device having electrode made of high work function material, method and apparatus for manufacturing the same

Family Applications After (2)

Application Number Title Priority Date Filing Date
US14/629,345 Active US9437704B2 (en) 2010-01-07 2015-02-23 Semiconductor device having electrode made of high work function material, method and apparatus for manufacturing the same
US15/228,840 Active US9653301B2 (en) 2010-01-07 2016-08-04 Semiconductor device having electrode made of high work function material, method and apparatus for manufacturing the same

Country Status (3)

Country Link
US (3) US20110163452A1 (ja)
JP (1) JP5721952B2 (ja)
TW (1) TWI427791B (ja)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130075800A1 (en) * 2011-09-26 2013-03-28 Hitachi Kokusai Electric Inc. Semiconductor device manufacturing method, semiconductor device and substrate processing apparatus
US20140287593A1 (en) * 2013-03-21 2014-09-25 Applied Materials, Inc. High throughput multi-layer stack deposition
FR3005201A1 (fr) * 2013-04-24 2014-10-31 St Microelectronics Crolles 2 Procede de realisation d'un transistor mos a grille metallique, en particulier un transistor pmos, et circuit integre correspondant
CN104851780A (zh) * 2014-02-19 2015-08-19 朗姆研究公司 用于处理晶片形物件的方法和装置
US20150247238A1 (en) * 2014-03-03 2015-09-03 Lam Research Corporation Rf cycle purging to reduce surface roughness in metal oxide and metal nitride films
US9425039B2 (en) 2014-03-26 2016-08-23 Hitachi Kokusai Electric Inc. Method of manufacturing semiconductor device, substrate processing apparatus and non-transitory computer-readable recording medium
CN106201936A (zh) * 2012-01-09 2016-12-07 联发科技股份有限公司 用于动态随机存取存储器的存取方法以及电子装置
US20170110552A1 (en) * 2015-10-20 2017-04-20 Taiwan Semiconductor Manufacturing Co., Ltd. Atomic layer deposition methods and structures thereof
US20180082871A1 (en) * 2016-09-22 2018-03-22 Globalfoundries Inc. Gas flow process control system and method using crystal microbalance(s)
US20190096984A1 (en) * 2017-09-28 2019-03-28 Stmicroelectronics S.R.L. High-voltage capacitor, system including the capacitor and method for manufacturing the capacitor
US10950688B2 (en) * 2019-02-21 2021-03-16 Kemet Electronics Corporation Packages for power modules with integrated passives
US11004676B2 (en) 2015-03-30 2021-05-11 Kokusai Electric Corporation Method for manufacturing semiconductor device, non-transitory computer-readable recording medium, and substrate processing apparatus

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6086892B2 (ja) 2014-11-25 2017-03-01 株式会社日立国際電気 半導体装置の製造方法、基板処理装置およびプログラム
US10170321B2 (en) * 2017-03-17 2019-01-01 Applied Materials, Inc. Aluminum content control of TiAIN films
US9983118B1 (en) * 2017-06-03 2018-05-29 Himax Technologies Limited Wafer holding apparatus
US20230178342A1 (en) * 2020-06-01 2023-06-08 Lam Research Corporation Mid-chamber flow optimizer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271133B1 (en) * 1999-04-12 2001-08-07 Chartered Semiconductor Manufacturing Ltd. Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication
US20040203229A1 (en) * 2003-04-08 2004-10-14 Sunfei Fang Salicide formation method
US20050082625A1 (en) * 2002-04-11 2005-04-21 Kim Byung-Hee Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers
US20080076216A1 (en) * 2006-09-25 2008-03-27 Sangwoo Pae Method to fabricate high-k/metal gate transistors using a double capping layer process

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3851752B2 (ja) 2000-03-27 2006-11-29 株式会社東芝 半導体装置の製造方法
US7473640B2 (en) 2003-01-15 2009-01-06 Sharp Laboratories Of America, Inc. Reactive gate electrode conductive barrier
US6861712B2 (en) * 2003-01-15 2005-03-01 Sharp Laboratories Of America, Inc. MOSFET threshold voltage tuning with metal gate stack control
JP2005244186A (ja) * 2004-02-23 2005-09-08 Sharp Corp 反応性ゲート電極導電性バリア
US7598545B2 (en) * 2005-04-21 2009-10-06 International Business Machines Corporation Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices
JP2008028058A (ja) * 2006-07-20 2008-02-07 Tokyo Electron Ltd 半導体装置の製造方法、半導体装置の製造装置、半導体装置及び記憶媒体
JP5513767B2 (ja) 2008-06-25 2014-06-04 株式会社日立国際電気 半導体装置の製造方法、基板処理方法、基板処理装置および半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271133B1 (en) * 1999-04-12 2001-08-07 Chartered Semiconductor Manufacturing Ltd. Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication
US20050082625A1 (en) * 2002-04-11 2005-04-21 Kim Byung-Hee Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers
US20040203229A1 (en) * 2003-04-08 2004-10-14 Sunfei Fang Salicide formation method
US20080076216A1 (en) * 2006-09-25 2008-03-27 Sangwoo Pae Method to fabricate high-k/metal gate transistors using a double capping layer process

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130075800A1 (en) * 2011-09-26 2013-03-28 Hitachi Kokusai Electric Inc. Semiconductor device manufacturing method, semiconductor device and substrate processing apparatus
CN106201936A (zh) * 2012-01-09 2016-12-07 联发科技股份有限公司 用于动态随机存取存储器的存取方法以及电子装置
US20140287593A1 (en) * 2013-03-21 2014-09-25 Applied Materials, Inc. High throughput multi-layer stack deposition
FR3005201A1 (fr) * 2013-04-24 2014-10-31 St Microelectronics Crolles 2 Procede de realisation d'un transistor mos a grille metallique, en particulier un transistor pmos, et circuit integre correspondant
US9257518B2 (en) 2013-04-24 2016-02-09 STMicrolectronics (Crolles 2) SAS Method for producing a metal-gate MOS transistor, in particular a PMOS transistor, and corresponding integrated circuit
CN104851780A (zh) * 2014-02-19 2015-08-19 朗姆研究公司 用于处理晶片形物件的方法和装置
US20150235876A1 (en) * 2014-02-19 2015-08-20 Lam Research Ag Method and apparatus for processing wafer-shaped articles
US9698029B2 (en) * 2014-02-19 2017-07-04 Lam Research Ag Method and apparatus for processing wafer-shaped articles
US20150247238A1 (en) * 2014-03-03 2015-09-03 Lam Research Corporation Rf cycle purging to reduce surface roughness in metal oxide and metal nitride films
US9425039B2 (en) 2014-03-26 2016-08-23 Hitachi Kokusai Electric Inc. Method of manufacturing semiconductor device, substrate processing apparatus and non-transitory computer-readable recording medium
US11004676B2 (en) 2015-03-30 2021-05-11 Kokusai Electric Corporation Method for manufacturing semiconductor device, non-transitory computer-readable recording medium, and substrate processing apparatus
US10923576B2 (en) * 2015-10-20 2021-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Atomic layer deposition methods and structures thereof
CN107017157A (zh) * 2015-10-20 2017-08-04 台湾积体电路制造股份有限公司 原子层沉积方法及其结构
US9972694B2 (en) * 2015-10-20 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Atomic layer deposition methods and structures thereof
US20180261678A1 (en) * 2015-10-20 2018-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Atomic layer deposition methods and structures thereof
US20170110552A1 (en) * 2015-10-20 2017-04-20 Taiwan Semiconductor Manufacturing Co., Ltd. Atomic layer deposition methods and structures thereof
US10658488B2 (en) 2015-10-20 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Atomic layer deposition methods and structures thereof
US20180082871A1 (en) * 2016-09-22 2018-03-22 Globalfoundries Inc. Gas flow process control system and method using crystal microbalance(s)
US10256126B2 (en) * 2016-09-22 2019-04-09 Globalfoundries Inc. Gas flow process control system and method using crystal microbalance(s)
US20190096984A1 (en) * 2017-09-28 2019-03-28 Stmicroelectronics S.R.L. High-voltage capacitor, system including the capacitor and method for manufacturing the capacitor
US10916622B2 (en) * 2017-09-28 2021-02-09 Stmicroelectronics S.R.L. High-voltage capacitor, system including the capacitor and method for manufacturing the capacitor
US11574996B2 (en) * 2017-09-28 2023-02-07 Stmicroelectronics S.R.L. High-voltage capacitor, system including the capacitor and method for manufacturing the capacitor
US10950688B2 (en) * 2019-02-21 2021-03-16 Kemet Electronics Corporation Packages for power modules with integrated passives

Also Published As

Publication number Publication date
US9653301B2 (en) 2017-05-16
TW201131773A (en) 2011-09-16
US20150171180A1 (en) 2015-06-18
TWI427791B (zh) 2014-02-21
JP5721952B2 (ja) 2015-05-20
JP2011142226A (ja) 2011-07-21
US9437704B2 (en) 2016-09-06
US20160343573A1 (en) 2016-11-24

Similar Documents

Publication Publication Date Title
US9653301B2 (en) Semiconductor device having electrode made of high work function material, method and apparatus for manufacturing the same
US9472637B2 (en) Semiconductor device having electrode made of high work function material and method of manufacturing the same
US8404603B2 (en) Method of manufacturing semiconductor device and substrate processing system
US8937022B2 (en) Method of manufacturing semiconductor device, substrate processing method and substrate processing apparatus
US8492258B2 (en) Method of manufacturing semiconductor device and substrate processing apparatus
US8685866B2 (en) Method of manufacturing semiconductor device and substrate processing apparatus
US8741731B2 (en) Method of manufacturing a semiconductor device
US8728935B2 (en) Method of manufacturing semiconductor device, method of processing substrate and substrate processing apparatus
KR101097753B1 (ko) 반도체 장치의 제조 방법 및 기판 처리 장치
US9190281B2 (en) Method of manufacturing semiconductor device
JP5801916B2 (ja) 半導体装置の製造方法、基板処理方法、および基板処理装置
JP5944549B2 (ja) 半導体装置の製造方法、基板処理装置および半導体装置
JP2011066345A (ja) 半導体装置の製造方法及び基板処理システム
JP2012064857A (ja) 半導体装置の製造方法及び基板処理装置
JP5174975B2 (ja) 半導体装置の製造方法、基板処理方法及び基板処理装置
JP2009170711A (ja) 半導体装置の製造方法及び基板処理装置

Legal Events

Date Code Title Description
AS Assignment

Owner name: HITACHI KOKUSAI ELECTRIC INC., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HORII, SADAYOSHI;OGAWA, ARITO;ITATANI, HIDEHARU;REEL/FRAME:025954/0141

Effective date: 20110112

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION