US20110147342A1 - Method for fabricating wiring structure of wiring board - Google Patents
Method for fabricating wiring structure of wiring board Download PDFInfo
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- US20110147342A1 US20110147342A1 US12/815,155 US81515510A US2011147342A1 US 20110147342 A1 US20110147342 A1 US 20110147342A1 US 81515510 A US81515510 A US 81515510A US 2011147342 A1 US2011147342 A1 US 2011147342A1
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- wiring board
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- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000009413 insulation Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000004020 conductor Substances 0.000 claims abstract description 14
- 238000005234 chemical deposition Methods 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 239000011888 foil Substances 0.000 claims description 12
- -1 palladium ions Chemical class 0.000 claims description 8
- 238000007772 electroless plating Methods 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 229910021645 metal ion Inorganic materials 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000011889 copper foil Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005553 drilling Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 3
- 238000000608 laser ablation Methods 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- VEQPNABPJHWNSG-UHFFFAOYSA-N Nickel(2+) Chemical compound [Ni+2] VEQPNABPJHWNSG-UHFFFAOYSA-N 0.000 claims description 2
- 229910001430 chromium ion Inorganic materials 0.000 claims description 2
- 238000007598 dipping method Methods 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 229910001453 nickel ion Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 238000007747 plating Methods 0.000 description 8
- 239000000126 substance Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
Definitions
- the present invention relates to a process of fabricating a wiring board, and more particularly to a method for fabricating a wiring structure of a wiring board.
- a wiring structure of the wiring board is usually formed by using electroless plating or electrical plating. Particularly, in a recent process of fabricating the wiring structure, usually perform electroless plating at first, so as to form a seed layer and a chemical plating layer in sequence on a dielectric layer, wherein the seed layer and the chemical plating layer completely cover the surface of the dielectric layer.
- a patterned photoresist layer is formed on the chemical plating layer by using a lithography method, and the patterned photoresist layer partially exposes the chemical plating layer. Then, perform the electrical plating, so as to form a plated metal layer on the chemical plating layer. Afterwards, perform an etching method and remove a portion of the chemical plating layer, so as to form a wiring layer. Thus, the wiring structure of the wiring board is completed.
- the present invention is directed to a method for fabricating a wiring structure of a wiring board.
- the present invention provides a method for fabricating a wiring structure of a wiring board.
- a substrate including an insulation layer and a film disposed on the insulation layer is provided, and the film has an outer surface.
- an intaglio pattern partially exposing the insulation layer is formed on the outer surface by removing a portion of the insulation layer and a portion of the film.
- an activated layer is formed on the outer surface and in the intaglio pattern, and the activated layer completely covers the outer surface and all surfaces of the intaglio pattern.
- the activated layer on the outer surface and the film are removed, and the activated layer in the intaglio pattern is remained.
- a conductive material is formed in the intaglio pattern by using a chemical deposition method.
- the activated layer involves in chemical reactions of the chemical deposition method.
- the conductive material is formed in the intaglio pattern by using the activated layer remained in the intaglio pattern and the chemical deposition method.
- the wiring structure of the wiring board is manufactured.
- FIGS. 1A to 1E are schematic views illustrating processes of a method for fabricating a wiring structure of a wiring board according to an embodiment of the present invention.
- FIGS. 1A to 1E are schematic views illustrating processes of a method for fabricating a wiring structure of a wiring board according to an embodiment of the present invention.
- a substrate 110 is provided in the method for fabricating a wiring structure of a wiring board of this embodiment.
- the substrate 110 includes an insulation layer 112 and a film 114 .
- the film 114 is disposed on the insulation layer 112 and has an outer surface 114 a.
- the film 114 may be a metal layer, and the material of the metal layer is such as copper, nickel, chromium, or aluminum.
- the insulation layer 112 may be formed of a prepreg, that is, the insulation layer 112 may be a film mixed with resin and glass fiber.
- the insulation layer 112 may also be a polymer material layer, and the material of the polymer material layer is such as polyimide (PI), liquid crystal polymer (LCP), or ajinomoto build-up film (ABF).
- a method for forming the substrate 110 may be depositing the metal layer on the insulation layer 112 , and a method for depositing the metal layer may be sputtering or electroless plating.
- the method for forming the substrate 110 is laminating a metal foil on the insulation layer 112 , and the metal foil is such as a copper foil or a resin coated copper foil (RCC).
- the thickness of the metal foil is reduced, so as to form the film 114 .
- the method for reducing the thickness of the metal foil is, for example, etching the metal foil.
- a portion of the metal foil can be removed, thereby reducing the thickness of the metal foil.
- the substrate 110 may further include a wiring layer 116 and an inner wiring substrate 118 .
- the wiring layer 116 is located on a position opposite to the film 114 and electrically connected to the inner wiring substrate 118 .
- the insulation layer 112 and the wiring layer 116 are both disposed on the inner wiring substrate 118 , and the insulation layer 112 covers the wiring layer 116 and a surface 118 a of the inner wiring substrate 118 .
- the thickness T 2 of the wiring layer 116 is greater than the thickness T 1 of the film 114 .
- At least one wiring layer exists inside the wiring substrate 118 .
- the inner wiring substrate 118 may be substantially considered as a wiring board, and in a subsequent fabricating process, the wiring layer is formed on the insulation layer 112 , so that the method for fabricating the wiring structure of this embodiment may be applied to fabricating a multilayer wiring board.
- the wiring layer 116 and the inner wiring substrate 118 are both selective elements and not necessary elements. That is, the substrate 110 not necessarily includes the wiring layer 116 and the inner wiring substrate 118 , and the method for fabricating the wiring structure of this embodiment may also be applied to fabricating a single-sided wiring board or a double-sided wiring board.
- the method for fabricating the wiring structure of this embodiment may be applied to fabricating the double-sided wiring board.
- the method for fabricating the wiring structure of this embodiment may be applied to fabricating the single-sided wiring board.
- an intaglio pattern 120 is formed on the outer surface 114 a .
- the intaglio pattern 120 partially exposes the insulation layer 112 and is formed by removing a portion of the film 114 and a portion of the insulation layer 112 .
- a method for forming the intaglio pattern 120 may perform laser ablation or plasma etching to the substrate 110 .
- the intaglio pattern 120 may include a plurality of trenches 122 partially exposing the insulation layer 112 and a plurality of blind vias 124 . At least one blind via 124 is located under one of the trenches 122 and communicates with the trench 122 .
- the number of the blind via 124 included by the intaglio pattern 120 may be only one, so the number of the blind via 124 as shown in FIG. 1B is only used for an exemplary description without limiting the present invention.
- the trenches 122 are formed on the outer surface 114 a of the film 114 by using, for example, laser ablation or plasma etching.
- the blind vias 124 partially exposing the wiring layer 116 are formed, and a method for forming the blind vias 124 may perform mechanical drilling, laser drilling, or plasma etching to the substrate 110 .
- the intaglio pattern 120 may only include the trenches 122 or the blind vias 124 . That is, the intaglio pattern 120 only includes the trenches 122 , but not includes any blind vias 124 , or the intaglio pattern 120 only includes at least one blind via 124 , but not includes any trench 122 . Therefore, the intaglio pattern 120 as shown in FIG. 1B is not used to limit the present invention.
- an activated layer 130 is formed on the outer surface 114 a and in the intaglio pattern 120 .
- the activated layer 130 completely covers the outer surface 114 a and all surfaces of the intaglio pattern 120 .
- the activated layer 130 not only completely covers the outer surface 114 a , but also completely covers the bottoms B 1 , B 2 and side walls S 1 , S 2 of the trenches 122 and the blind vias 124 . That is to say, the activated layer 130 also partially covers the wiring layer 116 .
- the activated layer 130 can contact with the insulation layer 112 , the film 114 , and the wiring layer 116 .
- the method for forming the activated layer 130 has many implementation means, and in this embodiment, the method for forming the activated layer 130 may perform dipping the film 114 and the insulation layer 112 into an ionic solution (not shown).
- the ionic solution contains a plurality of metal ions, and the metal ions are such as nickel ions, palladium ions, platinum ions, chromium ions, silver ions, or molybdenum ions.
- the film 114 and the insulation layer 112 are dipped in the ionic solution, the film 114 and the insulation layer 112 are both combined with the metal ions, thereby forming the activated layer 130 .
- a method for removing the film 114 and the activated layer 130 may perform a micro-etching process. In the micro-etching process, both the film 114 and the activated layer 130 are dipped in the same etchant, and can be removed by the etchant.
- a conductive material 140 is formed in the intaglio pattern 120 by using a chemical deposition method, and the chemical deposition method may be chemical vapor deposition (CVD) or electroless plating.
- the wiring structure of the wiring board is substantially manufactured so far.
- the activated layer 130 involves in chemical reactions of the chemical deposition method, that is, the conductive material 140 is formed through the chemical reactions occurred from the activated layer 130 , such that the chemical deposition method limits the formation of the conductive material 140 , so as to enable the conductive material 140 to be formed on the activated layer 130 only.
- a patterned conductive layer 142 may be formed in the trenches 122 , and conductive posts 144 are formed in the blind vias 124 .
- the patterned conductive layer 142 is a wiring layer, that is, the patterned conductive layer 142 includes a pad 142 a and a plurality of traces 142 b . Therefore, the conductive material 140 includes the patterned conductive layer 142 and at least one conductive post 144 .
- the conductive posts 144 may be electrically connected between the patterned conductive layer 142 and the wiring layer 116 , such that the patterned conductive layer 142 is electrically connected to the inner wiring substrate 118 through the conductive posts 144 and the wiring layer 116 .
- the blind vias 124 may be filled with the conductive posts 144 .
- the blind vias 124 may also not be filled with the conductive posts 144 , so the conductive post 144 as shown in FIG. 1E do not limit the present invention.
- the intaglio pattern 120 may only include the trench 122 or the blind via 124 , such that in the process of forming the conductive material 140 , only the conductive posts 144 or the patterned conductive layer 142 may be formed.
- the intaglio pattern 120 when the intaglio pattern 120 only includes the blind via 124 but not includes any trench 122 , only the conductive posts 144 are formed, but the patterned conductive layer 142 is not formed.
- the intaglio pattern 120 only includes the trenches 122 but not includes any blind via 124 , only the patterned conductive layer 142 is formed, but the conductive post 144 is not formed.
- the conductive material is formed in the intaglio pattern by using the activated layer remained in the intaglio pattern and the chemical deposition method, so as to fabricate the wiring structure including the wiring layer (that is, the patterned conductive layer) or the conductive post.
- the wiring structure may be manufactured without forming any patterned photoresist layer, and a lithography step may be omitted as well.
Abstract
Description
- This application claims the benefit of Taiwan Patent Application No. 098144177, filed on Dec. 22, 2009, which is hereby incorporated by reference for all purposes as if fully set forth herein.
- 1. Field of Invention
- The present invention relates to a process of fabricating a wiring board, and more particularly to a method for fabricating a wiring structure of a wiring board.
- 2. Related Art
- In a current technology for fabricating a wiring board, a wiring structure of the wiring board is usually formed by using electroless plating or electrical plating. Particularly, in a recent process of fabricating the wiring structure, usually perform electroless plating at first, so as to form a seed layer and a chemical plating layer in sequence on a dielectric layer, wherein the seed layer and the chemical plating layer completely cover the surface of the dielectric layer.
- Next, a patterned photoresist layer is formed on the chemical plating layer by using a lithography method, and the patterned photoresist layer partially exposes the chemical plating layer. Then, perform the electrical plating, so as to form a plated metal layer on the chemical plating layer. Afterwards, perform an etching method and remove a portion of the chemical plating layer, so as to form a wiring layer. Thus, the wiring structure of the wiring board is completed.
- The present invention is directed to a method for fabricating a wiring structure of a wiring board.
- The present invention provides a method for fabricating a wiring structure of a wiring board. In the method, first, a substrate including an insulation layer and a film disposed on the insulation layer is provided, and the film has an outer surface. Next, an intaglio pattern partially exposing the insulation layer is formed on the outer surface by removing a portion of the insulation layer and a portion of the film. Next, an activated layer is formed on the outer surface and in the intaglio pattern, and the activated layer completely covers the outer surface and all surfaces of the intaglio pattern. Then, the activated layer on the outer surface and the film are removed, and the activated layer in the intaglio pattern is remained. After the film and the activated layer on the outer surface are removed, a conductive material is formed in the intaglio pattern by using a chemical deposition method. The activated layer involves in chemical reactions of the chemical deposition method.
- In the present invention, the conductive material is formed in the intaglio pattern by using the activated layer remained in the intaglio pattern and the chemical deposition method. Thus, the wiring structure of the wiring board is manufactured.
- In order to make the aforementioned features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
- The present invention will become more fully understood from the detailed description given herein below for illustration only, and thus are not limitative of the present invention, and wherein:
-
FIGS. 1A to 1E are schematic views illustrating processes of a method for fabricating a wiring structure of a wiring board according to an embodiment of the present invention. -
FIGS. 1A to 1E are schematic views illustrating processes of a method for fabricating a wiring structure of a wiring board according to an embodiment of the present invention. Referring toFIG. 1A , in the method for fabricating a wiring structure of a wiring board of this embodiment, firstly a substrate 110 is provided. The substrate 110 includes aninsulation layer 112 and afilm 114. Thefilm 114 is disposed on theinsulation layer 112 and has anouter surface 114 a. - The
film 114 may be a metal layer, and the material of the metal layer is such as copper, nickel, chromium, or aluminum. Theinsulation layer 112 may be formed of a prepreg, that is, theinsulation layer 112 may be a film mixed with resin and glass fiber. In addition, theinsulation layer 112 may also be a polymer material layer, and the material of the polymer material layer is such as polyimide (PI), liquid crystal polymer (LCP), or ajinomoto build-up film (ABF). - When the
film 114 is the metal layer, a method for forming the substrate 110 may be depositing the metal layer on theinsulation layer 112, and a method for depositing the metal layer may be sputtering or electroless plating. In addition, the method for forming the substrate 110 is laminating a metal foil on theinsulation layer 112, and the metal foil is such as a copper foil or a resin coated copper foil (RCC). - Accordingly, after the metal foil is laminated, the thickness of the metal foil is reduced, so as to form the
film 114. The method for reducing the thickness of the metal foil is, for example, etching the metal foil. Thus, a portion of the metal foil can be removed, thereby reducing the thickness of the metal foil. - In this embodiment, the substrate 110 may further include a
wiring layer 116 and aninner wiring substrate 118. Thewiring layer 116 is located on a position opposite to thefilm 114 and electrically connected to theinner wiring substrate 118. Theinsulation layer 112 and thewiring layer 116 are both disposed on theinner wiring substrate 118, and theinsulation layer 112 covers thewiring layer 116 and asurface 118 a of theinner wiring substrate 118. In addition, the thickness T2 of thewiring layer 116 is greater than the thickness T1 of thefilm 114. - At least one wiring layer (not shown) exists inside the
wiring substrate 118. In other words, theinner wiring substrate 118 may be substantially considered as a wiring board, and in a subsequent fabricating process, the wiring layer is formed on theinsulation layer 112, so that the method for fabricating the wiring structure of this embodiment may be applied to fabricating a multilayer wiring board. - In addition, in other not shown embodiments, the
wiring layer 116 and theinner wiring substrate 118 are both selective elements and not necessary elements. That is, the substrate 110 not necessarily includes thewiring layer 116 and theinner wiring substrate 118, and the method for fabricating the wiring structure of this embodiment may also be applied to fabricating a single-sided wiring board or a double-sided wiring board. - In detail, when the substrate 110 includes the
wiring layer 116, but not includes theinner wiring substrate 118, the method for fabricating the wiring structure of this embodiment may be applied to fabricating the double-sided wiring board. When the substrate 110 does not include thewiring layer 116 and theinner wiring substrate 118, the method for fabricating the wiring structure of this embodiment may be applied to fabricating the single-sided wiring board. - Referring to
FIGS. 1A and 1B , next, anintaglio pattern 120 is formed on theouter surface 114 a. Theintaglio pattern 120 partially exposes theinsulation layer 112 and is formed by removing a portion of thefilm 114 and a portion of theinsulation layer 112. A method for forming theintaglio pattern 120 may perform laser ablation or plasma etching to the substrate 110. - In
FIG. 1B , theintaglio pattern 120 may include a plurality oftrenches 122 partially exposing theinsulation layer 112 and a plurality ofblind vias 124. At least one blind via 124 is located under one of thetrenches 122 and communicates with thetrench 122. In addition, in other not shown embodiments, the number of the blind via 124 included by theintaglio pattern 120 may be only one, so the number of the blind via 124 as shown inFIG. 1B is only used for an exemplary description without limiting the present invention. - In the process of forming the
intaglio pattern 120, thetrenches 122 are formed on theouter surface 114 a of thefilm 114 by using, for example, laser ablation or plasma etching. Next, theblind vias 124 partially exposing thewiring layer 116 are formed, and a method for forming theblind vias 124 may perform mechanical drilling, laser drilling, or plasma etching to the substrate 110. - It is noted that in other not shown embodiments, the
intaglio pattern 120 may only include thetrenches 122 or theblind vias 124. That is, theintaglio pattern 120 only includes thetrenches 122, but not includes anyblind vias 124, or theintaglio pattern 120 only includes at least one blind via 124, but not includes anytrench 122. Therefore, theintaglio pattern 120 as shown inFIG. 1B is not used to limit the present invention. - Referring to
FIG. 1C , next, an activatedlayer 130 is formed on theouter surface 114 a and in theintaglio pattern 120. The activatedlayer 130 completely covers theouter surface 114 a and all surfaces of theintaglio pattern 120. In detail, takingFIG. 1C as an example, the activatedlayer 130 not only completely covers theouter surface 114 a, but also completely covers the bottoms B1, B2 and side walls S1, S2 of thetrenches 122 and theblind vias 124. That is to say, the activatedlayer 130 also partially covers thewiring layer 116. In addition, the activatedlayer 130 can contact with theinsulation layer 112, thefilm 114, and thewiring layer 116. - The method for forming the activated
layer 130 has many implementation means, and in this embodiment, the method for forming the activatedlayer 130 may perform dipping thefilm 114 and theinsulation layer 112 into an ionic solution (not shown). The ionic solution contains a plurality of metal ions, and the metal ions are such as nickel ions, palladium ions, platinum ions, chromium ions, silver ions, or molybdenum ions. When thefilm 114 and theinsulation layer 112 are dipped in the ionic solution, thefilm 114 and theinsulation layer 112 are both combined with the metal ions, thereby forming the activatedlayer 130. - Referring to
FIGS. 1C and 1D , next, thefilm 114 and the activatedlayer 130 on theouter surface 114 a are removed, so as to partially expose theinsulation layer 112, and the activatedlayer 130 in theintaglio pattern 120 is remained. A method for removing thefilm 114 and the activatedlayer 130 may perform a micro-etching process. In the micro-etching process, both thefilm 114 and the activatedlayer 130 are dipped in the same etchant, and can be removed by the etchant. - Referring to
FIGS. 1D and 1E , then, aconductive material 140 is formed in theintaglio pattern 120 by using a chemical deposition method, and the chemical deposition method may be chemical vapor deposition (CVD) or electroless plating. The wiring structure of the wiring board is substantially manufactured so far. The activatedlayer 130 involves in chemical reactions of the chemical deposition method, that is, theconductive material 140 is formed through the chemical reactions occurred from the activatedlayer 130, such that the chemical deposition method limits the formation of theconductive material 140, so as to enable theconductive material 140 to be formed on the activatedlayer 130 only. - In addition, in the process of forming the
conductive material 140, a patternedconductive layer 142 may be formed in thetrenches 122, andconductive posts 144 are formed in theblind vias 124. The patternedconductive layer 142 is a wiring layer, that is, the patternedconductive layer 142 includes apad 142 a and a plurality oftraces 142 b. Therefore, theconductive material 140 includes the patternedconductive layer 142 and at least oneconductive post 144. - Accordingly, the
conductive posts 144 may be electrically connected between the patternedconductive layer 142 and thewiring layer 116, such that the patternedconductive layer 142 is electrically connected to theinner wiring substrate 118 through theconductive posts 144 and thewiring layer 116. Further, theblind vias 124 may be filled with theconductive posts 144. However, in other not shown embodiments, theblind vias 124 may also not be filled with theconductive posts 144, so theconductive post 144 as shown inFIG. 1E do not limit the present invention. - It is noted that in other not shown embodiment, the
intaglio pattern 120 may only include thetrench 122 or the blind via 124, such that in the process of forming theconductive material 140, only theconductive posts 144 or the patternedconductive layer 142 may be formed. - In detail, when the
intaglio pattern 120 only includes the blind via 124 but not includes anytrench 122, only theconductive posts 144 are formed, but the patternedconductive layer 142 is not formed. When theintaglio pattern 120 only includes thetrenches 122 but not includes any blind via 124, only the patternedconductive layer 142 is formed, but theconductive post 144 is not formed. - In view of the foregoing, in the present invention, the conductive material is formed in the intaglio pattern by using the activated layer remained in the intaglio pattern and the chemical deposition method, so as to fabricate the wiring structure including the wiring layer (that is, the patterned conductive layer) or the conductive post. As compared with the conventional method for fabricating the wiring structure of the wiring board, in the present invention, the wiring structure may be manufactured without forming any patterned photoresist layer, and a lithography step may be omitted as well.
- The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
Claims (19)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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TW98144177A | 2009-12-22 | ||
TW098144177 | 2009-12-22 | ||
TW098144177A TWI405514B (en) | 2009-12-22 | 2009-12-22 | Method for fabricating wiring structure of wiring board |
Publications (2)
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US20110147342A1 true US20110147342A1 (en) | 2011-06-23 |
US8273651B2 US8273651B2 (en) | 2012-09-25 |
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US12/815,155 Active 2031-03-08 US8273651B2 (en) | 2009-12-22 | 2010-06-14 | Method for fabricating wiring structure of wiring board |
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TW (1) | TWI405514B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014065465A1 (en) * | 2012-10-25 | 2014-05-01 | 한국생산기술연구원 | Method for manufacturing solar cells having nano-micro composite structure on silicon substrate and solar cells manufactured thereby |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9955590B2 (en) | 2015-10-21 | 2018-04-24 | Advanced Semiconductor Engineering, Inc. | Redistribution layer structure, semiconductor substrate structure, semiconductor package structure, chip structure, and method of manufacturing the same |
CN113973432A (en) * | 2020-07-23 | 2022-01-25 | 庆鼎精密电子(淮安)有限公司 | Embedded circuit board and manufacturing method thereof |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020055256A1 (en) * | 2000-11-09 | 2002-05-09 | Qing-Tang Jiang | Reducing copper line resistivity by smoothing trench and via sidewalls |
US6930257B1 (en) * | 2002-05-01 | 2005-08-16 | Amkor Technology, Inc. | Integrated circuit substrate having laminated laser-embedded circuit layers |
US6967124B1 (en) * | 2001-06-19 | 2005-11-22 | Amkor Technology, Inc. | Imprinted integrated circuit substrate and method for imprinting an integrated circuit substrate |
US20090280636A1 (en) * | 2008-05-09 | 2009-11-12 | Hsu Louis L | Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications |
US20110074039A1 (en) * | 2009-09-28 | 2011-03-31 | Chartered Semiconductor Manufacturing, Ltd. | Reliable interconnect for semiconductor device |
US20110139494A1 (en) * | 2009-12-10 | 2011-06-16 | Unimicron Technology Corp. | Embedded wiring board and method for manufacturing the same |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW396568B (en) | 1998-04-15 | 2000-07-01 | Taiwan Semiconductor Mfg | Method for forming damascene interconnect by selectively electroplating copper |
TW484203B (en) | 2000-12-01 | 2002-04-21 | Chartered Semiconductor Mfg | Method to deposit a platinum seed layer for use in selective copper plating |
CN1956635A (en) | 2005-10-27 | 2007-05-02 | 全懋精密科技股份有限公司 | Structure of thin wire of multi-dielectric layer circuit board and its manufacturing method |
TW200805611A (en) | 2006-07-07 | 2008-01-16 | Kinsus Interconnect Tech Corp | Manufacturing method of substrate without using exposure developing process and its inserted circuit structure |
TWI349319B (en) * | 2007-07-06 | 2011-09-21 | Unimicron Technology Corp | Structure with embedded circuit and process thereof |
TWI432110B (en) * | 2008-03-28 | 2014-03-21 | Unimicron Technology Corp | Circuit board and fabricating process thereof |
WO2009133969A2 (en) | 2008-04-30 | 2009-11-05 | Panasonic Electric Works Co., Ltd. | Method of producing circuit board by additive method, and circuit board and multilayer circuit board obtained by the method |
-
2009
- 2009-12-22 TW TW098144177A patent/TWI405514B/en active
-
2010
- 2010-06-14 US US12/815,155 patent/US8273651B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020055256A1 (en) * | 2000-11-09 | 2002-05-09 | Qing-Tang Jiang | Reducing copper line resistivity by smoothing trench and via sidewalls |
US6967124B1 (en) * | 2001-06-19 | 2005-11-22 | Amkor Technology, Inc. | Imprinted integrated circuit substrate and method for imprinting an integrated circuit substrate |
US6930257B1 (en) * | 2002-05-01 | 2005-08-16 | Amkor Technology, Inc. | Integrated circuit substrate having laminated laser-embedded circuit layers |
US20090280636A1 (en) * | 2008-05-09 | 2009-11-12 | Hsu Louis L | Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications |
US20110074039A1 (en) * | 2009-09-28 | 2011-03-31 | Chartered Semiconductor Manufacturing, Ltd. | Reliable interconnect for semiconductor device |
US20110139494A1 (en) * | 2009-12-10 | 2011-06-16 | Unimicron Technology Corp. | Embedded wiring board and method for manufacturing the same |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014065465A1 (en) * | 2012-10-25 | 2014-05-01 | 한국생산기술연구원 | Method for manufacturing solar cells having nano-micro composite structure on silicon substrate and solar cells manufactured thereby |
CN104756260A (en) * | 2012-10-25 | 2015-07-01 | 韩国生产技术研究院 | Method for manufacturing solar cells having nano-micro composite structure on silicon substrate and solar cells manufactured thereby |
US9530914B2 (en) | 2012-10-25 | 2016-12-27 | Korea Institute Of Industrial Technology | Method for manufacturing solar cells having nano-micro composite structure on silicon substrate and solar cells manufactured thereby |
US9972732B2 (en) | 2012-10-25 | 2018-05-15 | Korea Institute Of Industrial Technology | Method for manufacturing solar cells having nano-micro composite structure on silicon substrate and solar cells manufactured thereby |
Also Published As
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TWI405514B (en) | 2013-08-11 |
TW201124016A (en) | 2011-07-01 |
US8273651B2 (en) | 2012-09-25 |
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