CN102413646B - Manufacturing method of circuit board - Google Patents
Manufacturing method of circuit board Download PDFInfo
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- CN102413646B CN102413646B CN 201010288446 CN201010288446A CN102413646B CN 102413646 B CN102413646 B CN 102413646B CN 201010288446 CN201010288446 CN 201010288446 CN 201010288446 A CN201010288446 A CN 201010288446A CN 102413646 B CN102413646 B CN 102413646B
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Abstract
The invention provides a manufacturing method of a circuit board. The method comprises the following steps: providing a double-sided copper-clad board which comprises an insulating layer, a first copper-clad layer and a second copper-clad layer, wherein the insulating layer is arranged between the first copper-clad layer and the second copper-clad layer; using a chemical etching technology to form a plurality of first holes in the first copper-clad layer and form a plurality of second holes corresponding one-to-one to the first holes in the second copper-clad layer, wherein an aperture of the each first hole is greater than or equal to the aperture of the second hole corresponding to the first hole; using a laser ablation technology to form a plurality of third holes corresponding one-to-one to the second holes, wherein the aperture of the each third hole is less than or equal to the aperture of the second hole corresponding to the third hole, the each third hole is communicated between the first hole and the second hole so as to form a plurality of through holes in the double-sided copper-clad board; forming a conducting layer on a surface of the insulating layer which is exposed in the through holes; changing the first copper-clad layer to be a first conductive line and changing the second copper-clad layer to be a second conductive line.
Description
Technical field
The present invention relates to the circuit board manufacturing technology, relate in particular to a kind of circuit board manufacturing method.
Background technology
In information, communication and consumer electronics industry, circuit board is the indispensable basic comprising important documents of all electronic products.Along with electronic product develops toward miniaturization, high speed direction, circuit board also develops from the past double-sided PCB of single face circuit board, multilayer circuit board direction.Double-sided PCB and multilayer circuit board are widely used owing to having more wiring area and higher packaging density, see also Takahashi, A. wait the people to be published in IEEE Trans.on Components in 1992, Packaging, the document of and Manufacturing Technology " High density multilayer printed circuit board for HITAC M～880 ".
Double-sided PCB has two conductive layers, realizes that by guide hole signal connects between the two conductive layers.Guide hole generally forms by boring, chemical plating and electroplating technique.In the prior art, generally be only to adopt machine drilling technology for the drilling operating of making in the guide hole, perhaps only adopt laser drilling process.Yet the making precision of machine drilling is not good, though and the laser drill precision is higher, speed is slower when using laser to bore conductive layer, needs long Production Time.And, only have Ultra-Violet Laser to be suitable for boring conductive layer, but use the cost of Ultra-Violet Laser higher.
Therefore, being necessary to provide a kind of has higher make efficiency and makes the circuit board manufacturing method of precision.
Summary of the invention
Below will a kind of circuit board manufacturing method be described with embodiment.
A kind of circuit board manufacturing method comprises step: double face copper is provided, and described double face copper comprises insulating barrier, first copper foil layer and second copper foil layer, and described insulating barrier is between first copper foil layer and second copper foil layer; In first copper foil layer, form a plurality of first holes with chemical etching process, and in second copper foil layer, form a plurality of second holes, described a plurality of first hole is corresponding one by one with described a plurality of second holes, and the aperture in each first hole is all more than or equal to the aperture in second hole corresponding with it; In described insulating barrier, form and a plurality of the 3rd holes one to one, a plurality of second holes with laser ablation process, the aperture in each the 3rd hole is equal to or less than the aperture in second hole corresponding with it, each the 3rd hole all is communicated between first hole and second hole, thereby described a plurality of first hole, a plurality of second hole and a plurality of the 3rd hole constitute a plurality of through holes in described double face copper; Surface of insulating layer in being exposed to described a plurality of through hole forms conductive layer, thus conducting first copper foil layer and second copper foil layer; And first copper foil layer formed first conducting wire, and second copper foil layer is formed second conducting wire.
In the circuit board manufacturing method of the technical program, adopt first chemical etching first copper foil layer and second copper foil layer to make through hole with the technology of laser ablation insulating barrier again, because the cost of chemical etching is lower, and the speed of laser ablation insulating barrier is very fast, and is like this then realized the making of circuit board with lower production cost and higher make efficiency.And, when making through hole, the aperture in first hole in first copper foil layer so only need guarantee the making precision in second hole more than or equal to the aperture in second hole of second copper foil layer when producing, can guarantee the making precision in first hole, that is to say and reduced the difficulty of producing.And when forming the 3rd hole with the laser ablation insulating barrier, the aperture in the 3rd hole is equal to or less than the aperture in second hole, and is like this then guaranteed the making precision of through hole.
Description of drawings
The schematic flow sheet of the circuit board manufacturing method that Fig. 1 provides for the technical program execution mode.
The cross-sectional schematic of the double face copper that Fig. 2 provides for the technical program execution mode.
The cross-sectional schematic after the double face copper both sides form the first photoresist layer and the second photoresist layer respectively that Fig. 3 provides for the technical program execution mode.
The patterning first photoresist layer and second photoresist layer cross-sectional schematic afterwards that Fig. 4 provides for the technical program execution mode.
Etching first copper foil layer and second copper foil layer cross-sectional schematic afterwards that Fig. 5 provides for the technical program execution mode.
The removal first photoresist layer and second photoresist layer cross-sectional schematic afterwards that Fig. 6 provides for the technical program execution mode.
Form the cross-sectional schematic of a plurality of through holes after the insulating barrier of the employing laser ablation double face copper that Fig. 7 provides for the technical program execution mode.
The cross-sectional schematic of a plurality of through holes being made a plurality of guide holes that Fig. 8 provides for the technical program execution mode.
The cross-sectional schematic after the double face copper both sides form the 3rd photoresist layer and the 4th photoresist layer respectively that Fig. 9 provides for the technical program execution mode.
Patterning the 3rd photoresist layer and the 4th photoresist layer cross-sectional schematic afterwards that Figure 10 provides for the technical program execution mode.
Form the cross-sectional schematic of conducting wire after etching first copper foil layer that Figure 11 provides for the technical program execution mode and second copper foil layer.
Removal the 3rd photoresist layer and the 4th photoresist layer cross-sectional schematic afterwards that Figure 12 provides for the technical program execution mode.
The main element symbol description
First copper foil layer 11
Second copper foil layer 12
The first photoresist layer 14
The second photoresist layer 15
First opening 140
The 3rd hole 130
Through hole 100
First conducting wire 111
Second conducting wire 121
The 3rd photoresist layer 17
The 4th photoresist layer 18
The 3rd opening 170
The 4th opening 180
Double-sided PCB 20
Embodiment
Below in conjunction with a plurality of drawings and the embodiments, the circuit board manufacturing method that the technical program is provided is described in further detail.
See also Fig. 1, the technical program execution mode provides a kind of circuit board manufacturing method, comprises step:
The first step sees also Fig. 2, and double face copper 10 is provided.Described double face copper 10 comprises first copper foil layer 11, insulating barrier 13 and second copper foil layer 12 that stacks gradually.Described insulating barrier 13 has first surface 131 and and first surface 131 opposing second surface 132.Described first copper foil layer 11 is fitted in first surface 131, and described second copper foil layer 12 is fitted in second surface 132, that is to say, insulating barrier 13 is between first copper foil layer 11 and second copper foil layer 12.The material of described insulating barrier 13 is flexible material, polyimides (Polyimide for example, PI), polyethylene terephthalate glycol (Polyethylene Terephthalate, PET), PEN (Polyethylene naphthalate, PEN) etc., but also can be hard material, as epoxy resin, glass cloth etc.
Second step saw also Fig. 3 to Fig. 5, formed a plurality of first holes 110 with chemical etching process in first copper foil layer 11, and formed a plurality of second holes 120 in second copper foil layer 12.Chemical etching process refers to adopt the etching solution etching to remove the method for material.Described a plurality of first hole 110 is corresponding one by one with described a plurality of second holes 120, and the aperture in each first hole 110 is all more than or equal to the aperture in second hole 120 corresponding with it.
Particularly, see also Fig. 3, at first, form the first photoresist layer 14 on first copper foil layer, 11 surfaces, form the second photoresist layer 15 on second copper foil layer, 12 surfaces.The described first photoresist layer 14 and the second photoresist layer 15 can be positive light anti-etching agent, also can negative type photoresist.Secondly, the first photoresist layer 14 and the second photoresist layer 15 are exposed, develop, thus the patterning first photoresist layer 14 and the second photoresist layer 15.In the present embodiment, in the first photoresist layer 14, form a plurality of first openings 140, in the second photoresist layer 15, form a plurality of second openings 150, as shown in Figure 4.Need to prove that the quantity of a plurality of first openings 140 is not limit, can be plural any natural number; The position of a plurality of first openings 140 is corresponding with the position in a plurality of first holes 110 that need to form; The quantity of a plurality of second openings 150 is not limit, and can be plural any natural number; The position of a plurality of second openings 150 is corresponding with the position in a plurality of second holes 120 that need to form.In the diagram of present embodiment, be that example describes with two first openings 140 and two second openings 150.Again, utilize first copper foil layer 11 that the copper etchant solution etching exposes and second copper foil layer 12 that from a plurality of second openings 150, exposes from a plurality of first openings 140, thereby in first copper foil layer 11, form described a plurality of first holes 110, in second copper foil layer 12, form described a plurality of second holes 120, as shown in Figure 5.The first surface 131 of insulating barrier 13 is exposed in described a plurality of first hole 110, and the second surface of insulating barrier 13 is exposed in described a plurality of second hole 120.Described copper etchant solution can be the etching solution of acidic copper chloride etching solution, alkaline copper chloride etching solution or nitric acid system.For example, the main component of acid chlorization copper etchant solution comprises copper chloride, hydrogen peroxide, hydrochloric acid, common salt, ammonium chloride, sodium chlorate etc.At last, see also Fig. 6, by peel off, polish-brush or dissolving remove the first photoresist layer 14 and the second photoresist layer 15.
In the present embodiment, the aperture in each first hole 110 is all roughly between 20 microns to 50 microns, and the aperture in each first hole 110 is all more than or equal to the aperture in second hole 120 corresponding with it.Particularly, the aperture in each first hole 110 is 1 to 2 times of aperture in second hole 120 corresponding with it.That is to say that the aperture in each second hole 120 is between 20 microns to 100 microns.Need to prove that in the present embodiment, the aperture in each first hole 110 can be different, the aperture that only needs each first hole 110 is getting final product below 2 times in the aperture in second hole 120 corresponding with it all.
The 3rd step saw also Fig. 7, formed in described insulating barrier 13 and a plurality of the 3rd holes 130 one to one, a plurality of second holes 120 with laser ablation process.Laser ablation process refers to adopt laser ablation to remove the method for material.
Particularly, with carbon dioxide laser near the position of second copper foil layer 12 to the part that is exposed to a plurality of second holes 120 towards the direction ablation insulating barrier 13 of first copper foil layer 11, thereby in described insulating barrier 13, form and a plurality of the 3rd holes 130 one to one, a plurality of second holes 120.Because to a plurality of first holes 110 direction ablation insulating barriers 13, therefore, the aperture in each the 3rd hole 130 is equal to or less than the aperture in second hole 120 corresponding with it laser from a plurality of second holes 120.In the present embodiment, the aperture in each the 3rd hole 130 is equal to the aperture in second hole 120 corresponding with it.That is to say that the aperture in each the 3rd hole 130 is all between 20 microns to 50 microns.
Each the 3rd hole 130 all is communicated between first hole 110 and second hole 120, thereby described a plurality of first hole 110, a plurality of second hole 120 and a plurality of the 3rd hole 130 constitute a plurality of through holes 100 in double face copper 10.That is to say each the 3rd hole 130 and first hole 110 that is communicated with it and through hole 100 of second hole, 120 common formations.In the present embodiment, the aperture in each the 3rd hole 130 also can be different, and the aperture that only needs the aperture in the 3rd hole 130 to be less than or equal to second hole 120 that is communicated with it gets final product.
The 4th step saw also Fig. 8, and insulating barrier 13 surfaces in being exposed to described a plurality of through hole 100 form conductive layer 16, thereby a plurality of through holes 100 are made a plurality of guide holes, thus conducting first copper foil layer 11 and second copper foil layer 12.The thickness of conductive layer 16 is between 5 microns to 25 microns.
In the present embodiment, by melanism, the electroplating technology insulating barrier 13 surface deposition conductive layers 16 in being exposed to described a plurality of through hole 100.Particularly, earlier by blackening craft in the insulating barrier 13 surface deposition electrically conductive graphite layer (not shown) that are being exposed in described a plurality of through hole 100, and then by electroplating technology at electrically conductive graphite laminar surface, first copper foil layer 11 surface and second copper foil layer, 12 surface deposition copper electroplating layers, so the copper electroplating layer of electrically conductive graphite layer and electrically conductive graphite laminar surface has constituted the conductive layer 16 on insulating barrier 13 surfaces, thereby makes win copper foil layer 11 and second copper foil layer 12 by conductive layer 16 electric connections.Need explanation, because therefore the thinner thickness of electrically conductive graphite layer does not illustrate in the diagram of present embodiment.In addition, blackening craft can shadow technology, electroless copper plating technology or other related process substitute.And, in other embodiments, also can only form described conductive layer 16 by blackening craft or electroless copper plating technology.In other words, conductive layer 16 can or be sandwich construction for chemical copper layer, electrically conductive graphite layer.When conductive layer 16 is chemical copper layer or when the electrically conductive graphite layer, first copper foil layer, 11 surfaces and second copper foil layer, 12 surfaces are not formed with coating material.When conductive layer 16 was sandwich construction, first copper foil layer, 11 surfaces and second copper foil layer, 12 surfaces were formed with coating material.Sandwich construction can be the composite construction of electrically conductive graphite layer and copper electroplating layer, also can be the composite construction of chemical copper layer and copper electroplating layer, the composite construction that can also constitute with copper electroplating layer for other conductive material layers that can be deposited on the insulating material surface.
In addition, it will be appreciated by those skilled in the art that, when electrically conductive graphite laminar surface, first copper foil layer, 11 surfaces and second copper foil layer, 12 surface deposition copper electroplating layers, because point effect, may be greater than the thickness at the copper electroplating layer of other position deposition at the thickness of the copper electroplating layer of first surface 131 depositions.
The 5th step saw also Fig. 9 to Figure 12, and first copper foil layer 11 is formed first conducting wire 111, and second copper foil layer 12 is formed second conducting wire 121.The technology that forms the conducting wire can be chemical etching, also can be laser ablation.In the present embodiment, be that example is specifically described with the chemical etching.
At first, see also Fig. 9, form the 3rd photoresist layer 17 on the copper electroplating layer surface on first copper foil layer, 11 surfaces, form the 4th photoresist layer 18 on the copper electroplating layer surface on second copper foil layer, 12 surfaces.Secondly, see also Figure 10, by exposure, developing patternization the 3rd photoresist layer 17, while patterning the 4th photoresist layer 18.That is to say, in the 3rd photoresist layer 17, form a plurality of the 3rd openings 170, in the 4th photoresist layer 18, form a plurality of the 4th openings 180 simultaneously.The pattern of the 3rd photoresist layer 17 is corresponding with the pattern of the conducting wire that need form in first copper foil layer 11, and the pattern of the 4th photoresist layer 18 is corresponding with the pattern of the conducting wire that need form in second copper foil layer 12.Again, see also Figure 11, with first copper foil layer 11 of copper etchant solution etch exposed in a plurality of the 3rd openings 170 and the copper electroplating layer on surface thereof, second copper foil layer 12 of while etch exposed in a plurality of the 4th openings 180 and the copper electroplating layer on surface thereof, thereby patterning first copper foil layer 11 and second copper foil layer 12.That is to say, in first copper foil layer 11, form first conducting wire 111 corresponding with the pattern of the 3rd photoresist layer 17, in second copper foil layer 12, form second conducting wire 121 corresponding with the pattern of the 4th photoresist layer 18.At last, see also Figure 12, remove the 3rd photoresist layer 17 and the 4th photoresist layer 18 of patterning, the double-sided PCB 20 that can obtain to make.Described double-sided PCB 20 comprises first conducting wire 111, second conducting wire 121 and realizes electrically connecting by the conductive layer 16 in a plurality of through holes 100 in insulating barrier 13, the first conducting wires 111 between first conducting wire 111 and second conducting wire 121 and second conducting wire 121.
Certainly, it will be understood by those skilled in the art that forming first conducting wire 111, form after second conducting wire 121, can also be included in the step that 111 surfaces, first conducting wire and 121 surfaces, second conducting wire all paste coverlay.
And, need to prove that described double-sided PCB 20 also can be used for being made into multilayer circuit board.That is to say that double-sided PCB 20 can be again and more than one single face circuit board, double-sided PCB or multilayer circuit board pressing, constitute multilayer circuit board; Double-sided PCB 20 also can constitute multilayer circuit board with an above single-side coated copper plate pressing and by line manufacturing process again.
In the method for the making double-sided PCB 20 of the technical program, adopt first chemical etching first copper foil layer 11 and second copper foil layer 12 to make through hole 100 with the technology of laser ablation insulating barrier 13 again, because the cost of chemical etching is lower, and the speed of laser ablation insulating barrier 13 is very fast, and is like this then realized the making of double-sided PCB 20 with lower production cost and higher make efficiency.And, when making through hole 100, the aperture in first hole 110 in first copper foil layer 11 is more than or equal to the aperture in second hole 120 of second copper foil layer 12, so when producing, only need guarantee the making precision in second hole 120, can guarantee the making precision in first hole 110, that is to say and reduced the difficulty of producing.And when forming the 3rd hole 130 with laser ablation insulating barrier 13, ablate from second hole 120 to first hole, 110 directions, like this then guaranteed the pore diameter range in the 3rd hole 130, guaranteed the making precision of through hole 100.
Be understandable that, for the person of ordinary skill of the art, can make other various corresponding changes and distortion by technical conceive according to the present invention, and all these change the protection range that all should belong to claim of the present invention with distortion.
Claims (9)
1. circuit board manufacturing method comprises step:
Double face copper is provided, described double face copper comprises insulating barrier, first copper foil layer and second copper foil layer, described insulating barrier is between first copper foil layer and second copper foil layer, described insulating barrier has opposite first and second surface, described first copper foil layer contacts with first surface, and described second copper foil layer contacts with second surface;
In first copper foil layer, form a plurality of first holes with chemical etching process, and in second copper foil layer, form a plurality of second holes, described a plurality of first hole is corresponding one by one with described a plurality of second holes, and the aperture in each first hole is all more than or equal to the aperture in second hole corresponding with it, described a plurality of first hole is exposed to first surface, and described a plurality of second holes are exposed to second surface;
In described insulating barrier, form and a plurality of the 3rd holes one to one, a plurality of second holes with laser ablation process, the aperture in each the 3rd hole is equal to or less than the aperture in second hole corresponding with it, each the 3rd hole all is communicated between first hole and second hole, thereby described a plurality of first hole, a plurality of second hole and a plurality of the 3rd hole constitute a plurality of through holes in described double face copper;
Surface of insulating layer in being exposed to described a plurality of through hole forms conductive layer, thus conducting first copper foil layer and second copper foil layer; And
First copper foil layer is formed first conducting wire, and second copper foil layer is formed second conducting wire.
2. circuit board manufacturing method as claimed in claim 1 is characterized in that, the aperture in each second hole is all at 20 microns to 50 microns.
3. circuit board manufacturing method as claimed in claim 1 is characterized in that, the aperture in each first hole is all below the twice in the aperture in second hole corresponding with it.
4. circuit board manufacturing method as claimed in claim 1 is characterized in that, forms with a plurality of second holes one to one during a plurality of the 3rd hole, to utilize carbon dioxide laser to ablate from a plurality of second holes to a plurality of first hole directions in described insulating barrier.
5. circuit board manufacturing method as claimed in claim 1 is characterized in that, adopts chemical etching process that first copper foil layer is formed first conducting wire, adopts chemical etching process that second copper foil layer is formed second conducting wire.
6. circuit board manufacturing method as claimed in claim 1 is characterized in that, described conductive layer is the copper layer.
7. circuit board manufacturing method as claimed in claim 1 is characterized in that, the surface of insulating layer in being exposed to described through hole forms conductive layer and comprises step:
Surface of insulating layer sedimentation chemistry copper layer or electrically conductive graphite layer in being exposed to described through hole; And form copper electroplating layer by electroplating technology at chemical copper laminar surface or electrically conductive graphite laminar surface.
8. circuit board manufacturing method as claimed in claim 7 is characterized in that, when chemical copper laminar surface or electrically conductive graphite laminar surface form copper electroplating layer, also on first copper foil layer surface and second copper foil layer surface form copper electroplating layer.
9. circuit board manufacturing method as claimed in claim 1 is characterized in that, first copper foil layer is being formed first conducting wire, and after second copper foil layer formed second conducting wire, all forms cover layer on surface, first conducting wire and surface, second conducting wire.
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| CN 201010288446 CN102413646B (en) | 2010-09-21 | 2010-09-21 | Manufacturing method of circuit board |
Applications Claiming Priority (1)
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| CN 201010288446 CN102413646B (en) | 2010-09-21 | 2010-09-21 | Manufacturing method of circuit board |
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| CN102413646A CN102413646A (en) | 2012-04-11 |
| CN102413646B true CN102413646B (en) | 2013-08-28 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI452955B (en) * | 2012-10-08 | 2014-09-11 | Subtron Technology Co Ltd | Manufacturing method of substrate structure |
| CN104684279A (en) * | 2013-11-27 | 2015-06-03 | 深圳崇达多层线路板有限公司 | Processing method of blind hole in printed wiring board |
| CN110519941A (en) * | 2019-07-09 | 2019-11-29 | 安徽捷鑫光电科技有限公司 | A kind of processing method in flexibility led circuit board function hole |
| CN111465219B (en) * | 2020-04-15 | 2022-02-22 | 深圳市信维通信股份有限公司 | Circuit board processing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1454043A (en) * | 2002-04-26 | 2003-11-05 | 耀华电子股份有限公司 | Manufacture of laser-burnt multilayered circuit board |
| CN1641801A (en) * | 2004-01-09 | 2005-07-20 | 国巨股份有限公司 | Method for manufacturing surface-bonded metal foil chip resistor |
| CN101165514A (en) * | 2007-08-27 | 2008-04-23 | 西安理工大学 | Process for preparing high density inorganic material grating |
| CN101722367A (en) * | 2008-10-17 | 2010-06-09 | 华通电脑股份有限公司 | Method for drilling holes on printed circuit board |
-
2010
- 2010-09-21 CN CN 201010288446 patent/CN102413646B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1454043A (en) * | 2002-04-26 | 2003-11-05 | 耀华电子股份有限公司 | Manufacture of laser-burnt multilayered circuit board |
| CN1641801A (en) * | 2004-01-09 | 2005-07-20 | 国巨股份有限公司 | Method for manufacturing surface-bonded metal foil chip resistor |
| CN101165514A (en) * | 2007-08-27 | 2008-04-23 | 西安理工大学 | Process for preparing high density inorganic material grating |
| CN101722367A (en) * | 2008-10-17 | 2010-06-09 | 华通电脑股份有限公司 | Method for drilling holes on printed circuit board |
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Effective date of registration: 20170628 Address after: 066000 No. 18 Tengfei Road, Qinhuangdao Economic Development Zone, Hebei, China Co-patentee after: Peng Ding Polytron Technologies Inc Patentee after: Hongqisheng Precision Electronic (Qinhuangdao) Co., Ltd. Address before: 066000 Qinhuangdao economic and Technological Development Zone, Hebei Tengfei Road, No. 18 Co-patentee before: Zhending Technology Co., Ltd. Patentee before: Hongqisheng Precision Electronic (Qinhuangdao) Co., Ltd. |
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