US20100326504A1 - Solar cell and fabrication method thereof - Google Patents

Solar cell and fabrication method thereof Download PDF

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US20100326504A1
US20100326504A1 US12/572,724 US57272409A US2010326504A1 US 20100326504 A1 US20100326504 A1 US 20100326504A1 US 57272409 A US57272409 A US 57272409A US 2010326504 A1 US2010326504 A1 US 2010326504A1
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type impurity
layer
solar cell
silicon substrate
conductive type
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Hyun Jung Park
Jin Ho Kim
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LG Electronics Inc
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LG Electronics Inc
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Priority to US14/490,338 priority Critical patent/US9583653B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0232—Optical elements or arrangements associated with the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a solar cell and a fabrication method thereof, and more particularly, to a fabrication method of a silicon solar cell, especially, a slim-type solar cell capable of providing a high efficiency at economical unit costs by improving process conditions suitable for a slim-type silicon substrate.
  • a solar cell is advantageous in view of being pollution-free, being a sustainable resource, having a semi-permanent life span, etc., and being expected as a source of energy to allow human beings to ultimately solve the energy problem, without adversely affecting the environment.
  • Solar cells may be typed as a silicon solar cell, a thin film solar cell, a dye sensitized solar cell, and an organic polymer solar cell, etc., according to their constitutional material.
  • a crystalline silicon solar cell makes up a majority of the total production of the solar cells in the world over.
  • the crystalline silicon solar cell has a higher efficiency compared to that of other solar cells, and a technique to lower the unit cost of manufacturing crystalline silicon solar cell has continuously progressed, such that the crystalline silicon solar cell may be referred to as the most popular type of solar cell.
  • Solar cells are generally fabricated to include a p-n junction interface by forming an n-type semiconductor layer on a front surface of a p-type silicon substrate.
  • the n-type semiconductor layer formed on the front surface of the p-type silicon substrate acts as an emitter, wherein an antireflection film of silicon nitride or silicon oxide is coated thereon, and then electrodes are wired in such a way to minimize reflection of light.
  • the present invention relates to a structure and a process of making a solar cell that includes an emitter for improving photovoltaic efficiency of a crystalline silicon solar cell, as described above.
  • An object of the present invention is to secure cost effective mass production of a high efficiency solar cell by improving upon a fabrication method over a conventional method.
  • Another object of the present invention is to provide a fabrication method of a solar cell that easily forms an emitter layer improved to have an efficient structure on a slim-type silicon substrate, which maintains characteristic reliability and quality, and not hinder the efficiency of the solar cell.
  • the present invention is derived particularly from interest in improving a fabrication process of a slim-type solar cell that includes a method of forming an emitter on a slim-type silicon substrate of 150 ⁇ m or less, and improving an efficiency of the slim-type solar cell.
  • the emitter applied to the slim-type solar cell of the present invention includes not only an emitter of a crystalline silicon solar cell similar to those in a related art solar cell, but also a selective emitter where impurity doping concentrations of the emitter are different.
  • a fabrication method of a solar cell including doping a silicon substrate having a first conductive type impurity with a second conductive type impurity, the second conductive type impurity being opposite to the first conductive type impurity, and thereby forming an emitter layer at a front surface part of the silicon substrate; forming an antireflection film on the emitter layer; forming a front electrode on the antireflection film; forming a rear electrode on a rear surface of the silicon substrate; and forming a back surface field layer at a rear surface part of the silicon substrate, the back surface field layer having a concentration of the first conductive type impurity that is higher than that of the silicon substrate, the back surface field layer having a different concentration of the second conductive type impurity from that of the emitter layer.
  • a solar cell including a silicon substrate doped with a first conductive type impurity; an emitter layer formed at a front surface part of the silicon substrate, the emitter layer having a second conductive type impurity opposite to the first conductive type impurity; an antireflection film formed on the emitter layer; a front electrode formed on the antireflection layer, and which penetrates through the antireflection film to contact the emitter layer; a back surface field layer formed at a rear surface part of the silicon substrate, the back surface field layer being doped with a higher concentration of the first conductive type impurity than that of the silicon substrate, wherein the back surface field layer has a different concentration of the second conductive type impurity from that of the emitter layer; and a rear electrode formed on the back surface field layer.
  • a solar cell that includes a selective emitter having an excellent photovoltaic efficiency by way of improved short-circuit current, open-circuit voltage, and fill factor (FF) values and which is constituted in an ultra-thin form, compared to that of a silicon solar cell of a related art.
  • FF fill factor
  • a high efficiency silicon solar cell having the selective emitter on the slim-type silicon substrate, and being processed at low temperatures, to thereby maintain high quality and reliability.
  • the slim-type solar cell can be mass produced through an improvement in the manufacturing process for reduced production costs and reduced production time.
  • FIGS. 1 to 6 are cross-sectional views showing a fabrication method of a silicon solar cell having an emitter according to an embodiment of the present invention
  • FIGS. 7 and 8 are cross-sectional views of a solar cell fabricated using the fabrication method of a silicon solar cell according to the embodiment of the present invention.
  • FIGS. 9 to 17 are cross-sectional views of a fabrication method of a silicon solar cell having a selective emitter according to another embodiment of the present invention.
  • FIG. 18 is a flowchart showing processes of a fabrication method of a silicon solar cell according to the embodiment of the present invention.
  • FIGS. 1 to 6 are cross-sectional views showing a fabrication method of a silicon solar cell having an emitter according to an embodiment of the present invention.
  • a first conductive type e.g., a p-type
  • a second conductive type e.g., an n-type
  • a second conductive type i.e., an n-type
  • emitter layer 2 on a surface of the first conductive type silicon substrate 1 (hereinafter also referred to as simply a substrate 1 ).
  • the first conductive type silicon substrate 1 is doped with an impurity species of the first conductive type, which is opposite to an impurity species of the second conductive type that is doped to form the second conductive type emitter layer 2 .
  • the first conductive type refers to the p-type and the second conductive type refers to the n-type, so that the second conductive type emitter layer 2 is hereinafter referred to as an n-type emitter layer 2 .
  • the n-type impurity is doped on both side surfaces as well as a front surface and a rear surface of the silicon substrate 1 .
  • the doping layer on the side surfaces of the silicon substrate 1 will be removed later through an edge isolation process, such that only the n-type doping layers 2 and 2 a respectively on the front surface and the rear surface is shown in FIG. 1 .
  • the n-type emitter layer 2 on the first surface forms a p-n junction on an interface with the p-type silicon substrate 1 .
  • the n-type emitter layer 2 a formed on the rear surface of the p-type silicon substrate 1 will be removed later and will not function as an emitter layer.
  • the n-type emitter layer 2 a that is removed from the rear surface of the p-type silicon substrate 1 will be referred to as an n-type impurity doping layer 2 a .
  • the n-type emitter layers 2 and 2 a may be formed using a generally well-known deposition process of an impurity.
  • an antireflection film 3 is formed on the n-type emitter layer 2 formed on the front surface of the substrate 1 .
  • the antireflection film 3 having a single layer is shown in FIG. 2 , such is not limiting, and the antireflection film 3 may be formed to have a plurality of layers.
  • the material to constitute the antireflection layer 3 is not particularly limited, it may be constituted using a material that reduces or prevents incident light from escaping again to the outside, and may include, a silicon oxide, a silicon nitride, and/or a mixture film thereof.
  • the material to constitute the antireflection layer 3 may, specifically, use dielectric materials, for example, and may be a single layer of SiNx, a two layer structure of SiNx/SiON or SiNx/SiOx, or a three layer structure of SiOx/SiNx/SiOx, but not necessarily limited thereto.
  • a layer having SiOxNy may be a single layer of or included, in the antireflection layer 3 .
  • the antireflection layer 3 functions not only to minimize reflectivity of the solar cell but also as a passivation layer.
  • the n-type impurity doping layer 2 a formed on the rear surface of the p-type silicon substrate 1 is removed. It is preferable, but not required, to remove or reduce the thickness of the n-type impurity doping layer 2 a . It is also preferable, though not required, to not only reduce or remove the thickness of the n-type impurity doping layer 2 a , but to further remove a small thickness of the p-type silicon substrate 1 that is next to the n-type impurity doping layer 2 a to ensure that the n-type impurity doping layer 2 a is completely removed.
  • the method to reduce or remove the n-type impurity doping layer 2 a may be by any known or later developed method, and may include an optical scribing method, a mechanical scribing method, a plasma etching method, a wet etching method, a dry etching method, a lift-off method, and wire mask method, etc., and others.
  • the thickness of the p-type silicon substrate 1 may 80 to 180 ⁇ m, preferably 100 to 150 ⁇ m, though not required, and the p-type silicon substrate 1 with such a thickness may be referred to as a slim-type.
  • the n-type impurity doping layer 2 a may be removed using the chemical etching method rather than the mechanical etching method in order to reduce or prevent a mechanical or physical breakage of the p-type silicon substrate 1 .
  • the plasma etching method, the wet etching method, and the dry etching method, etc. may be used to reduce or remove the n-type impurity doping layer 2 a without the mechanical or physical breakage of the p-type silicon substrate 1 .
  • FIG. 3 The cross-sectional view of the solar cell where the n-type impurity doping layer 2 a is removed from the rear surface of the p-type substrate 1 , as described above, is shown in FIG. 3 .
  • the thickness of the p-type silicon substrate 1 in FIG. 3 is thinner than a thickness of a silicon substrate in a related art solar cell. Therefore, a slim-type solar cell can be fabricated.
  • the front electrode 4 may use a known method of forming an electrode whereby a front electrode paste such as silver (Ag) is patterned and coated on the antireflection film 3 of the p-type silicon substrate 1 .
  • a portion of the front electrode 4 penetrates through the antireflection film 3 by being subject to a thermal process to contact and be connected to the n-type emitter layer 2 .
  • a thermal processing temperature of the front electrode is generally 700 to 850° C. in a non-ultra thin-type silicon substrate.
  • the slim-type silicon substrate of 80 ⁇ m to 180 ⁇ m thickness is used as in the present invention, the slim-type silicon substrate is subject to the process where the n-type impurity doping layer 2 a formed on the rear surface is removed in forming of a slim-type solar cell. Accordingly, the thermal processing temperature for forming the front electrode 4 can be reduced.
  • the front electrode 4 may be formed by processing at a temperature from 600 to 750° C.
  • a rear electrode 5 is formed on the rear surface of the p-type silicon substrate 1 .
  • the rear electrode 5 may use a known or later developed method of forming an electrode, and the rear electrode 5 may be formed together at the same time with the front electrode 4 of FIG. 4 , or may be formed at a different time.
  • the feature that the rear electrode 5 is formed at the same time with the front electrode 4 refers to the respective electrode 4 and 5 being formed by coating pastes that form the front electrode 4 and the rear electrode 5 , respectively, and thermally heating the pastes at the same time.
  • the rear electrode 5 may be formed using a known method, such as a direct printing method, a screen printing method, a plating method, and a coating method, etc.
  • a paste coating method such as a direct printing method, a screen printing method, a plating method, and a coating method, etc.
  • the process of forming the rear electrode 5 includes coating an aluminum (Al) paste, an alloy paste of aluminum and silver (AlAg), etc., and then thermally heating the paste.
  • the solar cell that is subjected to the thermal process is formed with a back surface field layer 6 on the rear surface of the p-type silicon substrate 1 as a high-concentration doping layer of the p-type impurity.
  • the back surface field layer 6 which is doped with the p-type impurity at a high concentration, serves to induce a pair of electrons and holes that is separated by incident light to be moved and/or separated more easily, and to reduce or prevent the pair of electrons and holes from being re-combined, thereby making it possible to contribute to a high efficiency of the solar cell.
  • the process up to this point is explained on the assumption that the surface of the p-type substrate 1 is flat.
  • the surface of the p-type silicon substrate 1 may be imparted with an uneven structure through a texturing process. The uneven structure reduces reflection of the incident light.
  • the texturing process may use a wet chemical etching method, a dry chemical etching method, an electrical-chemical etching method, a mechanical etching method, etc., which are known, as well as other methods.
  • the thickness of the substrates used in embodiments of the present invention is thing, and the silicon substrates are a slim-type, such that the texturing process is performed without breakage or defect of the substrate by using the chemical etching method rather than the mechanical etching method, though such is not required.
  • FIGS. 7 and 8 The structure of the solar cell fabricated as the p-type silicon substrate 1 having the uneven structure on the front surface of the substrate, or on both front and rear surfaces thereof using the process as described above, is shown in FIGS. 7 and 8 .
  • both the front surface and the rear surface of the p-type silicon substrate 1 are textured to be uneven, wherein an unevenness (or a size of an uneven structure) on the rear surface part of the substrate becomes smaller than an unevenness (or a size of an uneven structure) on the front surface part of the substrate 1 during the process of removing the n-type impurity doping layer 2 a formed on the rear surface of the substrate 1 .
  • the unevenness on the rear surface part of the substrate 1 may be smaller than the unevenness on the front surface part thereof in view of a size, a frequency, a height, a sharpness, etc., as well as sizes of formed shapes or structures that constitute the uneven structure.
  • FIG. 8 shows a solar cell that has a flat rear surface as the unevenness is completely removed during the process of removing the n-type impurity doping layer 2 a .
  • the back surface field layer may also be formed on the interface between the rear surface of the p-type silicon substrate 1 and the rear electrode 5 during the processes of forming and thermally heating the rear electrode 5 (not shown in the drawings).
  • One fabrication method of a selective emitter layer having portions with differing impurity concentrations in an emitter layer 2 is by way of forming high-concentration impurity portions by first forming an oxide pattern on a silicon substrate using a photolithography process, implanting a high concentration of impurity into the silicon substrate using the oxide pattern as a mask to form the high-concentration impurity portions, and removing the oxide pattern to form a low-concentration impurity layer to overlap the high-concentration impurity portions. Then, an antireflection film is coated on a front surface part, and electrodes are formed on the high-concentration impurity regions on the front surface and/or the rear surface, etc.
  • the selective emitter layer is possible, such as forming the low-concentration impurity layer first, then using the oxide pattern to form the high-concentration impurity portions; deep diffusing the impurity over the surface part, then etching back selective portions of the surface part; or selectively using barrier layer to diffuse the impurity through the barrier layer in forming differing concentration portions.
  • forming the back surface field layer between the rear electrode 5 and the silicon substrate 1 in the rear surface of the solar cell is additionally performed, making it possible to obtain back surface field effects of the solar cell to reduce or prevent the recombination of electrons and holes, to reduce or prevent leakage current, and to have good or improved ohmic contact.
  • a fabrication method of the selective emitter of a crystalline silicon solar cell with a thick silicon substrate having thickness of 200 ⁇ m or more involves annealing being performed at high temperatures and having the back surface field effects of the rear surface field layer formed thereon degraded due to the same impurity doping layer as the emitter layer being formed on the rear surface of the substrate. Thereby an open-circuit voltage and a fill factor (FF) are reduced. Therefore, in a process of forming the selective emitter of an ultra-thin silicon substrate and a fabrication method of a solar cell having the ultra-thin silicon substrate, the following processes are proposed in order to improve the process and/or to address problems of degradation in the substrate quality and in the effects of the back surface field.
  • FIGS. 9 to 17 are cross-sectional views of a fabrication method of a silicon solar cell having a selective emitter according to another embodiment of the present invention.
  • a silicon oxide 20 is formed on a p-type (i.e., a first conductive type) silicon substrate 10 doped with a p-type impurity.
  • the silicon oxide 20 may be formed using any one of an atmospheric pressure chemical vapor deposition (APCVD) method, a low pressure chemical vapor deposition (LPCVD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, and an electronic beam deposition method.
  • APCVD atmospheric pressure chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • sputtering method a sputtering method
  • electronic beam deposition method an electronic beam deposition method.
  • the conductive type of a dopant of the silicon substrate 10 may be an n-type (i.e., a second conductive type) instead of the p-type (i.e., the first conductive type).
  • the silicon oxide 20 may preferably be silicon dioxide, though not required.
  • the surface of the silicon substrate 10 may have an uneven structure (or unevenness) by being chemically etched via acidic or alkaline etchants.
  • such a texturing method to form the uneven structure may be performed using a mechanical etching method, such as, a laser irradiation process, etc., and a dry chemical etching process, such as, a reactive ion etching (RIE) process, in addition to the wet chemical etching method.
  • a mechanical etching method such as, a laser irradiation process, etc.
  • a dry chemical etching process such as, a reactive ion etching (RIE) process
  • an opening part 25 is formed on the silicon oxide 20 .
  • the opening part 25 can be formed using a photolithography method that patterns, sensitizes and exposes a photoresist, and/or can be etched using an etching paste. This is the process to be applied to the slim-type silicon substrate, since a mechanical etching, such as, a laser scribing is not recommended, though the mechanical etching process may be used.
  • FIG. 11 shows a structure of the solar cell, where a region 30 doped with a high-concentration of the n-type impurity is formed through the opening part 25 by thermally diffusing an n-type impurity in a p-type silicon substrate 10 , and a layer 35 doped with the n-type impurity is formed in a lower part of the p-type silicon substrate 10 .
  • such an n-type impurity doped region may also be formed on a side surface part of the p-type silicon substrate 10 .
  • the boundary surface between the region 30 doped with the n-type impurity at the high concentration and the p-type silicon substrate 10 forms a p-n junction interface.
  • the n-type impurity may include a group-V element material, and may have a diffusion source.
  • the diffusion source for the group-V element may particularly be a dopant gas of phosphorous oxychloride (POCl 3 ), which includes phosphorous (P).
  • n-type impurity is thermally diffused again in the p-type silicon substrate 10 without the silicon oxide 20 , thereby forming a low-concentration n-type impurity region 40 on a front surface part of the p-type silicon substrate 10 .
  • the n-type doping concentration of the high-concentration n-type impurity region 30 and the n-type impurity doping layer 35 formed on a rear surface of the substrate will be maintained at a higher concentration by the n-type impurity doping that is performed twice in forming the high-concentration n-type impurity region 30 and the low-concentration n-type impurity region 40 on a front surface part of the p-type silicon substrate 10 .
  • the thermal diffusion processes of the n-type impurity performed in FIGS. 11 and 13 are different in view of the annealing temperature and process time necessary for the thermal diffusion as well as the impurity concentration, making it possible to form the high-concentration n-type impurity region 30 and the low-concentration n-type impurity region 40 on the p-type silicon substrate 10 to desired depths.
  • the high-concentration n-type impurity region 30 and the low-concentration n-type impurity region 40 form the selective emitter layer of the p-type silicon substrate 10 and the solar cell.
  • FIG. 14 shows a structure where an antireflection layer (or film) 50 is formed on the selective emitter layer that includes the high-concentration n-type impurity region 30 and the low-concentration n-type impurity region 40 .
  • the material to constitute the antireflection layer 50 may be one or more dielectric materials, for example, a single layer of SiNx, a two layer structure of SiNx/SiON or SiNx/SiOx, or a three layer structure of SiOx/SiNx/SiOx, but not necessarily limited thereto.
  • a layer having SiOxNy may be a single layer or included in any one of the structures.
  • the antireflection layer 50 functions not only to minimize reflectivity of the p-type silicon substrate 10 or the solar cell, but also as a passivation layer.
  • the antireflection layer 50 forming a stacked film, as shown in FIG. 14 is proposed as one embodiment, but the antireflection layer 50 may also be formed after the process in FIG. 15 is performed according to varying circumstances.
  • FIG. 15 shows a structure where an n-type impurity doping layer 35 formed on the rear surface of the p-type silicon substrate 10 is reduced or removed during the process of forming the solar cell including the selective emitter.
  • the n-type impurity doping layer 35 is formed on the rear surface of the substrate at a relatively high concentration during the process of forming the selective emitter, such that the process of removing the n-type impurity doping layer 35 is preferred, but not required, in the present invention.
  • the n-type impurity doping layer 35 When the n-type impurity doping layer 35 is removed, it facilitates and maximizes a contact between the back surface field layer, to be formed later on the rear surface of the substrate of the solar cell, and the silicon substrate, making it possible to maximize back surface field effects to reduce or prevent the recombination of a pair of electrons-holes. Further, the rear surface of the p-type silicon substrate 10 is planarized to be flat, making it also possible to expect increased effects in an open-circuit voltage Voc. The effect of removing the n-type impurity doping layer 35 from an ultra-thin silicon substrate is especially pronounced, and leads to improvement in the back surface field effects.
  • the n-type impurity doping layer 35 formed on the rear surface of the p-type silicon substrate 10 includes group-V elements such as phosphorous (P), arsenic (As), antimony (Sb), etc., but the n-type impurity doping layer 35 is completely removed in this operation, such that the group-V elements do not exist on the back surface field layer and in the rear electrode that contacts the rear surface of the substrate.
  • group-V elements such as phosphorous (P), arsenic (As), antimony (Sb), etc.
  • reference to the group-V elements not existing on the back surface field layer includes presence of the group-V elements in the back surface field layer that is negligible, or presence of the group-V elements in the back surface field layer that is not greater than an incidental contamination of the group-V elements, so that for practical purposes, the presence of the group-V elements can be said to be zero or none.
  • a presence or concentration of the impurities may refer to a presence or concentration in terms of a per unit area, a per unit volume or other known units.
  • the thickness of the n-type impurity doping layer 35 that is removed in an embodiment of the present invention may be equivalent to or thicker than the thickness of the n-type impurity doping layer formed on the front surface, that is, the thickness of the selective emitter layer that includes the high-concentration n-type impurity region 30 and the low-concentration n-type impurity region 40 .
  • the thickness of the selective emitter layer formed on the front surface part of the p-type silicon substrate 10 through the process is not particularly limited, but the high-concentration doped region 40 may extend 0.2 ⁇ m to 3.0 ⁇ m from the front surface part of the p-type silicon substrate 10 and the low-concentration doped region 40 may extend 0.1 ⁇ m to 0.5 ⁇ m from the front surface part of the p-type silicon substrate 10 .
  • the thickness of the n-type impurity doping layer 35 removed from the p-type silicon substrate 10 on the rear surface may be 0.1 ⁇ m at a minimum to 3.5 ⁇ m or more at a maximum according to the thickness of the n-type impurity doping layer 35 that was deposited on the rear surface based on the forming process or the doped concentration of n-type impurity.
  • the n-type impurity doping layer 35 may be removed to a thickness at which the n-type impurity is not detected from the p-type silicon substrate 10 on the rear surface thereof.
  • the n-type impurity doping layer 35 formed on the rear surface of the p-type silicon substrate 10 may be removed using an optical scribing method, a mechanical scribing method, a plasma etching method, a wet etching method, a dry etching method, a lift-off method, a wire mask method, etc., and may preferably use an etching method using a wet etchant, or a dry etchant such as plasma, though such is not required.
  • the etching speed at which the n-type impurity doping layer 35 is removed by the etching method may be varied according to the concentration of the doped impurity, or may be constant.
  • the wet etchant used may be a composite where nitric acid (HNO 3 ), hydrofluoric acid (HF), acetic acid (CH 3 COOH), and/or water (H 2 O) are mixed at volume ratios of 10:0.1-0.01:1-3:5-10.
  • HNO 3 nitric acid
  • HF hydrofluoric acid
  • CH 3 COOH acetic acid
  • H 2 O water
  • the n-type impurity doping layer 35 formed on the rear surface of the p-type silicon substrate 1 may have a higher impurity doped concentration towards the external surface, such that the n-type impurity doping layer 35 is removed at an etching rate of 0.08 to 0.12 ⁇ m/sec in a region of the surface doped with a high-concentration of the n-type impurity using the wet etchant.
  • the n-type impurity doping layer 35 is partially removed in the thickness of the high-concentration doped region using the higher etching rate of 0.08 to 0.12 ⁇ m/sec, removal of the remainder of the n-type impurity doping layer 35 is completed at a slower etching speed of 0.01 to 0.03 ⁇ m/sec.
  • the n-type impurity doping layer 35 may be removed at the high-speed etching rate 0.08 to 0.12 ⁇ m/sec for approximately the first 3 seconds of the etching process, and then the remaining portion may be removed at the low-speed etching rate of 0.01 to 0.03 ⁇ m/sec, to complete the removal of the n-type impurity doping layer 35 .
  • FIG. 16 shows a structure where a front electrode paste 60 and a rear surface paste 70 are applied to or printed and formed in order to form respective front and back electrodes respectively on a front surface part and a rear surface part of the p-type silicon substrate 10 of the solar cell.
  • the front electrode paste 60 is patterned and formed on an upper part of the selective emitter using a direct printing method or a screen printing method. Accordingly, the front electrode paste 60 is formed over the high-concentration n-type impurity region 30 .
  • the front electrode paste 60 may be thermally heated at the same time with the rear surface paste 70 , or at different times with the rear surface paste 70 , to infiltrate into the p-type silicon substrate 10 of the solar cell.
  • an annealing temperature for forming an electrode is generally 700 to 850° C.
  • the slim-type silicon substrate of thickness 80 ⁇ m to 180 ⁇ m is used as in the present invention, due to p-type silicon substrate 10 being thin or slim from having the n-type impurity doping layer 35 formed on the rear surface removed, the temperature for forming the front electrode and/or the rear electrode can be lowered.
  • the respective front and rear electrodes can be formed by co-firing the electrode pastes 60 and 70 during the thermal process at temperatures of 600 to 750° C.
  • the respective front and rear electrodes can be formed by firing the respective electrode pastes 60 and 70 during different thermal processes.
  • the temperatures during each of the thermal processes may be 600 to 750° C., or other temperatures.
  • the rear electrode may be formed by a separate process.
  • FIG. 17 shows a solar cell completed by way of a fabrication method of a solar cell according to an embodiment of the present invention.
  • a front electrode paste 60 is infiltrated into the antireflection film 50 through a thermal process to contact the high-concentration impurity region 30 of the selective emitter layer, to thereby form a front electrode 65 , which is also referred to as a finger electrode.
  • the rear electrode paste 70 printed on a rear surface of the p-type silicon substrate 10 which may be an aluminum paste or an alloy paste of aluminum and silver, is diffused through the thermal process so that a back surface field layer 80 is formed on the rear surface part of the p-type silicon substrate 10 as a high-concentration doping layer of a p-type impurity.
  • the back electrode 75 is formed from the rear electrode paste 70 at the same time the back surface field layer 80 is formed on the rear surface part.
  • the back surface field layer 80 may be formed at a different time from when the back electrode 75 is formed.
  • the n-type impurity doping layer 35 on the rear surface of the p-type silicon substrate 10 is removed, making it possible to maximize back surface field effects of the back surface field layer 80 and to increase open-circuit voltage.
  • the back surface field layer 80 since the n-type impurity doping layer 35 on the rear surface of the p-type silicon substrate 10 is removed, the back surface field layer 80 , that is formed after the removal of the n-type impurity doping layer 35 , has a different concentration of the second conductive type impurity from that of the emitter layer or the selective emitter layer. That is, the back surface field layer 80 has a different concentration of the second conductive type impurity (e.g., the n-type impurity) from that of at least one of the high-concentration impurity region 30 and the low-concentration n-type impurity region 40 . Such would not be the case if the n-type impurity doping layer 35 was not reduced or removed before the back surface field layer 80 is formed.
  • the second conductive type impurity e.g., the n-type impurity
  • FIG. 18 is a flowchart showing processes of a fabrication method of a silicon solar cell according to an embodiment of the present invention. Detailed description of the fabrication method has been described with reference to FIGS. 9-17 so that redundant explanation for each operation will be omitted.
  • a solar cell formed from the fabrication method as shown is but one example, and is not necessarily limited thereto. Therefore, a process of forming an antireflection film in operation S 160 and a process of removing an n-type impurity doping layer formed on a rear surface of a silicon substrate in operation S 170 are not restricted to the order shown, but may be changed or switched with other operations or with each other.
  • a process of printing front surface and rear electrode pastes in operation S 180 and a process of thermally heating the front surface and the rear electrode pastes in S 190 are not restricted to the order shown, but may be changed or switched with other operations.
  • Experimental examples of the fabrication method of the solar cell according to the present invention are as follows. In other words, a slim-type solar cell according to the fabrication method of the present invention and a solar cell having a general or a conventional thickness according to a method in the related art are fabricated by differentiating experimental conditions as shown in the table below and the efficiencies thereof are measured.
  • the thickness of the silicon substrate, which is subjected to the fabrication method of the solar cell according to the present invention is 140 ⁇ m. Accordingly, the silicon substrate is referred to as a slim-type.
  • solar cells in comparative examples 1 and 2 have the thickness of the general solar cell, 220 ⁇ m, and solar cells in other comparative examples 3 and 4 have an ultra-thin thickness (i.e., 140 ⁇ m).
  • Comparative examples 3 and 4 respectively disclose solar cells where a single emitter layer and a selective emitter layer are formed on a substrate having a thickness of 220 ⁇ m.
  • Comparative examples 1 and 2 disclose slim-type solar cells having a silicon substrate with a thickness of 140 ⁇ m as shown in the experimental example of the present invention, wherein they respectively include a single emitter layer and a selective emitter layer.
  • Experimental examples 5 and 6 also disclose slim-type solar cells having a silicon substrate with a thickness of 140 ⁇ m, wherein comparative example 5 includes a single emitter layer and comparative example 6 includes a selective emitter layer, and the n++ emitter layer (e.g., a high-concentration n-type impurity layer) formed on the rear surface of the substrate is removed only from experimental example 6 among the examples.
  • the n++ emitter layer e.g., a high-concentration n-type impurity layer
  • the comparative examples and the experimental examples of the present invention are all designed to have a textured structure by having the surface of the front surface substrate etched with an etchant, for example, an acid. It can be appreciated that the antireflection film is stacked on the front surface in all of the examples and there is no significant difference in the examples for other processes.
  • the method to pattern the opening part (such as opening part 35 in FIG. 10 ) on the front surface of the silicon substrate of the solar cell does not correspond to the examples having a single emitter layer, but corresponds to the examples having the selective emitter layer. For the examples having the selective emitter layer, there is no difference in the process of forming the opening part.
  • approximately zero refers to a concentration an impurity which results from unavoidable or unintended inclusion of the impurity.
  • the second conductive type (or n-type) impurity refers to inclusion of the second conductive type impurity when the process to remove the rear emitter portion is not fully completed, or the unintended inclusion of a small amount of the second conductive type impurity.
  • it also refers to a concentration of the second conductive type impurity that has the same or similar effect or characteristic as when the concentration of the second conductive type impurity is zero.
  • reference to the thickness of the substrate, the p-type silicon substrate, or first conductive type silicon substrate may be a thickness that includes the emitter layer, the selective emitter layer and/or the back surface field layer. In other embodiments, one or more of the emitter layer, the selective emitter layer and/or the back surface field layer need not be included when referencing the thickness of the substrate, the p-type silicon substrate, or first conductive type silicon substrate.
  • a reference to a first type impurity silicon substrate, a p-type silicon substrate or a silicon substrate is made throughout. Nevertheless, embodiments of the present invention are intended to include non-silicon substrates as well, such as any semiconductor substrate, whether they be inherent, compound, or doped, and others.
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